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order number: 320066-003us august 2009 intel ? ep80579 integrated processor product line datasheet
intel ? ep80579 integrated processor product line datasheet august 2009 2 order number: 320066-003us legal lines and disclaimers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. see http://www.intel.com/products/processor_number for details. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel, intel logo, intel strataflash and pentium are trademarks or registered trademarks of intel corporation or its subsidiari es in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2009, intel corporation. all rights reserved.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 3 product features ? system on a chip (soc) ? integrated intel ? architecture (ia) processor and chipset (mch/ich) technology ? extensive integration of standard intel architecture communications interfaces provide cost, power and board area savings (gigabit ethernet (gbe), time division multiplexing (tdm) ? processing, security services unit (ssu), ? and acceleration services units (asu) ? ) ? sku support 1 ? embedded: intel architecture compatibility and high-speed interfaces (gbes, pci express*) ? application services: security ? packet security compatibility and ip telephony packet security, tdm, and high-level data link control (hdlc) ? intel architecture processor ? low-power and high-performance architecture based on intel architecture (ia-32) processor ? three operating frequency skus: - 600 mhz, 1066 mhz, or 1200 mhz ? 256 kb l2 data coherent cache (2 way) ? integrated memory control hub (imch) and integrated i/o control hub (iich) compatible ? enhanced dma (edma) controller ? two sata gen1 or gen2 interfaces ? two usb 1.1 or usb 2.0 ports ? two integrated, 16550-compatible uarts ? lpc 1.1 interface ? serial peripheral interface (spi) ? ? two smbus 2.0 compliant interfaces ?gpios ? watchdog timer ? one 32/64-bit and two 32-bit high-precision event timers ? acceleration services unit (asu) ? ? high performance accelerator on-chip engines for packet processing ? support capabilities for commonly used protocol implementations such as tcp/ip, udp, ipsec, ssl, nat, and srtp ? security services unit (ssu) ? ? high-performance on-chip crypto accelerator ? support capabilities for commonly used cryptographic protocol implementations ? intel recommends using the spi for pre-boot firmware due to the reduced availability of lpc fwh. ? feature must be enabled with ep80579 software. refer to the ep80579 software documentation for more information. 1. for complete information about product features and skus, please refer to chapter 47.0, ?skus, power savings and pre-boot firmware? . ? single-channel double-data-rate (ddr) sdram memory ? supports ddr2 at 400/533/667/800 mt/s ? supports 32 or 64-bit interfaces ? error correction code (ecc); single-bit correct/ double-bit detect (sec/ded) coverage ? addressable from intel architecture processor and pci express ? three gigabit ethernet macs ? three 10/100/1000 ports with rgmii/rmii interfaces ? mdio interface for external phy configuration ? serial eeprom interface supports network boot and wake-on lan ? industry standard pci express interface ? supports 1x8, 2x4, or 2x1 configurations as a root complex ? integrated serial ata (sata) host controllers ? independent dma operation on two ports ? data transfer rates up to 3.0 gb/s ?alternate device id ? integrated high-speed serial interface (tdm) ? ? supports up to 12 external t1/e1 and codecs ? supports up to 128 hdlc channels ? local expansion bus (leb) ? supports up to eight chip selects ? 25-bit address and 16-bit data ? supports hpi-8 and hpi-16 ? dual controller area network (can) ? supports two can 2.0b interfaces ? single synchronous serial port (ssp) compatible ? ieee 1588-2008 hardware assistance ? supports two gbe and two can interfaces ? time master/target support ? 1088-ball fcbga package ? dimensions of 37.5 mm x 37.5 mm ? 1.092-mm solder ball pitch ? lead-free only ? rohs 5/6 compliant ? typical applications ? embedded, security and/or ip telephony applications
contents intel ? ep80579 integrated processor product line datasheet august 2009 4 order number: 320066-003us contents introduction and overview, volume 1 of 6 ................................... 91 1.0 introduction ............................................................................................................93 1.1 introduction ......................................................................................................93 1.2 document organization ......................................................................................93 1.3 referenced documents and related websites ........................................................94 1.4 acronyms .........................................................................................................95 1.5 glossary ...........................................................................................................98 2.0 architectural overview .......................................................................................... 103 2.1 overview ........................................................................................................ 103 2.1.1 block summary ...................................................................................... 103 2.1.2 external interfaces ................................................................................. 106 2.1.3 frequencies and gear ratios .................................................................... 107 2.2 signaling architecture ...................................................................................... 107 2.3 dma and peer-to-peer data transfers................................................................. 109 3.0 platform memory and device configuration ........................................................... 111 3.1 overview ........................................................................................................ 111 3.1.1 configuration objectives.......................................................................... 111 3.1.2 terminology and conventions .................................................................. 112 3.2 ia platform infrastructure ................................................................................. 113 3.2.1 ia platform view of endianness ................................................................ 113 3.2.2 ia platform view of configuration ............................................................. 114 3.3 high-level views ............................................................................................. 116 3.3.1 characteristics of external system memory (dram) .................................... 116 3.3.2 characteristics of internal and external memories ....................................... 117 3.3.3 characteristics of device configuration ...................................................... 118 3.4 memory map for ia-attached agents .................................................................. 119 3.5 memory map for aioc-attached devices ............................................................. 119 3.6 endianness ..................................................................................................... 119 3.7 pci configuration............................................................................................. 119 3.7.1 overview............................................................................................... 120 3.7.2 device tree ........................................................................................... 121 3.7.3 materializing device structures................................................................. 124 3.7.4 pci configuration headers ....................................................................... 124 4.0 signaling ................................................................................................................ 131 4.1 overview ........................................................................................................ 131 4.1.1 terminology and conventions .................................................................. 132 4.2 existing signaling capabilities............................................................................ 132 4.2.1 ia-32 core/platform ................................................................................ 133 4.2.1.1 msi and intx signaling.................................................................... 133 4.2.1.2 gpio signaling ............................................................................... 133 4.2.2 other agents ......................................................................................... 133 4.3 inter-agent signaling ....................................................................................... 134 4.3.1 signaling that travels around the signal bridge .......................................... 135 4.3.2 signaling that is bridged from a side-band source signal ............................ 135 4.3.2.1 targeting the ia-32 core with a bridged signal.................................... 136 5.0 error handling ....................................................................................................... 139 5.1 overview ........................................................................................................ 139 5.2 ep80579 view of error reporting ....................................................................... 139
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 5 contents 5.2.1 hardware capabilities ............................................................................. 139 5.2.2 software usage model ............................................................................ 141 5.3 error reporting by the imch ............................................................................. 141 5.3.1 overview of the first and next error architecture ....................................... 141 5.3.2 global error events ................................................................................ 142 5.3.3 unit-level errors from the buffer unit ....................................................... 143 5.3.4 unit-level errors from the dram interface ................................................ 143 5.3.5 unit-level errors from the fsb interface ................................................... 144 5.3.6 unit-level errors from the nsi ................................................................. 145 5.3.7 unit-level errors from the edma engine.................................................... 146 5.3.8 unit-level errors from pci express* ports a0 and a1 .................................. 147 5.4 error reporting by the iich .............................................................................. 149 5.4.1 smbus interface .................................................................................... 149 5.4.2 lpc interface......................................................................................... 150 5.4.3 usb 1.1 interface .................................................................................. 151 5.4.4 usb 2.0 interface .................................................................................. 151 5.4.5 sata interface ...................................................................................... 152 5.4.6 serial i/o interface ................................................................................ 153 5.5 error reporting by the system memory controller ............................................... 153 5.5.1 handling out-of-bounds addresses........................................................... 154 5.5.2 imch - memory controller ....................................................................... 154 5.6 error reporting by aioc devices ....................................................................... 155 5.6.1 gigabit ethernet mac ............................................................................. 155 5.6.2 can interface ........................................................................................ 156 5.6.3 ssp interface ........................................................................................ 157 5.6.4 local expansion bus ............................................................................... 158 5.6.5 ieee 1588, and gcu............................................................................... 159 6.0 reset and power management ............................................................................... 161 6.1 reset and powergood distribution ..................................................................... 161 6.1.1 types of reset ....................................................................................... 161 6.1.1.1 powergood implementation.............................................................. 161 6.1.1.2 hard reset implementation.............................................................. 162 6.1.1.3 software controlled reset ................................................................ 162 6.1.1.4 cpu only reset implementation ....................................................... 162 6.1.1.5 s-state wake events ....................................................................... 163 6.1.1.6 targeted reset implementation ........................................................ 163 6.1.2 platform reset and powergood................................................................. 163 6.1.2.1 platform powergood ........................................................................ 163 6.1.2.2 platform reset................................................................................ 163 6.1.2.3 reset and powergood distribution ..................................................... 164 6.1.3 ep80579 power sequencing and reset sequence........................................ 167 6.2 bios boot flow (initialization) .......................................................................... 175 6.2.1 memory configuration............................................................................. 176 6.2.2 memory initialization .............................................................................. 176 6.2.3 boot from network ................................................................................. 176 6.3 power management ......................................................................................... 177 6.3.1 power management states ...................................................................... 177 6.3.2 power management support .................................................................... 179 6.3.2.1 transitioning between power states .................................................. 181 6.3.2.2 power state transition timing diagrams ............................................ 181 6.3.3 thermal sensor ..................................................................................... 182 6.3.4 acpi implementation.............................................................................. 182 7.0 register summary ................................................................................................. 183 7.1 overview of register descriptions and summaries ............................................... 183
contents intel ? ep80579 integrated processor product line datasheet august 2009 6 order number: 320066-003us 7.1.1 register description tables ...................................................................... 183 7.1.2 register field access attributes ................................................................ 189 7.1.3 register nomenclature and values ............................................................ 189 7.1.4 ?sticky? register fields............................................................................ 190 7.2 ia-32 core registers ........................................................................................ 190 7.3 imch and iich registers .................................................................................. 191 7.3.1 imch registers: bus 0, device 0, function 0 ............................................. 191 7.3.2 imch error reporting registers: bus 0, device 0, function 1 ........................ 195 7.3.3 edma engine registers: bus 0, device 1, function 0 ................................... 197 7.3.4 pci express* port a registers: bus 0, device 2, function 0 ......................... 200 7.3.5 pci express* port a1 registers: bus 0, device 3, function 0 ........................ 203 7.3.6 usb (1.1) controller: bus 0, device 29, functions 0 ................................... 206 7.3.7 usb (2.0) controller: bus 0, device 29, function 7 .................................... 207 7.3.8 root complex: bus 0, device 31, function 0 ............................................. 209 7.3.9 lpc interface: bus 0, device 31, function 0 .............................................. 210 7.3.10 sata controller: bus 0, device 31, function 2............................................ 213 7.3.11 smbus controller: bus 0, device 31, function 3 .......................................... 216 7.3.12 ia-32 core interface i/o-mapped register ................................................. 217 7.3.13 imch pci configuration ........................................................................... 217 7.3.14 apic ..................................................................................................... 217 7.3.15 8259 interrupt controller (pic) ................................................................ 219 7.3.16 apm power management.......................................................................... 219 7.3.17 lpc dma ............................................................................................... 220 7.3.18 8254 timers .......................................................................................... 221 7.3.19 high precision event timers ..................................................................... 222 7.3.20 watchdog timer and serial i/o................................................................. 222 7.3.21 real time clock...................................................................................... 223 7.4 aioc registers ................................................................................................ 224 7.4.1 pci-to-pci bridge: bus 0, device 4, function 0 ........................................... 224 7.4.2 gigabit ethernet mac: bus m, devices 0, 1, and 2, function 0 ..................... 226 7.4.3 gcu: bus m, device 3, function 0............................................................. 240 7.4.4 can interface: bus m, device 4 and 5, function 0 ...................................... 242 7.4.5 ssp interface: bus m, device 6, function 0 ............................................... 245 7.4.6 ieee 1588 timestamp unit: bus m, device 7, function 0 ............................. 247 7.4.7 local expansion bus interface: bus m, device 8, function 0: ....................... 249 ia-32 core and integrated memory controller hub, volume 2 of 6 .............................................................................. 251 8.0 ia-32 core ............................................................................................................. 253 8.1 overview ........................................................................................................ 253 8.2 theory of operation ......................................................................................... 253 8.2.1 l2 cache size ........................................................................................ 253 8.2.2 platform and jtag identifiers ................................................................... 253 8.2.3 fsb physical interface ............................................................................. 254 8.2.4 ia-32 core and fsb frequency ................................................................. 254 9.0 cmi introduction ................................................................................................... 255 9.1 system architecture......................................................................................... 256 9.2 pci express*................................................................................................... 256 9.2.1 supported pci express configurations ....................................................... 257 9.2.1.1 low power sku with pci express ports removed ................................. 257 9.3 supported debug and management interfaces ..................................................... 257 9.4 supported imch integrated features.................................................................. 257 9.4.1 edma controller ..................................................................................... 257
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 7 contents 9.4.2 integrated memory init/test engine ......................................................... 258 9.4.3 coherent memory write buffer ................................................................. 258 9.4.4 rasum features .................................................................................... 258 9.4.4.1 sec-ded ecc................................................................................. 259 9.4.4.2 integrated memory scrub engine ...................................................... 259 9.5 imch feature list........................................................................................... 259 9.5.1 memory interface................................................................................... 259 9.5.2 pci express interface in imch ................................................................. 259 9.5.3 edma controller..................................................................................... 261 9.5.4 coherent memory write buffer ................................................................. 262 9.5.5 integrated memory scrub engine ............................................................. 262 9.5.6 hardware memory initialization engine...................................................... 262 9.5.7 system management functions ................................................................ 263 9.5.8 rasum ................................................................................................. 263 9.6 iich feature list ............................................................................................. 264 9.6.1 low-pin count (lpc) interface and fi rmware hub (fwh) interface ................ 264 9.6.2 serial peripheral interface (spi) ............................................................... 264 9.6.3 integrated serial ata host controllers ...................................................... 264 9.6.4 usb .................................................................................................... 264 9.6.5 interrupt controller ................................................................................ 264 9.6.6 power management logic ....................................................................... 265 9.6.7 dma controller ...................................................................................... 265 9.6.8 timers based on 82c54 .......................................................................... 265 9.6.9 high precision event timers (hpet) .......................................................... 265 9.6.10 real-time clock with 256-byte battery-backed cmos ram .......................... 265 9.6.11 system tco reduction circuits ............................................................... 265 9.6.12 smbus .................................................................................................. 265 9.6.13 watchdog timer..................................................................................... 266 9.6.14 serial port............................................................................................. 266 9.6.15 gpio .................................................................................................... 266 10.0 system address map ............................................................................................. 267 10.1 overview ....................................................................................................... 267 10.1.1 system memory spaces .......................................................................... 268 10.1.2 vga and mda memory spaces ................................................................. 268 10.1.3 pam memory spaces............................................................................... 270 10.1.4 tseg smm memory space ....................................................................... 274 10.1.5 pci express enhanced configuration aperture ............................................ 274 10.1.6 ioapic memory space ............................................................................ 275 10.1.7 fsb interrupt memory space ................................................................... 275 10.1.8 high smm memory space ........................................................................ 276 10.1.9 pci device memory (mmio) ..................................................................... 276 10.1.9.1 device 2 memory and prefetchable memory........................................ 277 10.1.9.2 device 3 memory and prefetchable memory........................................ 277 10.1.9.3 device 4 memory and prefetchable memory........................................ 277 10.2 imch responses to edma transactions .............................................................. 278 10.2.1 fixed address spaces (edma).................................................................. 278 10.2.2 relocatable address spaces (edma) ......................................................... 278 10.3 i/o address space........................................................................................... 279 10.3.1 configuration window ............................................................................. 279 10.3.2 vga and mda regions ............................................................................ 280 10.4 main memory addressing.................................................................................. 281 10.5 system management mode (smm) space............................................................ 281 10.5.1 smm addressing ranges ......................................................................... 281 10.5.1.1 smm space restrictions ................................................................... 281
contents intel ? ep80579 integrated processor product line datasheet august 2009 8 order number: 320066-003us 10.5.1.2 smm space definition ...................................................................... 282 10.6 memory reclaim background............................................................................. 283 10.6.1 memory remapping algorithm.................................................................. 283 10.7 iich register and memory mappings .................................................................. 284 10.7.1 i/o map ................................................................................................ 284 10.7.1.1 fixed i/o address ranges ................................................................ 284 10.7.1.2 variable i/o decode ranges ............................................................. 286 10.7.2 memory map .......................................................................................... 287 10.7.3 boot-block update scheme ...................................................................... 288 11.0 system memory controller ..................................................................................... 289 11.1 overview ........................................................................................................ 289 11.2 memory controller feature list .......................................................................... 289 11.3 configurations ................................................................................................. 291 11.3.1 rules for populating dimm slots ............................................................... 293 11.3.2 dram addressing ................................................................................... 294 11.3.3 memory address translation tables .......................................................... 295 11.3.3.1 ddr2 address translation tables ...................................................... 295 11.3.4 dram timings........................................................................................ 296 11.3.4.1 2t timing mode .............................................................................. 297 11.3.5 dq/dqs mapping ................................................................................... 298 11.3.6 32-bit mode ........................................................................................... 298 11.4 ddr2 features ................................................................................................ 298 11.4.1 interface signalling voltage ..................................................................... 298 11.4.2 on-dimm die termination (odt) .............................................................. 299 11.4.2.1 odt control of reads ...................................................................... 300 11.4.2.2 odt control of writes ...................................................................... 300 11.4.3 on-die termination (odtz) on the ep80579 ............................................. 301 11.4.4 refresh ................................................................................................. 302 11.4.5 self-refresh........................................................................................... 302 11.4.6 rcomp.................................................................................................. 303 11.4.7 ddr2 mr and emr settings...................................................................... 303 11.4.8 scrubbing support .................................................................................. 304 11.4.8.1 demand scrubbing .......................................................................... 304 11.4.8.2 background scrubbing ..................................................................... 304 11.5 error handling ................................................................................................. 304 12.0 enhanced direct memory access controller (edma) ............................................... 307 12.1 overview ........................................................................................................ 307 12.1.1 features................................................................................................ 308 12.1.2 logical block diagram ............................................................................. 309 12.2 channel programming interface......................................................................... 310 12.3 chaining operation .......................................................................................... 311 12.3.1 chain descriptor definition ...................................................................... 311 12.3.2 dma chain descriptor in memory .............................................................. 312 12.3.3 chain descriptor usage ........................................................................... 312 12.3.4 scatter/gather transfer........................................................................... 314 12.3.5 appending to a descriptor chain ............................................................... 314 12.3.6 splicing a descriptor chain into a linked list .............................................. 315 12.4 transfer types ................................................................................................ 316 12.4.1 local memory to local memory................................................................. 316 12.4.2 local memory to i/o subsystem memory ................................................... 316 12.4.3 i/o memory to local memory ................................................................... 317 12.4.4 i/o memory to i/o memory...................................................................... 317 12.5 addressing...................................................................................................... 317 12.5.1 address coherence ................................................................................. 317
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 9 contents 12.5.2 addressing modes .................................................................................. 318 12.5.2.1 standard byte movement mode ........................................................ 318 12.5.2.2 decrement/byte reversal mode ....................................................... 319 12.5.2.3 constant address modes .................................................................. 320 12.5.2.4 buffer and memory initialization modes.............................................. 326 12.5.3 pci express traffic class ......................................................................... 329 12.6 channel data queuing ..................................................................................... 329 12.7 error conditions .............................................................................................. 329 12.7.1 controller interface error ........................................................................ 330 12.7.2 memory interface error........................................................................... 330 12.7.3 i/o interface error ................................................................................. 331 12.8 channel arbitration.......................................................................................... 331 12.8.1 normal arbitration scheme...................................................................... 331 12.8.2 prioritized arbitration scheme.................................................................. 332 12.9 configuration .................................................................................................. 332 12.9.1 power up/default status ......................................................................... 333 12.9.2 channel-specific register definitions ........................................................ 333 12.9.2.1 channel control register ? ccr ........................................................ 333 12.9.2.2 channel status register ? csr ......................................................... 334 12.9.2.3 current descriptor address register ? cdar ...................................... 334 12.9.2.4 current descriptor upper address register ? cduar ........................... 334 12.9.2.5 source address register ? sar......................................................... 335 12.9.2.6 source upper address register ? suar ............................................. 335 12.9.2.7 destination address register ? dar .................................................. 335 12.9.2.8 destination upper address register ? duar ....................................... 335 12.9.2.9 next descriptor address register ? ndar .......................................... 335 12.9.2.10 next descriptor upper address register ? nduar ............................... 336 12.9.2.11 transfer count register ? tcr.......................................................... 336 12.9.2.12 descriptor control register ? dcr..................................................... 336 12.10 interrupts ...................................................................................................... 337 12.10.1 interrupt routing mechanisms ................................................................. 338 12.10.2 message signaled interrupt (msi) ............................................................ 339 12.10.2.1 msi control register ? msicr .......................................................... 339 12.10.2.2 msi address register ? msiar ......................................................... 339 12.10.2.3 msi data register ? msidr.............................................................. 340 12.10.3 interrupt ordering.................................................................................. 340 12.10.3.1 interrupt ordering for memory destination ......................................... 340 12.10.3.2 interrupt ordering for outbound destination ...................................... 340 12.11 initiating an edma transfer .............................................................................. 341 12.11.1 setup and initiation................................................................................ 341 12.11.2 suspend function................................................................................... 342 12.11.3 stop function ........................................................................................ 342 12.11.4 edma process flow ................................................................................ 343 13.0 platform configuration .......................................................................................... 345 13.1 rasum features - smbus access ....................................................................... 345 13.2 platform configuration structure conceptual overview ......................................... 345 13.2.1 imch pci devices .................................................................................. 346 13.2.2 iich pci devices.................................................................................... 347 13.3 routing configuration accesses ......................................................................... 349 13.3.1 standard pci bus configuration mechanism ............................................... 349 13.3.2 pci bus #0 configuration mechanism........................................................ 350 13.3.3 primary pci and downstream configuration mechanism .............................. 350 13.3.4 imch pci express bus configuration mechanism ........................................ 351 13.3.5 imch configuration cycle flow chart ....................................................... 352 13.4 imch register introduction............................................................................... 353 13.5 imch sticky registers...................................................................................... 353
contents intel ? ep80579 integrated processor product line datasheet august 2009 10 order number: 320066-003us 13.6 imch i/o mapped registers .............................................................................. 354 13.6.0.1 offset 0cf8h: config_address - configuration address register ........ 354 13.6.0.2 offset 0cfch: config_data - configuration data register .................. 355 13.7 imch memory mapped registers ........................................................................ 355 13.8 pci express enhanced configuration mechanisms................................................. 356 13.8.1 pci express configuration transaction header ............................................ 356 13.8.2 enhanced configuration hardware implications........................................... 356 13.8.3 enhanced configuration memory address map ............................................ 357 13.8.4 enhanced configuration fsb address format.............................................. 357 14.0 ras features and exception handling .................................................................... 359 14.1 ras features .................................................................................................. 359 14.1.1 data protection ...................................................................................... 359 14.1.1.1 dram ecc ..................................................................................... 359 14.1.1.2 pci express interface ...................................................................... 359 14.1.1.3 data error propagation between interfaces/units ................................ 359 14.1.2 dram data integrity ............................................................................... 360 14.1.2.1 periodic memory scrubbing............................................................... 360 14.1.2.2 dram hardware initialization ............................................................ 360 14.1.2.3 uncorrectable retries....................................................................... 360 14.1.2.4 dram refresh................................................................................. 361 14.1.2.5 ddr i/o hardware assisted calibration .............................................. 361 14.1.3 pci express data integrity ....................................................................... 361 14.1.3.1 pci express training........................................................................ 361 14.1.3.2 pci express retry ........................................................................... 361 14.1.3.3 pci express recovery ...................................................................... 361 14.1.3.4 pci express retrain ......................................................................... 361 14.1.4 test/support major buses........................................................................ 362 14.1.4.1 iich xor ....................................................................................... 362 14.1.4.2 smb (imch) ................................................................................... 362 14.1.4.3 smb (iich) .................................................................................... 362 14.1.4.4 i2c ............................................................................................... 362 14.2 exception handling .......................................................................................... 362 14.2.1 ferr/nerr global register scheme ......................................................... 362 14.2.1.1 ferr/nerr unit registers ................................................................ 363 14.2.1.2 clearing ferr/nerr registers .......................................................... 363 14.2.1.3 ferr/nerr unit specific .................................................................. 364 14.2.1.4 serr/smi/sci enabling registers...................................................... 364 14.2.1.5 mcerr enabling registers ................................................................ 365 14.2.1.6 error escalation register .................................................................. 365 14.2.1.7 error masking ................................................................................. 365 14.2.1.8 pci express errors and errors on behalf of pci express ........................ 366 14.2.1.9 configurable error containment at the legacy interface ....................... 367 14.3 error conditions signaled.................................................................................. 368 15.0 platform management (imch) ............................................................................... 371 15.1 integrated smbus interface............................................................................... 371 15.2 smbus target architecture ................................................................................ 371 15.2.1 high level operation............................................................................... 371 15.2.1.1 smbus register summary ................................................................ 371 15.2.1.2 internal register access mechanism .................................................. 373 15.2.1.3 smbus register definitions ............................................................... 373 15.2.1.4 unsupported access addresses ......................................................... 376 15.2.1.5 smbus transaction pictograms ......................................................... 376 15.2.2 suggested smbus usage models ............................................................... 380 15.2.2.1 remote error handling..................................................................... 380 15.2.2.2 remote platform monitoring ............................................................. 380 15.3 platform power management support ................................................................. 380
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 11 contents 15.3.1 supported system power states .............................................................. 380 15.3.1.1 supported cpu power states ............................................................ 381 15.3.1.2 supported device power states ........................................................ 381 15.3.1.3 supported bus power states ............................................................ 381 15.3.2 ddr2 interface power management.......................................................... 381 15.3.3 pci express interface power management ................................................. 382 15.3.3.1 pci express link power state definitions ........................................... 382 15.3.3.2 software controlled pci express link states....................................... 382 15.3.3.3 hardware controlled pci express link states...................................... 383 15.3.3.4 system clocking solution dependencies............................................. 384 15.3.3.5 device and link pm initialization ....................................................... 384 15.3.4 device and slot power limits ................................................................... 385 15.3.5 pme support.......................................................................................... 385 15.3.5.1 pme wake signaling ........................................................................ 385 15.3.5.2 pme messaging ............................................................................... 386 15.3.6 bios support for pci express pm messaging.............................................. 386 15.3.6.1 pci express pme_turn_off semantic .............................................. 386 16.0 imch registers ...................................................................................................... 389 16.1 imch registers: bus 0, device 0, function 0 ...................................................... 389 16.1.1 register details ..................................................................................... 391 16.1.1.1 offset 00h: vid ? vendor identification register ................................. 391 16.1.1.2 offset 02h: did ? device identification register ................................. 391 16.1.1.3 offset 04h: pcicmd: pci command register ...................................... 392 16.1.1.4 offset 06h: pcists: pci status register ............................................ 393 16.1.1.5 offset 08h: rid - revision identification register ................................ 394 16.1.1.6 offset 0ah: subc - sub-class code register ...................................... 394 16.1.1.7 offset 0bh: bcc ? base class code register....................................... 394 16.1.1.8 offset 0eh: hdr - header type register ............................................ 395 16.1.1.9 offset 14h: smrbase - system memory rcomp base address register............................................................................. 395 16.1.1.10 offset 2ch: svid - subsystem vendor identification register ............... 396 16.1.1.11 offset 2eh: sid - subsystem identification register ............................ 397 16.1.1.12 offset 4ch: nsibar - root complex block address register ................. 397 16.1.1.13 offset 50h: cfg0 - imch configuration 0 register............................... 398 16.1.1.14 offset 51h: imch_cfg1 ? imch configuration 1 register ..................... 399 16.1.1.15 offset 53h: cfgns1 - configuration 1 register ................................... 399 16.1.1.16 offset 58h: fdhc - fixed dram hole control register ......................... 400 16.1.1.17 offset 59h: pam0 - programmable attribute map 0 register ................. 401 16.1.1.18 offset 5ah: pam1 - programmable attribute map 1 register ................. 402 16.1.1.19 offset 5bh: pam2 - programmable attribute map 2 register ................. 403 16.1.1.20 offset 5ch: pam3 - programmable attribute map 3 register ................. 404 16.1.1.21 offset 5dh: pam4 - programmable attribute map 4 register ................. 405 16.1.1.22 offset 5eh: pam5 - programmable attribute map 5 register ................. 406 16.1.1.23 offset 5fh: pam6 - programmable attribute map 6 register.................. 407 16.1.1.24 offset 9ch: devpres - device present register .................................. 407 16.1.1.25 offset 9dh: exsmrc - extended system management ram control register. 409 16.1.1.26 offset 9eh: smram - system management ram control register .......... 411 16.1.1.27 offset 9fh: exsmramc - expansion system management ram control register ........................................................................................ 413 16.1.1.28 offset b8h: imch_mencbase - ia/asu shared non-coherent (aioc-direct) memory base address register ......................................................... 413 16.1.1.29 offset bch: imch_menclimit - ia/asu shared non-coherent (aioc-direct) memory limit address register......................................................... 414 16.1.1.30 offset c4h: tolm - top of low memory register................................. 414 16.1.1.31 offset c6h: remapbase - remap base address register...................... 416 16.1.1.32 offset c8h: remaplimit ? remap limit address register .................... 416 16.1.1.33 offset cah: remapoffset - remap offset register ............................ 417
contents intel ? ep80579 integrated processor product line datasheet august 2009 12 order number: 320066-003us 16.1.1.34 offset cch: tom - top of memory register ........................................ 417 16.1.1.35 offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register ..................................................................... 418 16.1.1.36 offset d8h: cachectl0 - write cache control 0 register ..................... 418 16.1.1.37 offset deh: skpd - scratchpad data register ..................................... 419 16.1.1.38 offset f6h: imch_tst2 - imch test byte 2 register ............................ 419 16.1.1.39 offset 60h: drb[0-3] ? dram row [3:0] boundary register ................. 420 16.1.1.40 offset 70h: dra[0-1] ? dram row [0:1] attribute register .................. 421 16.1.1.41 offset 78h: drt0 - dram timing register 0 ....................................... 424 16.1.1.42 offset 64h: drt1 ? dram timing register 1 ....................................... 431 16.1.1.43 offset 7ch: drc ? dram controller mode register .............................. 435 16.1.1.44 offset 84h: eccdiag ? ecc detection/correction diagnostic register.......................................................................... 437 16.1.1.45 offset 88h: sdrc ? ddr sdram secondary control register ................ 439 16.1.1.46 offset 8ch: ckdis ? ck/ck# clock disable register ............................ 441 16.1.1.47 offset 8dh: ckedis - cke clock disable register ................................ 442 16.1.1.48 offset 90h: sparectl - spare control register .................................. 443 16.1.1.49 offset b0h: ddr2odtc - ddr2 odt control register .......................... 443 16.2 dram controller error reporting registers: bus 0, device 0, function 1 ................. 445 16.2.1 register details ...................................................................................... 447 16.2.1.1 offset 00h: vid - vendor identification register .................................. 447 16.2.1.2 offset 02h: did - device identification register .................................. 447 16.2.1.3 offset 04h: pcicmd - pci command register ..................................... 448 16.2.1.4 offset 06h: pcists - pci status register ........................................... 448 16.2.1.5 offset 08h: rid - revision identification register ................................ 449 16.2.1.6 offset 0ah: subc - sub-class code register....................................... 449 16.2.1.7 offset 0bh: bcc - base class code register........................................ 449 16.2.1.8 offset 0dh: mlt - master latency timer register ................................ 450 16.2.1.9 offset 0eh: hdr - header type register............................................. 450 16.2.1.10 offset 2ch: svid - subsystem vendor identification register ................ 450 16.2.1.11 offset 2eh: sid - subsystem identification register............................. 451 16.2.1.12 offset 40h: global_ferr - global first error register......................... 451 16.2.1.13 offset 44h: global_nerr - global next error register........................ 453 16.2.1.14 offset 48h: nsi_ferr - nsi first error register .................................. 454 16.2.1.15 offset 4ch: nsi_nerr - nsi next error register ................................. 457 16.2.1.16 offset 50h: nsi_scicmd - nsi sci command register ........................ 459 16.2.1.17 offset 54h: nsi_smicmd - nsi smi command register ....................... 461 16.2.1.18 offset 58h: nsi_serrcmd - nsi serr command register ................... 464 16.2.1.19 offset 5ch: nsi_mcerrcmd - nsi mcerr command register .............. 466 16.2.1.20 offset 60h: fsb_ferr - fsb first error register.................................. 468 16.2.1.21 offset 62h: fsb_nerr - fsb next error register ................................. 469 16.2.1.22 offset 64h: fsb_emask - fsb error mask register .............................. 470 16.2.1.23 offset 68h: fsb_scicmd - fsb sci command register ....................... 471 16.2.1.24 offset 6ah: fsb_smicmd - fsb smi command register....................... 472 16.2.1.25 offset 6ch: fsb_serrcmd - fsb serr command register .................. 473 16.2.1.26 offset 6eh: fsb_mcerrcmd - fsb mcerr command register .............. 474 16.2.1.27 offset 70h: buf_ferr - memory buffer first error register .................. 475 16.2.1.28 offset 72h: buf_nerr - memory buffer next error register.................. 475 16.2.1.29 offset 74h: buf_emask - memory buffer error mask register ............... 476 16.2.1.30 offset 78h: buf_scicmd - memory buffer sci command register ........ 477 16.2.1.31 offset 7ah: buf_smicmd - memory buffer smi command register ....... 478 16.2.1.32 offset 7ch: buf_serrcmd - memory buffer serr command register .......................................................................... 479 16.2.1.33 offset 7eh: buf_mcerrcmd - memory buffer mcerr command register .......................................................................... 480 16.2.1.34 offset e4h: nsierrinjctl - nsi error injection control register ........... 481 16.2.1.35 offset e8h: berrinjctl - buffer error injection control register........... 481 16.2.1.36 offset 80h: dram_ferr - dram first error register ............................ 482 16.2.1.37 offset 82h: dram_nerr - dram next error register ........................... 484 16.2.1.38 offset 84h: dram_emask - dram error mask register ........................ 485
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 13 contents 16.2.1.39 offset 88h: dram_scicmd - dram sci command register ................. 486 16.2.1.40 offset 8ah: dram_smicmd - dram smi command register ................ 487 16.2.1.41 offset 8ch: dram_serrcmd - dram serr command register ............ 488 16.2.1.42 offset 8eh: dram_mcerrcmd - dram mcerr command register........ 490 16.2.1.43 offset 98h: thresh_sec0 - rank 0 sec error threshold register .......................................................................... 491 16.2.1.44 offset 9ah: thresh_sec1 - rank 1 sec error threshold register .......................................................................... 491 16.2.1.45 offset a0h: dram_secf_add - dram first single bit error correct address register ........................................................................................ 492 16.2.1.46 offset a4h: dram_ded_add - dram double bit error address register............................................................................. 492 16.2.1.47 offset a8h: dram_scrb_add - dram scrub error address register............................................................................. 493 16.2.1.48 offset b0h: dram_sec_r0 - dram rank 0 sec error counter register............................................................................. 493 16.2.1.49 offset b2h: dram_ded_r0 - dram rank 0 ded error counter register............................................................................. 494 16.2.1.50 offset b4h: dram_sec_r1 - dram rank 1 sec error counter register............................................................................. 494 16.2.1.51 offset b6h: dram_ded_r1 - dram rank 1 ded error counter register............................................................................. 495 16.2.1.52 offset c2h: thresh_ded - ded error threshold register .................... 495 16.2.1.53 offset c4h: dram_secf_syndrome - dram first single error correct syndrome register ......................................................................... 496 16.2.1.54 offset c6h: dram_secn_syndrome - dram next single error correct syndrome register ......................................................................... 496 16.2.1.55 offset c8h: dram_secn_add - dram next single bit e rror correct address register ........................................................................................ 497 16.2.1.56 offset dch: rankthrex - rank error threshold exceeded register....... 497 16.2.1.57 offset ech: derrinjctl - dram error injection control register .......... 499 16.3 edma registers: bus 0, device 1, function 0 ..................................................... 501 16.3.1 register details ..................................................................................... 502 16.3.1.1 offset 00h: vid - vendor identification register.................................. 502 16.3.1.2 offset 02h: did - device identification register .................................. 502 16.3.1.3 offset 04h: pcicmd - pci command register ..................................... 503 16.3.1.4 offset 06h: pcists - pci status register ........................................... 504 16.3.1.5 offset 08h: rid - revision identification register ................................ 504 16.3.1.6 offset 0ah: subc - sub-class code register ...................................... 505 16.3.1.7 offset 0bh: bcc - base class code register ....................................... 505 16.3.1.8 offset 0eh: hdr - header type register ............................................ 505 16.3.1.9 offset 10h: edmalbar - edma low base address register .................. 506 16.3.1.10 offset 2ch: svid - subsystem vendor identification register ............... 506 16.3.1.11 offset 2eh: sid - subsystem identification register ............................ 506 16.3.1.12 offset 34h: capptr - capabilities pointer register .............................. 507 16.3.1.13 offset 3ch: intrline - interrupt line register ................................... 507 16.3.1.14 offset 3dh: intrpin - interrupt pin register ...................................... 508 16.3.1.15 offset 40h: edmactl - edma control register ................................... 508 16.3.1.16 offset 80h: edma_ferr - edma first error register ............................ 508 16.3.1.17 offset 84h: edma_nerr - edma next error register ........................... 510 16.3.1.18 offset 88h: edma_emask - edma error mask register ........................ 512 16.3.1.19 offset a0h: edma_scicmd - edma sci command register ................. 514 16.3.1.20 offset a4h: edma_smicmd - edma smi command register................. 515 16.3.1.21 offset a8h: edma_serrcmd - edma serr command register ............ 516 16.3.1.22 offset ach: edma_mcerrcmd - edma mcerr command register........ 517 16.3.1.23 offset b0h: msicr - msi control register .......................................... 518 16.3.1.24 offset b4h: msiar - msi address register ......................................... 519 16.3.1.25 offset b8h: msidr - msi data register ............................................. 520 16.4 pci express* port a standard and enhanced registers: bus 0, devices 2 and 3, function 0 ............................................................................. 521
contents intel ? ep80579 integrated processor product line datasheet august 2009 14 order number: 320066-003us 16.4.1 register details ...................................................................................... 527 16.4.1.1 offset 00h: vid - vendor identification register .................................. 527 16.4.1.2 offset 02h: did - device identification register .................................. 527 16.4.1.3 offset 02h: did - device identification register .................................. 528 16.4.1.4 offset 04h: pcicmd - pci command register ..................................... 528 16.4.1.5 offset 06h: pcists - pci status register ........................................... 530 16.4.1.6 offset 08h: rid - revision identification register ................................ 531 16.4.1.7 offset 0ah: subc - sub-class code register....................................... 532 16.4.1.8 offset 0bh: bcc - base class code register........................................ 532 16.4.1.9 offset 0ch: cls - cache line size register ......................................... 533 16.4.1.10 offset 0eh: hdr - header type register............................................. 533 16.4.1.11 offset 18h: pbusn - primary bus number register .............................. 534 16.4.1.12 offset 19h: sbusn - secondary bus number register .......................... 534 16.4.1.13 offset 1ah: subusn - subordinate bus number register...................... 535 16.4.1.14 offset 1ch: iobase - i/o base address register ................................. 535 16.4.1.15 offset 1dh: iolimit - i/o limit address register ................................ 536 16.4.1.16 offset 1eh: secsts - secondary status register ................................. 536 16.4.1.17 offset 20h: mbase - memory base address register ............................ 538 16.4.1.18 offset 22h: mlimit - memory limit address register ........................... 538 16.4.1.19 offset 24h: pmbase - prefetchable memory base address register ........ 539 16.4.1.20 offset 26h: pmlimit - prefetchable memory limit address register ....... 540 16.4.1.21 offset 28h: pmbasu - prefetchable memory base upper address register.................................................................... 541 16.4.1.22 offset 2ch: pmlmtu - prefetchable memory limit upper address register ............................................................................. 541 16.4.1.23 offset 34h: capptr - capabilities pointer register ............................... 542 16.4.1.24 offset 3ch: intrline - interrupt line register.................................... 542 16.4.1.25 offset 3dh: intrpin - interrupt pin register ...................................... 543 16.4.1.26 offset 3eh: bctrl - bridge control register ....................................... 543 16.4.1.27 offset 44h: vscmd0 - vendor specific command byte 0 register .......... 544 16.4.1.28 offset 45h: vscmd1 - vendor specific command byte 1 register .......... 546 16.4.1.29 offset 46h: vssts0 - vendor specific status byte 0 register ................ 547 16.4.1.30 offset 47h: vssts1 - vendor specific status byte 1 register ................ 547 16.4.1.31 offset 48h: vscmd2 - vendor specific command byte 2 register .......... 548 16.4.1.32 offset 50h: pmcapid - power management capabilities structure register ........................................................................... 548 16.4.1.33 offset 51h: pmnptr - power management next capabilities pointer register 549 16.4.1.34 offset 52h: pmcapa - power management capabilities register ......................................................................................... 549 16.4.1.35 offset 54h: pmcsr - power management status and control register ......................................................................................... 550 16.4.1.36 offset 56h: pmcsrbse - power ma nagement status and control bridge extensions register ......................................................................... 551 16.4.1.37 offset 58h: msicapid - msi capabilities structure register .................. 551 16.4.1.38 offset 59h: msinptr - msi next capabilities pointer register ............... 552 16.4.1.39 offset 5ah: msicapa - msi capabilities register ................................. 552 16.4.1.40 offset 5ch: msiar - msi address for pci express* register.................. 553 16.4.1.41 offset 60h: msidr - msi data register .............................................. 554 16.4.1.42 offset 64h: peacapid - pci express* features capabilities id register ......................................................................................... 555 16.4.1.43 offset 65h: peanptr - pci express* next capabilities pointer register ......................................................................................... 556 16.4.1.44 offset 66h: peacapa - pci express* features capabilities register........ 556 16.4.1.45 offset 68h: peadevcap - pci express* device capabilities register ......................................................................................... 557 16.4.1.46 offset 6ch: peadevctl - pci express* device control register ............ 558 16.4.1.47 offset 6eh: peadevsts - pci express* device status register ............. 560 16.4.1.48 offset 70h: pealnkcap - pci express* link capabilities register .......... 561 16.4.1.49 offset 70h: pea1lnkcap - pci express* link capabilities register......... 561
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 15 contents 16.4.1.50 offset 74h: pealnkctl - pci express* link control register ................ 562 16.4.1.51 offset 76h: pealnksts - pci express* link status register ................. 564 16.4.1.52 offset 78h: peasltcap - pci express* slot capabilities register........... 565 16.4.1.53 offset 78h: pea1sltcap - pci express* slot capabilities register......... 566 16.4.1.54 offset 7ch: peasltctl - pci express* slot control register ................ 568 16.4.1.55 offset 7eh: peasltsts - pci express* slot status register ................. 569 16.4.1.56 offset 80h: pearpctl - pci express* root port control register........... 570 16.4.1.57 offset 84h: pearpsts - pci express* root port status register............ 571 16.4.1.58 offset 100h: enhcapst - enhanced capability structure register ......... 571 16.4.1.59 offset 104h: uncerrsts - uncorrect able error status register ............ 572 16.4.1.60 offset 108h: uncerrmsk - uncorrectable error mask register ............. 574 16.4.1.61 offset 10ch: uncerrsev - uncorrectable error severity register ......... 575 16.4.1.62 offset 110h: corerrsts - correctable error status register ............... 576 16.4.1.63 offset 114h: corerrmsk - correctable error mask register................. 578 16.4.1.64 offset 118h: aercacr - advanced error capabilities and control register.............................................................................. 579 16.4.1.65 offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register.......... 580 16.4.1.66 offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register ......... 580 16.4.1.67 offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register ......... 581 16.4.1.68 offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register.......... 581 16.4.1.69 offset 12ch: rperrcmd - root (port) error command register ............ 582 16.4.1.70 offset 130h: rperrmsts - root (port) error message status register ........................................................................................ 583 16.4.1.71 offset 134h: errsid - error source id register.................................. 585 16.4.1.72 offset 140h: peauniterr - pci express* unit error register................ 585 16.4.1.73 offset 144h: peamaskerr - pci express* unit mask error register ........................................................................................ 588 16.4.1.74 offset 148h: peaerrdocmd - pci express* error do command register ......................................................................... 589 16.4.1.75 offset 14ch: uncedmask - uncorrectable error detect mask register ........................................................................................ 591 16.4.1.76 offset 150h: coredmask - correctable error detect mask register ........................................................................................ 592 16.4.1.77 offset 158h: peaunitedmask - pci express* unit error detect mask register 594 16.4.1.78 offset 160h: peaferr - pci express* first error register .................... 595 16.4.1.79 offset 164h: peanerr - pci express* next error register.................... 597 16.4.1.80 offset 168h: peaerrinjctl - error injection control register .............. 597 16.5 memory mapped i/o registers for dram controller.............................................. 599 16.5.1 detailed register description ................................................................... 601 16.5.1.1 offset 00h: notespad - note (sticky) pad for bios support register ........................................................................................ 601 16.5.1.2 offset 02h: notepad - note pad for bios support register ................. 601 16.5.1.3 offset 40h: dcalcsr ? ddr calibration control and status register ........................................................................................ 602 16.5.1.4 offset 44h: dcaladdr - ddr calibration address register .................. 606 16.5.1.5 offset 48h: dcaldata[0-71] - dram calibration data registers........... 607 16.5.1.6 offset 94h: rcvenac - receiver enable algorithm control register ........................................................................................ 611 16.5.1.7 offset 98h: dsretc - dram self-refresh (sr) extended timing and control 611 16.5.1.8 offset 9ch: dqsfail1 - dqsfail1 configuration register .................... 612 16.5.1.9 offset a0h: dqsfail0 - dqsfail0 configuration register .................... 613 16.5.1.10 drrtc: receive enable reference output timing control registers ....... 614 16.5.1.11 offset a4h: drrtc00 - receive enable reference output timing control register ........................................................................................ 615 16.5.1.12 offset a8h: drrtc01 - receive enable reference output timing control register ........................................................................................ 616 16.5.1.13 offset c4h: drrtc02 - receive enable reference output timing control register ........................................................................................ 616
contents intel ? ep80579 integrated processor product line datasheet august 2009 16 order number: 320066-003us 16.5.1.14 dqs calibration registers................................................................. 616 16.5.1.15 offset b4h: dqsofcs00 - dqs calibration register ............................. 617 16.5.1.16 offset b8h: dqsofcs01 - dqs calibration register ............................. 617 16.5.1.17 offset c6h: dqsofcs02 - dqs calibration register ............................. 618 16.5.1.18 offset bch: dqsofcs10 - dqs calibration register............................. 618 16.5.1.19 offset c0h: dqsofcs11 - dqs calibration register ............................. 619 16.5.1.20 offset c7h: dqsofcs12 - dqs calibration register ............................. 619 16.5.1.21 wptrtc ddr i/o write pointer timing............................................... 620 16.5.1.22 offset cch: wptrtc0 - write pointer timing control 0 register ........... 620 16.5.1.23 offset d0h: wptrtc1 - write pointer timing control 1 register ............ 621 16.5.1.24 ddqscvdp and ddqscadp.............................................................. 621 16.5.1.25 offset d4h: ddqscvdp0 - dqs delay calibration victim pattern 0 register ......................................................................................... 621 16.5.1.26 offset d8h: ddqscvdp1 - dqs delay calibration victim pattern 1 register ......................................................................................... 622 16.5.1.27 offset dch: ddqscadp0 - dqs delay calibration aggressor pattern 0 register ...................................................................................... 622 16.5.1.28 offset e0h: ddqscadp1 - dqs delay calibration aggressor pattern 1 register ...................................................................................... 622 16.5.1.29 offset f0h: diomon - ddr i/o monitor register ................................. 623 16.5.1.30 offset f8h: dramisctl - miscellan eous dram ddr cluster control register 624 16.5.1.31 offset c8h: dramdllc - ddr i/o dll control register ........................ 625 16.5.1.32 offset e8h: fivesreg - fixed 5s pattern register................................ 625 16.5.1.33 offset ech: aaaareg - fixed as pattern register ............................... 626 16.5.1.34 memory bist registers .................................................................... 626 16.5.1.35 offset 140h: mbcsr - membist control register ............................... 626 16.5.1.36 offset 144h: mbaddr - memory test address register ........................ 629 16.5.1.37 offset 148h: mbdata[0:9] - memory test data register ...................... 629 16.5.1.38 offset 19ch: mb_start_addr - memory test start address register ......................................................................................... 631 16.5.1.39 offset 1a0h: mb_end_addr - memory test end address register......... 632 16.5.1.40 offset 1a4h: mblfsrsed - memory test circular shift and lfsr seed register ......................................................................................... 633 16.5.1.41 offset 1a8h: mbfaddrptr - memory test failure address pointer register . 633 16.5.1.42 offset 1b0h: mb_err_data00 - memory test error data 0 ................. 634 16.5.1.43 offset 1b4h: mb_err_data01 - memory test error data 0 ................. 634 16.5.1.44 offset 1b8h: mb_err_data02 - memory test error data 0 ................. 634 16.5.1.45 offset 1bch: mb_err_data03 - memory test error data 0 ................. 635 16.5.1.46 offset 1c0h: mb_err_data04 - memory test error data 0 ................. 635 16.5.1.47 offset 1c4h: mb_err_data10 - memory test error data 1 ................. 635 16.5.1.48 offset 1c8h: mb_err_data11 - memory test error data 1 ................. 636 16.5.1.49 offset 1cch: mb_err_data12 - memory test error data 1 ................. 636 16.5.1.50 offset 1d0h: mb_err_data13 - memory test error data 1 ................. 636 16.5.1.51 offset 1d4h: mb_err_data14 - memory test error data 1 ................. 637 16.5.1.52 offset 1d8h: mb_err_data20 - memory test error data 2 ................. 637 16.5.1.53 offset 1dch: mb_err_data21 - memory test error data 2 ................. 637 16.5.1.54 offset 1e0h: mb_err_data22 - memory test error data 2 ................. 638 16.5.1.55 offset 1e4h: mb_err_data23 - memory test error data 2 ................. 638 16.5.1.56 offset 1e8h: mb_err_data24 - memory test error data 2 ................. 638 16.5.1.57 offset 1ech: mb_err_data30 - memory test error data 3 ................. 639 16.5.1.58 offset 1f0h: mb_err_data31 - memory test error data 3 .................. 639 16.5.1.59 offset 1f4h: mb_err_data32 - memory test error data 3 .................. 639 16.5.1.60 offset 1f8h: mb_err_data33 - memory test error data 3 .................. 640 16.5.1.61 offset 1fch: mb_err_data34 - memory test error data 3 ................. 640 16.5.1.62 offset 260h: ddriomc0 - ddr io mode control register 0................... 640 16.5.1.63 offset 264h: ddriomc1 - ddr io mode control register 1................... 641 16.5.1.64 offset 268h: ddriomc2 - ddr io mode control register 2................... 644 16.5.1.65 offset 284h: wl_cntl[4:0] - write levelization[4:0] control
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 17 contents register ........................................................................................ 646 16.5.1.66 offset 298h: wdll_misc - dll miscellaneous control ......................... 648 16.6 memory mapped i/o for edma registers ............................................................ 651 16.6.1 register details ..................................................................................... 653 16.6.1.1 offset 00h: ccr0 - channel 0 channel control register ...................... 653 16.6.1.2 offset 04h: csr0 - channel 0 channel status register ....................... 656 16.6.1.3 offset 08h: cdar0 - channel 0 current descriptor address register ........................................................................................ 657 16.6.1.4 offset 0ch: cduar0 - channel 0 current descriptor upper address register 658 16.6.1.5 offset 10h: sar0 - channel 0 source address register ....................... 658 16.6.1.6 offset 14h: suar0 - channel 0 source upper address register............. 659 16.6.1.7 offset 18h: dar0 - channel 0 destination address register.................. 659 16.6.1.8 offset 1ch: duar0 - channel 0 destination upper address register ........................................................................................ 660 16.6.1.9 offset 20h: ndar0 - channel 0 next descriptor address register ......... 661 16.6.1.10 offset 24h: nduar0 - channel 0 next descriptor upper address register ............................................................................ 661 16.6.1.11 offset 28h: tcr0 - channel 0 transfer count register ......................... 662 16.6.1.12 offset 2ch: dcr0 - channel 0 descriptor control register .................... 663 16.6.1.13 offset 40h: ccr1 - channel 1 channel control register ....................... 665 16.6.1.14 offset 44h: csr1 - channel 1 channel status register ........................ 665 16.6.1.15 offset 48h: cdar1 - channel 1 current descriptor address register ........................................................................................ 665 16.6.1.16 offset 4ch: cduar1 - channel 1 current descriptor upper address register 666 16.6.1.17 offset 50h: sar1 - channel 1 source address register ....................... 666 16.6.1.18 offset 54h: suar1 - channel 1 source upper address register............. 666 16.6.1.19 offset 58h: dar1 - channel 1 destination address register.................. 667 16.6.1.20 offset 5ch: duar1 - channel 1 destination upper address register ........................................................................................ 667 16.6.1.21 offset 60h: ndar1 - channel 1 next descriptor address register.......... 667 16.6.1.22 offset 64h: nduar1 - channel 1 next descriptor upper address register............................................................................. 668 16.6.1.23 offset 68h: tcr1 - channel 1 transfer count register ......................... 668 16.6.1.24 offset 6ch: dcr1 - channel 1 descriptor control register ................... 668 16.6.1.25 offset 80h: ccr2 - channel 2 channel control register ....................... 669 16.6.1.26 offset 84h: csr2 - channel 2 channel status register ........................ 669 16.6.1.27 offset 88h: cdar2 - channel 2 current descriptor address register ........................................................................................ 669 16.6.1.28 offset 8ch: cduar2 - channel 2 current descriptor upper address register 670 16.6.1.29 offset 90h: sar2 - channel 2 source address register ....................... 670 16.6.1.30 offset 94h: suar2 - channel 2 source upper address register............. 670 16.6.1.31 offset 98h: dar2 - channel 2 destination address register.................. 671 16.6.1.32 offset 9ch: duar2 - channel 2 destination upper address register ........................................................................................ 671 16.6.1.33 offset a0h: ndar2 - channel 2 next descriptor address register ......... 671 16.6.1.34 offset a4h: nduar2 - channel 2 next descriptor upper address register ............................................................................ 672 16.6.1.35 offset a8h: tcr2 - channel 2 transfer count register ......................... 672 16.6.1.36 offset ach: dcr2 - channel 2 descriptor control register.................... 672 16.6.1.37 offset c0h: ccr3 - channel 3 channel control register ...................... 673 16.6.1.38 offset c4h: csr3 - channel 3 channel status register ........................ 673 16.6.1.39 offset c8h: cdar3 - channel 3 current descriptor address register ........................................................................................ 673 16.6.1.40 offset cch: cduar3 - channel 3 current descriptor upper address register 674 16.6.1.41 offset d0h: sar3 - channel 3 source address register........................ 674 16.6.1.42 offset d4h: suar3 - channel 3 source upper address register ............ 674
contents intel ? ep80579 integrated processor product line datasheet august 2009 18 order number: 320066-003us 16.6.1.43 offset d8h: dar3 - channel 3 destination address register.................. 675 16.6.1.44 offset dch: duar3 - channel 3 destination upper address register ......................................................................................... 675 16.6.1.45 offset e0h: ndar3 - channel 3 next descriptor address register .......... 675 16.6.1.46 offset e4h: nduar3 - channel 3 next descriptor upper address register ............................................................................. 676 16.6.1.47 offset e8h: tcr3 - channel 3 transfer count register ......................... 676 16.6.1.48 offset ech: dcr3 - channel 3 descriptor control register .................... 677 16.6.1.49 offset 100h: dcgc - edma controller global command ....................... 677 16.6.1.50 offset 104h: dcgs - edma controller global status............................. 678 16.7 memory mapped i/o for nsi registers ................................................................ 679 16.7.1 register details ...................................................................................... 680 16.7.1.1 offset 00h: nsivcech - nsi virtual channel enhanced capability header register ......................................................................................... 680 16.7.1.2 offset 04h: nsipvccap1 - nsi port vc capability register 1................. 680 16.7.1.3 offset 08h: nsipvccap2 - port vc capability register 2....................... 681 16.7.1.4 offset 0ch: nsipvcctl - nsi port vc control register ......................... 682 16.7.1.5 offset 10h: nsivc0rcap - nsi vc0 resource capability register .......... 682 16.7.1.6 offset 14h: nsivc0rctl - nsi vc0 resource control register .............. 683 16.7.1.7 offset 1ah: nsivc0rsts - nsi vc0 resource status register ............... 684 16.7.1.8 offset 80h: nsircilcech - nsi root complex internal link control enhanced capability header register................................................................ 684 16.7.1.9 offset 84h: nsilcap - nsi link capabilities register............................ 685 integrated i/o controller hub, volume 3 of 6 ............................. 687 17.0 bridging and configuration .................................................................................... 689 17.1 root complex memory-mapped configuration register details ............................... 689 17.1.1 vc configuration registers....................................................................... 691 17.1.1.1 offset 0000h: vch - virtual channel capability header register ............ 691 17.1.1.2 offset 0004h: vcap1 - virtual channel capability 1 register ................. 691 17.1.1.3 offset 0008h: vcap2 - virtual channel capability 2 register ................. 692 17.1.1.4 offset 000ch: pvc - port virtual channel control register .................... 692 17.1.1.5 offset 000eh: pvs - port virtual channel status register...................... 693 17.1.1.6 offset 0010h: v0cap - virtual channel 0 resource capability register ......................................................................................... 693 17.1.1.7 offset 0014h: v0ctl - virtual channel 0 resource control register ....... 694 17.1.1.8 offset 001ah: v0sts - virtual channel 0 resource status register ........ 695 17.1.2 root complex topology capability structure registers................................. 696 17.1.2.1 offset 0100h: rctcl- - root complex topology capabilities list register .... 696 17.1.2.2 offset 0104h: es - element self description register ........................... 696 17.1.2.3 offset 0110h: uld - upstream link description register....................... 697 17.1.2.4 offset 0118h: ulba - upstream link base address register .................. 697 17.1.3 internal link configuration registers ......................................................... 698 17.1.3.1 offset 01a0h: ilcl - internal link capabilities list register .................. 698 17.1.3.2 offset 01a4h: lcap - link capabilities register ................................... 698 17.1.3.3 offset 01a8h: lctl - link control register ......................................... 699 17.1.3.4 offset 01aah: lsts - link status register .......................................... 700 17.1.4 tco configuration .................................................................................. 700 17.1.4.1 offset 3000h: tctl - tco control register ......................................... 700 17.1.5 interrupt configuration registers .............................................................. 701 17.1.5.1 offset 3100h: d31ip - device 31 interrupt pin register ........................ 701 17.1.5.2 offset 3108h: d29ip - device 29 interrupt pin register ........................ 702 17.1.5.3 offset 3140h: d31ir - device 31 interrupt route register .................... 702 17.1.5.4 offset 3144h: d29ir - device 29 interrupt route register .................... 703 17.1.5.5 offset 31ffh: oic - other interrupt control register ........................... 704 17.1.6 general configuration registers................................................................ 704
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 19 contents 17.1.6.1 offset 3400h: rc - rtc configuration register ................................... 704 17.1.6.2 offset 3404h: hptc - high performance precision timer configuration register ........................................................................................ 705 17.1.6.3 offset 3410h: gcs: general control and status register...................... 706 17.1.6.4 offset 3414h: buc - backed up control register................................. 708 17.1.6.5 offset 3418h: fd - function disable register...................................... 709 17.1.6.6 offset 341ch: prc - power reduction control register clock gating ........................................................................................... 711 18.0 system management ............................................................................................. 713 18.1 overview ....................................................................................................... 713 18.2 tco i/o-mapped configuration register details ................................................... 714 18.2.1 tco pci configuration registers .............................................................. 715 18.2.2 bus 0, device 31, function 0: tco configuration register (i/o-mapped via abase bar) summary table ............................................................................. 715 18.2.2.1 offset 00h: trld - tco timer reload and current value register ......... 715 18.2.2.2 offset 02h: tdi - tco data in register.............................................. 715 18.2.2.3 offset 03h: tdo - tco data out register .......................................... 716 18.2.2.4 offset 04h: tsts1 - tco 1 status register ........................................ 716 18.2.2.5 offset 06h: tsts2 - tco 2 sts register ............................................ 718 18.2.2.6 offset 08h: tctl1 - tco 1 control register........................................ 720 18.2.2.7 offset 0ah: tctl2 - tco 2 control register ....................................... 721 18.2.2.8 offset 0ch: tmsg[1-2] - tco message register ................................ 721 18.2.2.9 offset 0eh: twds - tco watchdog status register ............................. 722 18.2.2.10 offset 10h: le - legacy elimination register....................................... 722 18.2.2.11 offset 12h: ttmr - tco timer initial value register ............................ 723 18.3 tco signal usage............................................................................................ 723 18.3.1 intruder# signal ................................................................................. 723 18.3.2 pin straps ............................................................................................. 723 18.3.3 smlink signals ..................................................................................... 723 18.4 tco theory of operation .................................................................................. 723 18.4.1 overview .............................................................................................. 723 18.4.2 detecting a doa cpu or system............................................................... 724 18.4.3 handling an operating system lockup ...................................................... 724 18.4.4 handling a cpu or other hardware lockup ................................................ 725 18.4.5 handling an intruder .............................................................................. 725 18.4.6 handling a potentially failing power supply ............................................... 725 18.4.7 handling an ecc error or other memory error............................................ 726 18.4.8 smm to operating system and operating system to smm calls .................... 726 18.4.9 detecting an improper fwh programming ................................................. 726 18.4.10 irq1 and irq12 for legacy elimination .................................................... 726 18.5 event reporting via smlink/smbus ................................................................... 727 18.5.1 overview .............................................................................................. 727 18.5.1.1 tco compatible mode ..................................................................... 727 18.5.2 message format..................................................................................... 731 18.5.3 connecting an external lan controller ...................................................... 732 19.0 lpc interface: bus 0, device 31, function 0 ........................................................... 733 19.1 overview ....................................................................................................... 733 19.2 lpc interface configuration register details........................................................ 733 19.2.1 pci configuration registers ..................................................................... 734 19.2.1.1 offset 00h: id: vendor identification register .................................... 734 19.2.1.2 offset 04h: cmd: device command register ...................................... 735 19.2.1.3 offset 06h: sts: status register ...................................................... 736 19.2.1.4 offset 08h: rid - revision id register............................................... 736 19.2.1.5 offset 09h: cc: class code register.................................................. 737 19.2.1.6 offset 0dh: mlt: master latency timer register ................................. 737 19.2.1.7 offset 0eh: htype: header type register .......................................... 738
contents intel ? ep80579 integrated processor product line datasheet august 2009 20 order number: 320066-003us 19.2.1.8 offset 2ch: sid: subsystem identifiers register.................................. 738 19.2.2 acpi/gpio configuration registers ........................................................... 738 19.2.2.1 offset 40h: abase: acpi base address register.................................. 738 19.2.2.2 offset 44h: act: acpi control register .............................................. 739 19.2.2.3 offset 48h: gba: gpio base address register..................................... 740 19.2.2.4 offset 4ch: gc: gpio control register ............................................... 741 19.2.3 interrupt configuration registers .............................................................. 741 19.2.3.1 offset 60h: parc: pirqa routing control register .............................. 741 19.2.3.2 offset 61h: pbrc: pirqb routing control register .............................. 742 19.2.3.3 offset 62h: pcrc: pirqc routing control register .............................. 742 19.2.3.4 offset 63h: pdrc: pirqd routing control register .............................. 743 19.2.3.5 offset 64h: scnt: serial irq control register..................................... 744 19.2.3.6 offset 68h: perc: pirqe routing control register............................... 745 19.2.3.7 offset 69h: pfrc: pirqf routing control register ............................... 745 19.2.3.8 offset 6ah: pgrc: pirqg routing control register .............................. 746 19.2.3.9 offset 6bh: phrc: pirqh routing control register .............................. 747 19.2.4 lpc i/o configuration registers................................................................ 747 19.2.4.1 offset 80h: iod: i/o decode ranges register...................................... 747 19.2.4.2 offset 82h: ioe: i/o enables register ................................................ 749 19.2.4.3 offset 84h: lg1: lpc generic decode range 1 register........................ 750 19.2.4.4 offset 88h: lg2: lpc generic decode range 2 register........................ 751 19.2.5 power management configuration registers ............................................... 751 19.2.6 fwh configuration registers .................................................................... 751 19.2.6.1 offset d0h: fs1: fwh id select 1 register ......................................... 751 19.2.6.2 offset d4h: fs2: fwh id select 2 register ......................................... 753 19.2.6.3 offset d8h: fde: fwh decode enable register.................................... 754 19.2.6.4 offset dch: bc: bios control register............................................... 756 19.2.7 root complex register block configuration register .................................... 756 19.2.7.1 offset f0h: rcba: root complex base address register ....................... 756 19.2.8 manufacturing information register .......................................................... 757 19.2.8.1 offset f8h: manid: manufacturer id register ..................................... 757 19.3 interface ........................................................................................................ 757 19.3.1 overview............................................................................................... 758 19.3.2 cycle types ........................................................................................... 758 19.3.3 aborting a cycle ..................................................................................... 759 19.3.4 memory cycle notes ............................................................................... 759 19.3.5 i/o cycle notes ...................................................................................... 760 19.3.6 dma cycle notes .................................................................................... 760 19.3.7 bus master cycle notes ........................................................................... 760 19.3.8 fwh cycle notes .................................................................................... 760 19.3.9 lpc pd# protocol ................................................................................... 760 19.3.10 cycle posting policies .............................................................................. 760 19.3.11 configuration ......................................................................................... 761 19.3.11.1 lpc interface decoders .................................................................... 761 19.3.11.2 bus master device mapping and start fields ..................................... 761 19.3.11.3 firmware memory idsel fields.......................................................... 761 19.3.12 serr# generation ................................................................................. 761 20.0 lpc dma ................................................................................................................ 763 20.1 overview ........................................................................................................ 763 20.2 lpc dma i/o-mapped register details ................................................................ 764 20.2.1 register descriptions .............................................................................. 766 20.2.1.1 offset 00h: dma_bca[0-3] - dma base and current address registers for channels 0-3 .................................................................................. 766 20.2.1.2 offset c4h: dma_bca[5-7] - dma base and current address registers for channels 5-7 .................................................................................. 767
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 21 contents 20.2.1.3 offset 01h: dma_bcc[0-3] - dma base and current count registers for channels 0-3 ................................................................................. 768 20.2.1.4 offset c6h: dma_bcc[5-7] - dma base and current count registers for channels 5-7 ................................................................................. 769 20.2.1.5 offset 08h: dma_command - dma command register........................ 770 20.2.1.6 offset 87h: dma_mpl[0-3] - dma memory low page registers for channels 0-3 ............................................................................................... 771 20.2.1.7 offset 8bh: dma_mpl[5-7] - dma memory low page registers for channels 5-7 ............................................................................................... 771 20.2.1.8 offset 08h: dma_status - dma status register ................................ 772 20.2.1.9 offset 0ah: dma_wsm - dma write single mask register .................... 773 20.2.1.10 offset 0bh: dma_chm - dma channel mode register .......................... 774 20.2.1.11 offset 0ch: dma_cbp - dma clear byte pointer register...................... 775 20.2.1.12 offset 0dh: dma_mc - dma master clear register .............................. 775 20.2.1.13 offset 0eh: dma_cm - dma clear mask register ................................. 776 20.2.1.14 offset 0fh: dma_wam - dma write all mask register .......................... 777 20.3 dma channel arbitration .................................................................................. 778 20.4 special cases in address/count......................................................................... 779 20.4.1 address overrun/underrun ...................................................................... 779 20.4.2 16-bit channels ..................................................................................... 779 20.4.3 autoinitialize ......................................................................................... 779 20.4.4 software commands .............................................................................. 779 20.5 theory of operation for lpc dma....................................................................... 780 20.5.1 asserting dma requests ......................................................................... 780 20.5.2 abandoning dma requests ...................................................................... 780 20.5.3 general flow of dma transfers ................................................................ 781 20.5.4 terminal count ...................................................................................... 781 20.5.5 verify mode ........................................................................................... 782 20.5.6 dma request deassertion ....................................................................... 782 20.5.7 sync field/ldrq# rules......................................................................... 783 21.0 serial peripheral interface .................................................................................... 785 21.1 overview ....................................................................................................... 785 21.1.1 features ............................................................................................... 785 21.2 external interface ........................................................................................... 785 21.3 spi protocol.................................................................................................... 786 21.3.1 spi pin-level protocol ............................................................................. 786 21.3.1.1 addressing..................................................................................... 787 21.3.1.2 data transaction ............................................................................ 787 21.3.1.3 bus errors .................................................................................... 788 21.3.1.4 instructions ................................................................................... 788 21.3.1.5 spi timings ................................................................................... 789 21.4 host side interface.......................................................................................... 789 21.4.1 spi host interface registers .................................................................... 789 21.4.2 register overview .................................................................................. 789 21.4.2.1 offset 3020h: spis ? spi status ....................................................... 790 21.4.2.2 offset 3022h: spic ? spi control...................................................... 791 21.4.2.3 offset 3024h: spia ? spi address ..................................................... 792 21.4.2.4 offset 3028h: spid0 ? spi data 0..................................................... 792 21.4.2.5 spid[0-6] ? spi data n ................................................................... 793 21.4.2.6 offset 3070h: bbar ? bios base address .......................................... 793 21.4.2.7 offset 3074h: preop ? prefix opcode configuration ............................ 794 21.4.2.8 offset 3076h: optype ? opcode type configuration ............................ 794 21.4.2.9 offset 3078h: opmenu ? opcode menu configuration .......................... 795 21.4.2.10 offset 3080h: pbr0 ? protected bios range [0-2] .............................. 796 21.4.3 running spi cycles from the host ............................................................ 797 21.4.3.1 memory reads ............................................................................... 797 21.4.3.2 generic programmed commands ...................................................... 799
contents intel ? ep80579 integrated processor product line datasheet august 2009 22 order number: 320066-003us 21.4.3.3 flash protection .............................................................................. 800 21.4.3.4 decoding memory ranges for spi ...................................................... 801 21.5 bios programming considerations ..................................................................... 801 21.5.1 spi initialization ..................................................................................... 801 22.0 general purpose i/o: bus 0, device 31, function 0 ................................................ 803 22.1 overview ........................................................................................................ 803 22.1.1 gpio summary table.............................................................................. 805 22.2 general purpose i/o-mapped configuration register details .................................. 806 22.2.1 register descriptions .............................................................................. 807 22.2.1.1 offset 00h: gpio_use_sel1 -gpio use select 1 {31:0} register ......................................................................................... 807 22.2.1.2 offset 04h: gp_io_sel1 - gpio input/output select 1 {31:0} register ......................................................................................... 808 22.2.1.3 offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register ......................................................................................... 809 22.2.1.4 offset 18h: gpo_blink - gpio blink enable register ........................... 810 22.2.1.5 offset 2ch: gpi_inv - gpio signal invert register .............................. 812 22.2.1.6 offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register ......................................................................................... 813 22.2.1.7 offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register 813 22.2.1.8 offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register ............................................................... 814 22.3 additional gpio theory of operation .................................................................. 815 22.3.1 smi# and sci routing ............................................................................ 815 22.3.2 triggering.............................................................................................. 815 23.0 sata: bus 0, device 31, function 2 ........................................................................ 817 23.1 sata pci configuration registers ...................................................................... 817 23.1.1 pci header ............................................................................................ 819 23.1.1.1 offset 00h: id - identifiers register ................................................... 819 23.1.1.2 offset 04h: cmd - command register................................................ 819 23.1.1.3 offset 06h: sts - device status register............................................ 820 23.1.1.4 offset 08h: rid - revision id register ............................................... 821 23.1.1.5 pi - programming interface register .................................................. 822 23.1.1.6 offset 0ah: cc - class code register ................................................. 823 23.1.1.7 offset 0dh: mlt ? master latency timer register ................................ 823 23.1.1.8 offset 10h: pcmdba ? primary command block base address register ......................................................................................... 823 23.1.1.9 offset 14h: pctlba ? primary control block base address register........ 824 23.1.1.10 offset 18h: scmdba ? secondary command block base address register ............................................................................. 824 23.1.1.11 offset 1ch: sctlba ? secondary control block base address register ......................................................................................... 825 23.1.1.12 offset 20h: lbar ? legacy bus master base address register ............... 825 23.1.1.13 offset 24h: abar ? ahci base address register.................................. 826 23.1.1.14 offset 2ch: ss - sub system identifiers register................................. 827 23.1.1.15 offset 34h: cap ? capabilities pointer register.................................... 827 23.1.1.16 offset 3ch: intr - interrupt information register ............................... 828 23.1.2 additional sff-8038i configuration registers.............................................. 828 23.1.2.1 offset 40h: ptim ? primary timing register ........................................ 829 23.1.2.2 stim ? secondary timing register .................................................... 830 23.1.2.3 offset 44h: d1tim ? device 1 ide timing register .............................. 830 23.1.2.4 offset 48h: syncc ? synchronous dma control register ...................... 831 23.1.2.5 offset 4ah: synctim ? synchronous dma timing register ................... 832 23.1.2.6 offset 54h: iioc ? ide i/o configuration register ............................... 833 23.1.3 pci power management capabilities .......................................................... 834 23.1.3.1 offset 70h: offset 70h: pid ? pci power management capability id register 834
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 23 contents 23.1.3.2 offset 72h: pc ? pci power management capabilities register .............. 834 23.1.3.3 offset 74h: pmcs ? pci power management control and status register............................................................................... 835 23.1.4 message signaled interrupt capability ...................................................... 836 23.1.4.1 offset 80h: mid ? message signaled interrupt identifiers register ........ 836 23.1.4.2 offset 82h: mc ? message signaled interrupt message control register.............................................................................. 837 23.1.4.3 offset 84h: ma ? message signaled interrupt message address register............................................................................. 838 23.1.4.4 offset 88h: md ? message signaled interrupt message data register ................................................................................. 838 23.1.5 additional configuration registers ............................................................ 838 23.1.5.1 offset 90h: map ? port mapping register ........................................... 839 23.1.5.2 offset 92h: pcs ? port control and status register ............................. 839 23.1.6 serial ata capability registers................................................................. 841 23.1.6.1 offset a8h: satacr0 ? serial ata capability register 0....................... 841 23.1.6.2 offset ach: satacr1 ? serial ata capability register 1 ...................... 841 23.1.7 additional configuration registers ............................................................ 842 23.1.7.1 offset c0h: atc ? apm trapping control register................................ 842 23.1.7.2 offset c4h: ats ? atm trapping status register................................. 843 23.1.7.3 offset d0h: sp ? scratch pad register ............................................... 844 23.1.7.4 offset e0h: bfcs ? bist fis control/status register........................... 844 23.1.7.5 offset e4h: bftd1 ? bist fis transmit data 1 register....................... 846 23.1.7.6 offset e8h: bftd2 ? bist fis transmit data 2 register....................... 846 23.1.7.7 offset f8h: manid ? manufacturing id register .................................. 847 23.2 sata i/o mapped registers .............................................................................. 847 23.2.1 primary devices ..................................................................................... 848 23.2.1.1 offset 00h: pcmd ? primary command register ................................. 848 23.2.1.2 offset 02h: psts ? primary status register........................................ 849 23.2.1.3 offset 04h: pdtp ? primary descriptor table pointer register ............... 849 23.2.2 secondary devices ................................................................................. 850 23.2.2.1 offset 08h: scmd ? secondary command register ............................. 850 23.2.2.2 offset 0ah: ssts ? secondary status register ................................... 850 23.2.2.3 offset 0ch: sdtp ? secondary descriptor table pointer register ........... 850 23.2.3 ahci index and data registers ................................................................ 850 23.2.3.1 offset 10h: index ? ahci index register .......................................... 850 23.2.3.2 offset 14h: data ? ahci data register ............................................. 851 23.3 sata memory mapped registers ....................................................................... 851 23.3.1 generic host controller ........................................................................... 852 23.3.1.1 offset 00h: hcap ? hba capabilities register ..................................... 853 23.3.1.2 offset 04h: ghc ? global hba control register................................... 855 23.3.1.3 offset 08h: is ? interrupt status register .......................................... 856 23.3.1.4 offset 0ch: pi ? ports implemented register ...................................... 856 23.3.1.5 offset 10h: vs ? ahci version register ............................................. 857 23.3.2 vendor specific registers ........................................................................ 857 23.3.2.1 offset a0h: sgpo - spgio control register........................................ 857 23.3.3 port dma registers................................................................................. 858 23.3.3.1 offset 100h: pxclb[0-1] ? port [0-1] command list base address register.. 858 23.3.3.2 offset 104h: pxclbu[0-1] ? port [0-1] command list base address upper 32- bits register................................................................................... 858 23.3.3.3 offset 108h: pxfb[0-1] ? port [0-1] fis base address register............. 859 23.3.3.4 offset 10ch: pxfbu[0-1] ? port [0-1] fis base address upper 32-bits register ........................................................................................ 859 23.3.3.5 offset 110h: pxis[0-1] ? port [0-1] interrupt status register ............... 860 23.3.3.6 offset 114h: pxie[0-1] ? port [0-1] interrupt enable register............... 861 23.3.3.7 offset 118h: pxcmd[0-1] ? port [0-1] command register.................... 863 23.3.4 port interface registers (one set per port) ................................................ 866
contents intel ? ep80579 integrated processor product line datasheet august 2009 24 order number: 320066-003us 23.3.4.1 offset 120h: pxtfd[0-1] ? port [0-1] task file data register................ 866 23.3.4.2 offset 124h: pxsig[0-1] ? port [0-1] signature register ...................... 867 23.3.4.3 offset 128h: pxssts[0-1] ? port [0-1] serial ata status register ......... 868 23.3.4.4 offset 12ch: pxsctl[0-1] ? port [0-1] serial ata control register ........ 869 23.3.4.5 offset 130h: pxserr[0-1] ? port [0-1] serial ata error register ........... 870 23.3.4.6 offset 134h: pxsact[0-1] ? port [0-1] serial ata active register.......... 872 23.3.4.7 offset 138h: pxci[0-1] ? port [0-1] command issue register ............... 872 23.3.4.8 offset 13ch: pxsntf[0-1] ? port [0-1] snotification register................ 873 23.4 overview ........................................................................................................ 873 23.5 legacy operation............................................................................................. 873 23.5.1 transfer examples .................................................................................. 873 23.5.1.1 register fis only ............................................................................ 873 23.5.1.2 non-queued dma data transfers ...................................................... 874 23.5.1.3 sw assisted queued dma transfer .................................................... 875 23.5.2 error handling........................................................................................ 876 23.5.2.1 errors on dmi ................................................................................. 876 23.5.2.2 errors on sata interface .................................................................. 876 23.5.3 hot plug operation ................................................................................. 878 23.5.4 48-bit (?large?) lba operation requirements............................................. 878 23.5.5 power management operation .................................................................. 879 23.5.5.1 introduction ................................................................................... 879 23.5.5.2 power state mappings...................................................................... 879 23.5.5.3 power state transitions ................................................................... 880 23.5.5.4 smi trapping (apm) ........................................................................ 881 23.5.6 interrupt architecture ............................................................................. 882 23.5.7 staggered spin-up.................................................................................. 882 23.5.8 hw/sw operation for detecting an sata device presence ........................... 882 23.5.8.1 introduction ................................................................................... 882 23.5.8.2 hardware flow................................................................................ 882 23.5.8.3 software flow................................................................................. 883 23.5.9 smi generation ...................................................................................... 883 23.5.10 led ...................................................................................................... 884 23.6 ahci operation ............................................................................................... 884 23.6.1 system memory structures ...................................................................... 884 23.6.2 error reporting and recovery................................................................... 885 23.6.2.1 error types .................................................................................... 885 23.6.2.2 error recovery................................................................................ 888 23.6.3 hot plug operation ................................................................................. 888 23.6.4 power management operation .................................................................. 889 23.6.4.1 introduction ................................................................................... 889 23.6.4.2 power state mappings...................................................................... 889 23.6.4.3 power state transitions ................................................................... 890 23.6.4.4 pme............................................................................................... 892 23.7 additional information ...................................................................................... 892 23.7.1 mode switching ...................................................................................... 892 23.7.1.1 ahci mode ..................................................................................... 893 23.7.1.2 ide mode ....................................................................................... 893 24.0 smbus controller functional description: bus 0, device 31, function 3 ................. 895 24.1 overview ........................................................................................................ 895 24.1.1 host controller ....................................................................................... 895 24.1.2 slave interface....................................................................................... 896 24.2 smbus controller pci configuration register details ............................................. 896 24.2.1 smbus controller pci configuration register descriptions ............................ 897 24.2.1.1 offset 00h: vid: vendor id register .................................................. 897 24.2.1.2 offset 02h: did: device id register .................................................. 897 24.2.1.3 offset 04h: cmd: command register................................................. 897
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 25 contents 24.2.1.4 offset 06h: ds ? device status register ............................................ 898 24.2.1.5 offset 08h: rid: revision id register................................................ 899 24.2.1.6 offset 09h: pi: programming interface register .................................. 900 24.2.1.7 offset 0ah: scc: sub class code register ......................................... 900 24.2.1.8 offset 0bh: bcc: base class code register ........................................ 900 24.2.1.9 offset 20h: sm_base: smb base address register.............................. 901 24.2.1.10 offset 2ch: svid: svid register ...................................................... 901 24.2.1.11 offset 2eh: sid: subsystem identification register ............................. 902 24.2.1.12 offset 3ch: intln: interrupt line register ......................................... 902 24.2.1.13 offset 3dh: ntpn: interrupt pin register ........................................... 903 24.2.1.14 offset 40h: hcfg: host configuration register ................................... 903 24.2.1.15 offset f8h: manid: manufacturer id register..................................... 904 24.3 smbus controller i/o-mapped configuration register details ................................. 905 24.3.1 smbus controller i/o-mapped configuration register descriptions ................ 906 24.3.1.1 offset 00h: hsts: host status register ............................................. 906 24.3.1.2 offset 02h: hctl: host control register ............................................ 908 24.3.1.3 offset 03h: hcmd: host command register ....................................... 912 24.3.1.4 offset 04h: tsa: transmit slave address register............................... 912 24.3.1.5 offset 05h: hd0: data 0 register ..................................................... 913 24.3.1.6 offset 06h: hd1: data 1 register ..................................................... 913 24.3.1.7 offset 07h: hbd: host block data register......................................... 914 24.3.1.8 offset 08h: pec: packet error check data register.............................. 915 24.3.1.9 offset 0ch: auxs: auxiliary status register ....................................... 915 24.3.1.10 offset 0dh: auxc: auxiliary control register...................................... 916 24.3.1.11 offset 0eh: smlc: smlink_pin_ctl register..................................... 916 24.3.1.12 offset 0fh: smbc: smbus_pin_ctl register ..................................... 917 24.4 host controller................................................................................................ 918 24.4.1 overview .............................................................................................. 918 24.4.2 command protocols................................................................................ 918 24.4.2.1 quick command ............................................................................. 918 24.4.2.2 send byte/receive byte................................................................... 919 24.4.2.3 write byte/word............................................................................. 920 24.4.2.4 read byte/word ............................................................................. 921 24.4.2.5 process call ................................................................................... 922 24.4.2.6 block read/write ............................................................................ 923 24.4.2.7 i2c read ...................................................................................... 925 24.4.2.8 block write-block read process call .................................................. 926 24.4.3 i2c behavior ......................................................................................... 928 24.4.4 heartbeat for use with external lan ......................................................... 928 24.5 bus arbitration................................................................................................ 928 24.6 bus timings.................................................................................................... 928 24.6.1 clock stretching..................................................................................... 928 24.6.2 bus time out (cmi as smb master) ......................................................... 929 24.7 interrupts/smi#.............................................................................................. 929 24.8 crc generation and checking ........................................................................... 930 24.8.1 slave interface i/o space ....................................................................... 930 24.8.2 register details ..................................................................................... 931 24.8.2.1 offset 09h: rsa: receive slave address register ................................ 931 24.8.2.2 offset 0ah: sd: slave data register ................................................. 931 24.8.2.3 offset 10h: ssts: slave status register ............................................ 932 24.8.2.4 offset 11h: scmd: slave command register ...................................... 932 24.8.2.5 offset 14h: nda: notify device address register ................................ 933 24.8.2.6 offset 16h: ndlb: notify data low byte register ................................ 934 24.8.2.7 offset 17h: ndhb: notify data high byte register .............................. 934 24.9 slave interface behavioral description ............................................................... 935 24.9.1 format of slave write cycle..................................................................... 935 24.9.2 format of read command ....................................................................... 936 24.9.3 format of the host notify command ......................................................... 938
contents intel ? ep80579 integrated processor product line datasheet august 2009 26 order number: 320066-003us 25.0 usb (1.1) controller: bus 0, device 29, function 0 ................................................. 941 25.1 usb (1.1) controller configuration register details .............................................. 941 25.1.1 register details ...................................................................................... 942 25.1.1.1 id - identifiers register ................................................................... 942 25.1.1.2 pcicmd - command register............................................................ 942 25.1.1.3 pcists - device status register........................................................ 943 25.1.1.4 rid - revision id register ................................................................ 944 25.1.1.5 subc - sub class code register........................................................ 945 25.1.1.6 bcc - base class code register ........................................................ 945 25.1.1.7 mlt - master latency timer register ................................................. 945 25.1.1.8 hdr - header type register ............................................................. 946 25.1.1.9 usbiobar - base address register ................................................... 946 25.1.1.10 usbx_svid - usb subsystem vendor id register................................ 947 25.1.1.11 usbx_sid - usb subsystem id register ............................................ 947 25.1.1.12 intl - interrupt line register ........................................................... 948 25.1.1.13 intp - interrupt pin register............................................................. 948 25.1.1.14 sbrn - serial bus release number register........................................ 948 25.1.1.15 usblkmcr - usb legacy keyboard/mouse control register .................. 949 25.1.1.16 usbren - usb resume enable register ............................................. 951 25.1.1.17 usbcwp - usb core well policy register ............................................ 951 25.1.1.18 manid - manufacturer id register..................................................... 952 25.2 usb (1.1) controller i/o-mapped register details ................................................ 953 25.2.1 register details ...................................................................................... 953 25.2.1.1 usbcmd: usb command register ..................................................... 953 25.2.1.2 usbsts: usb status register ........................................................... 957 25.2.1.3 usbintr: usb interrupt enable register............................................ 958 25.2.1.4 frnum: frame number register ....................................................... 959 25.2.1.5 frbaseadd: frame list base address register................................... 960 25.2.1.6 sofmod: start of frame modify register ........................................... 960 25.2.1.7 pscr - port status and control register ............................................. 962 25.3 data transfers to/from main memory ................................................................. 964 25.4 data structures in main memory ........................................................................ 964 25.5 data transfers to/from main memory ................................................................ 964 25.5.1 executing the schedule ........................................................................... 965 25.5.2 processing transfer descriptors ................................................................ 965 25.5.3 command register, status register, and td status bit interaction................ 966 25.5.4 transfer queuing.................................................................................... 966 25.6 usb buffer management ................................................................................... 969 25.7 data encoding and bit stuffing .......................................................................... 970 25.8 bus protocol.................................................................................................... 970 25.8.1 bit ordering ........................................................................................... 970 25.8.2 sync field............................................................................................. 970 25.8.3 packet field formats ............................................................................... 970 25.8.3.1 packet identifier field ...................................................................... 971 25.8.4 address fields ........................................................................................ 971 25.8.4.1 address field .................................................................................. 971 25.8.4.2 endpoint field................................................................................. 971 25.8.5 frame number field................................................................................ 971 25.8.6 data field.............................................................................................. 971 25.8.7 cyclic redundancy check (crc) ............................................................... 972 25.9 packet formats ............................................................................................... 972 25.10 usb interrupts ................................................................................................ 972 25.10.1 overview............................................................................................... 972 25.10.2 transaction-based interrupts ................................................................... 972 25.10.2.1 crc error/time-out ......................................................................... 972 25.10.2.2 interrupt on completion ................................................................... 973 25.10.2.3 short packet detect......................................................................... 973
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 27 contents 25.10.2.4 serial bus babble............................................................................ 973 25.10.2.5 stalled .......................................................................................... 973 25.10.2.6 data buffer error ............................................................................ 973 25.10.2.7 bit stuff error................................................................................. 974 25.10.3 non-transaction based interrupts ............................................................ 974 25.10.3.1 resume received ........................................................................... 974 25.10.3.2 process error ................................................................................. 974 25.10.3.3 host system error .......................................................................... 974 25.10.3.4 implementation notes ..................................................................... 974 25.11 usb power management .................................................................................. 974 25.12 usb legacy keyboard operation ....................................................................... 975 26.0 usb 2.0 host controller: bus 0, device 29, function 7 .......................................... 977 26.1 overview ....................................................................................................... 977 26.2 usb 2.0 pci configuration registers .................................................................. 978 26.2.1 register details ..................................................................................... 979 26.2.1.1 offset 00h: vid - vendor id register ................................................ 979 26.2.1.2 offset 02h: did - device identification register .................................. 979 26.2.1.3 offset 04h: cmd - command register ............................................... 980 26.2.1.4 offset 06h: dsr - device status register........................................... 981 26.2.1.5 offset 08h: rid - revision id register............................................... 983 26.2.1.6 offset 09h: pi - programming interface register ................................. 983 26.2.1.7 offset 0ah: scc - sub class code register ........................................ 983 26.2.1.8 offset 0bh: bcc - base class code register ....................................... 984 26.2.1.9 offset 0dh: mlt - master latency timer register ................................ 984 26.2.1.10 offset 10h: mbar - memory base address register ............................. 985 26.2.1.11 offset 2ch: ssvid - usb 2.0 subsystem vendor id register ................ 985 26.2.1.12 offset 2eh: ssid - usb 2.0 subsystem id register ............................ 986 26.2.1.13 offset 34h: cap_ptr - capabilities pointer register ............................ 986 26.2.1.14 offset 3ch: iline - interrupt line register......................................... 987 26.2.1.15 offset 3dh: ipin - interrupt pin register............................................ 987 26.2.1.16 offset 50h: pm_cid - pci power management capability id register ........................................................................................ 987 26.2.1.17 offset 51h: pm_next - next item pointer #1 register ........................ 988 26.2.1.18 offset 52h: pm_cap - power management capabilities register............. 989 26.2.1.19 offset 54h: pm_cs - power management control/status register .......... 990 26.2.1.20 offset 58h: dp_cid - debug port capability id register ...................... 991 26.2.1.21 offset 59h: dp_next - next item pointer #2 register ........................ 991 26.2.1.22 offset 5ah: dp_base - debug port base offset register ...................... 991 26.2.1.23 offset 60h: sbrn - serial bus release number register ...................... 992 26.2.1.24 offset 61h: fla - frame length adjustment register........................... 992 26.2.1.25 offset 62h: pwc - port wake capability register................................. 993 26.2.1.26 offset 64h: cuo - classic usb override register................................. 993 26.2.1.27 offset 68h: ulsec - usb 2.0 legacy support extended capability register .......................................................................... 994 26.2.1.28 offset 6ch: ulscs - usb 2.0 legacy support control/status register ........................................................................................ 995 26.2.1.29 offset 70h: isu2smi - intel specific usb 2.0 smi register ................... 997 26.2.1.30 offset 80h: ac - access control register............................................ 999 26.2.1.31 offset f8h: manid - manufacturer id register...................................1000 26.3 usb 2.0 memory-mapped i/o registers.............................................................1001 26.3.1 host controller capability register details ................................................1002 26.3.1.1 offset 00h: caplength - capability length register ..........................1002 26.3.1.2 offset 02h: hciversion - host controller interface version number register 1003 26.3.1.3 offset 04h: hcsparams - host controller structural parameters register .... 1003 26.3.1.4 offset 08h: hccparams - host cont roller capability parameters register .... 1004
contents intel ? ep80579 integrated processor product line datasheet august 2009 28 order number: 320066-003us 26.3.2 host controller operational register details ............................................. 1005 26.3.2.1 offset 20h: usb2cmd - usb 2.0 command register .......................... 1007 26.3.2.2 offset 24h: usb2sts - usb 2.0 status register ................................ 1009 26.3.2.3 offset 28h: usb2intr - usb 2.0 interrupt enable register ................. 1011 26.3.2.4 offset 2ch: frindex - frame index register .................................... 1013 26.3.2.5 offset 30h: ctrldssegment - control data structure segment register.......................................................................... 1013 26.3.2.6 offset 34h: periodiclistbase - periodic frame list base address register 1014 26.3.2.7 offset 38h: asynclistaddr - current asynchronous list address register . 1015 26.3.2.8 offset 60h: configflag - configure flag register ............................ 1015 26.3.2.9 offset 64h: portsc - port n status and control register ................... 1016 26.4 ehc initialization ........................................................................................... 1021 26.4.1 power on ............................................................................................ 1021 26.4.2 driver initialization ............................................................................... 1021 26.4.3 ehc resets .......................................................................................... 1021 26.5 data structures in main memory ...................................................................... 1022 26.6 usb 2.0 enhanced host controller dma ............................................................ 1022 26.6.1 periodic list execution........................................................................... 1022 26.6.1.1 read policies for periodic dma ........................................................ 1022 26.6.1.2 write policies for periodic dma ........................................................ 1024 26.6.2 asynchronous list execution .................................................................. 1025 26.6.2.1 read policies for asynchronous dma ................................................ 1025 26.6.2.2 write policies for asynchronous dma................................................ 1027 26.7 data encoding and bit stuffing ........................................................................ 1027 26.8 packet formats ............................................................................................. 1027 26.9 usb 2.0 interrupts and error conditions ........................................................... 1027 26.9.1 aborts on usb 2.0-initiated memory reads .............................................. 1028 26.9.2 host interface parity errors ................................................................... 1028 26.10 usb 2.0 power management ........................................................................... 1030 26.10.1 pause feature ...................................................................................... 1030 26.10.2 suspend feature .................................................................................. 1031 26.10.3 acpi device states ............................................................................... 1031 26.10.4 acpi system states .............................................................................. 1032 26.11 interaction with classic host controllers ........................................................... 1032 26.11.1 port-routing logic ................................................................................ 1033 26.11.2 device connects ................................................................................... 1033 26.11.3 device disconnects ............................................................................... 1034 26.11.4 effect of resets on port-routing logic ..................................................... 1034 26.12 usb 2.0 legacy keyboard operation ................................................................ 1035 26.13 usb 2.0 based debug port .............................................................................. 1035 26.13.1 usb 2.0 based debug port overview ....................................................... 1035 26.13.2 debug port register details ................................................................... 1036 26.13.2.1 offset a0h: cntl_sts - control/status register ............................... 1036 26.13.2.2 offset a4h: usbpid - usb pids register .......................................... 1039 26.13.2.3 offset a8h: databuf - data buffer bytes 7:0 ................................... 1039 26.13.2.4 offset b0h: config - configuration register .................................... 1040 26.13.3 usb 2.0 based debug port theory of operation ........................................ 1040 26.13.3.1 behavioral rules ........................................................................... 1040 26.13.3.2 out transactions .......................................................................... 1041 26.13.3.3 in transactions............................................................................. 1042 26.13.3.4 debug software ............................................................................ 1043 27.0 power management ............................................................................................. 1045 27.1 features ....................................................................................................... 1045 27.2 imch-iich messages...................................................................................... 1046
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 29 contents 27.3 power management register details .................................................................1047 27.3.1 power management pci configuration registers ........................................1047 27.3.1.1 offset a0h: gen_pmcon_1 - general pm configuration 1 register .......................................................................................1047 27.3.1.2 offset a2h: gen_pmcon_2 - general pm configuration 2 register .......................................................................................1049 27.3.1.3 offset a4h: gen_pmcon_3 - general pm configuration 3 register .......................................................................................1051 27.3.1.4 offset b8h: gpi_rout - gpi routing control register.........................1053 27.3.2 apm power management i/o-mapped registers .........................................1053 27.3.2.1 offset b2h: apm_cnt - advanced power management control .port register 1054 27.3.2.2 offset b3h: apm_sts - advanced power management status ..port register 1054 27.3.3 general power management i/o-mapped registers ....................................1055 27.3.3.1 offset 00h: pm1_sts ? power management 1 status register..............1056 27.3.3.2 offset 02h: pm1_en - power management 1 enables register ..............1058 27.3.3.3 offset 04h: pm1_cnt - power management 1 control register.............1059 27.3.3.4 offset 08h: pm1_tmr - power management 1 timer register ..............1060 27.3.3.5 offset 10h: proc_cnt - processor control register ...........................1060 27.3.3.6 offset 14h: lv2 - level 2 register....................................................1063 27.3.3.7 offset 28h: gpe0_sts - general purpose event 0 status register ........1063 27.3.3.8 offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register ................................................................1066 27.3.3.9 offset 30h: smi_en - smi control and enable register .......................1068 27.3.3.10 offset 34h: smi_sts - smi status register .......................................1070 27.3.3.11 offset 38h: alt_gpi_smi_en - alternate gpi smi enable register .......................................................................................1073 27.3.3.12 offset 3ah: alt_gpi_smi_sts - alternate gpi smi status register .......................................................................................1074 27.3.3.13 offset 44h: devtrap_sts - devtrap_sts register...........................1074 27.4 smi#/sci generation .....................................................................................1076 27.4.0.1 pci express* sci...........................................................................1078 27.5 dynamic processor clock control ......................................................................1079 27.5.1 overview .............................................................................................1079 27.5.2 transition rules among s0/cx and sx states............................................1080 27.5.3 s0/c0, s0/c2, entry/exit timings and sequences......................................1081 27.5.3.1 c0 c2 c0 timings and diagram ....................................................1081 27.5.3.2 c0 c2 entry sequence ..................................................................1082 27.5.3.3 c2 c0 break sequence .................................................................1083 27.6 sleep states ..................................................................................................1083 27.6.1 sleep state overview ............................................................................1083 27.6.2 initiating sleep states ...........................................................................1083 27.6.3 exiting sleep states ..............................................................................1084 27.6.4 sx-g3-sx, handling power failures..........................................................1085 27.7 processor thermal management .......................................................................1086 27.7.1 prochot# signal for smi# or sci ..........................................................1086 27.7.2 processor passive cooling.......................................................................1087 27.7.3 on-demand passive cooling ...................................................................1087 27.7.4 active cooling.......................................................................................1087 27.8 event input signals, messages and their usage..................................................1087 27.8.1 pwrbtn# ? power button ......................................................................1087 27.8.1.1 power button override function.......................................................1088 27.8.1.2 sleep button .................................................................................1088 27.8.2 ri# ? ring indicate signal .....................................................................1089 27.8.3 pme# ? pci power management event .....................................................1089 27.8.4 sys_reset# button..............................................................................1089
contents intel ? ep80579 integrated processor product line datasheet august 2009 30 order number: 320066-003us 27.8.5 processor thermal trip.......................................................................... 1089 27.8.6 sata sci ............................................................................................ 1090 27.8.7 pci express* pme event message ........................................................... 1090 27.9 alternate (alt) access mode ........................................................................... 1091 27.9.1 write only registers with read paths in alternate access mode .................. 1091 27.9.2 pic reserved bits ................................................................................. 1093 27.9.3 read-only registers with write paths in alt access mode .......................... 1094 27.10 system power supplies, planes, and signals...................................................... 1094 27.10.1 power plane control with slp_s3#, slp_s4# and slp_s5# ....................... 1094 27.10.2 slp_s4# and suspend-to-ram sequencing ............................................. 1094 27.10.3 pwrok signal ...................................................................................... 1095 27.10.4 cpupwrgd signal ................................................................................ 1095 27.10.5 controlling leakage and power consumption during low-power states........ 1095 27.10.6 vrmpwrok ......................................................................................... 1096 27.11 legacy power management theory of operation ................................................ 1096 27.11.1 overview............................................................................................. 1096 27.11.2 apm power management........................................................................ 1096 28.0 ia-32 core interface ............................................................................................ 1097 28.1 ia-32 core interface i/o-mapped register details .............................................. 1097 28.1.1 register descriptions ............................................................................ 1098 28.1.1.1 offset 61h: nmi_sc - nmi status and control register....................... 1098 28.1.1.2 offset 70h: nmi_en - nmi enable (and real time clock index) register ....................................................................................... 1099 28.1.1.3 offset 92h: port92 - fast a20 and init register ............................... 1100 28.1.1.4 offset f0h: coproc_err - coprocessor error register ...................... 1100 28.1.1.5 offset cf9h: rst_cnt - reset control register ................................. 1101 28.2 ia-32 core interface signals .......................................................................... 1102 28.2.1 a20m# (mask a20) ............................................................................... 1102 28.2.2 init# (initialization) ............................................................................. 1102 28.2.3 intr# (interrupt signals)...................................................................... 1103 28.2.4 stpclk# and cpuslp# (stop clock request and processor sleep signals) ... 1103 28.2.5 enhanced intel speedstep technology (eist) signals................................ 1103 28.2.6 dpslp# (deeper sleep)......................................................................... 1103 29.0 real time clock ................................................................................................... 1105 29.1 overview ...................................................................................................... 1105 29.2 rtc i/o registers .......................................................................................... 1105 29.3 real time clock indexed register details .......................................................... 1106 29.3.1 real time clock register details ............................................................. 1107 29.3.1.1 offset 0ah: rtc_rega - register a (general configuration) ............... 1107 29.3.1.2 offset 0bh: rtc_regb - register b (general configuration) ............... 1109 29.3.1.3 offset 0ch: rtc_regc - register c (flag register)............................ 1110 29.3.1.4 offset 0dh: rtc_regd - register d (flag register) ........................... 1111 29.4 update cycles ............................................................................................... 1112 29.5 interrupts ..................................................................................................... 1112 29.6 lockable ram ranges..................................................................................... 1112 29.7 century rollover............................................................................................ 1112 29.8 month and year alarms .................................................................................. 1113 30.0 interrupts ............................................................................................................ 1115 30.1 overview ...................................................................................................... 1115 30.2 8259 interrupt controllers (pic) ...................................................................... 1117 30.2.1 overview............................................................................................. 1117 30.2.2 i/o registers ....................................................................................... 1118 30.2.2.1 icw1[0-1] - initialization command word 1 register ......................... 1119 30.2.2.2 icw2[0-1] - initialization command word 2 register ......................... 1120
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 31 contents 30.2.2.3 micw3 - master initialization command word 3 register ....................1121 30.2.2.4 sicw3 - slave initialization command word 3 register ......................1121 30.2.2.5 icw4[0-1] - initialization command word 4 register..........................1122 30.2.2.6 ocw1[0-1] - operational control word 1 (interrupt mask) register .......................................................................................1122 30.2.2.7 ocw2[0-1] - operational control word 2 register..............................1123 30.2.2.8 ocw3[0-1] - operational control word 3 register..............................1124 30.2.2.9 elcr1 - master edge/level control register ......................................1125 30.2.2.10 elcr2 - slave edge/level control register ........................................1126 30.2.3 interrupt handling.................................................................................1127 30.2.3.1 generating interrupts.....................................................................1127 30.2.3.2 acknowledging interrupts ...............................................................1127 30.2.3.3 hardware/software interrupt sequence ............................................1127 30.2.4 initialization command words (icw) .......................................................1128 30.2.4.1 icw1 ...........................................................................................1128 30.2.4.2 icw2 ...........................................................................................1128 30.2.4.3 icw3 ...........................................................................................1128 30.2.4.4 icw4 ...........................................................................................1129 30.2.5 operation command words (ocw)..........................................................1129 30.2.6 modes of operation ...............................................................................1129 30.2.6.1 fully nested mode..........................................................................1129 30.2.6.2 special fully nested mode ...............................................................1129 30.2.6.3 automatic rotation mode (equal priority devices)...............................1130 30.2.6.4 specific rotation mode (specific priority)...........................................1130 30.2.6.5 poll mode......................................................................................1130 30.2.6.6 edge and level triggered mode .......................................................1130 30.2.7 end of interrupt (eoi) operations ............................................................1131 30.2.7.1 normal eoi ...................................................................................1131 30.2.7.2 automatic eoi mode.......................................................................1131 30.2.8 masking interrupts ................................................................................1131 30.2.8.1 masking on an individual interrupt request.......................................1131 30.2.8.2 special mask mode.........................................................................1131 30.2.9 steering of pci interrupts ......................................................................1131 30.3 advanced interrupt controller: apic .................................................................1132 30.3.1 interrupt handling.................................................................................1132 30.3.2 pci/pci express* message-based interrupts.............................................1132 30.3.2.1 front side bus interrupt delivery .....................................................1133 30.3.2.2 edge-triggered operation ...............................................................1133 30.3.2.3 level-triggered operation...............................................................1133 30.3.2.4 registers associated with front-side bus interrupt delivery ................1133 30.3.2.5 eoi ..............................................................................................1133 30.3.2.6 interrupt message format ..............................................................1133 30.3.3 apic memory-mapped register details .....................................................1135 30.3.3.1 apic_idx - index register ..............................................................1135 30.3.3.2 apic_dat ? data register .............................................................1136 30.3.3.3 apic_eoi - eoi register .................................................................1136 30.3.4 index registers.....................................................................................1137 30.3.4.1 apic_id ? identification register .....................................................1138 30.3.4.2 apic_vs - version register .............................................................1138 30.3.4.3 apic_rte[0-39] - redirection table entry.........................................1139 30.4 pci interrupts via /pci express* ......................................................................1142 30.5 serial interrupt ..............................................................................................1142 30.5.1 overview .............................................................................................1142 30.5.2 start frame..........................................................................................1142 30.5.3 data frames.........................................................................................1143 30.5.4 stop frame ..........................................................................................1143 30.5.5 serial interrupts not supported via serirq..............................................1143
contents intel ? ep80579 integrated processor product line datasheet august 2009 32 order number: 320066-003us 30.5.6 special notes on irq14 and irq15 ......................................................... 1144 30.5.7 data frame format............................................................................... 1144 31.0 8254 timers ......................................................................................................... 1145 31.1 overview ...................................................................................................... 1145 31.2 8254 timer i/o-mapped register details........................................................... 1145 31.2.1 timer registers .................................................................................... 1146 31.2.1.1 offset 43h: tcw - timer control word register................................. 1146 31.2.1.2 offset 40h: tsb[0-2] - interval timer status byte format register ....................................................................................... 1146 31.2.1.3 offset 40h: tcap[0-2] - interval timer counter access ports register ....................................................................................... 1148 31.3 counters ...................................................................................................... 1148 31.3.1 counter 0, system timer....................................................................... 1148 31.3.2 counter 1, refresh request signal .......................................................... 1148 31.3.3 counter 2, speaker tone ....................................................................... 1148 31.3.4 counter operating modes ...................................................................... 1149 31.4 timer programming ....................................................................................... 1149 31.5 reading from the interval timer ...................................................................... 1150 31.5.1 simple read ........................................................................................ 1150 31.5.2 counter latch command ....................................................................... 1150 31.5.3 read back command ............................................................................ 1151 32.0 high precision event timers ................................................................................. 1153 32.1 overview ...................................................................................................... 1153 32.2 register details ............................................................................................. 1153 32.2.1 register descriptions ............................................................................ 1155 32.2.1.1 offset 000h: gcap_id - general capabilities and id register .............. 1155 32.2.1.2 offset 010h: gen_conf - general configuration register................... 1156 32.2.1.3 offset 020h: gintr_sta - general interrupt status register .............. 1157 32.2.1.4 offset 0f0h: main_cnt - main counter value register....................... 1158 32.2.1.5 offset 100h: hptcc[0-2] - timer n configuration and capabilities register ...................................................................... 1159 32.2.1.6 offset 108h: hptcv[0-2] - timer n comparator value register ........... 1161 32.3 theory of operation....................................................................................... 1164 32.3.1 timer accuracy rules ............................................................................ 1164 32.3.2 interrupt mapping................................................................................. 1164 32.3.3 periodic vs. non-periodic modes.............................................................. 1165 32.3.3.1 non-periodic mode ........................................................................ 1165 32.3.3.2 periodic mode ............................................................................... 1165 32.3.4 enabling the timers ............................................................................. 1166 32.3.5 interrupt levels.................................................................................... 1166 32.3.6 handling interrupts............................................................................... 1166 32.3.7 unloading device driver issues .............................................................. 1167 33.0 serial i/o unit and watchdog timer .................................................................... 1169 33.1 overview ...................................................................................................... 1169 33.2 features ....................................................................................................... 1169 33.3 functional description .................................................................................... 1170 33.3.1 host processor interface (lpc) ............................................................... 1170 33.4 lpc interface ................................................................................................ 1170 33.4.1 lpc cycles........................................................................................... 1170 33.4.1.1 i/o read and write cycles.............................................................. 1171 33.4.2 policy.................................................................................................. 1171 33.4.3 lpc transfers....................................................................................... 1171 33.4.3.1 i/o transfers ................................................................................ 1171 33.5 logical devices 4 and 5: serial ports (uart1 and uart2) ................................... 1171
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 33 contents 33.5.1 uart feature list .................................................................................1172 33.5.2 uart operational description .................................................................1173 33.5.2.1 programmable baud rate generator.................................................1174 33.5.3 uart register details ............................................................................1175 33.5.3.1 offset 00h: rbr - receive buffer register .........................................1176 33.5.3.2 offset 00h: thr - transmit holding register .....................................1176 33.5.3.3 offset 01h: ier - interrupt enable register .......................................1177 33.5.3.4 offset 02h: iir - interrupt identification register ...............................1178 33.5.3.5 offset 02h: fcr - fifo control register ............................................1180 33.5.3.6 offset 03h: lcr - line control register.............................................1182 33.5.3.7 offset 04h: mcr - modem control register........................................1184 33.5.3.8 offset 05h: lsr - line status register ..............................................1185 33.5.3.9 offset 06h: msr - modem status register.........................................1188 33.5.3.10 offset 07h: scr - scratchpad register .............................................1190 33.5.3.11 offset 00h: dll - programmable baud rate generator divisor latch register low .............................................................................................1190 33.5.3.12 offset 01h: dlh - programmable baud rate generator divisor latch register high.............................................................................................1190 33.5.4 fifo operation .....................................................................................1191 33.5.4.1 fifo interrupt mode operation ........................................................1191 33.5.4.2 fifo polled mode operation ............................................................1192 33.6 logical device 6: watchdog timer ....................................................................1192 33.6.1 overview .............................................................................................1192 33.6.2 watchdog timer register details .............................................................1194 33.6.2.1 offset 00h: pv1r0 - preload value 1 register 0 .................................1194 33.6.2.2 offset 01h: pv1r1 - preload value 1 register 1 .................................1195 33.6.2.3 offset 02h: pv1r2 - preload value 1 register 2 .................................1195 33.6.2.4 offset 04h: pv2r0 - preload value 2 register 0 .................................1196 33.6.2.5 offset 05h: pv2r1 - preload value 2 register 1 .................................1196 33.6.2.6 offset 06h: pv2r2 - preload value 2 register 2 .................................1197 33.6.2.7 offset 08h: gisr - general interrupt status register..........................1197 33.6.2.8 offset 0ch: rr0 - reload register 0 .................................................1198 33.6.2.9 offset 0dh: rr1 - reload register 1.................................................1199 33.6.2.10 offset 10h: wdtcr - wdt configuration register ..............................1199 33.6.2.11 offset 18h: wdtlr - wdt lock register ...........................................1201 33.6.3 theory of operation ..............................................................................1202 33.6.3.1 rtc well and wdt_tout# functionality ...........................................1202 33.6.3.2 register unlocking sequence...........................................................1202 33.6.3.3 reload sequence ...........................................................................1202 33.6.3.4 low power state............................................................................1202 33.7 serial irq .....................................................................................................1203 33.7.1 timing diagrams for siw_serirq cycle..................................................1203 33.7.1.1 siw_serirq cycle control .............................................................1203 33.7.1.2 siw_serirq data frame ...............................................................1204 33.7.1.3 stop cycle control .........................................................................1205 33.7.1.4 latency ........................................................................................1205 33.7.1.5 eoi/isr read latency ....................................................................1205 33.7.1.6 reset and initialization ...................................................................1205 33.8 configuration .................................................................................................1206 33.8.1 configuration port address ....................................................................1206 33.8.2 primary configuration address decoder....................................................1206 33.8.2.1 entering the configuration state ......................................................1206 33.8.2.2 exiting the configuration state ........................................................1206 33.8.2.3 configuration sequence ..................................................................1206 33.8.2.4 configuration mode ........................................................................1206 33.8.3 siw configuration register summary ......................................................1207 33.8.3.1 global control/configuration registers [00h - 2fh].............................1208 33.8.3.2 logical device configuration registers [30h ? ffh]............................1209
contents intel ? ep80579 integrated processor product line datasheet august 2009 34 order number: 320066-003us acceleration and i/o complex, volume 4 of 6 ........................... 1213 34.0 pci-to-pci bridge ................................................................................................ 1215 34.1 summary ..................................................................................................... 1215 34.2 pci-to-pci bridge detailed register descriptions................................................ 1215 34.2.1 pci-to-pci bridge header ...................................................................... 1216 34.2.2 pci-to-pci bridge configuration space .................................................... 1217 34.2.2.1 offset 0h: vid ? vendor identification register ................................. 1217 34.2.2.2 offset 2h: did ? device identification register.................................. 1217 34.2.2.3 offset 4h: pcicmd ? device command register ................................ 1217 34.2.2.4 offset 6h: pcists ? device status register ...................................... 1218 34.2.2.5 offset 8h: rid ? revision id register .............................................. 1219 34.2.2.6 offset 9h: cc ? class code register ................................................ 1219 34.2.2.7 offset ch: cls ? cacheline size register .......................................... 1219 34.2.2.8 offset dh: lt ? latency timer register ............................................ 1220 34.2.2.9 offset eh: hdr ? header type register............................................ 1220 34.2.2.10 offset 10h: csrbar0 ? control and status registers base address register 1220 34.2.2.11 offset 14h: csrbar1 ? control and status registers base address register 1221 34.2.2.12 offset 18h: pbnum ? primary bus number register ........................... 1221 34.2.2.13 offset 19h: secbnm ? secondary bus number register ..................... 1221 34.2.2.14 offset 1ah: subbnm ? subordinate bus number register................... 1222 34.2.2.15 offset 1bh: seclt ? secondary latency timer register...................... 1222 34.2.2.16 offset 1ch: iob ? i/o base register ................................................ 1222 34.2.2.17 offset 1dh: iol ? i/o limit register ................................................ 1223 34.2.2.18 offset 1eh: secsta ? secondary status register .............................. 1223 34.2.2.19 offset 20h: memb ? memory base register....................................... 1224 34.2.2.20 offset 22h: meml ? memory limit register ....................................... 1224 34.2.2.21 offset 24h: pmbase ? prefetchable memory base register.................. 1225 34.2.2.22 offset 26h: pmlimit ? prefetchable memory limit register ................. 1225 34.2.2.23 offset 28h: pmbasu ? prefetchable memory base upper register ........ 1226 34.2.2.24 offset 2ch: pmlmtu ? prefetchable memory limit upper register ........ 1226 34.2.2.25 offset 30h: iobu ? i/o base upper register ..................................... 1227 34.2.2.26 offset 32h: iolu ? i/o limit upper register ..................................... 1227 34.2.2.27 offset 34h: cp ? capabilities pointer register.................................... 1227 34.2.2.28 offset 3ch: irql ? interrupt line register........................................ 1228 34.2.2.29 offset 3dh: irqp ? interrupt pin register......................................... 1228 34.2.2.30 offset 3eh: bctl ? bridge control register....................................... 1228 34.2.2.31 offset dch: pcid ? power management capability id register ............ 1229 34.2.2.32 offset ddh: pcp ? power management next capability pointer register ....................................................................................... 1230 34.2.2.33 offset deh: pmcap ? power management capability register .............. 1230 34.2.2.34 offset e0h: pmcs ? power management control and status register ....................................................................................... 1231 34.2.2.35 offset e2h: pmcse ? power management control and status extension register ....................................................................................... 1232 35.0 pci-to-pci bridge: aioc configuration ............................................................... 1233 35.1 overview ...................................................................................................... 1233 35.2 feature list .................................................................................................. 1233 35.3 pci configuration registers............................................................................. 1233 35.3.1 description of pci configuration header space ......................................... 1233 35.4 interrupt handling for aioc devices................................................................. 1235 35.5 power management of aioc devices ................................................................ 1236 35.6 gigabit ethernet mac configuration spaces: bus m, device 0-2, function 0 ........... 1237 35.6.1 register details .................................................................................... 1237 35.6.1.1 offset 00h: vid ? vendor identification register................................ 1240 35.6.1.2 offset 02h: did ? device identification register ................................ 1241
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 35 contents 35.6.1.3 offset 02h: did ? device identification register ................................1242 35.6.1.4 offset 02h: did ? device identification register ................................1242 35.6.1.5 offset 04h: pcicmd ? device command register ...............................1243 35.6.1.6 offset 06h: pcists ? device status register .....................................1244 35.6.1.7 offset 08h: rid ? revision id register .............................................1245 35.6.1.8 offset 09h: cc ? class code register ...............................................1245 35.6.1.9 offset 0eh: hdr ? header type register...........................................1246 35.6.1.10 offset 10h: csrbar ? control and status registers base address register............................................................................1246 35.6.1.11 offset 14h: iobar ? csr i/o mapped bar register............................1247 35.6.1.12 offset 2ch: svid ? subsystem vendor id register.............................1248 35.6.1.13 offset 2eh: sid ? subsystem id register..........................................1248 35.6.1.14 offset 34h: cp ? capabilities pointer register ....................................1248 35.6.1.15 offset 3ch: irql ? interrupt line register ........................................1249 35.6.1.16 offset 3dh: irqp ? interrupt pin register .........................................1250 35.6.1.17 offset dch: pcid ? power management capability id register.............1251 35.6.1.18 offset ddh: pcp ? power management next capability pointer register .......................................................................................1251 35.6.1.19 offset deh: pmcap ? power management capability register...............1252 35.6.1.20 offset e0h: pmcs ? power management control and status register .......................................................................................1253 35.6.1.21 offset e4h: scid ? signal target capability id register ......................1254 35.6.1.22 offset e5h: scp ? signal target next capability pointer register..........1254 35.6.1.23 offset e6h: sbc ? signal target byte count register ..........................1255 35.6.1.24 offset e7h: styp ? signal target capability type register...................1255 35.6.1.25 offset e8h: smia ? signal target ia mask register.............................1256 35.6.1.26 offset e9h: reserved register .........................................................1256 35.6.1.27 offset eah: reserved register .........................................................1256 35.6.1.28 offset ech: sint ? signal target raw interrupt register.....................1257 35.6.1.29 offset f0h: mcid ? message signalled interrupt capability id register .......................................................................................1258 35.6.1.30 offset f1h: mcp ? message signalled interrupt next capability pointer register .......................................................................................1258 35.6.1.31 offset f2h: mctl ? message signalled interrupt control register .........1259 35.6.1.32 offset f4h: madr ? message signalled interrupt address register .......................................................................................1259 35.6.1.33 offset f8h: mdata ? message signalled interrupt data register ..........1260 35.7 gigabit ethernet mac i/o spaces: bus m, device 0-2, function 0 .........................1261 35.7.1 register details ....................................................................................1262 35.7.1.1 offset 0000h: ioaddr - ioaddr register ........................................1262 35.7.1.2 offset 0004h: iodata - iodata register .........................................1264 35.8 gcu configuration space: bus m, device 3, function 0........................................1265 35.8.1 register details ....................................................................................1265 35.8.1.1 offset 00h: vid ? vendor identification register ................................1265 35.8.1.2 offset 02h: did ? device identification register ................................1266 35.8.1.3 offset 04h: pcicmd ? device command register ...............................1266 35.8.1.4 offset 06h: pcists ? device status register .....................................1267 35.8.1.5 offset 08h: rid ? revision id register .............................................1267 35.8.1.6 offset 09h: cc ? class code register ...............................................1268 35.8.1.7 offset 0eh: hdr ? header type register...........................................1268 35.8.1.8 offset 10h: csrbar ? control and status registers base address register............................................................................1269 35.8.1.9 offset 2ch: svid ? subsystem vendor id register.............................1269 35.8.1.10 offset 2eh: sid ? subsystem id register..........................................1270 35.8.1.11 offset 34h: cp ? capabilities pointer register ....................................1270 35.8.1.12 offset dch: pcid ? power management capability id register.............1270 35.8.1.13 offset ddh: pcp ? power management next capability pointer register .......................................................................................1271 35.8.1.14 offset deh: pmcap ? power management capability register...............1271
contents intel ? ep80579 integrated processor product line datasheet august 2009 36 order number: 320066-003us 35.8.1.15 offset e0h: pmcs ? power management control and status register ....................................................................................... 1272 35.9 can controller configuration spaces: bus m, device 4-5, function 0 .................... 1273 35.9.1 register details .................................................................................... 1273 35.9.1.1 offset 00h: vid ? vendor identification register................................ 1275 35.9.1.2 offset 02h: did ? device identification register ................................ 1275 35.9.1.3 offset 02h: did ? device identification register ................................ 1276 35.9.1.4 offset 04h: pcicmd ? device command register .............................. 1276 35.9.1.5 offset 06h: pcists ? device status register .................................... 1277 35.9.1.6 offset 08h: rid ? revision id register............................................. 1278 35.9.1.7 offset 09h: cc ? class code register............................................... 1278 35.9.1.8 offset 0eh: hdr ? header type register .......................................... 1279 35.9.1.9 offset 10h: csrbar ? control and status registers base address register ........................................................................... 1279 35.9.1.10 offset 2ch: svid ? subsystem vendor id register ............................ 1280 35.9.1.11 offset 2eh: sid ? subsystem id register ......................................... 1280 35.9.1.12 offset 34h: cp ? capabilities pointer register.................................... 1281 35.9.1.13 offset 3ch: irql ? interrupt line register........................................ 1281 35.9.1.14 offset 3dh: irqp ? interrupt pin register......................................... 1282 35.9.1.15 offset 40h: canctl ? can control register ...................................... 1282 35.9.1.16 offset dch: pcid ? power management capability id register ............ 1283 35.9.1.17 offset ddh: pcp ? power management next capability pointer register ....................................................................................... 1283 35.9.1.18 offset deh: pmcap ? power management capability register .............. 1284 35.9.1.19 offset e0h: pmcs ? power management control and status register ....................................................................................... 1284 35.9.1.20 offset e4h: scid ? signal target capability id register ..................... 1285 35.9.1.21 offset e5h: scp ? signal target next capability pointer register ......... 1285 35.9.1.22 offset e6h: sbc ? signal target byte count register ......................... 1286 35.9.1.23 offset e7h: styp ? signal target capability type register .................. 1286 35.9.1.24 offset e8h: smia ? signal target ia mask register ............................ 1287 35.9.1.25 offset e9h: reserved register......................................................... 1287 35.9.1.26 offset eah: reserved register ........................................................ 1287 35.9.1.27 offset ech: sint ? signal target raw interrupt register .................... 1287 35.9.1.28 offset f0h: mcid ? message signalled interrupt capability id register ....................................................................................... 1288 35.9.1.29 offset f1h: mcp ? message signalled interrupt next capability pointer register ....................................................................................... 1288 35.9.1.30 offset f2h: mctl ? message signalled interrupt control register......... 1289 35.9.1.31 offset f4h: madr ? message signalled interrupt address register ....................................................................................... 1289 35.9.1.32 offset f8h: mdata ? message signalled interrupt data register.......... 1290 35.10 ssp controller configuration space: bus m, device 6, function 0 ........................ 1291 35.10.1 register details .................................................................................... 1291 35.10.1.1 offset 00h: vid ? vendor identification register................................ 1292 35.10.1.2 offset 02h: did ? device identification register ................................ 1292 35.10.1.3 offset 04h: pcicmd ? device command register .............................. 1292 35.10.1.4 offset 06h: pcists ? device status register .................................... 1293 35.10.1.5 offset 08h: rid ? revision id register............................................. 1294 35.10.1.6 offset 09h: cc ? class code register............................................... 1295 35.10.1.7 offset 0eh: hdr ? header type register .......................................... 1295 35.10.1.8 offset 10h: csrbar ? control and status registers base address register ........................................................................... 1295 35.10.1.9 offset 2ch: svid ? subsystem vendor id register ............................ 1296 35.10.1.10 offset 2eh: sid ? subsystem id register ......................................... 1296 35.10.1.11 offset 34h: cp ? capabilities pointer register.................................... 1297 35.10.1.12 offset 3ch: irql ? interrupt line register........................................ 1297 35.10.1.13 offset 3dh: irqp ? interrupt pin register......................................... 1298 35.10.1.14 offset dch: pcid ? power management capability id register ............ 1298
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 37 contents 35.10.1.15 offset ddh: pcp ? power management next capability pointer register .......................................................................................1299 35.10.1.16 offset deh: pmcap - power management capability ...........................1299 35.10.1.17 offset e0h: pmcs ? power management control and status register .......................................................................................1300 35.10.1.18 offset e4h: scid ? signal target capability id register ......................1300 35.10.1.19 offset e5h: scp ? signal target next capability pointer register..........1301 35.10.1.20 offset e6h: sbc ? signal target byte count register ..........................1301 35.10.1.21 offset e7h: styp ? signal target capability type register...................1301 35.10.1.22 offset e8h: smia ? signal target ia mask register.............................1302 35.10.1.23 offset e9h: reserved register .........................................................1302 35.10.1.24 offset eah: reserved register .........................................................1302 35.10.1.25 offset ech: sint ? signal target raw interrupt register.....................1302 35.10.1.26 offset f0h: mcid ? message signalled interrupt capability id register .......................................................................................1302 35.10.1.27 offset f1h: mcp ? message signalled interrupt next capability pointer register .......................................................................................1303 35.10.1.28 offset f2h: mctl ? message signalled interrupt control register .......................................................................................1303 35.10.1.29 offset f4h: madr ? message signalled interrupt address register .......................................................................................1304 35.10.1.30 offset f8h: mdata ? message signalled interrupt data register ..........1304 35.11 ieee 1588 hardware assist unit configuration space: bus m, device 7, function 0 1305 35.11.1 register details ....................................................................................1305 35.11.1.1 offset 00h: vid ? vendor identification register ................................1306 35.11.1.2 offset 02h: did ? device identification register ................................1306 35.11.1.3 offset 04h: pcicmd ? device command register ...............................1306 35.11.1.4 offset 06h: pcists ? device status register .....................................1307 35.11.1.5 offset 08h: rid ? revision id register .............................................1308 35.11.1.6 offset 09h: cc ? class code register ...............................................1308 35.11.1.7 offset 0eh: hdr ? header type register ..........................................1309 35.11.1.8 offset 10h: csrbar ? control and status registers base address register............................................................................1309 35.11.1.9 offset 2ch: svid ? subsystem vendor id register.............................1310 35.11.1.10 offset 2eh: sid ? subsystem id register..........................................1310 35.11.1.11 offset 34h: cp ? capabilities pointer register ....................................1310 35.11.1.12 offset 3ch: irql ? interrupt line register ........................................1311 35.11.1.13 offset 3dh: irqp ? interrupt pin register .........................................1311 35.11.1.14 offset dch: pcid ? power management capability id register.............1312 35.11.1.15 offset ddh: pcp ? power management next capability pointer register .......................................................................................1312 35.11.1.16 offset deh: pmcap ? power management capability register...............1313 35.11.1.17 offset e0h: pmcs ? power management control and status register .......................................................................................1313 35.11.1.18 offset e4h: scid ? signal target capability id register ......................1314 35.11.1.19 offset e5h: scp ? signal target next capability pointer register..........1314 35.11.1.20 offset e6h: sbc ? signal target byte count register ..........................1314 35.11.1.21 offset e7h: styp ? signal target capability type register...................1315 35.11.1.22 offset e8h: smia ? signal target ia mask register.............................1315 35.11.1.23 offset e9h: reserved register .........................................................1315 35.11.1.24 offset eah: reserved register .........................................................1315 35.11.1.25 offset ech: sint ? signal target raw interrupt register.....................1316 35.11.1.26 offset f0h: mcid ? message signalled interrupt capability id register .......................................................................................1316 35.11.1.27 offset f1h: mcp ? message signalled interrupt next capability pointer register .......................................................................................1317 35.11.1.28 offset f2h: mctl ? message signalled interrupt control register .......................................................................................1317 35.11.1.29 offset f4h: madr ? message signalled interrupt address register .......................................................................................1318
contents intel ? ep80579 integrated processor product line datasheet august 2009 38 order number: 320066-003us 35.11.1.30 offset f8h: mdata ? message signalled interrupt data register.......... 1318 35.12 expansion bus configuration space: bus m, device 8, function 0 ........................ 1319 35.12.1 register details .................................................................................... 1319 35.12.1.1 offset 00h: vid ? vendor identification register................................ 1320 35.12.1.2 offset 02h: did ? device identification register ................................ 1320 35.12.1.3 offset 04h: pcicmd ? device command register .............................. 1321 35.12.1.4 offset 06h: pcists ? device status register .................................... 1321 35.12.1.5 offset 08h: rid ? revision id register............................................. 1322 35.12.1.6 offset 09h: cc ? class code register............................................... 1323 35.12.1.7 offset 0eh: hdr ? header type register .......................................... 1323 35.12.1.8 offset 10h: csrbar ? control and status registers base address register ........................................................................... 1323 35.12.1.9 offset 14h: mmbar ? expansion bus base address register................ 1324 35.12.1.10 offset 2ch: svid ? subsystem vendor id register ............................ 1325 35.12.1.11 offset 2eh: sid ? subsystem id register ......................................... 1325 35.12.1.12 offset 34h: cp ? capabilities pointer register.................................... 1326 35.12.1.13 offset 3ch: irql ? interrupt line register........................................ 1326 35.12.1.14 offset 3dh: irqp ? interrupt pin register......................................... 1327 35.12.1.15 offset 40h: lebctl ? leb control register ....................................... 1327 35.12.1.16 offset dch: pcid ? power management capability id register ............ 1327 35.12.1.17 offset ddh: pcp ? power management next capability pointer register ....................................................................................... 1328 35.12.1.18 offset deh: pmcap ? power management capability register .............. 1328 35.12.1.19 offset e0h: pmcs ? power management control and status register ....................................................................................... 1329 35.12.1.20 offset e4h: scid ? signal target capability id register ..................... 1329 35.12.1.21 offset e5h: scp ? signal target next capability pointer register ......... 1330 35.12.1.22 offset e6h: sbc ? signal target byte count register ......................... 1330 35.12.1.23 offset e7h: styp ? signal target capability type register .................. 1330 35.12.1.24 offset e8h: smia ? signal target ia mask register ............................ 1331 35.12.1.25 offset e9h: reserved register......................................................... 1331 35.12.1.26 offset eah: reserved register ........................................................ 1331 35.12.1.27 offset ech: sint ? signal target raw interrupt register .................... 1331 35.12.1.28 offset f0h: mcid ? message signalled interrupt capability id register ....................................................................................... 1332 35.12.1.29 offset f1h: mcp ? message signalled interrupt next capability pointer register ....................................................................................... 1332 35.12.1.30 offset f2h: mctl ? message signalled interrupt control register ....................................................................................... 1333 35.12.1.31 offset f4h: madr ? message signalled interrupt address register ....................................................................................... 1333 35.12.1.32 offset f8h: mdata ? message signalled interrupt data register.......... 1334 36.0 aioc interfaces ................................................................................................... 1335 36.1 overview ...................................................................................................... 1335 36.2 gigabit ethernet (gbe) ................................................................................... 1335 36.2.1 integrated dma features ....................................................................... 1336 36.2.2 mac features....................................................................................... 1336 36.2.3 host off-loading features ..................................................................... 1337 36.2.4 interfaces............................................................................................ 1337 36.2.5 power management .............................................................................. 1337 36.2.6 serial eeprom interface ........................................................................ 1338 36.3 local expansion bus interface (leb)................................................................. 1338 36.4 serial synchronous port (ssp)......................................................................... 1339 36.5 controller area network (can) ........................................................................ 1339 36.6 ieee 1588 time synchronization hardware assist ............................................. 1340 37.0 gigabit ethernet controller .................................................................................. 1341 37.1 overview ...................................................................................................... 1341
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 39 contents 37.1.1 terminology and conventions .................................................................1341 37.1.1.1 register and bit references.............................................................1341 37.1.1.2 byte and bit designations ...............................................................1341 37.1.1.3 numbering....................................................................................1341 37.1.1.4 memory alignment terminology.......................................................1342 37.1.1.5 alignment and byte ordering...........................................................1342 37.1.1.6 packet buffer ................................................................................1342 37.1.2 wake on lan .......................................................................................1343 37.2 feature list ...................................................................................................1343 37.3 functional block diagram ................................................................................1344 37.4 usage model ..................................................................................................1345 37.4.1 protocol translation ...............................................................................1346 37.4.2 power management ...............................................................................1346 37.4.3 software initialization and diagnostics .....................................................1346 37.4.3.1 power up state .............................................................................1346 37.4.3.2 memory initialization ......................................................................1347 37.4.3.3 general configuration.....................................................................1348 37.4.3.4 link setup mechanisms and control/status bit summary ....................1348 37.4.3.5 receive initialization ......................................................................1348 37.4.3.6 transmit initialization.....................................................................1349 37.4.3.7 initialization of statistics.................................................................1350 37.4.3.8 gbe line rate configuration change ................................................1350 37.4.3.9 network boot ................................................................................1350 37.4.3.10 diagnostics ...................................................................................1351 37.5 functional description.....................................................................................1351 37.5.1 ethernet addressing ..............................................................................1351 37.5.2 interrupt control & tuning .....................................................................1352 37.5.2.1 interrupt cause set/read registers..................................................1353 37.5.2.2 interrupt mask set (read)/clear registers ........................................1353 37.5.2.3 interrupt throttling register............................................................1353 37.5.3 hardware acceleration capability ............................................................1353 37.5.3.1 checksum off-loading....................................................................1353 37.5.3.2 tcp segmentation .........................................................................1354 37.5.4 buffer and descriptor structure...............................................................1354 37.5.5 packet reception...................................................................................1354 37.5.5.1 packet address filtering..................................................................1354 37.5.5.2 receive data storage .....................................................................1355 37.5.5.3 receive descriptor format ..............................................................1355 37.5.5.4 receive descriptor fetching ............................................................1358 37.5.5.5 receive descriptor write-back .........................................................1358 37.5.5.6 receive descriptor queue structure .................................................1359 37.5.5.7 receive interrupts .........................................................................1360 37.5.5.8 receive packet checksum off loading ...............................................1363 37.5.6 packet transmission ..............................................................................1365 37.5.6.1 transmit data storage ...................................................................1365 37.5.6.2 transmit descriptor formats ...........................................................1365 37.5.6.3 legacy transmit descriptor format ..................................................1366 37.5.6.4 tcp/ip context transmit descriptor format.......................................1369 37.5.6.5 tcp/ip data descriptor format ........................................................1373 37.5.6.6 transmit descriptor structure..........................................................1375 37.5.6.7 transmit descriptor fetching ...........................................................1377 37.5.6.8 transmit descriptor write-back .......................................................1377 37.5.6.9 transmit interrupts........................................................................1378 37.5.6.10 transmit checksum off loading .......................................................1379 37.5.7 tcp segmentation.................................................................................1380 37.5.7.1 assumptions .................................................................................1381 37.5.7.2 transmission process .....................................................................1381 37.5.7.3 tcp segmentation performance .......................................................1382
contents intel ? ep80579 integrated processor product line datasheet august 2009 40 order number: 320066-003us 37.5.7.4 packet format .............................................................................. 1382 37.5.7.5 tcp segmentation indication .......................................................... 1383 37.5.7.6 tcp segmentation data descriptors................................................. 1383 37.5.7.7 ip and tcp/udp headers ................................................................ 1384 37.5.7.8 transmit checksum off loading with tcp segmentation...................... 1388 37.5.7.9 ip/tcp/udp header updating.......................................................... 1389 37.5.7.10 data flow..................................................................................... 1391 37.5.8 ethernet interfaces ............................................................................... 1391 37.5.8.1 mac/phy gmii/mii interface .......................................................... 1392 37.5.8.2 duplex operation .......................................................................... 1393 37.5.8.3 physical layer auto-negotiation & link setup features....................... 1394 37.5.8.4 10/100mbps specific performance enhancements .............................. 1396 37.5.8.5 flow control ................................................................................. 1397 37.5.9 802.1q vlan support............................................................................ 1400 37.5.9.1 transmitting and receiving 802.1q packets ...................................... 1401 37.5.9.2 802.1q vlan packet filtering .......................................................... 1401 37.5.10 wake on lan ....................................................................................... 1402 37.5.10.1 advanced power management wakeup............................................. 1402 37.5.10.2 acpi power management wakeup ................................................... 1403 37.5.10.3 wake-up packets: pre-defined filters ............................................... 1404 37.5.10.4 wake-up packets: flexible filters .................................................... 1409 37.5.11 serial eeprom ..................................................................................... 1412 37.5.11.1 eeprom device............................................................................. 1412 37.5.11.2 software accesses......................................................................... 1412 37.5.11.3 signature field ............................................................................. 1413 37.5.11.4 eeprom map ................................................................................ 1413 37.5.11.5 hardware accessed words.............................................................. 1415 37.5.11.6 software accessed words............................................................... 1417 37.5.12 error handling...................................................................................... 1418 37.5.12.1 csr (target) accesses ................................................................... 1418 37.5.12.2 dma host (master) accesses........................................................... 1418 37.5.12.3 internal memories ......................................................................... 1419 37.5.13 reset operation ................................................................................... 1420 37.5.13.1 soft reset .................................................................................... 1422 37.5.13.2 mac disable ................................................................................. 1422 37.5.14 endianness .......................................................................................... 1422 37.6 gbe controller register summary .................................................................... 1425 37.6.1 registers overview ............................................................................... 1425 37.6.1.1 memory-mapped access to intern al registers and memories ............... 1436 37.6.1.2 i/o-mapped access to internal registers and memories ...................... 1436 37.6.1.3 register conventions ..................................................................... 1437 37.6.2 general registers: detailed descriptions.................................................. 1438 37.6.2.1 ctrl ? device control register ....................................................... 1438 37.6.2.2 status ? device status register .................................................... 1441 37.6.2.3 ctrl_ext ? extended device control register .................................. 1442 37.6.2.4 ctrl_aux ? auxiliary device control/status register ........................ 1444 37.6.2.5 eeprom_ctrl ? eeprom control register ....................................... 1446 37.6.2.6 eeprom_rr ? eeprom read register .............................................. 1448 37.6.2.7 fcal ? flow control address low register ........................................ 1449 37.6.2.8 fcah ? flow control address high register ...................................... 1450 37.6.2.9 fct ? flow control type register .................................................... 1451 37.6.2.10 vet ? vlan ethertype register....................................................... 1452 37.6.2.11 fcttv ? flow control transmit timer value register.......................... 1452 37.6.2.12 pba ? packet buffer allocation register ............................................ 1453 37.6.3 interrupt registers: detailed descriptions ................................................ 1454 37.6.3.1 icr0 ? interrupt 0 cause read register ........................................... 1454 37.6.3.2 itr0 ? interrupt 0 throttling register .............................................. 1457 37.6.3.3 ics0 ? interrupt 0 cause set register ............................................ 1458
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 41 contents 37.6.3.4 ims0 ? interrupt 0 mask set/read register .......................................1459 37.6.3.5 imc0 ? interrupt 0 mask clear register ...........................................1460 37.6.3.6 icr1 ? interrupt 1 cause read register............................................1462 37.6.3.7 ics1 ? interrupt 1 cause set register .............................................1464 37.6.3.8 ims1 ? interrupt 1 mask set/read register .......................................1466 37.6.3.9 imc1 ? interrupt 1 mask clear register ...........................................1467 37.6.3.10 icr2 ? error interrupt cause read register ......................................1469 37.6.3.11 ics2 ? error interrupt cause set register ........................................1471 37.6.3.12 ims2 ? error interrupt mask set/read register..................................1472 37.6.3.13 imc2 ? error interrupt mask clear register ......................................1473 37.6.4 receive registers: detailed descriptions ..................................................1474 37.6.4.1 rctl ? receive control register ......................................................1474 37.6.4.2 fcrtl: flow control receive threshold low register .........................1478 37.6.4.3 fcrth ? flow control receive threshold high register ......................1479 37.6.4.4 rdbal ? receive descriptor base address low register ......................1480 37.6.4.5 rdbah ? receive descriptor base address high register ...................1480 37.6.4.6 rdlen ? receive descriptor length register ....................................1481 37.6.4.7 rdh ? receive descriptor head register ..........................................1481 37.6.4.8 rdt ? receive descriptor tail register .............................................1482 37.6.4.9 rdtr ? rx interrupt delay timer (packet timer) register ..................1482 37.6.4.10 rxdctl ? receive descriptor control register ..................................1483 37.6.4.11 radv ? receive interrupt absolute delay timer register ...................1485 37.6.4.12 rsrpd ? receive small packet detect interrupt register.....................1486 37.6.4.13 rxcsum ? receive checksum control register ..................................1487 37.6.4.14 mta[0-127] ? 128 multicast table array registers .............................1488 37.6.4.15 ral[0-15] ? receive address low register........................................1488 37.6.4.16 rah[0-15] ? receive address high register ......................................1489 37.6.4.17 vfta[0-127] ? 128 vlan filter table array registers .........................1490 37.6.5 transmit registers: detailed descriptions .................................................1491 37.6.5.1 tctl ? transmit control register .....................................................1491 37.6.5.2 tipg ? transmit ipg register .........................................................1493 37.6.5.3 ait ? adaptive ifs throttle register.................................................1495 37.6.5.4 tdbal ? transmit descriptor base address low register ....................1496 37.6.5.5 tdbah ? transmit descriptor base address high register ...................1496 37.6.5.6 tdlen ? transmit descriptor length register ...................................1497 37.6.5.7 tdh ? transmit descriptor head register..........................................1497 37.6.5.8 tdt ? transmit descriptor tail register ............................................1498 37.6.5.9 tidv ? transmit interrupt delay value register .................................1499 37.6.5.10 txdctl ? transmit descriptor control register .................................1500 37.6.5.11 tadv ? transmit absolute interrupt delay value register ...................1502 37.6.5.12 tspmt ? tcp segmentation pad and minimum threshold register ........1503 37.6.6 statistical registers: detailed descriptions ...............................................1505 37.6.6.1 crcerrs ? crc error count register ...............................................1505 37.6.6.2 algnerrc ? alignment error count register .....................................1506 37.6.6.3 rxerrc ? receive error count register ............................................1506 37.6.6.4 mpc ? missed packet count register ................................................1507 37.6.6.5 scc ? single collision count register ...............................................1507 37.6.6.6 ecol ? excessive collisions count register .......................................1508 37.6.6.7 mcc ? multiple collision count register ............................................1508 37.6.6.8 latecol ? late collisions count register..........................................1509 37.6.6.9 colc ? collision count register.......................................................1509 37.6.6.10 dc ? defer count register ..............................................................1510 37.6.6.11 tncrs ? transmit with no crs count register ..................................1510 37.6.6.12 cexterr ? carrier extension error count register .............................1511 37.6.6.13 rlec ? receive length error count register......................................1511 37.6.6.14 xonrxc ? xon received count register ..........................................1512 37.6.6.15 xontxc ? xon transmitted count register ......................................1512 37.6.6.16 xoffrxc ? xoff received count register ........................................1513 37.6.6.17 xofftxc ? xoff transmitted count register ....................................1513
contents intel ? ep80579 integrated processor product line datasheet august 2009 42 order number: 320066-003us 37.6.6.18 fcruc ? fc received unsupported count register ............................ 1514 37.6.6.19 prc64 ? good packets received count (64 bytes) register................. 1514 37.6.6.20 prc127 ? good packets received count (65-127 bytes) register ........ 1515 37.6.6.21 prc255 ? good packets received count (128-255 bytes) register ....................................................................................... 1515 37.6.6.22 prc511 ? good packets received count (256-511 bytes) register ....................................................................................... 1516 37.6.6.23 prc1023 ? good packets received count (512-1023 bytes) register ...................................................................................... 1516 37.6.6.24 prc1522 ? good packets received count (1024 to max bytes) register ...................................................................................... 1517 37.6.6.25 gprc ? good packets received count (total) register ....................... 1518 37.6.6.26 bprc ? broadcast packets received count register ........................... 1518 37.6.6.27 mprc ? multicast packets received count register ........................... 1519 37.6.6.28 gptc ? good packets transmitted count register.............................. 1519 37.6.6.29 gorcl ? good octets received count low register ........................... 1520 37.6.6.30 gorch ? good octets received count high register ......................... 1521 37.6.6.31 gotcl ? good octets transmitted count low register....................... 1521 37.6.6.32 gotch ? good octets transmitted count high register ..................... 1522 37.6.6.33 rnbc ? receive no buffers count register ....................................... 1523 37.6.6.34 ruc ? receive undersize count register ......................................... 1523 37.6.6.35 rfc ? receive fragment count register ........................................... 1524 37.6.6.36 roc ? receive oversize count register............................................ 1524 37.6.6.37 rjc ? receive jabber count register ............................................... 1525 37.6.6.38 torl ? total octets received low register....................................... 1525 37.6.6.39 torh ? total octets received high register ..................................... 1526 37.6.6.40 totl ? total octets transmitted low register................................... 1527 37.6.6.41 toth ? total octets transmitted high register ................................. 1527 37.6.6.42 tpr ? total packets received register ............................................. 1528 37.6.6.43 tpt ? total packets transmitted register ......................................... 1529 37.6.6.44 ptc64 ? packets transmitted count (64 bytes) register..................... 1529 37.6.6.45 ptc127 ? packets transmitted count (65-127 bytes) register ............ 1530 37.6.6.46 ptc255 ? packets transmitted count (128-255 bytes) register........... 1530 37.6.6.47 ptc511 ? packets transmitted count (256-511 bytes) register........... 1530 37.6.6.48 ptc1023 ? packets transmitted count (512-1023 bytes) register ....... 1531 37.6.6.49 ptc1522: packets transmitted count (1024-1522 bytes) register ....... 1531 37.6.6.50 mptc ? multicast packets transmitted count register ........................ 1532 37.6.6.51 bptc ? broadcast packets transmitted count register ....................... 1532 37.6.6.52 tsctc ? tcp segmentation context transmitted count register ......... 1533 37.6.6.53 tsctfc ? tcp segmentation context transmit fail count register ...................................................................................... 1533 37.6.7 management register descriptions.......................................................... 1534 37.6.7.1 wuc ? wake up control register (0x05800; rw) .............................. 1534 37.6.7.2 wufc ? wake up filter control register (0x05808; rw) .................... 1535 37.6.7.3 wus ? wake up status register (0x05810; rw) ............................... 1536 37.6.7.4 ipav ? ip address valid register (0x05838; rw) ............................... 1537 37.6.7.5 ip4at[0-3] - (0x5840 - 0x5858; rw) ? ipv4 address table registers ..................................................................................... 1538 37.6.7.6 ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4 .................................................................................. 1538 37.6.7.7 ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8 .................................................................................. 1539 37.6.7.8 ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12 ................................................................................. 1540 37.6.7.9 ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16 ............................................................................... 1540 37.6.7.10 fflt[0-3] ? flexible filter length table registers (0x5f00 - 0x5f18; rw) ................................................................. 1541 37.6.7.11 ffmt[0-127] ? flexible filter mask table registers (0x9000 - 0x93f8; rw) ................................................................. 1542
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 43 contents 37.6.7.12 ffvt[0-127] ? flexible filter value table registers ............................1543 37.6.8 error register descriptions .....................................................................1544 37.6.8.1 intbus_err_stat ? internal bus error status register .....................1544 37.6.8.2 mem_tst ? memory error test register............................................1545 37.6.8.3 mem_sts ? memory error status register ........................................1546 37.7 power management ........................................................................................1549 37.7.1 assumptions.........................................................................................1549 37.7.2 d3cold support .....................................................................................1549 37.7.3 power states ........................................................................................1550 37.7.3.1 dr................................................................................................1550 37.7.3.2 d0u state .....................................................................................1551 37.7.3.3 d0a .............................................................................................1551 37.7.3.4 d3 ...............................................................................................1551 37.7.4 timing of power-state transitions ...........................................................1551 37.7.4.1 power up (off to dr to d0u to d0a) ..................................................1552 37.7.4.2 transition from d0a to d3 and back without reset .............................1554 37.7.4.3 transition from d0a to d3 and back with reset..................................1555 37.7.4.4 reset without transition to d3.........................................................1556 37.7.4.5 timing requirements .....................................................................1556 37.7.4.6 timing guarantees.........................................................................1557 37.7.5 power management extended capabilities registers...................................1557 38.0 global configuration unit ....................................................................................1559 38.1 overview ......................................................................................................1559 38.2 feature list ...................................................................................................1559 38.3 usage model ..................................................................................................1559 38.3.1 rcomp ...............................................................................................1559 38.3.1.1 gbe ............................................................................................1560 38.3.1.2 leb..............................................................................................1560 38.4 register summary..........................................................................................1561 38.4.1 detailed register descriptions.................................................................1562 38.4.1.1 offset 0x00000010h: mdio_status - mdio status register...............1562 38.4.1.2 offset 0x00000014h: mdio_command - mdio command register .......................................................................................1562 38.4.1.3 offset 0x00000018h: mdio_drive - mdio drive register ..................1563 38.4.1.4 offset 0x00000020h: mdc_drive - mdc drive register ....................1563 38.4.1.5 offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register.............................................................................1564 38.4.1.6 offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register .............................................................................1564 38.4.1.7 offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register .............................................1565 38.4.1.8 offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register.............................................1566 38.4.1.9 offset 0x00000060h: ssp_drive - ssp drive register ......................1566 38.4.1.10 offset 0x00000064h: tdm_drive_3 - tdm drive register for tdm port 3 ..................................................................................1567 38.4.1.11 offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2........................................................................1567 38.4.1.12 offset 0x00000028h: can_drive - can drive register .....................1568 39.0 controller area network - can .............................................................................1569 39.1 overview ......................................................................................................1569 39.2 feature list ...................................................................................................1569 39.3 functional block diagram ................................................................................1570 39.4 usage model ..................................................................................................1571 39.4.1 can basics...........................................................................................1571 39.4.2 addressing and bus arbitration ...............................................................1571
contents intel ? ep80579 integrated processor product line datasheet august 2009 44 order number: 320066-003us 39.4.3 frame types ........................................................................................ 1572 39.4.3.1 data frame .................................................................................. 1572 39.4.3.2 remote frame .............................................................................. 1575 39.4.3.3 error frames ................................................................................ 1576 39.4.3.4 overload frames........................................................................... 1577 39.4.4 can bit timing ..................................................................................... 1577 39.4.4.1 introduction ................................................................................. 1577 39.4.4.2 setting proper bit rate, tseg1 and tseg2 .......................................... 1579 39.5 theory of operation ....................................................................................... 1580 39.5.1 modes of operation............................................................................... 1580 39.5.2 error handling...................................................................................... 1580 39.5.3 send/receive procedure ........................................................................ 1581 39.5.3.1 send procedure ............................................................................ 1581 39.5.3.2 receive procedures ....................................................................... 1581 39.5.3.3 rx message processing .................................................................. 1582 39.5.3.4 acceptance filter........................................................................... 1582 39.5.3.5 rtr auto-reply............................................................................. 1583 39.5.3.6 rxbuffer linking............................................................................ 1583 39.5.4 txmessage registers............................................................................. 1584 39.6 register summary ......................................................................................... 1585 39.6.1 detailed register descriptions ................................................................ 1587 39.6.1.1 offset 00000000h: int_status - interrupt status register .................. 1587 39.6.1.2 offset 00000004h: int_ebl - interrupt enable register ...................... 1588 39.6.1.3 offset 00000008h: buffer status - buffer status indicators................. 1589 39.6.1.4 offset 0000000ch: errorstatus - error status indicators .................... 1590 39.6.1.5 offset 00000010h: command - operating modes............................... 1591 39.6.1.6 offset 00000014h: config - can configuration register ..................... 1592 39.6.1.7 offset 00000020h: txmessagecontrol[0-7] - transmit message control and command .................................................................................... 1593 39.6.1.8 offset 00000024h: txmessageid[0-7] - transmit message id ............. 1595 39.6.1.9 offset 00000028h: txmessagedatahigh[0-7] - transmit message data high 1596 39.6.1.10 offset 0000002ch: txmessagedatalow[0-7] - transmit message data low.. 1597 39.6.1.11 offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control .................................................................................. 1598 39.6.1.12 offset 000000a4h: rxmessageid[0-15] - receive message id............. 1600 39.6.1.13 offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high 1600 39.6.1.14 offset 000000ach: rxmessagedatalow[0-15] - receive message data low . 1601 39.6.1.15 offset 000000b0h: rxmessageamr[0-15] - receive message amr ....... 1601 39.6.1.16 offset 000000b4h: rxmessageacr[0-15] - receive message acr........ 1602 39.6.1.17 offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data 1603 39.6.1.18 offset 000000bch: rxmessageacr_data[0-15] - receive message acr data 1603 40.0 ssp serial port ..................................................................................................... 1605 40.1 overview ...................................................................................................... 1605 40.2 feature list .................................................................................................. 1605 40.3 theory of operation ....................................................................................... 1605 40.3.1 endianness .......................................................................................... 1605 40.3.2 error handling...................................................................................... 1605 40.4 register summary ......................................................................................... 1606 40.4.1 ssp control register 0 .......................................................................... 1607 40.4.1.1 offset 00h: sscr0 - ssp control register 0 details ........................... 1607 40.4.1.2 data size select (dss) .................................................................. 1609
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 45 contents 40.4.1.3 frame format (frf) .......................................................................1609 40.4.1.4 external clock select (ecs).............................................................1609 40.4.1.5 synchronous serial port enable (sse) ..............................................1609 40.4.1.6 serial clock rate (scr) ..................................................................1609 40.4.2 ssp control register 1 ...........................................................................1610 40.4.2.1 offset 04h: sscr1 - ssp control register 1 details ............................1610 40.4.2.2 receive fifo interrupt enable (rie) .................................................1611 40.4.2.3 transmit fifo interrupt enable (tie) ...............................................1611 40.4.2.4 loop back mode (lbm) ...................................................................1611 40.4.2.5 serial clock polarity (spo) ..............................................................1612 40.4.2.6 serial clock phase (sph) ................................................................1612 40.4.2.7 national microwire* data size (mwds) .............................................1613 40.4.2.8 transmit fifo interrupt threshold (tft)...........................................1613 40.4.2.9 receive fifo interrupt threshold (rft) ............................................1613 40.4.2.10 enable fifo write/read function (efwr)..........................................1613 40.4.2.11 select fifo for enable fifo write/read (strf)..................................1614 40.4.3 ssp status register...............................................................................1614 40.4.3.1 offset 08h: sssr - ssp status register details .................................1614 40.4.3.2 transmit fifo not full flag (tnf) (read-only, non-interruptible)..........................................................................1615 40.4.3.3 receive fifo not empty flag (rne) (read-only, non-interruptible) ........................................................1615 40.4.3.4 ssp busy flag (bsy) (read-only, non-interruptible) ..........................1615 40.4.3.5 transmit fifo service request flag (tfs) (read-only, maskable interrupt) .......................................................................1616 40.4.3.6 receive fifo service request flag (rfs) (read-only, maskable interrupt) .......................................................................1616 40.4.3.7 receiver overrun status (ror) (read/write, non-maskable interrupt).................................................................1616 40.4.3.8 transmit fifo level .......................................................................1616 40.4.3.9 receive fifo level.........................................................................1616 40.4.4 ssp interrupt test register ....................................................................1616 40.4.4.1 offset 0ch: ssitr - ssp interrupt test register details ......................1616 40.4.5 ssp data register .................................................................................1617 40.4.5.1 offset 10h: ssdr - ssp data register details....................................1617 41.0 ieee 1588 time synchronization hardware assist ................................................1619 41.1 overview ......................................................................................................1619 41.2 feature list ...................................................................................................1619 41.2.1 signal descriptions................................................................................1620 41.3 functional block diagram ................................................................................1620 41.4 usage model ..................................................................................................1622 41.4.1 channel mapping ..................................................................................1622 41.5 functional description.....................................................................................1622 41.5.1 ieee 1588 overview ..............................................................................1622 41.5.1.1 initialization ..................................................................................1623 41.5.1.2 time synchronization .....................................................................1623 41.5.1.3 ptp message formats .....................................................................1628 41.5.2 time stamping operation.......................................................................1629 41.5.2.1 sync messages ..............................................................................1630 41.5.2.2 follow-up messages .......................................................................1630 41.5.2.3 delay_req message .......................................................................1630 41.5.2.4 delay_response messages ..............................................................1631 41.5.2.5 error handling ...............................................................................1631 41.5.3 ieee1588 over ethernet .........................................................................1631 41.5.3.1 timestamping mechanism ...............................................................1631 41.5.3.2 ptp message detection in ethernet frames........................................1632 41.5.3.3 modes of operation ........................................................................1633
contents intel ? ep80579 integrated processor product line datasheet august 2009 46 order number: 320066-003us 41.5.4 ieee1588 over can .............................................................................. 1634 41.5.5 auxiliary snapshots .............................................................................. 1635 41.5.6 target time expiration .......................................................................... 1636 41.5.7 system time........................................................................................ 1636 41.5.8 interrupts............................................................................................ 1637 41.5.9 reset ................................................................................................. 1637 41.6 register summary ......................................................................................... 1637 41.6.1 detailed register descriptions ................................................................ 1639 41.6.1.1 offset 0000h: ts_control - time sync control register ...................... 1639 41.6.1.2 offset 0004h: ts_event - time sync event register .......................... 1641 41.6.1.3 offset 0008h: ts_addend - addend register..................................... 1643 41.6.1.4 offset 000ch: ts_accum - accumulator register ............................... 1643 41.6.1.5 offset 0010h: ts_test - time sync test register .............................. 1644 41.6.1.6 offset 0014h: ts_pps - pps compare register.................................. 1646 41.6.1.7 offset 0018h: ts_tsystimelo - raw system time low register ......... 1647 41.6.1.8 offset 001ch: ts_rsystimehi - raw system time high register ........ 1648 41.6.1.9 offset 0020h: ts_systimelo - system time low register .................. 1649 41.6.1.10 offset 0024h: ts_systimehi - system time high register.................. 1650 41.6.1.11 offset 0028h: ts_trgtlo - target time low register ......................... 1650 41.6.1.12 offset 002ch: ts_trgthi - target time high register......................... 1651 41.6.1.13 offset 0030h: ts_asmlo - auxiliary slave mode snapshot low register................................................................................. 1652 41.6.1.14 offset 0034h: ts_asmhi - auxiliary slave mode snapshot high register............................................................................... 1653 41.6.1.15 offset 0038h: ts_ammslo - auxiliary master mode snapshot low register................................................................................. 1654 41.6.1.16 offset 003ch: ts_ammshi - auxiliary master mode snapshot high register . 1655 41.6.1.17 offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel) ...................................................... 1656 41.6.1.18 offset 0044h: ts_ch_event[0-7] - time synchronization channel event register (per ethernet channel) ...................................................... 1658 41.6.1.19 offset 0048h: ts_txsnaplo[0-7] - transmit snapshot low register (per ethernet channel) ......................................................................... 1659 41.6.1.20 offset 004ch: ts_txsnaphi[0-7] - transmit snapshot high register (per ethernet channel) ......................................................................... 1660 41.6.1.21 offset 0050h: ts_rxsnaplo[0-7] - receive snapshot low register (per ethernet channel) ......................................................................... 1661 41.6.1.22 offset 0054h: ts_rxsnaphi[0-7] - receive snapshot high register (per ethernet channel) ......................................................................... 1662 41.6.1.23 offset 0058h: ts_srcuuidlo[0-7] - source uuid0 low register (per ethernet channel) ......................................................................... 1663 41.6.1.24 offset 005ch: ts_srcuuidhi[0-7] - sequenceid/sourceuuid high register (per ethernet channel) .................................................................. 1664 41.6.1.25 offset 0140h: ts_canx_status[0-1] - time synchronization channel event register (per can channel) ............................................................ 1665 41.6.1.26 offset 0144h: ts_cansnaplo[0-1] - transmit snapshot low register (per can channel) ............................................................................... 1666 41.6.1.27 offset 0148h: ts_cansnaphi[0-1] - transmit snapshot high register (per can channel) ............................................................................... 1667 41.6.1.28 offset 01f0h: ts_aux_trgtlo - auxiliary target time low register ....................................................................................... 1668 41.6.1.29 offset 01f4h: ts_aux_trgthi -auxiliary target time high register ....................................................................................... 1668 41.6.1.30 offset 0200h: l2_ethertype - l2 ethertype register ......................... 1669 41.6.1.31 offset 0204h: ud_ethertype - user defined ethertype register .......... 1669 41.6.1.32 offset 0208h: ud_header_offset - user defined header offset register ....................................................................................... 1670 41.6.1.33 offset 020ch: ud_header - user defined header register .................. 1670
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 47 contents 42.0 local expansion bus controller .............................................................................1671 42.1 overview ......................................................................................................1671 42.2 feature list ...................................................................................................1671 42.3 block diagram ...............................................................................................1672 42.4 theory of operation........................................................................................1672 42.4.1 outbound transfers...............................................................................1672 42.4.1.1 chip select address allocation .........................................................1673 42.4.1.2 address and data byte steering ......................................................1675 42.4.1.3 expansion bus interface configuration..............................................1676 42.4.1.4 using i/o wait ..............................................................................1680 42.4.1.5 parity ...........................................................................................1681 42.4.1.6 special design knowledge for using hpi mode ...................................1681 42.4.1.7 expansion bus outbound timing diagrams ........................................1682 42.5 register summary..........................................................................................1696 42.5.1 timing and control registers ..................................................................1698 42.5.1.1 exp_timing_cs0 - expansion bus timing register ............................1698 42.5.1.2 exp_timing_cs[1-7] - expansion bus timing registers .....................1700 42.5.2 configuration and status registers ..........................................................1702 42.5.2.1 exp_cnfg0 - configuration register 0..............................................1702 42.5.2.2 exp_parity_status - expansion bus parity status register...............1703 42.6 performance estimation ..................................................................................1703 test and debug, volume 5 of 6 .................................................. 1707 43.0 global design for test features ............................................................................1709 43.1 jtag ...........................................................................................................1709 43.1.1 jtag functions overview ......................................................................1709 43.1.2 ep80579 tap controllers ........................................................................1709 43.1.2.1 ia-32 core....................................................................................1709 43.1.2.2 mch tap extension ........................................................................1709 43.1.3 ep80579 jtag id codes.........................................................................1710 43.1.4 special requirements and limitations ......................................................1710 43.1.5 jtag instructions summary: mch ...........................................................1710 43.2 i/o testing ...................................................................................................1713 43.2.1 jtag boundary scan .............................................................................1713 43.2.1.1 pins excluded from boundary scan chain ..........................................1713 44.0 ia-32 core ............................................................................................................1715 44.1 jtag ............................................................................................................1715 44.1.1 usage..................................................................................................1715 44.1.1.1 description ...................................................................................1716 45.0 imch design for test ............................................................................................1717 45.1 imch design for test features .......................................................................1717 45.1.1 features .............................................................................................1717 45.2 jtag ............................................................................................................1717 45.2.1 imch jtag instructions .........................................................................1717 45.2.1.1 jtag chain details.........................................................................1717 45.3 high speed i/o testing ...................................................................................1719 46.0 ich design for test ..............................................................................................1721 46.1 jtag ............................................................................................................1721 46.2 i/o test mode................................................................................................1721 46.2.1 test mode entry methods .......................................................................1721 46.2.1.1 non-functional test mode entry.......................................................1721 46.2.2 test mode registers ..............................................................................1723 46.2.2.1 test0 - test control register 0 .......................................................1723
contents intel ? ep80579 integrated processor product line datasheet august 2009 48 order number: 320066-003us 46.2.3 xor chains ........................................................................................ 1725 technical specifications, volume 6 of 6 ..................................... 1727 47.0 skus, power savings and pre-boot firmware ...................................................... 1729 47.1 overview ...................................................................................................... 1729 47.2 skus, strap options and pre-boot firmware programmable configuration modes ... 1729 47.2.1 sku features ....................................................................................... 1729 47.2.2 ddr2 frequencies supported by the ep80579 .......................................... 1731 47.2.3 strap options (platform-based configuration)........................................... 1731 47.2.4 pre-boot firmware programmable sku options ........................................ 1732 48.0 package specifications ......................................................................................... 1733 48.1 package introduction ..................................................................................... 1733 48.2 functional signal definitions............................................................................ 1733 48.3 jtag boundary scan chain (bsc) and xor chain .............................................. 1733 48.4 signal pin descriptions ................................................................................... 1734 48.4.1 ia-32 core .......................................................................................... 1736 48.4.1.1 thermal diode .............................................................................. 1736 48.4.1.2 global clock cru .......................................................................... 1736 48.4.1.3 sideband miscellaneous signals....................................................... 1737 48.4.2 integrated memory controller hub (imch) ............................................... 1739 48.4.2.1 imch reset .................................................................................. 1739 48.4.2.2 ddr2 sdram ............................................................................... 1739 48.4.2.3 pci express* ................................................................................ 1741 48.4.3 integrated i/o controller hub (iich)....................................................... 1744 48.4.3.1 real time clock ............................................................................ 1744 48.4.3.2 general purpose i/o (gpio) and interrupts ...................................... 1744 48.4.3.3 serial peripheral interface (spi) ...................................................... 1749 48.4.3.4 low pin count (lpc) interface......................................................... 1749 48.4.3.5 smbus ......................................................................................... 1750 48.4.3.6 uart interface ............................................................................. 1751 48.4.3.7 serial ata (sata) interface ............................................................ 1753 48.4.3.8 universal serial bus (usb) interface ................................................ 1755 48.4.3.9 power management interface.......................................................... 1756 48.4.3.10 iich miscellaneous signals ............................................................. 1758 48.4.4 acceleration and i/o complex (aioc)...................................................... 1759 48.4.4.1 controller area network (can) bus.................................................. 1759 48.4.4.2 gigabit ethernet (gbe) interface ..................................................... 1760 48.4.4.3 time division multiplexing (tdm) interface ....................................... 1764 48.4.4.4 local expansion bus (leb) interface ................................................ 1765 48.4.4.5 synchronous serial port (ssp) interface........................................... 1768 48.4.4.6 ieee 1588-2008 hardware assist interface ....................................... 1768 48.4.5 miscellaneous....................................................................................... 1769 48.4.5.1 jtag ........................................................................................... 1769 48.4.5.2 miscellaneous signals .................................................................... 1770 48.4.5.3 reserved ..................................................................................... 1770 48.4.5.4 no connect .................................................................................. 1771 48.4.6 power ................................................................................................. 1772 48.5 flip-chip ball grid array (fcbga) package dimensions ....................................... 1773 48.6 ball map information ...................................................................................... 1778 49.0 electrical specifications ....................................................................................... 1819 49.1 absolute maximum ratings ............................................................................. 1820 49.1.1 input and i/o pin undershoot and overshoot specifications........................ 1820 49.2 power characteristics ..................................................................................... 1823 49.2.1 power supply requirements................................................................... 1823
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 49 contents 49.3 clocks ..........................................................................................................1829 49.3.1 external clock requirements ..................................................................1829 49.4 power and reset sequencing ...........................................................................1830 49.5 ac/dc characteristics .....................................................................................1831 49.5.1 power management ...............................................................................1831 49.5.1.1 power management signal list ........................................................1831 49.5.1.2 power management ac characteristics..............................................1832 49.5.2 ddr2 ..................................................................................................1836 49.5.2.1 ddr2 signal list............................................................................1836 49.5.2.2 ddr2 dc characteristics.................................................................1836 49.5.2.3 ddr2 ac characteristics .................................................................1838 49.5.3 pci express* ........................................................................................1846 49.5.3.1 pci express* signal list .................................................................1846 49.5.3.2 pci express* differential transmitter and receiver specifications.........1846 49.5.3.3 pci express* clock specifications ....................................................1850 49.5.4 serial ata (sata) .................................................................................1854 49.5.4.1 sata signal list ............................................................................1854 49.5.4.2 sata dc characteristics .................................................................1854 49.5.4.3 sata dc output characteristics.......................................................1855 49.5.4.4 sata led .....................................................................................1855 49.5.4.5 sata ac characteristics .................................................................1856 49.5.5 universal serial bus (usb) .....................................................................1856 49.5.5.1 usb signal list ..............................................................................1856 49.5.5.2 usb dc characteristics...................................................................1857 49.5.5.3 usb ac characteristics ...................................................................1859 49.5.5.4 usb ac specifications ....................................................................1859 49.5.6 system management bus (smbus) ..........................................................1863 49.5.6.1 smbus signal list ..........................................................................1863 49.5.6.2 smbus dc characteristics ...............................................................1863 49.5.6.3 smbus ac characteristics ...............................................................1864 49.5.7 uart...................................................................................................1867 49.5.7.1 uart signal list ............................................................................1867 49.5.7.2 uart dc characteristics .................................................................1867 49.5.7.3 uart ac characteristics .................................................................1868 49.5.7.4 uart receiver ac specifications ......................................................1868 49.5.8 serial peripheral interface (spi) ..............................................................1869 49.5.8.1 spi signal list ...............................................................................1869 49.5.8.2 spi dc characteristics ....................................................................1869 49.5.8.3 spi ac characteristics ....................................................................1869 49.5.9 low pin count (lpc) ..............................................................................1870 49.5.9.1 lpc signal list ..............................................................................1870 49.5.9.2 lpc dc characteristics ...................................................................1871 49.5.9.3 lpc ac characteristics....................................................................1872 49.5.10 general purpose i/o (gpio) ...................................................................1874 49.5.10.1 gpio signal list ............................................................................1874 49.5.10.2 gpio dc characteristics .................................................................1874 49.5.10.3 gpio ac specifications ...................................................................1875 49.5.11 iich interrupt signal .............................................................................1875 49.5.11.1 iich interrupt signal list ................................................................1875 49.5.11.2 iich interrupt signal dc characteristics ...........................................1875 49.5.11.3 iich interrupt signal ac input, output characteristics........................1876 49.5.11.4 iich interrupt signal timing specification .........................................1876 49.5.11.5 iich clock ac specifications............................................................1876 49.5.12 real time clock (rtc) ...........................................................................1877 49.5.12.1 rtc signal list ..............................................................................1877 49.5.12.2 rtc dc characteristics ...................................................................1877 49.5.12.3 rtc ac characteristics ...................................................................1878
contents intel ? ep80579 integrated processor product line datasheet august 2009 50 order number: 320066-003us 49.5.13 gigabit ethernet (gbe: rmii, rgmii, mdio, eeprom) ............................... 1879 49.5.13.1 gigabit ethernet signal list ............................................................ 1879 49.5.13.2 gigabit ethernet dc characteristics ................................................. 1879 49.5.13.3 gigabit ethernet ac characteristics.................................................. 1882 49.5.13.4 gbe reset conditions .................................................................... 1890 49.5.13.5 rcomp ........................................................................................ 1890 49.5.13.6 voltage domains ........................................................................... 1891 49.5.14 time division multiplex (tdm) ................................................................ 1891 49.5.14.1 tdm signal list ............................................................................. 1891 49.5.14.2 tdm dc characteristics .................................................................. 1891 49.5.14.3 tdm dc clock specification ............................................................ 1892 49.5.14.4 tdm ac characteristics .................................................................. 1893 49.5.15 local expansion bus (leb) ..................................................................... 1894 49.5.15.1 leb signal list .............................................................................. 1894 49.5.15.2 leb dc characteristics ................................................................... 1895 49.5.15.3 leb ac characteristics ................................................................... 1896 49.5.16 controller area network (can) ............................................................... 1897 49.5.16.1 can signal list ............................................................................. 1897 49.5.16.2 can dc characteristics .................................................................. 1897 49.5.17 synchronous serial port (ssp)................................................................ 1897 49.5.17.1 ssp signal list.............................................................................. 1897 49.5.17.2 ssp dc characteristics................................................................... 1898 49.5.17.3 ssp ac characteristics ................................................................... 1900 49.5.18 ieee 1588-2008 hardware assist interface .............................................. 1901 49.5.18.1 ieee 1588-2008 hardware assist signal list ..................................... 1901 49.5.18.2 ieee 1588-2008 hardware assist dc characteristics .......................... 1901 49.5.18.3 ieee 1588-2008 hardware assist ac characteristics ......................... 1901 49.5.19 iich miscellaneous signals (pme#, pcirst#, spkr) ................................. 1901 49.5.19.1 iich miscellaneous signal list ......................................................... 1901 49.5.19.2 iich miscellaneous signals dc characteristics ................................... 1902 49.5.19.3 iich miscellaneous signals ac characteristics ................................... 1902 49.5.20 clock resource unit (cru)..................................................................... 1902 49.5.20.1 cru signal list ............................................................................. 1902 49.5.20.2 cru dc characteristics .................................................................. 1903 49.5.20.3 cru ac specifications .................................................................... 1904 49.5.21 sideband miscellaneous signals .............................................................. 1905 49.5.21.1 sideband miscellaneous signals signal list ....................................... 1905 49.5.21.2 sideband miscellaneous signals dc characteristics ............................ 1905 49.5.21.3 sideband miscellaneous signals ac characteristics............................. 1906 49.5.22 imch reset ......................................................................................... 1906 49.5.22.1 imch reset signal list ................................................................... 1906 49.5.22.2 imch reset signals dc characteristics ............................................. 1906 49.5.22.3 imch reset signals ac characteristics ............................................. 1906 49.5.23 jtag................................................................................................... 1907 49.5.23.1 jtag signal list ............................................................................ 1907 49.5.23.2 jtag dc characteristics ................................................................ 1907 49.5.23.3 jtag ac characteristics ................................................................. 1907 50.0 thermal specifications and design considerations ............................................... 1911 50.1 thermal characteristics .................................................................................. 1911 50.1.1 specifications....................................................................................... 1912 50.1.2 thermal design power (tdp) dissipation.................................................. 1912 50.2 thermal sensor ............................................................................................. 1912 50.2.1 catastrophic thermal protection ............................................................. 1913 50.2.1.1 thrmtrip# control sequence ........................................................ 1913 50.2.2 thermal sensor features ....................................................................... 1914 50.2.2.1 prochot# control sequence ......................................................... 1914
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 51 contents 50.2.2.2 processor passive cooling ...............................................................1915 50.2.2.3 on-demand passive cooling ............................................................1915 figures 2-1 intel ? ep80579 integrated processor block diagram ............................................. 104 2-2 intel ? ep80579 integrated processor with intel? quickassist technology block diagram................................................................................. 105 3-1 device-centric logical view of ep80579 devices ................................................... 112 3-2 logical overview of the cmi pci infrastructure..................................................... 115 3-3 attaching the aioc to the cmi pci fabric (logical perspective) .............................. 120 3-4 overview of pci infrastructure for on-die devices................................................. 121 4-1 logical overview of signaling architecture ........................................................... 131 4-2 logical view of signaling flow ............................................................................ 134 4-3 signal bridging ................................................................................................ 135 6-1 powergood and reset interface .......................................................................... 164 6-2 reset sequence ............................................................................................... 167 6-3 ep80579 rail power on sequence ...................................................................... 169 6-4 power rail sequence timings (sustain well power management) ............................ 170 6-5 power rail sequence timing (no sustain well power management)......................... 171 6-6 powergood reset sequence ............................................................................... 172 6-7 hard reset sequence........................................................................................ 173 6-8 bios boot flow (cold boot, s3/s4->s0) ............................................................. 175 6-9 global system power states and transitions ........................................................ 177 9-1 cmi block diagram ........................................................................................... 255 10-1 basic memory regions ...................................................................................... 267 10-2 dos legacy region .......................................................................................... 269 10-3 memory region from 1 mbyte through 4 gbytes ................................................... 271 10-4 pam associated attribute bits............................................................................. 273 11-1 memory address tables for 64 bit, burst size 4 and x8 ddr2 devices ..................... 296 11-2 memory address tables for 32 bit, burst size 8 and x8 ddr2 devices ..................... 296 11-3 2t and 1t timing mode..................................................................................... 297 11-4 odt timing on back-to-back reads to different slots ........................................... 300 11-5 odt timing on back-to-back writes to different slots ........................................... 301 12-1 concept diagram of edma data path .................................................................. 308 12-2 conceptual diagram of four channel edma engine ............................................... 310 12-3 chain descriptor in memory ............................................................................... 312 12-4 chaining mechanism ......................................................................................... 313 12-5 source and destination in increment mode transfer.............................................. 319 12-6 source in decrement and destination in increment mode transfer (byte reversal).... 320 12-7 source in increment and destination in 1-byte granularity constant mode transfer .. 321 12-8 source in increment and destination in 2-byte granularity constant mode transfer .. 322 12-9 source in increment and destination in 4-byte granularity constant mode transfer .. 323 12-10 source in decrement and destination in 1-byte granularity constant mode transfer . 324 12-11 source in decrement and destination in 2-byte granularity constant mode transfer . 325 12-12 source in decrement and destination in 4-byte granularity constant mode transfer . 326 12-13 source in memory initialization and destination in increment mode transfer ............ 327 12-14 source in buffer initialization and destination in 1-byte granularity constant mode transfer .......................................................................................................... 328 12-15 source in buffer initialization and destination in 2-byte granularity constant mode transfer .......................................................................................................... 328 12-16 source in buffer initialization and destination in 4-byte granularity constant mode transfer .......................................................................................................... 329 12-17 initiation flow chart ......................................................................................... 343 12-18 completion flow chart ...................................................................................... 344
contents intel ? ep80579 integrated processor product line datasheet august 2009 52 order number: 320066-003us 13-1 bus 0 device map ............................................................................................. 348 13-2 nsi type 0 configuration address translation ...................................................... 350 13-3 nsi type 1 configuration address translation ...................................................... 351 13-4 mechanism #1 type 1 configuration address to pci address mapping...................... 351 13-5 imch configuration flow chart ........................................................................... 352 13-6 pci express configuration transaction header ...................................................... 356 13-7 enhanced configuration memory address map ...................................................... 357 14-1 global ferr/nerr register representation .......................................................... 362 14-2 ferr/nerr service routine ............................................................................... 364 14-3 pci express error handling ................................................................................ 368 15-1 dword configuration read protocol ..................................................................... 377 15-2 dword configuration write protocol ..................................................................... 377 15-3 dword memory read protocol ............................................................................. 377 15-4 dword memory write protocol ............................................................................ 377 15-5 dword configuration read protocol ..................................................................... 378 15-6 dword configuration write protocol ..................................................................... 378 15-7 dword memory read protocol ............................................................................. 379 15-8 dword configuration write protocol ..................................................................... 379 19-1 lpc interface diagram ...................................................................................... 758 19-2 lpc bridge serr# ........................................................................................... 762 20-1 iich dma controller.......................................................................................... 763 20-2 dma request assertion through ldrq#............................................................... 780 21-1 basic spi protocol ............................................................................................. 787 23-1 legacy mode host controller power state hierarchy .............................................. 880 23-2 hardware flow for port enable/device present bits................................................ 883 23-3 port system memory structure ........................................................................... 884 23-4 power state hierarchy ....................................................................................... 890 25-1 example queue conditions................................................................................. 967 25-2 usb data encoding ........................................................................................... 970 26-1 usb port connections...................................................................................... 1033 27-1 c0 c2 c0 entry/exit timings......................................................................... 1081 28-1 coprocessor error timing diagram .................................................................... 1103 33-1 example uart data frame .............................................................................. 1173 33-2 wdt block diagram ........................................................................................ 1193 33-3 start frame timing with source sampled a low pulse on irq1 ............................. 1203 33-4 stop frame timing with host using quiet mode sampling period........................... 1203 35-1 pci configuration command register layout ...................................................... 1234 35-2 pci configuration status register layout ........................................................... 1234 35-3 pci power management register block .............................................................. 1236 37-1 gbe controller block diagram........................................................................... 1344 37-2 gbe ethernet complex .................................................................................... 1345 37-3 multicast table array algorithm ........................................................................ 1349 37-4 example address byte ordering........................................................................ 1352 37-5 da byte ordering ........................................................................................... 1352 37-6 receive descriptor (rdesc) layout................................................................... 1355 37-7 receive status (rdesc.status) layout .............................................................. 1356 37-8 receive errors (rdesc.errors) layout ............................................................ 1357 37-9 special descriptor field layout ......................................................................... 1358 37-10 receive descriptor ring structure ..................................................................... 1359 37-11 packet delay timer operation illustrated with a state diagram............................... 1361 37-12 case a: using only an absolute timer ............................................................... 1361 37-13 case b: using an absolute timer in conjunction with the packet timer................... 1362 37-14 case c: packet timer expires even though a packet was being transferred to the host memory. ....................................................................................... 1362 37-15 ipv6 extension header structure ...................................................................... 1364
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 53 contents 37-16 transmit descriptor (tdesc) layout ..................................................................1366 37-17 legacy transmit descriptor (tdesc) layout .......................................................1366 37-18 transmit command (tdesc.cmd) layout...........................................................1367 37-19 transmit status layout (tdesc.status) ...........................................................1368 37-20 transmit special field layout (tdesc.special) ..................................................1369 37-21 tcp/ip context transmit descriptor (tdesc) - (type = 0000)...............................1370 37-22 tcp/ip context transmit descriptor command field (tdesc.tucmd).....................1371 37-23 tcp/ip context transmit descriptor status (tdesc.tustatus).............................1372 37-24 tcp/ip data transmit descriptor layout (tdesc) - (type = 0001).........................1373 37-25 tcp/ip data transmit descriptor command field (tdesc.dcmd) ..........................1373 37-26 tcp/ip data transmit descriptor status (tdesc.dstatus) ..................................1375 37-27 tcp/ip data transmit descriptor packet options field (tdesc.popts) ...................1375 37-28 tcp/ip data transmit descriptor special field (tdesc.vlan) ................................1375 37-29 transmit descriptor ring structure ....................................................................1376 37-30 transmit descriptor and tucmd field (tdesc) layouts - (type = 0000) ................1380 37-31 tcp/ip packet format ......................................................................................1382 37-32 tcp/ip context transmit descriptor & command layout.......................................1383 37-33 tcp partial pseudo-header checksum for ipv4 ....................................................1384 37-34 tcp partial pseudo-header checksum for ipv6 ....................................................1384 37-35 ipv4 header (traditional representation) ...........................................................1385 37-36 ipv4 header (little-endian order)......................................................................1385 37-37 ipv6 header (traditional representation) ...........................................................1385 37-38 tcp header (traditional representation) ............................................................1386 37-39 tcp header (little-endian order) ......................................................................1386 37-40 tcp pseudo header content (traditional representation)......................................1387 37-41 tcp pseudo-header content for ipv6 .................................................................1387 37-42 udp header (traditional representation)............................................................1387 37-43 udp header (little-endian order) ......................................................................1387 37-44 udp pseudo header diagram for ipv4 ................................................................1388 37-45 udp pseudo-header diagram for ipv6 ................................................................1388 37-46 data flow.......................................................................................................1391 37-47 802.3x mac control frame format ....................................................................1398 37-48 tci bit ordering ..............................................................................................1401 37-49 memory protection in the gbe ...........................................................................1419 37-50 power state transitions ...................................................................................1550 37-51 reset deasserted after 1st eeprom read completes............................................1552 37-52 reset deasserted after before eeprom read completes .......................................1553 37-53 transition from d0a to d3 and back without reset...............................................1554 37-54 transition from d0a to d3 and back with reset ...................................................1555 37-55 reset without transition to d3 ..........................................................................1556 39-1 can block diagram .........................................................................................1570 39-2 standard can data frame................................................................................1572 39-3 extended can data frame ...............................................................................1574 39-4 standard can remote frame............................................................................1575 39-5 extended can remote frame ...........................................................................1576 39-6 can timing parameters ...................................................................................1578 39-7 bit rate and time settings ...............................................................................1579 39-8 receive message handler .................................................................................1581 39-9 message arbitration .........................................................................................1584 41-1 programming model.........................................................................................1621 41-2 example network topology...............................................................................1623 41-3 clock synchronization ......................................................................................1625 41-4 transparent clock switch protocol flow ..............................................................1627 41-5 time stamp reference point .............................................................................1632 42-1 expansion bus controller..................................................................................1672
contents intel ? ep80579 integrated processor product line datasheet august 2009 54 order number: 320066-003us 42-2 chip select address allocation when there are no 32-mbyte devices programmed.. 1674 42-3 expansion bus memory sizing .......................................................................... 1674 42-4 chip select address allocation when a 32 mbyte device is programmed ................. 1675 42-5 expansion bus i/o wait operation .................................................................... 1681 42-6 expansion-bus write (intel, multiplexed mode) ................................................... 1683 42-7 expansion-bus read (intel, multiplexed mode).................................................... 1683 42-8 expansion-bus write (intel-simplex mode, synchronous intel) ............................. 1684 42-9 expansion-bus read (intel, simplex mode) ........................................................ 1684 42-10 intel synchronous 8-word read ........................................................................ 1685 42-11 intel synchronous one-word read.................................................................... 1686 42-12 micron* zbt write/read/write ......................................................................... 1687 42-13 expansion-bus write (motorola*, multiplexed mode) ............................................ 1688 42-14 expansion-bus read (motorola*, multiplexed mode) ............................................ 1689 42-15 expansion-bus write (motorola*, simplex mode)................................................. 1690 42-16 expansion-bus read (motorola*, simplex mode) ................................................. 1690 42-17 expansion-bus write (ti* hpi-8 mode) .............................................................. 1691 42-18 expansion-bus read (ti* hpi-8 mode) .............................................................. 1692 42-19 expansion-bus write (ti* hpi-16, multiplexed mode) .......................................... 1693 42-20 expansion-bus read (ti* hpi-16, multiplexed mode) ........................................... 1694 42-21 expansion-bus write (ti* hpi-16, simplex mode) ............................................... 1695 42-22 expansion-bus read (ti* hpi-16, simplex mode)................................................ 1696 46-1 serial test mode entry for write ....................................................................... 1722 46-2 serial test mode entry for read ........................................................................ 1722 48-1 fcbga package ? top and side views .............................................................. 1775 48-2 fcbga package ? front and detail views .......................................................... 1776 48-3 fcbga package ? bottom view........................................................................ 1777 49-1 g3 (mechanical off) to s0 timings .................................................................... 1834 49-2 s0 to s1 to s0 timing ..................................................................................... 1834 49-3 s0 to s5 to s0 timings, s3 cold ........................................................................ 1835 49-4 dq and cb (ecc) setup/hold relationship to/from dqs (read operation) .............. 1843 49-5 dq and cb (ecc) valid before and after dqs (write operation)............................ 1843 49-6 write preamble duration.................................................................................. 1844 49-7 write postamble duration ................................................................................ 1844 49-8 control signals valid before and after ddr_ck rising edge .................................. 1844 49-9 clock cycle time ............................................................................................ 1844 49-10 skew between any system memory differential clock pair (ddr_ck/ddr_ck#) ..... 1845 49-11 ddr2 command clock high time ..................................................................... 1845 49-12 ddr2 command clock low time ...................................................................... 1845 49-13 ddr2 command clock to dqs skew.................................................................. 1846 49-14 pci express* transmitter test load .................................................................. 1851 49-15 pci express* receiver compliance eye diagram ................................................. 1851 49-16 pci express* transmitter compliance eye diagram ............................................. 1852 49-17 differential clock waveform ............................................................................. 1853 49-18 differential clock cross-point specification ......................................................... 1853 49-19 clock timing .................................................................................................. 1860 49-20 usb rise and fall times .................................................................................. 1861 49-21 usb jitter ...................................................................................................... 1862 49-22 usb eop width .............................................................................................. 1862 49-23 smbus transaction ......................................................................................... 1865 49-24 smbus timeout .............................................................................................. 1866 49-25 spi timing diagram ........................................................................................ 1870 49-26 lpc clock (pciclk) timing diagram.................................................................. 1872 49-27 lpc input setup and hold timing diagram ......................................................... 1873 49-28 lpc valid delay from rising clock edge diagram................................................. 1873 49-29 lpc output enable delay diagram .................................................................... 1873
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 55 contents 49-30 lpc float delay diagram ..................................................................................1874 49-31 iich interrupt signal timing diagram ................................................................1876 49-32 iich clock (clk14) timing diagram ..................................................................1877 49-33 rtc clock output (susclk) timing diagram ......................................................1878 49-34 gbe rgmii mode signal connection block diagram ..............................................1883 49-35 rgmii 125 mhz reference clock timing diagram ................................................1884 49-36 gbe transmit waveform ? rgmii mode .............................................................1885 49-37 gbe receive waveform ? rgmii mode ..............................................................1886 49-38 gbe rmii mode signal connection block diagram ? external clock source .............1887 49-39 gbe rmii transmit and receive waveforms ? rmii mode ....................................1887 49-40 mdio output timing diagram (ep80579 is sourcing mdio) ..................................1888 49-41 mdio input timing diagram (phy is sourcing mdio) ...........................................1888 49-42 eeprom interface timing diagram ....................................................................1889 49-43 tdm, serial timings.........................................................................................1894 49-44 local expansion bus synchronous timing ...........................................................1896 49-45 ssp signal connection block diagram - multi-drop connections ............................1899 49-46 ssp interface timing diagram ..........................................................................1900 49-47 cru differential clock waveform.......................................................................1903 49-48 cru differential clock cross-point specification...................................................1904 49-49 jtag output timing measurement waveforms ....................................................1908 49-50 jtag input timing measurement waveforms ......................................................1909 tables 1-1 referenced documents ...................................................................................... 94 1-2 related websites ............................................................................................... 95 1-3 acronym table................................................................................................... 95 1-4 glossary table .................................................................................................. 98 2-1 ep80579 external interface summary ................................................................ 106 2-2 ia-32 core / fsb frequency ratios (depends on sku and configuration) .................. 107 2-3 memory controller frequencies .......................................................................... 107 2-4 summary of communication .............................................................................. 107 2-5 dma and peer-to-peer data transfer options ....................................................... 109 3-1 main memory dram organization ..................................................................... 112 3-2 basic cmi platform address space requirements for imch and iich devices............ 115 3-3 memory regions .............................................................................................. 116 3-4 supported operations by memory type ............................................................... 117 3-5 supported operations by memory type ............................................................... 118 3-6 device exposure from an ia-attached memory map perspective .............................. 119 3-7 address space sizes of aioc-attached devices .................................................... 119 3-8 expansion bus byte ordering for inbound transactions using lebctl register .......... 119 3-9 imch and iich pci device summary .................................................................. 122 3-10 aioc pci device summary ................................................................................ 123 3-11 pci configuration header support for type 0 headers in aioc devices ................... 125 3-12 pci configuration header support for type 1 headers in aioc devices ................... 127 4-1 supported inter-agent signaling ........................................................................ 134 5-1 summary of imch global error conditions ........................................................... 142 5-2 summary of imch buffer unit error conditions..................................................... 143 5-3 summary of imch buffer unit error reporting capabilities ..................................... 143 5-4 summary of imch fsb error conditions .............................................................. 144 5-5 summary of imch fsb error reporting capabilities .............................................. 144 5-6 summary of imch nsi error conditions .............................................................. 145 5-7 summary of imch nsi error reporting capabilities............................................... 146 5-8 summary of imch edma error conditions ........................................................... 146
contents intel ? ep80579 integrated processor product line datasheet august 2009 56 order number: 320066-003us 5-9 summary of imch edma error reporting capabilities ............................................ 147 5-10 summary of imch pci-express error conditions ................................................... 148 5-11 summary of imch pci-express error reporting capabilities.................................... 149 5-12 summary of smbus interface error conditions...................................................... 150 5-13 summary of smbus controller error reporting capabilities ..................................... 150 5-14 summary of lpc interface error conditions .......................................................... 150 5-15 summary of lpc interface error reporting capabilities .......................................... 150 5-16 summary of usb 1.1 interface error conditions.................................................... 151 5-17 summary of usb 1.1 interface error reporting capabilities .................................... 151 5-18 summary of usb 2.0 interface error conditions.................................................... 152 5-19 summary of usb 2.0 interface error reporting capabilities .................................... 152 5-20 summary of sata interface error conditions........................................................ 152 5-21 summary of sata interface error reporting capabilities ........................................ 153 5-22 summary of serial i/o interface error conditions.................................................. 153 5-23 summary of serial i/o interface error reporting capabilities .................................. 153 5-24 summary of memory controller error conditions................................................... 154 5-25 summary of memory controller error reporting capabilities ................................... 155 5-26 summary of gigabit ethernet mac error conditions............................................... 156 5-27 summary of gigabit ethernet mac error reporting capabilities ............................... 156 5-28 summary of can error conditions....................................................................... 157 5-29 summary of can error reporting capabilities ....................................................... 157 5-30 summary of ssp error conditions ....................................................................... 158 5-31 summary of ssp error reporting capabilities ....................................................... 158 5-32 summary of local expansion bus error conditions ................................................ 158 5-33 summary of local expansion bus error reporting capabilities................................. 159 6-1 types of reset and wake-up from power saving states ......................................... 161 6-2 power wells and external voltages ...................................................................... 162 6-3 ep80579 power supply pins ............................................................................... 168 6-4 power rail sequence signal timings.................................................................... 171 6-5 powergood reset timings .................................................................................. 173 6-6 hard reset timings........................................................................................... 174 6-7 global power states .......................................................................................... 178 6-8 device states................................................................................................... 178 6-9 sleeping states ................................................................................................ 179 6-10 cpu states ...................................................................................................... 179 6-11 acpi states ..................................................................................................... 180 6-12 power wells status for supported acpi states* .................................................... 180 7-1 definition of the views used in register description tables..................................... 184 7-2 view convention to describe single versus multiple physical registers ..................... 185 7-3 offset convention to describe multiple physical registers in the same device ........... 186 7-4 eg_single: example single register with different views ..................................... 187 7-5 eg_multi_diff: example multiple registers in different devices with different views.............................................................................................................. 187 7-6 eg_multi_same[1-2]: example multiple registers in same device with different views.............................................................................................................. 188 7-7 eg_index: example single indexed register ....................................................... 188 7-8 register field access attributes .......................................................................... 189 7-9 bus 0, device 0, function 0: summary of imch pci configuration registers ............. 191 7-10 bus 0, device 0, function 0: summary of imch configuration registers mapped through nsibar memory bar ........................................................................................ 192 7-11 bus 0, device 0, function 0: summary of imch smrbase registers ........................ 193 7-12 bus 0, device 0, function 1: summary of imch error reporting pci configuration registers ......................................................................................................... 195 7-13 bus 0, device 1, function 0: summary of edma pci configuration registers ............ 197
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 57 contents 7-14 bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar ................................................................................... 197 7-15 bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers ..................................................................................... 200 7-16 bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers ..................................................................................... 203 7-17 bus 0, device 29, functions 0, summary of usb (1.1) controller pci configuration registers ........................................................................................................ 206 7-18 summary of usb (1.1) controller configuration registers mapped through usbiobar i/o bar .......................................................................................................... 206 7-19 bus 0, device 29, function 7: summary of usb (2.0) controller pci configuration registers ........................................................................................................ 207 7-20 bus 0, device 29, function 7: summary of usb (2.0) controller configuration registers mapped through mbar memory bar .................................................................. 208 7-21 bus 0, device 31, function 0: summary of root complex configuration registers mapped through rcba memory bar............................................................................... 209 7-22 bus 0, device 31, function 0: summary of lpc interface pci configuration registers 210 7-23 bus 0, device 31, function 0: summary of lpc interface power management pci configuration registers ..................................................................................... 211 7-24 bus 0, device 31, function 0: summary of tco configuration registers mapped through tcobase i/o bar?........................................................................................... 211 7-25 bus 0, device 31, function 0: summary of lpc interface power management general configuration registers mapped through pmbase i/o bar .................................... 211 7-26 bus 0, device 31, function 0: summary of general purpose i/o configuration registers mapped through gba bar io bar...................................................................... 212 7-27 bus 0, device 31, function 2: summary of sata controller pci configuration registers ........................................................................................................ 213 7-28 bus 0, device 31, function 2: summary of sata controller configuration registers mapped through lbar i/o bar.......................................................................... 214 7-29 bus 0, device 31, function 2: summary of sata controller configuration registers mapped through abar memory bar ................................................................... 214 7-30 bus 0, device 31, function 3: summary of smbus controller pci configuration registers ........................................................................................................ 216 7-31 bus 0, device 31, function 3: summary of smbus controller configuration registers mapped through sm_base i/o bar.................................................................... 216 7-32 summary of ia-32 core interface registers mapped in i/o space ........................... 217 7-33 summary of imch pci configuration registers mapped in i/o space ....................... 217 7-34 summary of apic registers mapped in memory space? ......................................... 217 7-35 summary of apic indexed registers................................................................... 218 7-36 summary of 8259 interrupt controller (pic) registers mapped in i/o space ............ 219 7-37 summary of apm registers mapped in i/o space.................................................. 219 7-38 summary of lpc dma registers mapped in i/o space ........................................... 220 7-39 0000h (io) base address registers in the ia f1 view ............................................ 220 7-40 0000h (io) base address registers in the ia f2 view ............................................ 221 7-41 summary of 8254 timer registers mapped in i/o space........................................ 221 7-42 summary of hpet registers mapped in memory space .......................................... 222 7-43 summary of uart timer registers in i/o space .................................................... 222 7-44 summary of watchdog timer registers in i/o space............................................. 223 7-45 summary of real time clock indexed registers ................................................... 223 7-46 bus 0, device 4, function 0: summary of pci-to-pci bridge pci configuration registers ........................................................................................................ 224 7-47 bus m, device 0, function 0: summary of gigabit ethernet mac interface pci configuration registers ..................................................................................... 226 7-48 bus m, device 1, function 0: summary of gigabit ethernet mac interface pci configuration registers ..................................................................................... 227
contents intel ? ep80579 integrated processor product line datasheet august 2009 58 order number: 320066-003us 7-49 bus m, device2, function 0: summary of gigabit ethernet mac interface pci configuration registers ......................................................................................................... 228 7-50 bus m, device 0, function 0: gigabit ethernet mac i/o spaces registers ................. 229 7-51 bus m, device 1, function 0: gigabit ethernet mac i/o spaces registers ................. 229 7-52 bus m, device 2, function 0: gigabit ethernet mac i/o spaces registers ................. 229 7-53 bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar ........................................................................... 229 7-54 bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar ........................................................................... 233 7-55 bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar ........................................................................... 236 7-56 bus m, device 3, function 0: summary of gcu pci configuration registers .............. 240 7-57 bus m, device 3, function 0: summary of gcu registers mapped through csrbar memory bar .................................................................................................... 240 7-58 bus m, device 4, function 0: summary of can interface pci configuration registers. 242 7-59 bus m, devices 5, function 0: summary of can interface pci configuration registers243 7-60 bus m, device 4, function 0: summary of can registers mapped through csrbar memory bar .................................................................................................... 244 7-61 bus m, device 5, function 0: summary of can registers mapped through csrbar memory bar .................................................................................................... 244 7-62 bus m, device 6, function 0: summary of ssp controller pci configuration registers 245 7-63 bus m, device 6, function 0: summary of ssp csrs ............................................. 246 7-64 bus m, device 7, function 0: summary of ieee 1588 timestamp unit pci configuration registers ......................................................................................................... 247 7-65 bus m, device 7, function 0: summary of ieee 1588 tsync csrs .......................... 248 7-66 bus m, device 8, function 0: summary of local expansion bus pci configuration registers ......................................................................................................... 249 7-67 bus m, device 8, function 0: summary of local expansion bus registers mapped through csrbar pci memory bar"................................................................................. 250 8-1 processor version identification signature (cpuid) ............................................... 254 9-1 supported pci express configurations ................................................................ 257 10-1 regions of memory ranges ................................................................................ 267 10-2 system memory space ...................................................................................... 268 10-3 imch vga and mda memory spaces ................................................................... 268 10-4 imch pam memory address ranges .................................................................... 270 10-5 pam associated attribute bits ............................................................................ 273 10-6 tseg smm memory space ................................................................................. 274 10-7 pci express enhanced configuration aperture ...................................................... 274 10-8 ioapic memory space ...................................................................................... 275 10-9 fsb interrupt memory space.............................................................................. 275 10-10 high smm memory space................................................................................... 276 10-11 device 2 memory and prefetchable memory.......................................................... 277 10-12 device 3 memory and prefetchable memory.......................................................... 277 10-13 device 4 memory and prefetchable memory.......................................................... 277 10-14 edma accesses to fixed address spaces ............................................................. 278 10-15 edma accesses to relocatable address spaces ..................................................... 279 10-16 supported smm ranges ..................................................................................... 282 10-17 fixed i/o ranges decoded by iich .................................................................... 284 10-18 variable i/o decode ranges .............................................................................. 286 10-19 iich memory decode ranges (from ia-32 core perspective) .................................. 287 11-1 supported ddr2 device densities and width........................................................ 291 11-2 supported dram capacity for 64b mode .............................................................. 291 11-3 supported dram capacity for 32b mode .............................................................. 292 11-4 raw cards supported by the ep80579 ................................................................ 292 11-5 supported ddr2 data speeds ............................................................................ 292
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 59 contents 11-6 supported dimm populations ............................................................................. 293 11-7 supported rank configurations in single and dual dimm mode .............................. 293 11-8 256mb addressing ............................................................................................ 294 11-9 512mb addressing ............................................................................................ 294 11-10 1gb addressing................................................................................................ 294 11-11 2gb addressing................................................................................................ 295 11-12 supported dram timings .................................................................................. 296 11-13 dra mapping for dqs ....................................................................................... 298 11-14 dqs to dq mapping for x8 devices ..................................................................... 298 11-15 odt timing parameters .................................................................................. 299 11-16 supported ddr2 mr and emr settings ................................................................ 303 11-17 poisoning granularity........................................................................................ 305 12-1 channel 0 memory-mapped register set ............................................................. 332 12-2 interrupt summary ........................................................................................ 338 13-1 pci devices and functions on bus 0 ................................................................... 346 13-2 summary of imch pci configuration registers mapped in i/o space ....................... 354 13-3 offset 0cf8h: config_address: configuration address register ........................ 354 13-4 offset 0cfch: config_data: configuration data register .................................... 355 13-5 enhanced configuration fsb address format ....................................................... 357 14-1 pseudocode for edma errors ............................................................................ 369 15-1 smbus register summary ................................................................................. 372 15-2 smbus memory-mapped register summary ......................................................... 372 15-3 addr3 memory assignments ............................................................................ 372 15-4 command (cmd) register ................................................................................ 373 15-5 byte count register.......................................................................................... 374 15-6 address byte 3 register .................................................................................... 374 15-7 addr2 ? address byte 2 register....................................................................... 375 15-8 addr1 ? address byte 1 register....................................................................... 375 15-9 addr0 ? address byte 0 register....................................................................... 375 15-10 offset 04-07: data - data register .................................................................... 376 15-11 status register ................................................................................................ 376 15-12 relationship between link and device pm states .................................................. 383 16-1 bus 0, device 0, function 0: summary of imch pci configuration registers............. 389 16-2 offset 00h: vid ? vendor identification register .................................................. 391 16-3 offset 02h: did ? device identification register .................................................. 391 16-4 offset 04h: pcicmd: pci command register ...................................................... 392 16-5 offset 06h: pcists: pci status register ........................................................... 393 16-6 offset 8h: rid - revision identification register ................................................. 394 16-7 offset 0ah: subc - sub-class code register ...................................................... 394 16-8 offset 0bh: bcc ? base class code register ....................................................... 394 16-9 offset 0eh: hdr - header type register ............................................................ 395 16-10 offset 14h: smrbase - system memory rcomp base address register ................. 396 16-11 offset 2ch: svid - subsystem vendor identification register ............................... 396 16-12 offset 2eh: sid - subsystem identification register ............................................ 397 16-13 offset 34h: capptr - capabilities pointer register .............................................. 397 16-14 offset 4ch: nsibar - root complex block address register ................................. 397 16-15 offset 50h: cfg0- imch configuration 0 register ............................................... 398 16-16 offset 51h: imch_cfg1 ? imch configuration 1 register .................................... 399 16-17 offset 53h: cfgns1 - configuration 1 (n on-sticky) register ................................ 399 16-18 offset 58h: fdhc - fixed dram hole control register ......................................... 400 16-19 offset 59h: pam0 - programmable attribute map 0 register ................................. 401 16-20 offset 5ah: pam1: programmable attribute map 1 register .................................. 402 16-21 offset 5bh: pam2 - programmable attrib ute map 2 register ................................. 403 16-22 offset 5ch: pam3 - programmable attrib ute map 3 register ................................. 404 16-23 offset 5dh: pam4 - programmable attribute map 4 register ................................. 405
contents intel ? ep80579 integrated processor product line datasheet august 2009 60 order number: 320066-003us 16-24 offset 5eh: pam5 - programmable attribute map 5 register ................................. 406 16-25 offset 5fh: pam6 - programmable attribute map 6 register ................................. 407 16-26 offset 9ch: devpres - device present register .................................................. 408 16-27 offset 9dh: exsmrc - extended system management ram control register ........... 409 16-28 offset 9eh: smram - system management ram control register .......................... 411 16-29 offset 9fh: exsmramc - expansion system management ram control register ...... 413 16-30 offset b8h: imch_mencbase: ia/asu shared non-coherent (aioc-direct) memory base address register ............................................................................................ 413 16-31 offset bch: imch_menclimit - ia/asu shared non-coherent (aioc-direct) memory limit address register ..................................................................................... 414 16-32 offset c4h: tolm - top of low memory register ................................................. 415 16-33 offset c6h: remapbase - remap base address register ..................................... 416 16-34 offset c8h: remaplimit ? remap limit address register ..................................... 416 16-35 offset cah: remapoffset - remap offset register ............................................ 417 16-36 offset cch: tom - top of memory register ........................................................ 417 16-37 offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register ......................................................................................................... 418 16-38 offset d8h: cachectl0 - write cache control 0 register .................................... 418 16-39 offset deh: skpd - scratchpad data register ..................................................... 419 16-40 offset f6h: imch_tst2 - imch test byte 2 register ........................................... 419 16-41 drb to dimm designation .................................................................................. 420 16-42 offset 60h: drb[0-3] - dram row [3:0] boundary register ................................. 421 16-43 dra[1:0] field selection.................................................................................... 422 16-44 offset 70h: dra[0-1] - dram row [0:1] attribute register .................................. 422 16-45 offset 78h: drt0 - dram timing register 0 ........................................................ 424 16-46 offset 64h: drt1 - dram timing register 1 ........................................................ 431 16-47 offset 7ch: drc - dram controller mode register .............................................. 435 16-48 offset 84h: eccdiag - ecc detection/correction diagnostic register ..................... 437 16-49 offset 88h: sdrc - ddr sdram secondary control register ................................ 439 16-50 offset 8ch: ckdis - ck/ck# clock disable register ............................................ 441 16-51 offset 8dh: ckedis - cke clock enable register ................................................ 442 16-52 offset 90h: sparectl - spare control register .................................................. 443 16-53 offset b0h: ddr2odtc - ddr2 odt control register ........................................... 444 16-54 bus 0, device 0, function 1: summary of imch error reporting pci configuration registers ......................................................................................................... 445 16-55 offset 00h: vid - vendor identification register .................................................. 447 16-56 offset 02h: did - device identification register ................................................... 447 16-57 offset 04h: pcicmd - pci command register ..................................................... 448 16-58 offset 06h: pcists - pci status register ........................................................... 448 16-59 offset 08h: rid - revision identification register ................................................ 449 16-60 offset 0ah: subc - sub-class code register ...................................................... 449 16-61 offset 0bh: bcc - base class code register ....................................................... 449 16-62 offset 0dh: mlt - master latency timer register ................................................ 450 16-63 offset 0eh: hdr - header type register ............................................................ 450 16-64 offset 2ch: svid - subsystem vendor identification register ............................... 450 16-65 offset 2eh: sid - subsystem identification register ............................................ 451 16-66 offset 40h: global_ferr - global first error register ........................................ 451 16-67 offset 44h: global_nerr - global next error register ....................................... 453 16-68 offset 48h: nsi_ferr - nsi first error register .................................................. 454 16-69 offset 4ch: nsi_nerr - nsi next error register ................................................. 457 16-70 offset 50h: nsi_scicmd - nsi sci command register ....................................... 459 16-71 offset 54h: nsi_smicmd: nsi smi command register ........................................ 461 16-72 offset 58h: nsi_serrcmd - nsi serr command register .................................. 464 16-73 offset 5ch: nsi_mcerrcmd - nsi mcerr command register .............................. 466 16-74 offset 60h: fsb_ferr - fsb first error register ................................................. 468
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 61 contents 16-75 offset 62h: fsb_nerr - fsb next error register ................................................ 469 16-76 offset 64h: fsb_emask - fsb error mask register ............................................. 470 16-77 offset 68h: fsb_scicmd - fsb sci command register ....................................... 471 16-78 offset 6ah: fsb_smicmd - fsb smi command register ...................................... 472 16-79 offset 6ch: fsb_serrcmd - fsb serr command register ................................. 473 16-80 offset 6eh: fsb_mcerrcmd - fsb mcerr command register ............................. 474 16-81 offset 70h: buf_ferr - memory buffer first error register ................................. 475 16-82 offset 72h: buf_nerr - memory buffer next error register ................................. 475 16-83 offset 74h: buf_emask - memory buffer error mask register .............................. 476 16-84 offset 78h: buf_scicmd - memory buffer sci command register ....................... 477 16-85 offset 7ah: buf_smicmd - memory buffer smi command register ...................... 478 16-86 offset 7ch: buf_serrcmd - memory buffer serr command register .................. 479 16-87 offset 7eh: buf_mcerrcmd - memory buffer mcerr command register .............. 480 16-88 offset e4h: nsierrinjctl - nsi error injection control register .......................... 481 16-89 offset e8h: berrinjctl - buffer error injection control register .......................... 482 16-90 offset 80h: dram_ferr - dram first error register ........................................... 483 16-91 offset 82h: dram_nerr - dram next error register .......................................... 484 16-92 offset 84h: dram_emask - dram error mask register ....................................... 486 16-93 offset 88h: dram_scicmd - dram sci command register ................................. 487 16-94 offset 8ah: dram_smicmd - dram smi command register ................................ 488 16-95 offset 8ch: dram_serrcmd - dram serr command register ............................ 489 16-96 offset 8eh: dram_mcerrcmd - dram mcerr command register ....................... 490 16-97 offset 98h: thresh_sec0 - rank 0 sec error threshold register ......................... 491 16-98 offset 9ah: thresh_sec1 - rank 1 sec error threshold register ........................ 491 16-99 offset a0h: dram_secf_add - dram first single bit error correct address register ........................................................................................................ 492 16-100 offset a4h: dram_ded_add - dram double bit error address register ................ 492 16-101 offset a8h: dram_scrb_add - dram scrub error address register ..................... 493 16-102 offset b0h: dram_sec_r0 - dram rank 0 sec error counter register ................. 494 16-103 offset b2h: dram_ded_r0 - dram rank 0 ded error counter register ................ 494 16-104 offset b4h: dram_sec_r1 - dram rank 1 sec error counter register ................. 494 16-105 offset b6h: dram_ded_r1 - dram rank 1 ded error counter register ................ 495 16-106 offset c2h: thresh_ded - ded error threshold register .................................... 495 16-107 offset c4h: dram_secf_syndrome - dram first single error correct syndrome register ......................................................................................... 496 16-108 offset c6h: dram_secn_syndrome - dram next single error correct syndrome register .......................................................................................... 496 16-109 offset c8h: dram_secn_add - dram next single bit error correct address register ......................................................................................................... 497 16-110 offset dch: rankthrex - rank error threshold exceeded register ...................... 498 16-111 offset ech: derrinjctl - dram error injection control register .......................... 499 16-112 bus 0, device 1, function 0: summary of edma pci configuration registers ............ 501 16-113 offset 00h: vid - vendor identification register ................................................. 502 16-114 offset 02h: did - device identification register ................................................. 502 16-115 offset 04h: pcicmd - pci command register .................................................... 503 16-116 offset 06h: pcists - pci status register .......................................................... 504 16-117 offset 08h: rid - revision identification register ............................................... 504 16-118 offset 0ah: subc - sub-class code register ...................................................... 505 16-119 offset 0bh: bcc - base class code register ....................................................... 505 16-120 offset 0eh: hdr - header type register ............................................................ 505 16-121 offset 10h: edmalbar - edma low base address register .................................. 506 16-122 offset 2ch: svid - subsystem vendor identification register ................................ 506 16-123 offset 2eh: sid - subsystem identification register ............................................. 507 16-124 offset 34h: capptr - capabilities pointer register .............................................. 507 16-125 offset 3ch: intrline - interrupt line register ................................................... 507
contents intel ? ep80579 integrated processor product line datasheet august 2009 62 order number: 320066-003us 16-126 offset 3dh: intrpin - interrupt pin register ...................................................... 508 16-127 offset 40h: edmactl - edma control register ................................................... 508 16-128 offset 80h: edma_ferr - edma first error register ............................................ 509 16-129 offset 84h: edma_nerr - edma next error register ........................................... 511 16-130 offset 88h: edma_emask - edma error mask register ........................................ 513 16-131 offset a0h: edma_scicmd - edma sci command register ................................. 514 16-132 offset a4h: edma_smicmd - edma smi command register .................................. 515 16-133 offset a8h: edma_serrcmd - edma serr command register ............................ 516 16-134 offset ach: edma_mcerrcmd - edma mcerr command register ......................... 517 16-135 offset b0h: msicr - msi control register .......................................................... 518 16-136 offset b4h: msiar - msi address register ......................................................... 519 16-137 offset b8h: msidr - msi data register ............................................................. 520 16-138 bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers ................................................................. 522 16-139 bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers ................................................................. 524 16-140 offset 00h: vid - vendor identification register .................................................. 527 16-141 offset 02h: did - device identification register .................................................. 527 16-142 offset 02h: did - device identification register ................................................... 528 16-143 offset 04h: pcicmd - pci command register ..................................................... 528 16-144 offset 06h: pcists - pci status register ............................................................ 530 16-145 offset 08h: rid - revision identification register ................................................ 531 16-146 offset 0ah: subc - sub-class code register ...................................................... 532 16-147 offset 0bh: bcc - base class code register ....................................................... 532 16-148 offset 0ch: cls - cache line size register ........................................................ 533 16-149 offset 0eh: hdr - header type register ............................................................ 533 16-150 offset 18h: pbusn - primary bus number register ............................................. 534 16-151 offset 19h: sbusn - secondary bus number register .......................................... 534 16-152 offset 1ah: subusn: subordinate bus number register ...................................... 535 16-153 offset 1ch: iobase - i/o base address register ................................................. 535 16-154 offset 1dh: iolimit - i/o limit address register ................................................ 536 16-155 offset 1eh: secsts - secondary status register ................................................ 536 16-156 offset 20h: mbase - memory base address register ........................................... 538 16-157 offset 22h: mlimit - memory limit address register ........................................... 539 16-158 offset 24h: pmbase - prefetchable memory base address register ........................ 540 16-159 offset 26h: pmlimit - prefetchable memory limit address register ....................... 540 16-160 offset 28h: pmbasu - prefetchable memory base upper address register .............. 541 16-161 offset 2ch: pmlmtu - prefetchable memory limit upper address register .............. 541 16-162 offset 34h: capptr - capabilities pointer register .............................................. 542 16-163 offset 3ch: intrline - interrupt line register ................................................... 542 16-164 offset 3dh: intrpin - interrupt pin register ...................................................... 543 16-165 offset 3eh: bctrl - bridge control register ....................................................... 543 16-166 offset 44h: vscmd0 - vendor specific command byte 0 register ......................... 545 16-167 offset 45h: vscmd1 - vendor specific command byte 1 register ......................... 546 16-168 offset 46h: vssts0 - vendor specific status byte 0 register ................................ 547 16-169 offset 47h: vssts1 - vendor specific status byte 1 register ................................ 547 16-170 offset 48h: vscmd2 - vendor specific command byte 2 register ......................... 548 16-171 offset 50h: pmcapid - power management capabilities structure register ............. 548 16-172 offset 51h: pmnptr - power management next capabilities pointer register .......... 549 16-173 offset 52h: pmcapa - power management capabilities register ............................ 549 16-174 offset 54h: pmcsr - power management status and control register .................... 550 16-175 offset 56h: pmcsrbse - power management status and control bridge extensions register ........................................................................................................ 551 16-176 offset 58h: msicapid - msi capabilities structure register ................................. 551 16-177 offset 59h: msinptr - msi next capabilities pointer register ............................... 552
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 63 contents 16-178 offset 5ah: msicapa - msi capabilities register ................................................ 553 16-179 offset 5ch: msiar - msi address for pci express register .................................. 553 16-180 offset 60h: msidr - msi data register ............................................................. 554 16-181 offset 64h: peacapid - pci express features capabilities id register ................... 555 16-182 offset 65h: peanptr - pci express next capabilities pointer register ................... 556 16-183 offset 66h: peacapa - pci express features capabilities register ........................ 556 16-184 offset 68h: peadevcap - pci express device capabilities register ....................... 557 16-185 offset 6ch: peadevctl - pci express device control register ............................. 558 16-186 offset 6eh: peadevsts - pci express device status register ............................... 560 16-187 offset 70h: pealnkcap - pci express link capabilities register ........................... 561 16-188 offset 70h: pea1lnkcap - pci express link capabilities register ......................... 561 16-189 offset 74h: pealnkctl - pci express link control register ................................. 562 16-190 offset 76h: pealnksts - pci express link status register .................................. 564 16-191 offset 78h: peasltcap - pci express slot capabilities register ............................ 565 16-192 offset 78h: pea1sltcap - pci express slot capabilities register .......................... 566 16-193 offset 7ch: peasltctl - pci express slot control register .................................. 568 16-194 offset 7eh: peasltsts - pci express slot status register ................................... 569 16-195 offset 80h: pearpctl - pci express root port control register ............................ 570 16-196 offset 84h: pearpsts - pci express root port status register ............................. 571 16-197 offset 100h: enhcapst - enhanced capability structure register ......................... 571 16-198 offset 104h: uncerrsts - uncorrectable error status register ............................ 572 16-199 offset 108h: uncerrmsk - uncorrectable error mask register ............................. 574 16-200 offset 10ch: uncerrsev - uncorrectable error severity register .......................... 575 16-201 offset 110h: corerrsts - correctable error status register ................................ 576 16-202 offset 114h: corerrmsk - correctable error mask register ................................ 578 16-203 offset 118h: aercacr - advanced error capabilities and control register ............. 579 16-204 offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register ......................... 580 16-205 offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register ........................ 580 16-206 offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register .......................... 581 16-207 offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register ......................... 581 16-208 offset 12ch: rperrcmd - root (port) error command register ............................ 582 16-209 offset 130h: rperrmsts - root (port) error message status register ................... 583 16-210 offset 134h: errsid - error source id register ................................................. 585 16-211 offset 140h: peauniterr - pci express unit error register ................................. 586 16-212 offset 144h: peamaskerr - pci express unit mask error register ........................ 588 16-213 offset 148h: peaerrdocmd - pci express error do command register ................ 589 16-214 offset 14ch: uncedmask - uncorrectable error detect mask register ................... 591 16-215 offset 150h: coredmask - correctable error detect mask register ...................... 592 16-216 offset 158h: peaunitedmask - pci express unit error detect mask register ......... 594 16-217 offset 160h: peaferr - pci express first error register ....................................... 595 16-218 offset 164h: peanerr - pci express next error register ..................................... 597 16-219 offset 168h: peaerrinjctl - error injection control register .............................. 597 16-220 bus 0, device 0, function 0: summary of imch smrbase registers ....................... 599 16-221 offset 00h: notespad - note (sticky) pad for bios support register ................... 601 16-222 offset 02h: notepad - note pad for bios support register ................................. 601 16-223 offset 40h: dcalcsr ? dcal control and status register ................................... 602 16-224 dcalcsr.opmods in receive enable mode ......................................................... 604 16-225 dcalcsr.opmods in zq calibration mode .......................................................... 604 16-226 rules about issuing self-refresh and refresh commands using dcalcsr.opcode .... 604 16-227 dcalcsr.opmods in dqs cal mode................................................................... 605 16-228 dcalcsr.opmods in error monitor/read ddrio fifo mode .................................. 605 16-229 offset 44h: dcaladdr - dcal address register .................................................. 606 16-230 interpretation of dcaladdr based on dcalcsr.opcode...................................... 606 16-231 offset 48h: dcaldata[0-71] - dram calibration data register.............................. 607 16-232 dcaldata based on dcalcsr.opcode.............................................................. 608
contents intel ? ep80579 integrated processor product line datasheet august 2009 64 order number: 320066-003us 16-233 offset 94h: rcvenac - receiver enable algorithm control register ......................... 611 16-234 offset 98h: dsretc - dram self-refresh (sr) extended timing and control register 611 16-235 offset 9ch: dqsfail1 - dqs failure configuration register 1................................. 612 16-236 offset a0h: dqsfail0 - dqs failure configuration register 0................................. 613 16-237 offset a4h: drrtc00 - receive enable reference output timing control register ..... 615 16-238 offset a8h: drrtc01 - receive enable reference output timing control register ..... 616 16-239 offset c4h: drrtc02 - receive enable reference output timing control register ..... 616 16-240 offset b4h: dqsofcs00 - dqs calibration register .............................................. 617 16-241 offset b8h: dqsofcs01 - dqs calibration register .............................................. 617 16-242 offset c6h: dqsofcs02 - dqs calibration register .............................................. 618 16-243 offset bch: dqsofcs10 - dqs calibration register .............................................. 618 16-244 offset c0h: dqsofcs11 - dqs calibration register .............................................. 619 16-245 offset c7h: dqsofcs12 - dqs calibration register .............................................. 619 16-246 offset cch: wptrtc0 - write pointer timing control register................................. 620 16-247 offset d0h: wptrtc1 - write pointer timing control 1 register .............................. 621 16-248 offset d4h: ddqscvdp0 - dqs delay calibration victim pattern 0 register.............. 621 16-249 offset d8h: ddqscvdp1 - dqs delay calibration victim pattern 1 register.............. 622 16-250 offset dch: ddqscadp0 - dqs delay calibration aggressor pattern 0 register ........ 622 16-251 offset e0h: ddqscadp1 - dqs delay calibration aggressor pattern 1 register......... 623 16-252 offset f0h: diomon - ddr i/o monitor register .................................................. 623 16-253 offset f8h: dramisctl - miscellaneous dram ddr cluster control register ............ 624 16-254 offset c8h: dramdllc - ddr i/o dll control register ......................................... 625 16-255 offset e8h: fivesreg - fixed 5s pattern register ................................................. 625 16-256 offset ech: aaaareg - fixed a pattern register ................................................... 626 16-257 offset 140h: mbcsr - membist control register ................................................ 626 16-258 offset 144h: mbaddr - memory test address register.......................................... 629 16-259 offset 148h: mbdata[0:9] - memory test data register ....................................... 629 16-260 mbdata failure address register correspondence to dram address ....................... 631 16-261 bl4 column and chunk correspondence to dram address ..................................... 631 16-262 bl8 column and chunk correspondence to dram address ..................................... 631 16-263 offset 19ch: mb_start_addr - memory test start address register .................... 632 16-264 offset 1a0h: mb_end_addr - memory test end address register .......................... 632 16-265 offset 1a4h: mblfsrsed - memory test circular shift and lfsr seed register ........ 633 16-266 offset 1a8h: mbfaddrptr - memory test failure address pointer register .............. 633 16-267 offset 1b0h: mb_err_data00 - memory test error data 0 ................................... 634 16-268 offset 1b4h: mb_err_data01 - memory test error data 0 ................................... 634 16-269 offset 1b8h: mb_err_data02 - memory test error data 0 ................................... 634 16-270 offset 1bch: mb_err_data03 - memory test error data 0 ................................... 635 16-271 offset 1c0h: mb_err_data04 - memory test error data 0 ................................... 635 16-272 offset 1c4h: mb_err_data10 - memory test error data 1 ................................... 635 16-273 offset 1c8h: mb_err_data11 - memory test error data 1 ................................... 636 16-274 offset 1cch: mb_err_data12 - memory test error data 1 .................................. 636 16-275 offset 1d0h: mb_err_data13 - memory test error data 1 .................................. 636 16-276 offset 1d4h: mb_err_data14 - memory test error data 1 .................................. 637 16-277 offset 1d8h: mb_err_data20 - memory test error data 2 .................................. 637 16-278 offset 1dch: mb_err_data21 - memory test error data 2 .................................. 637 16-279 offset 1e0h: mb_err_data22 - memory test error data 2 ................................... 638 16-280 offset 1e4h: mb_err_data23 - memory test error data 2 ................................... 638 16-281 offset 1e8h: mb_err_data24 - memory test error data 2 ................................... 638 16-282 offset 1ech: mb_err_data30 - memory test error data 3 ................................... 639 16-283 offset 1f0h: mb_err_data31 - memory test error data 3 ................................... 639 16-284 offset 1f4h: mb_err_data32 - memory test error data 3 ................................... 639 16-285 offset 1f8h: mb_err_data33 - memory test error data 3 ................................... 640 16-286 offset 1fch: mb_err_data34 - memory test error data 3 ................................... 640 16-287 offset 260h: ddriomc0 - ddrio mode register control register .......................... 641
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 65 contents 16-288 offset 264h: ddriomc1 - ddrio mode register control register 1 ....................... 642 16-289 legoverride details ........................................................................................... 644 16-290 legoverride - gray code .................................................................................... 644 16-291 offset 268h: ddriomc2 - ddrio mode control register 2 .................................... 645 16-292 mapping of dq and dqs/# byte lanes to wl_cntl[4:0] csr?s ............................... 646 16-293 offset 284h: wl_cntl[4:0] - write levelization control register .......................... 647 16-294 delay of dq/dqs ............................................................................................ 648 16-295 offset 298h: wdll_misc - dll miscellaneous control........................................... 649 16-296 bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar ................................................................................... 652 16-297 offset 00h: ccr0 - channel 0 channel control register ....................................... 653 16-298 offset 04h: csr0 - channel 0 channel status register ........................................ 656 16-299 offset 08h: cdar0 - channel 0 current descriptor address register ...................... 657 16-300 offset 0ch: cduar0 - channel 0 current descriptor upper address register .......... 658 16-301 offset 10h: sar0 - channel 0 source address register ....................................... 658 16-302 offset 14h: suar0 - channel 0 source upper address register ............................. 659 16-303 offset 18h: dar0 - channel 0 destination address register ................................. 659 16-304 offset 1ch: duar0 - channel 0 destination upper address register ....................... 660 16-305 offset 20h: ndar0 - channel 0 next descriptor address register ......................... 661 16-306 offset 24h: nduar0 - channel 0 next descriptor upper address register .............. 662 16-307 offset 28h: tcr0 - channel 0 transfer count register ......................................... 662 16-308 offset 2ch: dcr0 - channel 0 descriptor control register ................................... 663 16-309 offset 40h: ccr1 - channel 1 channel control register ........................................ 665 16-310 offset 44h: csr1 - channel 1 channel status register ......................................... 665 16-311 offset 48h: cdar1 - channel 1 current descriptor address register ..................... 665 16-312 offset 4ch: cduar1 - channel 1 current descriptor upper address register ........... 666 16-313 offset 50h: sar1 - channel 1 source address register ....................................... 666 16-314 offset 54h: suar1 - channel 1 source upper address register ............................. 666 16-315 offset 58h: dar1 - channel 1 destination address register ................................. 667 16-316 offset 5ch: duar1 - channel 1 destination upper address register ....................... 667 16-317 offset 60h: ndar1 - channel 1 next descriptor address register .......................... 667 16-318 offset 64h: nduar1 - channel 1 next descriptor upper address register ............... 668 16-319 offset 68h: tcr1 - channel 1 transfer count register ......................................... 668 16-320 offset 6ch: dcr1 - channel 1 descriptor control register ................................... 668 16-321 offset 80h: ccr2 - channel 2 channel control register ........................................ 669 16-322 offset 84h: csr2 - channel 2 channel status register ........................................ 669 16-323 offset 88h: cdar2: channel 2 current descriptor address register ...................... 669 16-324 offset 8ch: cduar2 - channel 2 current descriptor upper address register .......... 670 16-325 offset 90h: sar2 - channel 2 source address register ....................................... 670 16-326 offset 94h: suar2 - channel 2 source upper address register ............................ 670 16-327 offset 98h: dar2 - channel 2 destination address register ................................. 671 16-328 offset 9ch: duar2 - channel 2 destination upper address register ...................... 671 16-329 offset a0h: ndar2 - channel 2 next descriptor address register ......................... 671 16-330 offset a4h: nduar2 - channel 2 next descriptor upper address register .............. 672 16-331 offset a8h: dcr2 - channel 2transfer control register ....................................... 672 16-332 offset ach: dcr2 - channel 2 descriptor control register ................................... 672 16-333 offset c0h: ccr3 - channel 3 channel control register ...................................... 673 16-334 offset c4h: csr3 - channel 3 channel status register ........................................ 673 16-335 offset c8h: cdar3 - channel 3 current descriptor address register ..................... 673 16-336 offset cch: cduar3 - channel 3 current descriptor upper address register .......... 674 16-337 offset d0h: sar3 - channel 3 source address register ........................................ 674 16-338 offset d4h: suar3 - channel 3 source upper address register ............................ 674 16-339 offset d8h: dar3 - channel 3 destination address register ................................. 675 16-340 offset dch: duar3 - channel 3 destination upper address register ..................... 675 16-341 offset e0h: ndar3 - channel 3 next descriptor address register .......................... 675
contents intel ? ep80579 integrated processor product line datasheet august 2009 66 order number: 320066-003us 16-342 offset e4h: nduar3 - channel 3 next descriptor upper address register ............... 676 16-343 offset e8h: tcr3 - channel 3 transfer count register .......................................... 676 16-344 offset ech: dcr3 - channel 3 descriptor control register .................................... 677 16-345 offset 100h: dcgc - edma controller global command ....................................... 677 16-346 offset 104h: dcgs - edma controller global status ............................................ 678 16-347 bus 0, device 0, function 0: summary of imch configuration registers mapped through nsibar memory bar ........................................................................................ 679 16-348 offset 00h: snsivcech - nsi virtual channel enhanced capability header register . 680 16-349 offset 04h: nsipvccap1 - nsi port vc capability register 1 ................................ 680 16-350 offset 08h: nsipvccap2 - port vc capability register 2 ...................................... 681 16-351 offset 0ch: nsipvcctl - nsi port vc control register ........................................ 682 16-352 offset 10h: nsivc0rcap - nsi vc0 resource capability register .......................... 682 16-353 offset 14h: nsivc0rctl - nsi vc0 resource control register .............................. 683 16-354 offset 1ah: nsivc0rsts - nsi vc0 resource status register .............................. 684 16-355 offset 80h: nsircilcech - nsi root complex internal link control enhanced capability header register .............................................................................................. 684 16-356 offset 84h: nsilcap - nsi link capabilities register ........................................... 685 17-1 bus 0, device 31, function 0: summary of root complex configuration registers mapped through rcba memory bar ............................................................................... 689 17-2 rcba base address registers in the ia f view ...................................................... 690 17-3 offset 0000h: vch - virtual channel capability header register ............................. 691 17-4 offset 0004h: vcap1 - virtual channel capability 1 register .................................. 691 17-5 offset 0008h: vcap2 - virtual channel capability 2 register .................................. 692 17-6 offset 000ch: pvc - port virtual channel control register ..................................... 692 17-7 offset 000eh: pvs -port virtual channel status register ........................................ 693 17-8 offset 0010h: v0cap - virtual channel 0 resource capability register ..................... 693 17-9 offset 0014h: v0ctl - virtual channel 0 resource control register ......................... 694 17-10 offset 001ah: v0sts - virtual channel 0 resource status register.......................... 695 17-11 offset 0100h: rctcl - root complex topology capabilities list register .................. 696 17-12 offset 0104h: esd - element self description register .......................................... 696 17-13 offset 0110h: uld - upstream link description register ........................................ 697 17-14 offset 0118h: ulba - upstream link base address register ................................... 697 17-15 offset 01a0h: ilcl - internal link capabilities list register.................................... 698 17-16 offset 01a4h: lcap - link capabilities register .................................................... 698 17-17 offset 01a8h: lctl - link control register .......................................................... 699 17-18 offset 01aah: lsts - link status register .......................................................... 700 17-19 offset 3000h: tctl - tco control register .......................................................... 700 17-20 offset 3100h: d31ip - device 31 interrupt pin register ........................................ 701 17-21 offset 3108h: d29ip - device 29 interrupt pin register ........................................ 702 17-22 offset 3140h: d31ir - device 31 interrupt route register .................................... 702 17-23 offset 3144h: d29ir - device 29 interrupt route register .................................... 703 17-24 offset 31ffh: oic - other interrupt control register ............................................ 704 17-25 offset 3400h: rc - rtc configuration register ..................................................... 704 17-26 offset 3404h: hptc - high performance precision timer configuration register ........ 705 17-27 offset 3410h: gcs - general control and status register ...................................... 706 17-28 offset 3414h: buc - backed up control register .................................................. 708 17-29 offset 3418h: fd - function disable register ....................................................... 709 17-30 offset 341ch: prc - power reduction control register clock gating ....................... 711 18-1 bus 0, device 31, function 0: summary of tco configuration registers mapped through tcobase i/o bar? ........................................................................................... 714 18-2 offset 00h: trld - tco timer reload and current value register ......................... 715 18-3 offset 02h: tdi - tco data in register .............................................................. 715 18-4 offset 03h: tdo - tco data out register .......................................................... 716 18-5 offset 04h: tsts1 - tco 1 status register ........................................................ 716 18-6 offset 06h: tsts2 - tco 2 sts register ............................................................. 718
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 67 contents 18-7 offset 08h: tctl1 - tco 1 control register ....................................................... 720 18-8 offset 0ah: tctl2 - tco 2 control register ....................................................... 721 18-9 offset 0ch: tmsg[1-2] - tco message register ............................................... 721 18-10 offset 0eh: twds - tco watchdog status register ............................................ 722 18-11 offset 10h: le - legacy elimination register ...................................................... 722 18-12 offset 12h: ttmr - tco timer initial value register ........................................... 723 18-13 event transitions that cause messages .............................................................. 728 18-14 smbus message format .................................................................................... 731 18-15 message address byte ...................................................................................... 732 19-1 bus 0, device 31, function 0: summary of lpc interface pci configuration registers 733 19-2 offset 00h: id: vendor identification register ...................................................... 734 19-3 offset 04h: cmd: device command register ....................................................... 735 19-4 offset 06h: sts: status register ....................................................................... 736 19-5 offset 08h: rid: revision id register ................................................................. 737 19-6 offset 09h: cc: class code register .................................................................. 737 19-7 offset 0dh: mlt: master latency timer register ................................................. 737 19-8 offset 0eh: htype: header type register ........................................................... 738 19-9 offset 2ch: sid: subsystem identifiers register .................................................. 738 19-10 offset 40h: abase: acpi base address register .................................................. 739 19-11 offset 44h: actl: acpi control register ............................................................ 739 19-12 offset 48h: gba: gpio base address register ..................................................... 740 19-13 offset 4ch: gc: gpio control register ............................................................... 741 19-14 offset 60h: parc: pirqa routing control register ............................................. 741 19-15 offset 61h: pbrc: pirqb routing control register .............................................. 742 19-16 offset 62h: pcrc: pirqc routing control register .............................................. 742 19-17 offset 63h: pdrc: pirqdq routing control register ............................................ 743 19-18 offset 64h: scnt: serial irq control register...................................................... 744 19-19 offset 68h: perc: pirqeq routing control register ............................................ 745 19-20 offset 69h: pfrc: pirqf routing control register .............................................. 745 19-21 offset 6ah: pgrc: pirqg routing control register ............................................. 746 19-22 offset 6bh: phrc: pirqh routing control register ............................................. 747 19-23 offset 80h: iod: i/o decode ranges register ..................................................... 747 19-24 offset 82h: ioe: i/o enables register ................................................................ 749 19-25 offset 84h: lg1: lpc generic decode range 1 register ........................................ 750 19-26 offset 88h: lg2: lpc generic decode range 2 register ........................................ 751 19-27 offset d0h: fs1: fwh id select 1 register ......................................................... 752 19-28 offset d4h: fs2: fwh id select 2 register ......................................................... 753 19-29 offset d8h: fde: fwh decode enable register .................................................... 754 19-30 offset dch: bc: bios control register ............................................................... 756 19-31 offset f0h: rcba: root complex base address register ....................................... 757 19-32 offset f8h: manid: manufacturer id register .................................................... 757 19-33 lpc cycle types supported .............................................................................. 759 20-1 summary of lpc dma registers mapped in i/o space ........................................... 764 20-2 0000h (io) base address registers in the ia f1 view ............................................ 764 20-3 0000h (io) base address registers in the ia f2 view ............................................ 765 20-4 offset 00h: dma_bca[0-3] - dma base and current address registers for channels 0-3 .............................................................................. 766 20-5 offset c4h: dma_bca[5-7] - dma base and current address registers for channels 5-7 .............................................................................. 767 20-6 offset 01h: dma_bcc[0-3] - dma base and current count registers for channels 0-3 ................................................................................ 768 20-7 offset c6h: dma_bcc[5-7] - dma base and current count registers for channels 5-7 ................................................................................ 769 20-8 offset 08h: dma_command - dma command register ........................................ 770 20-9 offset 87h: dma_mpl[0-3] - dma memory low page registers for channels 0-3 ...... 771
contents intel ? ep80579 integrated processor product line datasheet august 2009 68 order number: 320066-003us 20-10 offset 8bh: dma_mpl[5-7]: dma memory low page registers for channels 5-7 ....... 771 20-11 offset 08h: dma_status - dma status register ................................................ 772 20-12 offset 0ah: dma_wsm - dma write single mask register ..................................... 773 20-13 offset 0bh: dma_chm - dma channel mode register .......................................... 774 20-14 offset 0ch: dma_cbp - dma clear byte pointer register ....................................... 775 20-15 offset 0dh: dma_mc - dma master clear register ............................................... 775 20-16 offset 0eh: dma_cm - dma clear mask register ................................................. 776 20-17 offset 0fh: dma_wam - dma write all mask register .......................................... 777 20-18 dma channel priority ........................................................................................ 778 20-19 address shifting in 16-bit dma transfers ............................................................. 779 21-1 spi pin interface .............................................................................................. 785 21-2 gpio boot source selection ............................................................................... 786 21-3 spi cycle timings ............................................................................................. 789 21-4 bus 0, device 31, function 0, pci registers mapped through rcba bar ................... 789 21-5 offset 3020h: spis - spi status ........................................................................ 790 21-6 offset 3022h: spic - spi control ....................................................................... 791 21-7 offset 3024h: spia - spi address ..................................................................... 792 21-8 offset 3028h: spid0 - spi data 0 ..................................................................... 792 21-9 offset 3030h, 3038h, 3040h, 3048h, 3050h, 3058h, 3060h: spi[0-6] - spi data [0-6] ................................................................................................ 793 21-10 offset 3070h: bbar - bios base address .......................................................... 793 21-11 offset 3074h: preop - prefix opcode configuration ............................................. 794 21-12 offset 3076h: optype - op code type .............................................................. 794 21-13 offset 3078h: opmenu - opcode menu configuration .......................................... 795 21-14 offset 3080h: pbr0 - protected bios range #0 .................................................. 796 21-15 byte enable handling on direct memory reads ..................................................... 798 21-16 flash protection mechanism summary ................................................................. 800 22-1 gpio pin?s alternative function........................................................................... 804 22-2 gpio summary table ....................................................................................... 805 22-3 bus 0, device 31, function 0: summary of general purpose i/o configuration registers mapped through gba bar io bar ...................................................................... 806 22-4 offset 00h: gpio_use_sel1 - gpio use select 1 {31:0} register ........................ 807 22-5 offset 04h: gp_io_sel1 - gpio input/output select 1 {31:0} register ................. 808 22-6 offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register ............... 809 22-7 offset 18h: gpo_blink - gpio blink enable register .......................................... 810 22-8 offset 2ch: gpi_inv - gpio signal invert register .............................................. 812 22-9 offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register ....................... 813 22-10 offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register ............... 813 22-11 offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register ............. 814 23-1 bus 0, device 31, function 2: summary of sata controller pci configuration registers ......................................................................................................... 817 23-2 offset 00h: id ? identifiers register.................................................................... 819 23-3 offset 04h: cmd - command register ................................................................ 819 23-4 offset 06h: sts - device status register ............................................................ 820 23-5 offset 08h: rid - revision id register................................................................. 821 23-6 programming interface, did and cc.scc register value definitions ........................ 822 23-7 programming interface when cc.scc = ?01h? ...................................................... 822 23-8 programming interface when cc.scc = ?06h? ...................................................... 823 23-9 offset 0ah: cc - class code register .................................................................. 823 23-10 offset 0dh: mlt ? master latency timer register ................................................. 823 23-11 offset 10h: pcmdba ? primary command block base address register.................... 824 23-12 offset 14h: pctlba ? primary control block base address register ......................... 824 23-13 offset 18h: scmdba ? secondary command block base address register................ 825 23-14 offset 1ch: sctlba ? secondary control block base address register..................... 825 23-15 offset 20h: lbar ? legacy bus master base address register when scc is sata
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 69 contents with ahci pi.................................................................................................... 826 23-16 offset 24h: abar ? ahci base address register................................................... 826 23-17 offset 2ch: ss - sub system identifiers register.................................................. 827 23-18 offset 34h: cap ? capabilities pointer register..................................................... 827 23-19 offset 3ch: intr - interrupt information register ................................................ 828 23-20 offset 40h: ptim ? primary timing register ......................................................... 829 23-21 offset 44h: d1tim ? device 1 ide timing register ............................................... 830 23-22 offset 48h: syncc ? synchronous dma control register ....................................... 831 23-23 offset 4ah: synctim ? synchronous dma timing register .................................... 832 23-24 offset 54h: iioc ? ide i/o configuration register .............................................. 833 23-25 offset 70h: pid ? pci power management capability id register ............................ 834 23-26 offset 72h: pc ? pci power management capabilities register ............................... 834 23-27 offset 74h: pmcs ? pci power management control and status register ............... 835 23-28 offset 80h: mid ? message signaled interrupt identifiers register .......................... 836 23-29 offset 82h: mc ? message signaled interrupt message control register................... 837 23-30 offset 84h: ma ? message signaled interrupt message address register.................. 838 23-31 offset 88h: md ? message signaled interrupt message data register ...................... 838 23-32 offset 90h: map ? port mapping register............................................................. 839 23-33 offset 92h: pcs ? port control and status register............................................... 840 23-34 offset a8h: satacr0 ? serial ata capability register 0 ........................................ 841 23-35 offset ach: satacr1 ? serial ata capability register 1 ........................................ 841 23-36 offset c0h: atc ? apm trapping control register ................................................. 842 23-37 offset c4h: ats ? atm trapping status register .................................................. 843 23-38 offset d0h: sp ? scratch pad register ................................................................ 844 23-39 offset e0h: bfcs ? bist fis control/status register ............................................ 844 23-40 offset e4h: bftd1 ? bist fis transmit data 1 register ........................................ 846 23-41 offset e8h: bftd2 ? bist fis transmit data 2 register ........................................ 846 23-42 offset f8h: manid ? manufacturing id register ................................................. 847 23-43 bus 0, device 31, function 2: summary of sata controller configuration registers mapped through lbar i/o bar.......................................................................... 848 23-44 offset 00h: pcmd ? primary command register ................................................. 848 23-45 offset 02h: psts ? primary status register ....................................................... 849 23-46 offset 04h: pdtp ? primary descriptor ta ble pointer register ............................... 849 23-47 offset 10h: index ? ahci index register ............................................................ 850 23-48 offset 14h: data ? ahci data register............................................................... 851 23-49 bus 0, device 31, function 2: summary of sata controller configuration registers mapped through abar memory bar ................................................................... 852 23-50 offset 00h: hcap ? hba capabilities register ..................................................... 853 23-51 offset 04h: ghc ? global hba control register .................................................... 855 23-52 offset 08h: is ? interrupt status register .......................................................... 856 23-53 offset 0ch: pi ? ports implemented register ....................................................... 856 23-54 offset 10h: vs ? ahci version register............................................................... 857 23-55 offset a0h: sgpo -spgio control register .......................................................... 857 23-56 offset 100h: pxclb[0-1] ? port [0-1] command list base address register .......... 858 23-57 offset 104h: pxclbu[0-1] ? port [0-1] command list base address register ......... 858 23-58 offset 108h: pxfb[0-1] ? port [0-1] fis base address register ............................ 859 23-59 offset 10ch: pxfbu[0-1] ? port [0-1] fis base address upper 32-bits register ...... 859 23-60 offset 110h: pxis[0-1] ? port [0-1] interrupt status register ............................... 860 23-61 offset 114h: pxie[0-1] ? port [0-1] interrupt enable register ............................... 861 23-62 offset 118h: pxcmd[0-1] ? port [0-1] command register .................................... 863 23-63 port interface registers for ports[1:0] ................................................................ 866 23-64 offset 120h: pxtfd[0-1] ? port [0-1] task file data register .............................. 866 23-65 offset 124h: pxsig[0-1] ? port [0-1] signature register ..................................... 867 23-66 offset 128h: pxssts[0-1] ? port [0-1] serial ata status register ........................ 868 23-67 offset 12ch: pxsctl[0-1] ? port [0-1] serial ata control register ........................ 869
contents intel ? ep80579 integrated processor product line datasheet august 2009 70 order number: 320066-003us 23-68 offset 130h: pxserr[0-1] ? port [0-1] serial ata error register ........................... 870 23-69 offset 134h: pxsact[0-1] ? port [0-1] serial ata active register ......................... 872 23-70 offset 138h: pxci[0-1] ? port [0-1] command issue register ................................ 872 23-71 offset 13ch: pxsntf[0-1] ? port [0-1] snotification register ............................... 873 23-72 errors during non-data fis reception................................................................ 877 23-73 errors during pio data fis reception.................................................................. 877 23-74 errors during dma data fis reception ................................................................ 877 23-75 errors during unknown fis type3 reception .......................................................... 878 23-76 errors during fis transmission ........................................................................... 878 23-77 msi vs. pci irq actions .................................................................................... 882 24-1 smbus signals .................................................................................................. 895 24-2 bus 0, device 31, function 3: summary of smbus controller pci configuration registers ..................................................................................... 896 24-3 offset 00h: vid: vendor id register .................................................................. 897 24-4 offset 02h: did: device id register .................................................................. 897 24-5 offset 04h: cmd: command register ................................................................ 897 24-6 offset 06h: ds ? device status register ............................................................ 898 24-7 offset 08h: rid: revision id register ................................................................ 899 24-8 offset 09h: pi: programming interface register .................................................. 900 24-9 offset 0ah: scc: sub class code register ......................................................... 900 24-10 offset 0bh: bcc: base class code register ........................................................ 900 24-11 offset 20h: sm_base: smb base address register .............................................. 901 24-12 offset 2ch: svid: svid register ...................................................................... 901 24-13 offset 2eh: sid: subsystem identification register ............................................. 902 24-14 offset 3ch: intln: interrupt line register ......................................................... 902 24-15 offset 3dh: ntpn: interrupt pin register ............................................................ 903 24-16 offset 40h: hcfg: host configuration register ................................................... 903 24-17 offset f8h: manid: manufacturer id register ..................................................... 904 24-18 bus 0, device 31, function 3: summary of smbus controller configuration registers mapped through sm_base i/o bar .................................................................... 905 24-19 offset 00h: hsts: host status register ............................................................. 906 24-20 offset 02h: hctl: host control register ............................................................ 908 24-21 offset 03h: hcmd: host command register ........................................................ 912 24-22 offset 04h: tsa: transmit slave address register .............................................. 912 24-23 offset 05h: hd0: data 0 register ..................................................................... 913 24-24 offset 06h: hd1: data 1 register ..................................................................... 913 24-25 offset 07h: hbd: host block data register ......................................................... 914 24-26 offset 08h: pec: packet error check data register ............................................. 915 24-27 offset 0ch: auxs: auxiliary status register ....................................................... 915 24-28 offset 0dh: auxc: auxiliary control register ...................................................... 916 24-29 offset 0eh: smlc: smlink_pin_ctl register ...................................................... 916 24-30 offset 0fh: smbc: smbus_pin_ctl register ...................................................... 917 24-31 quick protocol .................................................................................................. 919 24-32 send/receive byte protocol without pec .............................................................. 919 24-33 pec send/receive order.................................................................................... 919 24-34 write byte/word protocol without pec ................................................................ 920 24-35 pec bit order .................................................................................................. 920 24-36 read byte/word protocol without pec ................................................................. 921 24-37 read byte/word protocol with pec ...................................................................... 921 24-38 process call protocol without pec........................................................................ 922 24-39 process call protocol with pec ........................................................................... 923 24-40 block read/write protocol without pec ............................................................... 924 24-41 block read/write protocol with pec .................................................................... 925 24-42 block write-block read process call protocol with/without pec .............................. 927 24-43 summary of enables for smbalert# .................................................................. 929
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 71 contents 24-44 summary of enables for smbus slave write, and smbus host events ...................... 929 24-45 summary of enables for the host notify command ............................................... 930 24-46 bus 0, device 31, function 3, slave pci registers mapped through sm_base (io) .... 930 24-47 offset 09h: rsa: receive slave address register ............................................... 931 24-48 offset 0ah: sd: slave data register ................................................................. 931 24-49 offset 10h: ssts: slave status register ............................................................ 932 24-50 offset 11h: scmd: slave command register ..................................................... 932 24-51 offset 14h: nda: notify device address register ................................................ 933 24-52 offset 16h: ndlb: notify data low byte register ............................................... 934 24-53 offset 17h: ndhb: notify data high byte register .............................................. 934 24-54 slave write cycle format .................................................................................. 935 24-55 slave write registers........................................................................................ 936 24-56 command types ............................................................................................. 936 24-57 slave read cycle format................................................................................... 937 24-58 data values for slave read registers ................................................................. 937 24-59 host notify protocol ......................................................................................... 939 25-1 bus 0, device 29, functions 0, summary of usb (1.1) controller pci configuration registers ........................................................................................................ 941 25-2 id - identifiers register ................................................................................... 942 25-3 pcicmd - command register ........................................................................... 942 25-4 pcists - device status register ....................................................................... 943 25-5 rid - revision id register ............................................................................... 944 25-6 subc - sub class code register ....................................................................... 945 25-7 bcc - base class code register ....................................................................... 945 25-8 mlt - master latency timer register ................................................................ 945 25-9 hdr - header type register ............................................................................ 946 25-10 usbiobar - base address register ................................................................... 946 25-11 usbx_svid - usb subsystem vendor id register ............................................... 947 25-12 usbx_sid - usb subsystem id register ........................................................... 947 25-13 intl - interrupt line register .......................................................................... 948 25-14 intp - interrupt pin register ............................................................................ 948 25-15 sbrn - serial bus release number register ....................................................... 948 25-16 usblkmcr - usb legacy keyboard/mouse control register ................................. 949 25-17 usbren - usb resume enable register ............................................................ 951 25-18 usbcwp - usb core well policy register ........................................................... 951 25-19 manid - manufacturer id register .................................................................... 952 25-20 summary of usb (1.1) controller configuration registers mapped through usbiobar i/o bar .......................................................................................... 953 25-21 usbcmd: usb command register .................................................................... 954 25-22 run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation............ 956 25-23 usbsts: usb status register .......................................................................... 957 25-24 usbintr: usb interrupt enable register ........................................................... 959 25-25 frnum: frame number register ...................................................................... 959 25-26 frbaseadd: frame list base address register .................................................. 960 25-27 sofmod: start of frame modify register .......................................................... 961 25-28 pscr - port status and control register ............................................................ 962 25-29 queue advance criteria..................................................................................... 968 25-30 usb schedule list traversal decision table ......................................................... 969 25-31 data field ....................................................................................................... 971 25-32 bits maintained in low power states ................................................................... 975 25-33 usb legacy keyboard/mouse control register bit implementation ......................... 975 26-1 usb 1.1 and usb 2.0 comparison ..................................................................... 977 26-2 bus 0, device 29, function 7: summary of usb (2.0) controller pci configuration registers ........................................................................................................ 978 26-3 offset 00h: vid - vendor id register ................................................................ 979
contents intel ? ep80579 integrated processor product line datasheet august 2009 72 order number: 320066-003us 26-4 offset 02h: did - device identification register .................................................... 979 26-5 offset 04h: cmd - command register ............................................................... 980 26-6 offset 06h: dsr - device status register ........................................................... 981 26-7 offset 08h: rid - revision id register................................................................. 983 26-8 offset 09h: pi - programming interface register................................................... 983 26-9 offset 0ah: scc - sub class code register .......................................................... 983 26-10 offset 0bh: bcc - base class code register ......................................................... 984 26-11 offset 0dh: mlt - master latency timer register .................................................. 984 26-12 offset 10h: mbar - memory base address register ............................................... 985 26-13 offset 2ch: ssvid - usb 2.0 subsystem vendor id register .................................. 985 26-14 offset 2eh: ssid - usb 2.0 subsystem id register ............................................... 986 26-15 offset 34h: cap_ptr - capabilities pointer register............................................... 986 26-16 offset 3ch: iline - interrupt line register........................................................... 987 26-17 offset 3dh: ipin - interrupt pin register.............................................................. 987 26-18 offset 50h: pm_cid - pci power management capability id register ....................... 987 26-19 offset 51h: pm_next - next item pointer #1 register ........................................... 988 26-20 offset 52h: pm_cap - power management capabilities register ............................ 989 26-21 offset 54h: pm_cs - power management control/status register .......................... 990 26-22 offset 58h: dp_cid - debug port capability id register......................................... 991 26-23 offset 59h: dp_next - next item pointer #2 register ........................................... 991 26-24 offset 5ah: dp_base - debug port base offset register ........................................ 991 26-25 offset 60h: sbrn - serial bus release number register ...................................... 992 26-26 offset 61h: fla - frame length adjustment register ........................................... 992 26-27 offset 62h: pwc - port wake capability register ................................................. 993 26-28 offset 64h: cuo - classic usb override register .................................................. 994 26-29 offset 68h: ulsec - usb 2.0 legacy support extended capability register ............ 994 26-30 offset 6ch: ulscs - usb 2.0 legacy support control/status register ................... 995 26-31 offset 70h: isu2smi - intel specific usb 2.0 smi register ................................... 997 26-32 offset 80h: ac - access control register ............................................................ 999 26-33 offset f8h: manid - manufacturer id register .................................................. 1000 26-34 bus 0, device 29, function 7: summary of usb (2.0) controller configuration registers mapped through mbar memory bar ................................................................. 1001 26-35 offset 00h: caplength - capability length register ........................................... 1002 26-36 offset 02h: hciversion - host controller interface version number register ........ 1003 26-37 offset 04h: hcsparams - host controller structural parameters register ............ 1003 26-38 offset 08h: hccparams - host controller capability parameters register ............ 1004 26-39 host controller operational register details summary table ................................ 1006 26-40 offset 20h: usb2cmd - usb 2.0 command register ......................................... 1007 26-41 offset 24h: usb2sts - usb 2.0 status register ................................................ 1009 26-42 offset 28h: usb2intr - usb 2.0 interrupt enable register ................................ 1012 26-43 offset 2ch: frindex - frame index register ................................................... 1013 26-44 offset 30h: ctrldssegment - control data structure segment register .............. 1014 26-45 offset 34h: periodiclistbase - periodic frame list base address register ........ 1014 26-46 offset 38h: asynclistaddr - current asynchronous list address register ......... 1015 26-47 offset 60h: configflag - configure flag register ............................................ 1015 26-48 offset 64h: portsc - port n status and control register .................................... 1016 26-49 hcreset bit summary ................................................................................... 1021 26-50 periodic dma engine memory reads ................................................................. 1022 26-51 asynchronous dma engine reads ..................................................................... 1025 26-52 asynchronous dma engine writes .................................................................... 1027 26-53 host interface parity errors ............................................................................. 1028 26-54 effect of resets on port-routing logic ............................................................... 1035 26-55 offset a0h: cntl_sts - control/status register ............................................... 1037 26-56 offset a4h: usbpid - usb pids register .......................................................... 1039 26-57 offset a8h: databuf - data buffer bytes 7:0 ................................................... 1039
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 73 contents 26-58 offset b0h: config - configuration register ....................................................1040 26-59 debug port behavior .......................................................................................1041 27-1 imch-iich messages ......................................................................................1046 27-2 bus 0, device 31, function 0: summary of lpc interface power management pci configuration registers ....................................................................................1047 27-3 offset a0h: gen_pmcon_1 - general pm configuration 1 register ........................1047 27-4 offset a2h: gen_pmcon_2 - general pm configuration 2 register ........................1049 27-5 offset a4h: gen_pmcon_3 - general pm configuration 3 register .......................1051 27-6 offset b8h: gpi_rout - gpi routing control register .........................................1053 27-7 summary of apm registers mapped in i/o space.................................................1053 27-8 offset b2h: apm_cnt - advanced power management control port register ...........1054 27-9 offset b3h: apm_sts - advanced power management status port register .............1054 27-10 bus 0, device 31, function 0: summary of lpc interface power management general configuration registers mapped through pmbase i/o bar ...................................1055 27-11 offset 00h: pm1_sts ? power management 1 status register .............................1056 27-12 offset 02h: pm1_en - power management 1 enables register .............................1058 27-13 offset 04h: pm1_cnt - power management 1 control register ............................1059 27-14 offset 08h: pm1_tmr - power management 1 timer register ..............................1060 27-15 offset 10h: proc_cnt - processor control register ...........................................1060 27-16 offset 14h: lv2 - level 2 register ...................................................................1063 27-17 offset 28h: gpe0_sts - general purpose event 0 status register ........................1063 27-18 offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register ..........1067 27-19 offset 30h: smi_en - smi control and enable register .......................................1068 27-20 offset 34h: smi_sts - smi status register ......................................................1071 27-21 offset 38h: alt_gpi_smi_en - alternate gpi smi enable register .......................1073 27-22 offset 3ah: alt_gpi_smi_sts - alternate gpi smi status register .....................1074 27-23 offset 44h: devtrap_sts - devtrap_sts register ...........................................1074 27-24 causes of sci .................................................................................................1076 27-25 causes of tco sci ..........................................................................................1076 27-26 causes of smi# .............................................................................................1077 27-27 causes of tco smi#........................................................................................1078 27-28 break events .................................................................................................1079 27-29 c0 c2 c0 timings .......................................................................................1082 27-30 sleep state output conditions ..........................................................................1083 27-31 sleep types ...................................................................................................1084 27-32 causes of wake events ...................................................................................1085 27-33 gpi wake events ............................................................................................1085 27-34 transitions due to power failure.......................................................................1086 27-35 transitions due to power button .......................................................................1088 27-36 transitions due to ri# signal ...........................................................................1089 27-37 write-only registers with read paths in alternate access mode ............................1092 27-38 pic reserved bits return values ......................................................................1093 27-39 register write accesses in alternate access mode................................................1094 28-1 ia-32 core interface signal state ......................................................................1097 28-2 summary of ia-32 core interface registers mapped in i/o space ..........................1097 28-3 offset 61h: nmi_sts_cnt - nmi status and control register ..............................1098 28-4 offset 70h: nmi_en - nmi enable (and real time clock index) register ...............1099 28-5 offset 92h: port92 - fast a20 and init register ...............................................1100 28-6 offset f0h: coproc_err - coprocessor error register ......................................1100 28-7 offset cf9h: rst_cnt - reset control register .................................................1101 28-8 init# going active .........................................................................................1102 28-9 nmi sources...................................................................................................1103 29-1 i/o registers ..................................................................................................1106 29-2 rtc (standard) ram bank................................................................................1106 29-3 summary of real time clock indexed registers ..................................................1107
contents intel ? ep80579 integrated processor product line datasheet august 2009 74 order number: 320066-003us 29-4 offset 0ah: rtc_rega - register a (general configuration) ............................... 1107 29-5 offset 0bh: rtc_regb - register b (general configuration) ............................... 1109 29-6 offset 0ch: rtc_regc - register c (flag register) ........................................... 1110 29-7 offset 0dh: rtc_regd - register d (flag register) .......................................... 1111 30-1 interrupt options - 8259 mode ......................................................................... 1115 30-2 interrupt options - apic mode.......................................................................... 1116 30-3 signals associated with interrupt logic .............................................................. 1117 30-4 8259 core connection .................................................................................... 1117 30-5 summary of 8259 interrupt controller (pic) registers mapped in i/o space ........... 1118 30-6 icw1[0-1] - initialization command word 1 register .......................................... 1119 30-7 icw2[0-1] - initialization command word 2 register ......................................... 1120 30-8 micw3 - master initialization command word 3 register ................................... 1121 30-9 sicw3 - slave initialization command word 3 register ..................................... 1121 30-10 icw4[0-1] - initialization command word 4 register .......................................... 1122 30-11 ocw1[0-1]- operational control word 1 (interrupt mask) register ....................... 1122 30-12 ocw2[0-1] - operational control word 2 register .............................................. 1123 30-13 ocw3[0-1] - operational control word 3 register ............................................. 1124 30-14 elcr1 - master edge/level control register ..................................................... 1125 30-15 elcr2 - slave edge/level control register ....................................................... 1126 30-16 interrupt handling ......................................................................................... 1127 30-17 content of interrupt vector byte....................................................................... 1127 30-18 interrupt delivery address format ................................................................... 1134 30-19 interrupt delivery data format ........................................................................ 1134 30-20 summary of apic registers mapped in memory space?........................................ 1135 30-21 apic_idx - index register .............................................................................. 1135 30-22 apic_dat ? data register ............................................................................. 1136 30-23 apic_eoi - eoi register ................................................................................ 1136 30-24 apic index register space............................................................................... 1137 30-25 summary of apic indexed registers ................................................................. 1137 30-26 apic_id ? identification register ..................................................................... 1138 30-27 apic_vs - version register ............................................................................ 1138 30-28 apic_rte[0-39] - redirection table entry ........................................................ 1139 30-29 stop frame definition ..................................................................................... 1143 30-30 data frame format......................................................................................... 1144 31-1 spkr signal ................................................................................................... 1145 31-2 summary of 8254 timer registers mapped in i/o space ...................................... 1145 31-3 offset 43h: tcw - timer control word register .................................................. 1146 31-4 offset 40h: tsb[0-2] - interval timer status byte format register ..................... 1147 31-5 offset 40h: tcap[0-2] - interval timer counter access ports register ................... 1148 31-6 counter operating modes ............................................................................... 1149 31-7 counter latch command ................................................................................ 1150 31-8 read back command ..................................................................................... 1151 32-1 summary of hpet registers mapped in memory space ........................................ 1154 32-2 offset 000h: gcap_id - general capabilities and id register ............................. 1155 32-3 offset 010h: gen_conf - general configuration register ................................... 1156 32-4 offset 020h: gintr_sta - general interrupt status register ............................... 1157 32-5 offset 0f0h: main_cnt - main counter value register ....................................... 1158 32-6 offset 100h: hptcc[0-2] - timer n configuration and capabilities register .......... 1159 32-7 offset 108h: hptcv[0-2] - timer n comparator value register ........................... 1163 32-8 legacy replacement routing............................................................................ 1164 33-1 address map ................................................................................................. 1170 33-2 supported lpc cycle types ............................................................................. 1170 33-3 i/o sync bits description ................................................................................ 1171 33-4 uart clock divider support ............................................................................ 1172 33-5 baud rate example ........................................................................................ 1172
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 75 contents 33-6 uart register/signal reset states ...................................................................1174 33-7 summary of uart registers in i/o space (dlab=0) ............................................1175 33-8 summary of uart registers in i/o space (dlab=1) ............................................1175 33-9 summary of uart timer registers in i/o space ...................................................1175 33-10 internal register descriptions ..........................................................................1176 33-11 offset 00h: rbr - receive buffer register ........................................................1176 33-12 offset 00h: thr - transmit holding register .....................................................1177 33-13 offset 01h: ier - interrupt enable register .......................................................1177 33-14 interrupt conditions .......................................................................................1178 33-15 offset 02h: iir - interrupt identification register ..............................................1179 33-16 interrupt identification register decode ............................................................1179 33-17 offset 02h: fcr - fifo control register ...........................................................1180 33-18 offset 03h: lcr - line control register ............................................................1182 33-19 offset 04h: mcr - modem control register .......................................................1184 33-20 offset 05h: lsr - line status register .............................................................1186 33-21 offset 06h: msr - modem status register ........................................................1189 33-22 offset 07h: scr - scratchpad register .............................................................1190 33-23 offset 00h: dll - programmable baud rate generator divisor latch register low .1190 33-24 offset 01h: dlh - programmable baud rate generator divisor latch register high .1190 33-25 summary of watchdog timer registers in i/o space............................................1194 33-26 offset 00h: pv1r0 - preload value 1 register 0 .................................................1194 33-27 offset 01h: pv1r1 - preload value 1 register 1 .................................................1195 33-28 offset 02h: pv1r2 - preload value 1 register 2 .................................................1195 33-29 offset 04h: pv2r0 - preload value 2 register 0 .................................................1196 33-30 offset 05h: pv2r1 - preload value 2 register 1 .................................................1196 33-31 offset 06h: pv2r2 - preload value 2 register 2 .................................................1197 33-32 offset 08h: gisr - general interrupt status register .........................................1197 33-33 offset 0ch: rr0 - reload register 0 ................................................................1198 33-34 offset 0dh: rr1 - reload register 1 ................................................................1199 33-35 offset 10h: wdtcr - wdt configuration register ..............................................1199 33-36 offset 18h: wdtlr - wdt lock register ..........................................................1201 33-37 siw_serirq sampling periods ........................................................................1204 33-38 configuration register summary ......................................................................1207 33-39 logical device 4 (serial port 1) ........................................................................1210 33-40 logical device 5 (serial port 2) ........................................................................1211 33-41 logical device 6 (watch dog timer) .................................................................1212 34-1 bus 0, device 4, function 0: summary of pci-to-pci bridge pci configuration registers ....................................................................................1215 34-2 pci-to-pci bridge pci header .........................................................................1216 34-3 offset 0h: vid: vendor identification register ...................................................1217 34-4 offset 2h: did: device identification register ...................................................1217 34-5 offset 4h: pcicmd: device command register ..................................................1217 34-6 offset 6h: pcists: pci device status register ..................................................1218 34-7 offset 8h: rid: revision id register ................................................................1219 34-8 offset 9h: cc: class code register ..................................................................1219 34-9 offset ch: cls: cacheline size register ...........................................................1219 34-10 offset dh: lt: latency timer register ..............................................................1220 34-11 offset eh: hdr: header type register .............................................................1220 34-12 offset 10h: csrbar0: control and status registers base address register ...........1220 34-13 offset 14h: csrbar1: control and status registers base address register ...........1221 34-14 offset 18h: pbnum: primary bus number register .............................................1221 34-15 offset 19h: secbnm: secondary bus number register .......................................1221 34-16 offset 1ah: subbnm: subordinate bus number register ....................................1222 34-17 offset 1bh: seclt: secondary latency timer register .......................................1222 34-18 offset 1ch: iob: i/o base register ..................................................................1222
contents intel ? ep80579 integrated processor product line datasheet august 2009 76 order number: 320066-003us 34-19 offset 1dh: iol: i/o limit register ................................................................. 1223 34-20 offset 1eh: secsta: secondary status register ............................................... 1223 34-21 offset 20h: memb: memory base register ........................................................ 1224 34-22 offset 22h: meml: memory limit register ........................................................ 1224 34-23 offset 24h: pmase: prefetchable memory base register .................................... 1225 34-24 offset 26h: pmlimit: prefetchable memory limit register .................................. 1225 34-25 offset 28h: pmbasu: memory limit register .................................................... 1226 34-26 offset 2ch: pmlmtu: prefetchable memory limit upper register ......................... 1226 34-27 offset 30h: iobu: i/o base upper register ...................................................... 1227 34-28 offset 32h: iolu: i/o limit upper register ...................................................... 1227 34-29 offset 34h: cp: capabilities pointer register ..................................................... 1227 34-30 offset 3ch: irql: interrupt line register ......................................................... 1228 34-31 offset 3dh: irqp: interrupt pin register .......................................................... 1228 34-32 offset 3eh: bctl: bridge control register ........................................................ 1228 34-33 offset dch: pcid: power management capability id register ............................. 1229 34-34 offset ddh: pcp: power management next capability pointer register ................. 1230 34-35 offset deh: pmcap: power management capability register ............................... 1230 34-36 offset e0h: pmcs: power management control and status register ..................... 1231 34-37 offset e2h: pmcse: power management control and status extension register ..... 1232 35-1 type 0 pci configuration header .................................................................... 1233 35-2 messaging and signalling capability record per pci device ................................ 1235 35-3 bus m, device 0, function 0: summary of gigabit ethernet mac interface pci configuration registers ................................................................................... 1237 35-4 bus m, device 1, function 0: summary of gigabit ethernet mac interface pci configuration registers ................................................................................... 1238 35-5 bus m, device2, function 0: summary of gigabit ethernet mac interface pci configuration registers ....................................................................................................... 1239 35-6 offset 00h: vid: vendor identification register ................................................. 1241 35-7 offset 02h: did: device identification register ................................................. 1241 35-8 offset 02h: did: device identification register ................................................. 1242 35-9 offset 02h: did: device identification register ................................................. 1242 35-10 offset 04h: pcicmd: device command register ............................................... 1243 35-11 offset 06h: pcists: pci device status register ................................................ 1244 35-12 offset 08h: rid: revision id register .............................................................. 1245 35-13 offset 09h: cc: class code register ................................................................ 1245 35-14 offset 0eh: hdr: header type register ........................................................... 1246 35-15 offset 10h: csrbar: control and status registers base address register ............ 1246 35-16 offset 14h: iobar: csr i/o mapped bar register ............................................ 1247 35-17 offset 2ch: svid: subsystem vendor id register ............................................. 1248 35-18 offset 2eh: sid: subsystem id register .......................................................... 1248 35-19 offset 34h: cp: capabilities pointer register ..................................................... 1249 35-20 offset 3ch: irql: interrupt line register ......................................................... 1249 35-21 offset 3dh: irqp: interrupt pin register .......................................................... 1250 35-22 offset dch: pcid: power management capability id register ............................. 1251 35-23 offset ddh: pcp: power management next capability pointer register ................. 1251 35-24 offset deh: pmcap: power management capability register ............................... 1252 35-25 offset e0h: pmcs: power management control and status register ..................... 1253 35-26 offset e4h: scid: signal target capability id register ...................................... 1254 35-27 offset e5h: scp: signal target next capability pointer register .......................... 1254 35-28 offset e6h: sbc: signal target byte count register .......................................... 1255 35-29 offset e7h: styp: signal target capability type register ................................... 1255 35-30 offset e8h: smia: signal target ia mask register ............................................. 1256 35-31 offset ech: sint: signal target raw interrupt register ...................................... 1257 35-32 offset f0h: mcid: message signalled interrupt capability id register .................. 1258 35-33 offset f1h: mcp: message signalled interrupt next capability pointer register ..... 1258
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 77 contents 35-34 offset f2h: mctl: message signalled interrupt control register ..........................1259 35-35 offset f4h: madr: message signalled interrupt address register ........................1259 35-36 offset f8h: mdata: message signalled interrupt data register ...........................1260 35-37 bus m, device 0, function 0: gigabit ethernet mac i/o spaces registers................1262 35-38 bus m, device 1, function 0: gigabit ethernet mac i/o spaces registers................1262 35-39 bus m, device 2, function 0: gigabit ethernet mac i/o spaces registers................1262 35-40 gigabit ethernet mac i/o iobar register summary ............................................1262 35-41 offset 0000h: ioaddr - ioaddr register ........................................................1263 35-42 offset 0004h: iodata - iodata register .........................................................1264 35-43 bus m, device 3, function 0: summary of gcu pci configuration registers ............1265 35-44 offset 00h: vid: vendor identification register .................................................1265 35-45 offset 02h: did: device identification register .................................................1266 35-46 offset 04h: pcicmd: device command register ................................................1266 35-47 offset 06h: pcists: pci device status register ................................................1267 35-48 offset 08h: rid: revision id register ..............................................................1268 35-49 offset 09h: cc: class code register ................................................................1268 35-50 offset 0eh: hdr: header type register ............................................................1268 35-51 offset 10h: csrbar: control and status registers base address register .............1269 35-52 offset 2ch: svid: subsystem vendor id register ..............................................1269 35-53 offset 2eh: sid: subsystem id register ...........................................................1270 35-54 offset 34h: cp: capabilities pointer register .....................................................1270 35-55 offset dch: pcid: power management capability id register ..............................1270 35-56 offset ddh: pcp: power management next capability pointer register .................1271 35-57 offset deh: pmcap: power management capability register ................................1271 35-58 offset e0h: pmcs: power management control and status register .....................1272 35-59 bus m, device 4, function 0: summary of can interface pci configuration registers ....................................................................................1273 35-60 bus m, devices 5, function 0: summary of can interface pci configuration registers ....................................................................................1274 35-61 offset 00h: vid: vendor identification register .................................................1275 35-62 offset 02h: did: device identification register .................................................1275 35-63 offset 02h: did: device identification register .................................................1276 35-64 offset 04h: pcicmd: device command register ................................................1276 35-65 offset 06h: pcists: pci device status register ................................................1277 35-66 offset 08h: rid: revision id register ..............................................................1278 35-67 offset 09h: cc: class code register ................................................................1278 35-68 offset 0eh: hdr: header type register ............................................................1279 35-69 offset 10h: csrbar: control and status registers base address register .............1279 35-70 offset 2ch: svid: subsystem vendor id register ..............................................1280 35-71 offset 2eh: sid: subsystem id register ...........................................................1280 35-72 offset 34h: cp: capabilities pointer register .....................................................1281 35-73 offset 3ch: irql: interrupt line register .........................................................1281 35-74 offset 3dh: irqp: interrupt pin register ..........................................................1282 35-75 offset 40h: canctl - can control register .......................................................1282 35-76 offset dch: pcid: power management capability id register ..............................1283 35-77 offset ddh: pcp: power management next capability pointer register .................1283 35-78 offset deh: pmcap: power management capability register ................................1284 35-79 offset e0h: pmcs: power management control and status register .....................1284 35-80 offset e4h: scid: signal target capability id register .......................................1285 35-81 offset e5h: scp: signal target next capability pointer register ...........................1285 35-82 offset e6h: sbc: signal target byte count register ...........................................1286 35-83 offset e7h: styp: signal target capability type register ....................................1286 35-84 offset e8h: smia: signal target ia mask register ..............................................1287 35-85 offset ech: sint: signal target raw interrupt register .......................................1287 35-86 offset f0h: mcid: message signalled interrupt capability id register ..................1288
contents intel ? ep80579 integrated processor product line datasheet august 2009 78 order number: 320066-003us 35-87 offset f1h: mcp: message signalled interrupt next capability pointer register ..... 1288 35-88 offset f2h: mctl: message signalled interrupt control register ......................... 1289 35-89 offset f4h: madr: message signalled interrupt address register ........................ 1289 35-90 offset f8h: mdata: message signalled interrupt data register ........................... 1290 35-91 bus m, device 6, function 0: summary of ssp controller pci configuration registers ................................................................................... 1291 35-92 offset 00h: vid: vendor identification register ................................................. 1292 35-93 offset 02h: did: device identification register ................................................. 1292 35-94 offset 04h: pcicmd: device command register ............................................... 1292 35-95 offset 06h: pcists: pci device status register ................................................ 1293 35-96 offset 08h: rid: revision id register .............................................................. 1294 35-97 offset 09h: cc: class code register ................................................................ 1295 35-98 offset 0eh: hdr: header type register ........................................................... 1295 35-99 offset 10h: csrbar: control and status registers base address register ............ 1296 35-100 offset 2ch: svid: subsystem vendor id register ............................................. 1296 35-101 offset 2eh: sid: subsystem id register .......................................................... 1297 35-102 offset 34h: cp: capabilities pointer register ..................................................... 1297 35-103 offset 3ch: irql: interrupt line register ......................................................... 1297 35-104 offset 3dh: irqp: interrupt pin register .......................................................... 1298 35-105 offset dch: pcid: power management capability id register ............................. 1298 35-106 offset ddh: pcp: power management next capability pointer register ................. 1299 35-107 offset deh: pmcap: power management capability register ............................... 1299 35-108 offset e0h: pmcs: power management control and status register ..................... 1300 35-109 offset e4h: scid: signal target capability id register ...................................... 1300 35-110 offset e5h: scp: signal target next capability pointer register .......................... 1301 35-111 offset e6h: sbc: signal target byte count register .......................................... 1301 35-112 offset e7h: styp: signal target capability type register ................................... 1301 35-113 offset e8h: smia: signal target ia mask register ............................................. 1302 35-114 offset ech: sint: signal target raw interrupt register ...................................... 1302 35-115 offset f0h: mcid: message signalled interrupt capability id register .................. 1303 35-116 offset f1h: mcp: message signalled interrupt next capability pointer register ..... 1303 35-117 offset f2h: mctl: message signalled interrupt control register ......................... 1303 35-118 offset f4h: madr: message signalled interrupt address register ........................ 1304 35-119 offset f8h: mdata: message signalled interrupt data register ........................... 1304 35-120 bus m, device 7, function 0: summary of ieee 1588 timestamp unit pci configuration registers ....................................................................................................... 1305 35-121 offset 00h: vid: vendor identification register ................................................. 1306 35-122 offset 02h: did: device identification register ................................................. 1306 35-123 offset 04h: pcicmd: device command register ............................................... 1306 35-124 offset 06h: pcists: pci device status register ................................................ 1307 35-125 offset 08h: rid: revision id register .............................................................. 1308 35-126 offset 09h: cc: class code register ................................................................ 1308 35-127 offset 0eh: hdr: header type register ........................................................... 1309 35-128 offset 10h: csrbar: control and status registers base address register ............ 1309 35-129 offset 2ch: svid: subsystem vendor id register ............................................. 1310 35-130 offset 2eh: sid: subsystem id register .......................................................... 1310 35-131 offset 34h: cp: capabilities pointer register ..................................................... 1310 35-132 offset 3ch: irql: interrupt line register ......................................................... 1311 35-133 offset 3dh: irqp: interrupt pin register .......................................................... 1311 35-134 offset dch: pcid: power management capability id register ............................. 1312 35-135 offset ddh: pcp: power management next capability pointer register ................. 1312 35-136 offset deh: pmcap: power management capability register ............................... 1313 35-137 offset e0h: pmcs: power management control and status register ..................... 1313 35-138 offset e4h: scid: signal target capability id register ...................................... 1314 35-139 offset e5h: scp: signal target next capability pointer register .......................... 1314
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 79 contents 35-140 offset e6h: sbc: signal target byte count register ...........................................1314 35-141 offset e7h: styp: signal target capability type register ....................................1315 35-142 offset e8h: smia: signal target ia mask register ..............................................1315 35-143 offset ech: sint: signal target raw interrupt register .......................................1316 35-144 offset f0h: mcid: message signalled interrupt capability id register ..................1316 35-145 offset f1h: mcp: message signalled interrupt next capability pointer register ......1317 35-146 offset f2h: mctl: message signalled interrupt control register ..........................1317 35-147 offset f4h: madr: message signalled interrupt address register ........................1318 35-148 offset f8h: mdata: message signalled interrupt data register ...........................1318 35-149 bus m, device 8, function 0: summary of local expansion bus pci configuration registers ....................................................................................1319 35-150 offset 00h: vid: vendor identification register .................................................1320 35-151 offset 02h: did: device identification register .................................................1320 35-152 offset 04h: pcicmd: device command register ................................................1321 35-153 offset 06h: pcists: pci device status register ................................................1321 35-154 offset 08h: rid: revision id register ..............................................................1322 35-155 offset 09h: cc: class code register ................................................................1323 35-156 offset 0eh: hdr: header type register ............................................................1323 35-157 offset 10h: csrbar: control and status registers base address register .............1324 35-158 offset 14h: mmbar: expansion bus base address register .................................1324 35-159 mmbar addr field behavior ............................................................................1325 35-160 offset 2ch: svid: subsystem vendor id register ..............................................1325 35-161 offset 2eh: sid: subsystem id register ...........................................................1326 35-162 offset 34h: cp: capabilities pointer register .....................................................1326 35-163 offset 3ch: irql: interrupt line register .........................................................1326 35-164 offset 3dh: irqp: interrupt pin register ..........................................................1327 35-165 offset 40h: lebctl: leb control register ..........................................................1327 35-166 offset dch: pcid: power management capability id register ..............................1327 35-167 offset ddh: pcp: power management next capability pointer register .................1328 35-168 offset deh: pmcap: power management capability register ................................1328 35-169 offset e0h: pmcs: power management control and status register .....................1329 35-170 offset e4h: scid: signal target capability id register .......................................1329 35-171 offset e5h: scp: signal target next capability pointer register ...........................1330 35-172 offset e6h: sbc: signal target byte count register ...........................................1330 35-173 offset e7h: styp: signal target capability type register ....................................1330 35-174 offset e8h: smia: signal target ia mask register ..............................................1331 35-175 offset ech: sint: signal target raw interrupt register .......................................1331 35-176 offset f0h: mcid: message signalled interrupt capability id register ..................1332 35-177 offset f1h: mcp: message signalled interrupt next capability pointer register ......1332 35-178 offset f2h: mctl: message signalled interrupt control register ..........................1333 35-179 offset f4h: madr: message signalled interrupt address register ........................1333 35-180 offset f8h: mdata: message signalled interrupt data register ...........................1334 37-1 supported receive checksum capabilities ........................................................1363 37-2 vlan tag insertion decision table when vlan mode enabled (ctrl.vme=1) ..........1368 37-3 vlan tag insertion decision table.....................................................................1374 37-4 untagged 802.3 packet vs 802.1q vlan tagged packet ........................................1400 37-5 packet reception decision table........................................................................1402 37-6 eeprom address map ......................................................................................1413 37-7 initialization control word 1 .............................................................................1415 37-8 initialization control word 2 .............................................................................1416 37-9 initialization control word 3 .............................................................................1416 37-10 management control word ...............................................................................1416 37-11 ipv4 address ..................................................................................................1417 37-12 ipv6 address ..................................................................................................1417 37-13 memory protection ..........................................................................................1419
contents intel ? ep80579 integrated processor product line datasheet august 2009 80 order number: 320066-003us 37-14 gbe reset effects ........................................................................................... 1421 37-15 long word little endian, byte little endian ordering ........................................... 1423 37-16 endianness control for gigabit ethernet macs .................................................... 1423 37-17 endianness mode 0: long word little endian, byte big endian .............................. 1423 37-18 endianness mode 1: long word little endian, byte little endian (default) .............. 1423 37-19 endianness mode 2: long word big endian, byte big endian................................. 1424 37-20 endianness mode 3: long word big endian, byte little endian .............................. 1424 37-21 bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar ......................................................................... 1425 37-22 bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar ......................................................................... 1429 37-23 bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar ......................................................................... 1432 37-24 i/o mapped registers...................................................................................... 1436 37-25 ctrl: device control register ........................................................................ 1438 37-26 status: device status register ..................................................................... 1441 37-27 ctrl_ext: extended device control register ................................................... 1442 37-28 ctrl_aux: auxiliary device control register .................................................... 1444 37-29 eeprom_ctrl - eeprom control register ....................................................... 1446 37-30 eeprom_rr ? eeprom read register ............................................................... 1448 37-31 fcal: flow control address low register ......................................................... 1449 37-32 fcah: flow control address high register ....................................................... 1450 37-33 fct: flow control type register ..................................................................... 1451 37-34 vet: vlan ethertype register ........................................................................ 1452 37-35 fcttv: flow control transmit timer value register ........................................... 1452 37-36 pba: packet buffer allocation register ............................................................. 1453 37-37 icr0: interrupt 0 cause read register ............................................................ 1454 37-38 itr0: interrupt 0 throttling register ............................................................... 1457 37-39 ics0: interrupt 0 cause set register .............................................................. 1458 37-40 ims0: interrupt 0 mask set/read register ....................................................... 1459 37-41 imc0: interrupt 0 mask clear register ............................................................. 1460 37-42 icr1: interrupt 1cause read register ............................................................. 1462 37-43 ics1: interrupt 0 cause set register .............................................................. 1464 37-44 ims1: interrupt 1 mask set/read register ....................................................... 1466 37-45 imc1: interrupt 1 mask clear register ............................................................. 1467 37-46 icr2: error interrupt cause read register ....................................................... 1469 37-47 ics2: error interrupt cause set register ......................................................... 1471 37-48 ims2: error interrupt mask set/read register ................................................... 1472 37-49 imc2: error interrupt mask clear register ......................................................... 1473 37-50 rctl: receive control register ....................................................................... 1474 37-51 fcrtl: flow control receive threshold low register .......................................... 1478 37-52 fcrth: flow control receive threshold high register ........................................ 1479 37-53 rdbal: receive descriptor base address low register ...................................... 1480 37-54 rdbah: receive descriptor base address high register ..................................... 1480 37-55 rdlen: receive descriptor length register ...................................................... 1481 37-56 rdh: receive descriptor head register ........................................................... 1481 37-57 rdt: receive descriptor tail register .............................................................. 1482 37-58 rdtr: rx interrupt delay timer (packet timer) register ................................... 1483 37-59 rxdctl: receive descriptor control register ................................................... 1483 37-60 radv: receive interrupt absolute delay timer register ..................................... 1485 37-61 rsrpd: receive small packet detect interrupt register ..................................... 1486 37-62 rxcsum: receive checksum control register ................................................... 1487 37-63 mta[0-127] ? 128 multicast table array registers ............................................ 1488 37-64 ral[0-15] - receive address low register ....................................................... 1488 37-65 rah[0-15] - receive address high register ...................................................... 1489
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 81 contents 37-66 vfta[0-127] - 128 vlan filter table array registers .........................................1490 37-67 tctl: transmit control register ......................................................................1491 37-68 tipg: transmit ipg register ...........................................................................1493 37-69 ait: adaptive ifs throttle register ..................................................................1495 37-70 tdbal: transmit descriptor base address low register .....................................1496 37-71 tdbah: transmit descriptor base address high register ....................................1496 37-72 tdlen: transmit descriptor length register .....................................................1497 37-73 tdh: transmit descriptor head register ...........................................................1497 37-74 tdt: transmit descriptor tail register .............................................................1498 37-75 tidv: transmit interrupt delay value register ..................................................1499 37-76 txdctl: transmit descriptor control register ...................................................1500 37-77 tadv: transmit absolute interrupt delay value register ....................................1502 37-78 tspmt: tcp segmentation pad and minimum threshold register .........................1504 37-79 crcerrs: crc error count register ................................................................1505 37-80 algnerrc: alignment error count register ......................................................1506 37-81 rxerrc: receive error count register .............................................................1506 37-82 mpc: missed packet count register .................................................................1507 37-83 scc: single collision count register ................................................................1507 37-84 ecol: excessive collisions count register ........................................................1508 37-85 mcc: multiple collision count register .............................................................1508 37-86 latecol: late collisions count register ..........................................................1509 37-87 colc: collision count register ........................................................................1509 37-88 dc: defer count register ...............................................................................1510 37-89 tncrs: transmit with no crs count register ...................................................1510 37-90 cexterr: carrier extension error count register ..............................................1511 37-91 rlec: receive length error count register .......................................................1511 37-92 xonrxc: xon received count register ...........................................................1512 37-93 xontxc: xon transmitted count register .......................................................1512 37-94 xoffrxc: xoff received count register .........................................................1513 37-95 xofftxc: xoff transmitted count register .....................................................1513 37-96 fcruc: fc received unsupported count register ..............................................1514 37-97 prc64: good packets received count (64 bytes) register ..................................1514 37-98 prc127: good packets received count (65-127 bytes) register ..........................1515 37-99 prc255: good packets received count (128-255 bytes) register ........................1515 37-100 prc511 - good packets received count (256-511 bytes) register .......................1516 37-101 prc1023: good packets received count (512-1023 bytes) register .....................1516 37-102 prc1522: good packets received count (1024 to max bytes) register .................1517 37-103 gprc: good packets received count (total) register .........................................1518 37-104 bprc: broadcast packets received count register .............................................1518 37-105 mprc: multicast packets received count register ..............................................1519 37-106 gptc: good packets transmitted count register ...............................................1519 37-107 gorcl: good octets received count low register ............................................1520 37-108 gorch: good octets received count high register ...........................................1521 37-109 gotcl: good octets transmitted count low register ........................................1522 37-110 gotch: good octets transmitted count high register .......................................1522 37-111 rnbc: receive no buffers count register .........................................................1523 37-112 ruc: receive undersize count register ............................................................1523 37-113 rfc: receive fragment count register ............................................................1524 37-114 roc: receive oversize count register .............................................................1524 37-115 rjc: receive jabber count register .................................................................1525 37-116 torl: total octets received low register ........................................................1526 37-117 torh: total octets received high register .......................................................1526 37-118 totl: total octets transmitted low register ....................................................1527 37-119 toth: total octets transmitted high register ...................................................1528 37-120 tpr: total packets received register ...............................................................1528
contents intel ? ep80579 integrated processor product line datasheet august 2009 82 order number: 320066-003us 37-121 tpt: total packets transmitted register .......................................................... 1529 37-122 ptc64 - packets transmitted count (64 bytes) register ..................................... 1529 37-123 ptc255: packets transmitted count (128-255 bytes) register ............................ 1530 37-124 ptc511: packets transmitted count (256-511 bytes) register ............................ 1530 37-125 ptc1023: packets transmitted count (512-1023 bytes) register ........................ 1531 37-126 ptc1522: packets transmitted count (1024-1522 bytes) register ...................... 1531 37-127 mptc: multicast packets transmitted count register ......................................... 1532 37-128 bptc: broadcast packets transmitted count register ........................................ 1532 37-129 tsctc: tcp segmentation context transmitted count register .......................... 1533 37-130 tsctfc: tcp segmentation context transmit fail count register ....................... 1533 37-131 wuc - wake up control register (0x05800; rw) ................................................ 1534 37-132 wufc - wake up filter control register (0x05808; rw) ...................................... 1535 37-133 wus - wake up status register (0x05810; rw) ................................................ 1536 37-134 ipav - ip address valid register (0x05838; rw)................................................. 1537 37-135 ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers ...................... 1538 37-136 ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4 ...... 1539 37-137 ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8 .................... 1539 37-138 ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12 ................. 1540 37-139 ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16 .............. 1541 37-140 fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw) .............. 1542 37-141 flexible filter mask table ................................................................................. 1542 37-142 ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw) ............ 1543 37-143 flexible filter mask table ................................................................................. 1543 37-144 ffvt[0-127]: flexible filter value table registers ............................................. 1544 37-145 intbus_err_stat - internal bus error status register ..................................... 1544 37-146 mem_tst - memory error test register ........................................................... 1546 37-147 mem_sts - memory error status register ........................................................ 1547 37-148 mac timing ................................................................................................... 1556 37-149 gbe timing guarantees ................................................................................... 1557 38-1 bus m, device 3, function 0: summary of gcu registers mapped through csrbar memory bar .................................................................................................. 1561 38-2 register-table legend..................................................................................... 1561 38-3 offset 0x00000010h: mdio_status - mdio status register................................ 1562 38-4 offset 0x00000014h: mdio_command - mdio command register....................... 1562 38-5 offset 0x00000018h: mdio_drive - mdio drive register ................................... 1563 38-6 offset 0x00000020h: mdc_drive - mdc drive register ...................................... 1563 38-7 offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register ....... 1564 38-8 offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register ........ 1564 38-9 offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register ........................................................................................................ 1565 38-10 offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register ........................................................................................................ 1566 38-11 offset 0x00000060h: ssp_drive - ssp drive register ........................................ 1566 38-12 offset 0x00000064h: tdm_drive_3 - tdm drive register for tdm ports 3 ............ 1567 38-13 offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2 ..... 1567 38-14 offset 0x00000028h: can_drive - can drive register ....................................... 1568 39-1 cia recommended bit rate and timing parameters ............................................. 1578 39-2 can recommended bit rate and timing parameters ........................................... 1580 39-3 can higher level protocol (hlp) bit assignment ................................................. 1583 39-4 bus m, device 4, function 0: summary of can registers mapped through csrbar memory bar .................................................................................................. 1585 39-5 bus m, device 5, function 0: summary of can registers mapped through csrbar memory bar .................................................................................................. 1586 39-6 offset 00000000h: int_status - interrupt status register .................................... 1587 39-7 offset 00000004h: int_ebl - interrupt enable register ........................................ 1588
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 83 contents 39-8 offset 00000008h: buffer status indicators ........................................................1589 39-9 offset 0000000ch: errorstatus - error status indicators ......................................1590 39-10 offset 00000010h: command - operating modes.................................................1591 39-11 offset 00000014h: config - can configuration register .......................................1592 39-12 offset 00000020h: txmessagecontrol[0-7] - transmit message control and command ....................................................................................................1593 39-13 offset 00000024h: txmessageid[0-7] - transmit message id ...............................1595 39-14 offset 00000028h: txmessagedatahigh[0-7] - transmit message data high ...........1596 39-15 offset 0000002ch: txmessagedatalow[0-7] - transmit message data low.............1597 39-16 offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control ........................................................................................................1598 39-17 offset 000000a4h: rxmessageid[0-15] - receive message id...............................1600 39-18 offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high...........1600 39-19 offset 000000ach: rxmessagedatalow[0-15] - receive message data low ............1601 39-20 offset 000000b0h: rxmessageamr[0-15] - receive message amr .........................1601 39-21 offset 000000b4h: rxmessageacr[0-15] - receive message acr..........................1602 39-22 offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data .......1603 39-23 offset 000000bch: rxmessageacr_data[0-15] - receive message acr data..........1604 40-1 bus m, device 6, function 0: summary of ssp csrs ............................................1606 40-2 offset 00h: sscr0 - ssp control register 0 details ............................................1607 40-3 offset 04h: sscr1 - ssp control register 1 details ............................................1610 40-4 motorola* spi frame formats for spo and sph programming ..............................1613 40-5 offset 08h: sssr - ssp status register details ..................................................1614 40-6 offset 0ch: ssitr - ssp interrupt test register details ......................................1617 40-7 offset 10h: ssdr - ssp data register details ....................................................1618 41-1 channel mapping to interfaces ..........................................................................1622 41-2 clock synchronization protocol flow...................................................................1625 41-3 transparent clock synchronization protocol flow .................................................1626 41-4 ieee1588 version 1 and ieee1588-2008 ptp message formats .............................1628 41-5 message decoding for v1 .................................................................................1629 41-6 message decoding for ieee1588-2008 ...............................................................1629 41-7 ptp frame identification ..................................................................................1632 41-8 timestamping configurations............................................................................1633 41-9 addend values ................................................................................................1636 41-10 bus m, device 7, function 0: summary of ieee 1588 tsync csrs .........................1637 41-11 offset 0000h: ts_control register ....................................................................1639 41-12 offset 0004h: ts_event register .....................................................................1641 41-13 offset 0008h: ts_addend register ..................................................................1643 41-14 offset 000ch: ts_accum register ...................................................................1643 41-15 offset 0010h: ts_test register .......................................................................1644 41-16 offset 0014h: ts_pps_compare register .........................................................1646 41-17 offset 0018h: ts_rsystimelo register ............................................................1647 41-18 offset 001ch: ts_rsystimehi register ............................................................1648 41-19 offset 0020h: ts_systimelo register ..............................................................1649 41-20 offset 0024h: ts_systimehi register ..............................................................1650 41-21 offset 0028h: ts_trgtlo register ....................................................................1650 41-22 offset 002ch: ts_trgthi register ....................................................................1651 41-23 offset 0030h: ts_asmslo register .................................................................1652 41-24 offset 0034h: ts_asmshi register ...................................................................1653 41-25 offset 0038h: ts_ammslo register ..................................................................1654 41-26 offset 003ch: ts_ammshi register ..................................................................1655 41-27 offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel) ........................................................................1656 41-28 offset 0044h: ts_ch_event[0-7] - time synchronization channel event register per ethernet channel) .........................................................................1658
contents intel ? ep80579 integrated processor product line datasheet august 2009 84 order number: 320066-003us 41-29 offset 0048h: ts_txsnaplo[0-7] - transmit snapshot low register (per ethernet channel) .................................................................................... 1659 41-30 offset 004ch: ts_txsnaphi[0-7] - transmit snapshot high register (per ethernet channel) .................................................................................... 1660 41-31 offset 0050h: ts_rxsnaplo[0-7] - receive snapshot low register (per ethernet channel) .................................................................................... 1661 41-32 offset 0054h: ts_rxsnaphi[0-7] - receive snapshot high register (per ethernet channel) .................................................................................... 1662 41-33 offset 0058h: ts_srcuuidlo[0-7] - source uuid0 low register (per ethernet channel) .................................................................................... 1663 41-34 offset 005ch: ts_srcuuidhi[0-7] - sequenceid/sourceuuid high register (per ethernet channel) ................................................................................... 1664 41-35 offset 0140h: ts_canx_status[0-1] - time synchronization channel event register (per can channel) ............................................................................. 1665 41-36 offset 0144h: ts_cansnaplo[0-1] - transmit snapshot low register (per can channel).......................................................................................... 1666 41-37 offset 0148h: ts_cansnaphi[0-1] - transmit snapshot high register (per can channel).......................................................................................... 1667 41-38 offset 01f0h: ts_aux_trgtlo register ............................................................. 1668 41-39 offset 01f4h: ts_aux_trgthi register .............................................................. 1668 41-40 offset 0200h: l2 ethertype register ................................................................. 1669 41-41 offset 0204h: user defined ethertype register .................................................. 1669 41-42 offset 0208h:user defined header offset register .............................................. 1670 41-43 offset 020ch:user defined header register ....................................................... 1670 42-1 example expansion bus pin mappings to target devices ...................................... 1673 42-2 expansion bus address and data byte steering ................................................. 1676 42-3 multiplexed output pins for hpi operation.......................................................... 1682 42-4 hpi hcntl control signal decoding .................................................................. 1682 42-5 bus m, device 8, function 0: summary of local expansion bus registers mapped through csrbar pci memory bar"............................................................................... 1697 42-6 exp_timing_cs0 - expansion bus timing register ............................................. 1698 42-7 exp_timing_cs[1-7] - expansion bus timing registers .................................... 1700 42-8 exp_cnfg0 -configuration register 0 ............................................................... 1702 42-9 exp_parity_status - expansion bus parity status register .............................. 1703 42-10 leb performance calculation - estimated aioc latencies ..................................... 1704 42-11 outbound performance estimation examples ...................................................... 1705 43-1 ep80579 taps public instructions...................................................................... 1710 43-2 ep80579 tap idcode values ............................................................................ 1710 43-3 jtag instructions summary for mch ............................................................... 1711 43-4 compliance pins excluded from boundary scan chain .......................................... 1713 44-1 1149.1 public instructions in the ia-32 core tap ............................................... 1715 44-2 device id register bit-fields ............................................................................ 1716 45-1 imch jtag instructions .................................................................................. 1717 45-2 jtag device identification register field designations ........................................ 1718 45-3 jtag id code for cmi ..................................................................................... 1718 46-1 serial test mode entry command field .............................................................. 1722 46-2 test control register 0 ................................................................................... 1723 46-3 xor chains.................................................................................................... 1725 47-1 base features of ep80579 skus ....................................................................... 1730 47-2 ia-32 core internal bus and ddr2 frequencies .................................................. 1731 47-3 tolapai strap options ...................................................................................... 1731 47-4 ep80579 pre-boot firmware programmable options ............................................ 1732 48-1 signal type definitions .................................................................................... 1733 48-2 xor chain elements ....................................................................................... 1734 48-3 signal pin description references ..................................................................... 1735
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 85 contents 48-4 ia-32 core thermal signals ..............................................................................1736 48-5 global clock and reset (cru) signals ................................................................1736 48-6 sideband miscellaneous signals.........................................................................1737 48-7 imch reset signals .........................................................................................1739 48-8 ddr2 interface signals ....................................................................................1739 48-9 pci express interface signals ...........................................................................1741 48-10 real time clock interface signals ......................................................................1744 48-11 general-purpose io signals ..............................................................................1744 48-12 iich interrupt signals......................................................................................1748 48-13 spi interface signals .......................................................................................1749 48-14 lpc and fwh interface signals .........................................................................1749 48-15 smbus interface signals...................................................................................1750 48-16 uart signals ..................................................................................................1751 48-17 serial ata interface signals..............................................................................1753 48-18 usb interface signals ......................................................................................1755 48-19 power management interface signals.................................................................1756 48-20 iich miscellaneous signals ...............................................................................1758 48-21 controller area network bus signals ..................................................................1759 48-22 gigabit ethernet interface signals .....................................................................1760 48-23 tdm interface signals, .....................................................................................1764 48-24 expansion bus signals .....................................................................................1765 48-25 ssp interface signals ......................................................................................1768 48-26 ieee 1588-2008 hardware assist interface signals ..............................................1768 48-27 jtag interface signals .....................................................................................1769 48-28 miscellaneous signals ......................................................................................1770 48-29 reserved pin list.............................................................................................1770 48-30 no connect pin list .........................................................................................1771 48-31 power and ground summary pin list .................................................................1772 48-32 alphabetical ball listing....................................................................................1779 48-33 alphabetical signal listing ................................................................................1788 48-34 ep80579 ball map (bottom view, left side) ..........................................................1797 48-35 ep80579 ball map (bottom view, right side) ........................................................1799 48-36 ep80579 ball map (top view, left side) ...............................................................1801 48-37 ep80579 ball map (top view, right side) .............................................................1803 48-38 package trace length ......................................................................................1805 49-1 absolute maximum ratings...............................................................................1820 49-2 undershoot and overshoot for pci, jtag, sata and cru signal groups .................1821 49-3 undershoot and overshoot for ddr2 signal group...............................................1821 49-4 undershoot and overshoot for gbe signal group .................................................1822 49-5 undershoot and overshoot for rtc, spi, usb, tdm, lebus, can, ssp, ieee 1588-2008, ich miscellaneous, iich, smbus, uart, lpc, gpio, sideband miscellaneous, imch, pmi, and miscellaneous signal groups .......................................................................1822 49-6 operating conditions power supply rails ............................................................1823 49-7 maximum supply current embedded sku...........................................................1825 49-8 maximum supply current accelerated sku .........................................................1827 49-9 platform external/internal clock interface ..........................................................1829 49-10 power management dc input characteristics ......................................................1831 49-11 power management dc output characteristics ....................................................1831 49-12 power sequencing signal timings......................................................................1832 49-13 ddr2 dc input characteristics..........................................................................1836 49-14 ddr2 dc output characteristics........................................................................1836 49-15 ddr2 differential input/output ac levels...........................................................1838 49-16 ddr2-400 interface ac characteristics ..............................................................1839 49-17 ddr2-533 interface ac characteristics ..............................................................1840 49-18 ddr2-667 interface ac characteristics ..............................................................1841
contents intel ? ep80579 integrated processor product line datasheet august 2009 86 order number: 320066-003us 49-19 ddr2-800 interface ac characteristics .............................................................. 1842 49-20 pci express* differential receiver (rx) specifications ......................................... 1847 49-21 pci express* differential transmitter (tx) specifications ..................................... 1848 49-22 pci express* clock dc specifications ................................................................ 1850 49-23 pci express* clock timings ............................................................................. 1850 49-24 sata dc input characteristics (sata_rx[p,n]) .................................................. 1854 49-25 sata dc input characteristics (gpio and sataled#) ......................................... 1854 49-26 sata dc output characteristics (sata_tx(p,n)) ................................................ 1855 49-27 sata dc output characteristics (sataled#) ..................................................... 1855 49-28 sata dc clock specifications (sata_clkn, sata_clkp) ..................................... 1855 49-29 sata clock (sata_clkp, sata_clkn) .............................................................. 1856 49-30 sata interface timings ................................................................................... 1856 49-31 usb overcurrent indicators dc input (oc[1:0]) ................................................. 1857 49-32 usb lv differential dc characteristics (usbn[1:0], usbp[1:0]) ............................ 1858 49-33 usb clock (clk48) dc input specifications ........................................................ 1859 49-34 usb input clock (clk48) ac specifications ........................................................ 1859 49-35 usb timing specifications ................................................................................ 1860 49-36 smbus dc input characteristics........................................................................ 1863 49-37 smbus dc output characteristics...................................................................... 1863 49-38 smbus dc clock specification........................................................................... 1863 49-39 smbus input ac characteristics ........................................................................ 1864 49-40 smbus clock timings (smbclk) ....................................................................... 1865 49-41 smbus output ac characteristics ...................................................................... 1865 49-42 uart dc input characteristics ......................................................................... 1867 49-43 uart dc output characteristics ....................................................................... 1867 49-44 uart dc clock specification ............................................................................ 1868 49-45 uart timing .................................................................................................. 1868 49-46 uart timing .................................................................................................. 1868 49-47 spi dc input characteristics ............................................................................ 1869 49-48 spi dc output characteristics .......................................................................... 1869 49-49 spi timing specifications ................................................................................. 1869 49-50 lpc dc input characteristics ............................................................................ 1871 49-51 lpc dc output characteristics .......................................................................... 1871 49-52 lpc dc clock specifications ............................................................................. 1871 49-53 lpc clock ac characteristics ............................................................................ 1872 49-54 lpc input timing specification ......................................................................... 1872 49-55 lpc output timing specification ....................................................................... 1872 49-56 gpio dc input characteristics .......................................................................... 1874 49-57 gpio dc output characteristics ........................................................................ 1875 49-58 iich interrupt signal dc input characteristics.................................................... 1875 49-59 iich interrupt signal dc output characteristics.................................................. 1875 49-60 iich interrupt signal timing specification.......................................................... 1876 49-61 iich clock (clk14) ac specifications ................................................................ 1876 49-62 rtc dc input characteristics (rtest#) ............................................................. 1877 49-63 rtc dc clock input characteristics (rtcx[2:1]) ................................................. 1878 49-64 rtc clock input (rtcx[2:1])timing values ........................................................ 1878 49-65 rtc clock output (susclk) timings ................................................................. 1878 49-66 dc input characteristics: rmii mode of operation............................................... 1879 49-67 dc output characteristics: rmii mode of operation............................................. 1880 49-68 dc input characteristics: rgmii mode of operation............................................. 1880 49-69 dc output characteristics: rgmii mode of operation........................................... 1880 49-70 dc input characteristics: mdio mode of operation.............................................. 1881 49-71 dc output characteristics: mdio mode of operation ........................................... 1881 49-72 dc input characteristics: eeprom interface ....................................................... 1881 49-73 dc output characteristics: eeprom interface..................................................... 1882
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 87 contents 49-74 reference clock dc input specification: (gbe_refclk_rmii, gbe_refclk) ...........1882 49-75 frequencies of all input clocks..........................................................................1882 49-76 gbe rgmii reference clock timing values..........................................................1883 49-77 gbe transmit timing values ? rgmii mode........................................................1884 49-78 gbe receive timing values ? rgmii mode .........................................................1886 49-79 gbe transmit and receive timing values ? rmii 100/10 base mode .....................1888 49-80 mdio timings values.......................................................................................1889 49-81 eeprom read operation ..................................................................................1889 49-82 eeprom timing values ....................................................................................1890 49-83 tdm dc input characteristics ...........................................................................1891 49-84 tdm dc output characteristics .........................................................................1892 49-85 tdm dc clock input specifications (rx_clkn) ....................................................1892 49-86 tdm dc clock output specifications (tx_clkn)...................................................1892 49-87 tdm, serial timings values...............................................................................1893 49-88 leb dc input characteristics ............................................................................1895 49-89 leb dc output characteristics ..........................................................................1895 49-90 leb dc clock input specifications (external clock) ..............................................1895 49-91 local expansion bus synchronous operation timing values ..................................1896 49-92 can dc input characteristics............................................................................1897 49-93 can dc output characteristics..........................................................................1897 49-94 ssp dc input characteristics ............................................................................1898 49-95 ssp dc output characteristics ..........................................................................1898 49-96 ssp dc clock specification ...............................................................................1898 49-97 ssp timing values and test conditions ..............................................................1900 49-98 ieee 1588-2008 hardware assist dc input characteristics....................................1901 49-99 ieee 1588-2008 hardware assist dc output characteristics..................................1901 49-100 iich miscellaneous signals dc input characteristics ............................................1902 49-101 iich miscellaneous signals dc output characteristics ..........................................1902 49-102 cru differential clock dc specifications .............................................................1903 49-103 cru differential input clock timing specifications ...............................................1904 49-104 sideband miscellaneous signals dc input characteristics ......................................1905 49-105 sideband miscellaneous signals dc output characteristics ....................................1906 49-106 imch reset signals dc input characteristics.......................................................1906 49-107 jtag dc specifications (except bpm4_prdy_out)...............................................1907 49-108 jtag dc output specifications (bpm4_prdy_out) ..............................................1907 49-109 jtag timing specifications ...............................................................................1907 50-1 ep80579 thermal design power (tdp) and maximum case temperature specifications (tc-max) .......................................................................................................1912 50-2 prochot_dty/thtl_dty throttle ratios...........................................................1916
revision history intel ? ep80579 integrated processor product line datasheet august 2009 88 order number: 320066-003us revision history date revision description august 2009 003 changed the following signal names: ?ex_req_gnt# to reserved 19 ?ex_slave_cs# to reserved 20 ?ex_gnt_req# to nc57 ?ex_wait# to nc58 ? ex_wdtxfer to nc59 corrected signal name: ? siu_cst1 to siu_cst1# ? siu_cst2 to siu_cst2# updated: ? section product features ? ta b l e 1 - 4 , ? g l o s s a r y ta b l e ? ? table 2-1, ?ep80579 external interface summary? ? table 5-32, ?summary of local expansion bus error conditions? ? table 6-5, ?powergood reset timings? ? section 6.3.2.1, ?transitioning between power states? ? section 11.4.6, ?rcomp? ? section 16.5.1.64, ?offset 268h: ddriomc2 - ddr io mode control register 2? ? section 23.1.1.5, ?pi - programming interface register? ? section 37.5.11.6.3, ?checksum word calculation? ? section 42.5, ?register summary? ? table 42-7, ?exp_timing_cs[1-7] - expansion bus timing registers? ? table 42-9, ?exp_parity_status - expansion bus parity status register? ? table 42-10, ?leb performance calculation - estimated aioc latencies? ? table 48-24, ?expansion bus signals? ? table 48-22, ?gigabit ethernet interface signals? with signal name changes ? figure 49-28, ?lpc valid delay from rising clock edge diagram? and figure 49-32, ?iich clock (clk14) timing diagram? with signal name corrections ? table 49-10, ?power management dc input characteristics? pwrbtn# pin ? table 49-11, ?power management dc output characteristics? pwrbtn# pin ? table 49-36, ?smbus dc input characteristics? intruder# pin ? table 49-37, ?smbus dc output characteristics? intruder# pin ? table 49-106, ?imch reset signals dc input characteristics? clk100 ( continued next page )
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 89 revision history august 2009 003 added: ? industrial temperatures to chapter 49.0, ?electrical specifications? and chapter 50.0, ?thermal specifications and design considerations? the following changes were made due to defeaturing leb mastering: ? section 2.2, ?signaling architecture? ? table 2-1, ?ep80579 external interface summary? - leb description ? table 2-4, ?summary of communication? - removed ?leb master? ? table 3-7, ?address space sizes of aioc-attached devices? - removed leb row ?note e in table 3-11, ?pci configuration header support for type 0 headers in aioc devices? ? section 4.2.2, ?other agents? - fourth bullet removed ?master? ? table 5-32, ?summary of local expansion bus error conditions? - notes description ?removed rows in table 7-67, ?bus m, device 8, function 0: summary of local expansion bus registers mapped through csrbar pci memory bar"? containing leb content ? removed leb content from section 36.3, ?local expansion bus interface (leb)? ? removed content from section 42.0, ?local expansion bus controller? ??exp_mst_control - expansion bus control register? ??exp_lock0 - expansion bus lock register? ??offset d0500010h: cmd_trns1_w[0-3] - command translation window register ? ? removed leb content from section 42.1, ?overview? and section 42.2, ?feature list? ? removed leb content from figure 42-1, ?expansion bus controller? ? removed leb content and also ?inbound transfers? , ?arbitration?, ?expansion bus inbound timing diagrams? and ?external expansion bus timing diagram? content from section 42.4, ?theory of operation? ? removed table 42-16 and section 42.5.2.6 removed: removed two rows with d30/d31 content from ta b l e 1 - 4 , section 6.1.2.3.1, ?iich? , table 28-9 , and from pcirst# description in table 48-28 . date revision description
revision history intel ? ep80579 integrated processor product line datasheet august 2009 90 order number: 320066-003us december 2008 002 added: ? chapter 28.0, ?ia-32 core interface? updated: ? figure 6-1, ?powergood and reset interface? ? table 49-12, ?power sequencing signal timings? ? table 16-26, ?offset 9ch: devpres - device present register? ? table 16-40, ?offset f6h: imch_tst2 - imch test byte 2 register? ? section 22.1, ?overview? ?text in section 35.12.1.9, ?offset 14h: mmbar ? expansion bus base address register? ?text in section 42.5.1.2, ?exp_timing_cs[1-7 ] - expansion bus timing registers? ? figure 42-2, ?chip select address allocation when there are no 32-mbyte devices programmed? ? figure 42-4, ?chip select address allocation when a 32 mbyte device is programmed? ? figure 48-3, ?fcbga package ? bottom view? ? table 48-24, ?expansion bus signals? ? table 48-29, ?reserved pin list? ? table 48-30, ?no connect pin list? ? table 49-7, ?maximum supply current embedded sku? ? table 49-11, ?power management dc output characteristics? ? table 49-36, ?smbus dc input characteristics? ? table 49-38, ?smbus dc clock specification? ? table 49-48, ?spi dc output characteristics? ? table 49-67, ?dc output characteristics: rmii mode of operation? ? table 49-82, ?eeprom timing values? ? table 49-84, ?tdm dc output characteristics? ? table 49-89, ?leb dc output characteristics? ? table 49-93, ?can dc output characteristics? ? table 49-95, ?ssp dc output characteristics? ? table 49-99, ?ieee 1588-2008 hardware assist dc output characteristics? ? table 49-101, ?iich miscellaneous signals dc output characteristics? ? table 49-108, ?jtag dc output specifications (bpm4_prdy_out)? july 2008 001 initial release of this document. date revision description
order number: 320066-003us introduction and overview, volume 1 of 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 92 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 93 intel ? ep80579 integrated processor 1.0 introduction 1.1 introduction the intel ? ep80579 integrated processor product line is made of up of the intel ? ep80579 integrated processor and the intel ? ep80579 integrated processor with intel? quickassist technology. the intel ? ep80579 integrated processor product line is an integrated system on a chip (soc). the intel ? ep80579 integrated processor with intel? quickassist technology architecture combines intel architecture (ia)-based communications processors, a memory hub controller (imch), an i/o architecture (iich), and high speed i/o interfaces (pci express*, gigabit ethernet). the intel ? ep80579 integrated processor with intel? quickassist technology also features high- performance packet processing and security capabilities. the intel ? ep80579 integrated processor product line architecture is designed to provide best-in-class processing performance, stringent power usage, and reasonable cost targets while maintaining ia implementation and providing the required i/o throughput. the intended audience for this document is architects, hardware/software design engineers or designer who may need specific technical information for the development and programming of the ep80579 integrated processor soc. this document is also intended for an audience that has a thorough understanding of ia-32 microprocessor, memory controller and i/o architectures as well as a basic understanding of system software architectures (operating system and pre-boot firmware). 1.2 document organization note: the intel ? ep80579 integrated processor product line is referred to as the "ep80579". in cases where the features are specific to a given processor we will use intel ? ep80579 integrated processor or intel ? ep80579 integrated processor with intel? quickassist technology. this document first provides an overview of the intel ? ep80579 integrated processor product line architecture. the overview chapter provides a block diagram and defines the ?s external and internal interfaces. this is followed by a functional description of the following blocks: ? ia complex (including the ia-32 core, imch and iich). ? acceleration and i/o complex (including asu, ssu, and high-speed i/o interfaces such as gigabit ethernet and tdm). ? test and debug information, including jtag. ? technical specifications (skus, packaging, electrical and thermal).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 94 order number: 320066-003us 1.3 referenced document s and related websites visit the intel ? ep80579 integrated processor product line website for other information: http://www.intel.com/go/soc table 1-1. referenced documents document title location advanced configuration and power interface (acpi) specification http://www.acpi.info/ enhanced host controller specification (ehci and uhci) http://www.intel.com/technology/usb/spec.htm/ ieee 1149.1: ieee standard test access port and boundary-scan architecture http://ieeexplore.ieee.org ieee 1588:precision clock synchronization protocol for networked measurement and control systems http://ieeexplore.ieee.org intel architecture software developer?s manual, volumes 1?3 http://developer.intel.com/design/pentium4/ manuals/index_new.htm#sdm_vol1 intel corporation, advanced host controller interface specification for serial ata http://www.intel.com/technology/serialata/ ahci.htm intel corporation, enhanced host controller interface specification for universal serial bus http://www.intel.com/technology/usb/ ehcispec.htm intel corporation, low pin count (lpc) interface specification http://www.intel.com/design/chipsets/industry/ lpc.htm intel corporation, multiprocessor specification http://www.intel.com/design/archives/processors/ pro/docs/242016.htm intel corporation, universal host controller interface (uhci) specification http://www.intel.com/technology/usb/ ehcispec.htm intel corporation, universal serial bus (usb) specification http://www.intel.com/technology/usb/spec.htm intel corporation, usb2 debug device functional specification http://www.intel.com/technology/usb/download/ debugdevicespec_r090.pdf intel ? 82093aa i/o advanced programmable interrupt controller (i/o apic) http://www.intel.com/design/chipsets/specupdt/ 290710.htm?iid=search& intel ? ep80579 integrated processor product line platform design guide http://www.intel.com/go/soc intel ? ep80579 integrated processor product line specification update http://www.intel.com/go/soc intel ? ep80579 integrated processor product line thermal/mechanical design guide http://www.intel.com/go/soc jedec specification http://www.jedec.org/default.cfm low pin count specification (lpc) http://www.intel.com/design/chipsets/industry/ lpc.htm serial ata specification http://www.serialata.org/specifications.asp smbus specification http://www.smbus.org/specs/ universal host controller specification (ehci and uhci) http://www.intel.com/technology/usb/spec.htm/ universal serial bus specification http://www.usb.org/developers/docs/ http://www.intel.com/technology/usb/spec.htm/
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 95 intel ? ep80579 integrated processor 1.4 acronyms this section describes acronyms that are used throughout this document. table 1-2. related websites specification or technology website ac?97 rev 2.2 specification http://developer.intel.com/ial/scalableplatforms/ audio/index.htm #97spec/ acpi and related specifications http://www.acpi.info/spec.htm at attachment-6 with packet interface (ata/atapi-6) http://t13.org (t13 1410d) bios boot specifications http://www.phoenix.com/en/customer+services/ white+papers-specs/ communication and network riser rev 1.2 specification http://developer.intel.com/technology/cnr/ download.htm front panel i/o connectivity design guide http://www.formfactors.org/developerresources.asp pci and pci express* related specifications http://www.pcisig.com/specifications pirq routing table information http://www.microsoft.com/whdc/archive/pciirq.mspx power management specifications http://www.microsoft.com/whdc/resources/respec/ specs/pmref/default.mspx table 1-3. acronym table term description acpi advanced configuration and power interface specification, an industry specification of the common interfaces enabling robust operating system (os)-directed motherboard device configuration and power management of both devices and entire systems. ahci advanced host controller interface, an industry specification of the interface between memory and sata devices. aio imch a-unit i/o mux leg aioc acceleration and i/o complex amc audio/modem codec arp address resolution protocol asf alert specification format. this is the next generation of ?alert on lan*? implementation. asu acceleration services unit bar pci base address register used to define the base and limit of an i/o or memory region assigned to a pci device. ber bit error rate bga ball grid array cm coherent memory cmc common mode choke cmi c ore (ia-32 core) interface, m emory controller hub, i /o controller hub cnr communications and networking riser crc see cyclic redundancy check in ta b l e 1 - 4 . csma/cd carrier sense multiple access/carrier detect ddp direct data placement protocol ddr ddr sdram (double data rate synchronous dynamic random access memory) is a system memory technology.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 96 order number: 320066-003us ded double-bit error detect dma see direct memory access in ta b l e 1 - 4 . dw double word. a legacy reference to 32 bits of data on a naturally aligned four-byte boundary (i.e. the least significant two bits of the byte address are b00). this is a legacy term used by pci and must not be used other than in that context. ecc error checking and correction edma enhanced dma emi electro magnetic interference emts electrical mechanical thermal specification used for processor specifications. eop/eof end of packet / end of frame esd electrostatic discharge exp a generic designation for the i/o interconnect technology also known as pci express*. fru field replaceable unit fs full-speed. refers to usb. fsb front side bus (a common external interface for ia processors) fwh firmware hub. a non-volatile memory device used to store the system bios/pre-boot firmware. gbe gigabit ethernet controller gmii gigabit mii hba host bus adapter - necessary when connecting a peripheral to a computer that doesn?t have native support for that peripheral?s interface. hcd host controller device - usb interface for programmers hecbase pci express* enhanced configuration base register hpet high precision event time (hpet) - the ia-pc hpet architecture defines a set of timers that can be used by the operating system. the timers are defined such that the os may be able to assign specific timers to be used directly by specific applications. each timer can be configured to generate a separate interrupt. hsi high speed interface. refers to usb. i/o 1. input/output. 2. when used as a qualifier to a transaction type, specifies that transaction targets intel architecture? specific i/o space (e.g., i/o read). ia intel architecture instruction set commonly known as ?x86? ia-cpu ia-cpu, ia complex and ia processor are the same terminology ich i/o controller hub, ich and iich are interchangeable for entire document iich integrated i/o controller hub, ich and iich are interchangeable for entire document imch integrated memory controller hub, mch and imch are interchangeable for the entire document intx legacy pci interrupt architecture that encodes interrupts on one of four side-band signals (inta, intb, intc, and intd). ip internet protocol isa see industry standard architecture in ta b l e 1 - 4 leb local expansion bus, or le bus lml latency measurement logic lpc low pin count ls low-speed. refers to usb. lsb least significant bit table 1-3. acronym table term description
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 97 intel ? ep80579 integrated processor lsb least significant byte mch memory controller hub, mch and imch are interchangeable for the entire document mii media independent interface (16 pins per port) mmio memory mapped i/o mmr memory mapped register msb most significant bit msb most significant byte msi message-signaled interrupt that encodes inte rrupts as an in-band 32-bit write transaction. mtbf mean time between failures ncm non coherent memory nic network interface controller nos network operating system nsi north south interface. the designation for the proprietary, internal high-speed serial interconnect between the imch and the iich. os operating system. ospm operating system directed power management p2p see peer-to-peer in ta b l e 1 - 4 pb packet buffer pbm packet buffer memory pci peripheral component interconnect local bus. a 32- or 64-bit bus with multiplexed address and data lines that is primarily inte nded for use as an interconnect mechanism within a system between processor/memory and peripheral components or add-in cards. pcm pulse code modulation pec packet error checking. this is an smbus 2.0 feature. phy physical layer device poc power-on-configuration rasum reliability, availability, serviceability, usabilit y, and manageability, which are all important characteristics of servers. rcba root complex base address register at d31:f0:regf0h. it specifies the physical address of the cmi configuration space. also used in rcba + offset xxxxh or rcba + xxxxh (where xxxxh is the offset) to indicate register location in the cmi configuration space. rcrb root complex register block, as defined in the pci express* specification v1.0a . in the iich context, it refers to a part of the cmi configuration space (see rcba, above). rdma remote direct memory access rfl receive fifo level rgmii reduced gmii rmii reduced mii (7 pins per port) rmw read-modify-write operation rtc real-time clock rtcreset# signal that resets the rtc well (but does not clear the rtc ram memory contents). rx receive sata serial advanced technology attachment sata* serial ata, an industry specification of the interface for storage controllers and devices. table 1-3. acronym table term description
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 98 order number: 320066-003us 1.5 glossary this section presents a glossary for this document. sec single-bit error correct sec/ded single error correct/double error detect - a specific data protection algorithm that distributes data and ecc across 144 bits. enables correction of single bit errors. allows detection of double bit errors. sop/sof start of packet / start of frame smm system management mode spd serial presence detect ssu security services unit str suspend to ram tap test access port used for testability and debug of the component. tx transmit tco total cost of ownership tcp transmission control protocol tdm time division multiplexed tdr time domain reflectometry tfl transit fifo level tid see transaction identifier in ta b l e 1 - 4 usb universal serial bus vcmi ia-32 core, ia-32 c ore interface, m emory controller hub, i /o controller hub vlan virtual local area network wdt watch dog timer table 1-3. acronym table term description table 1-4. glossary table (sheet 1 of 5) term definition bga micro ball grid array aioc direct (ad) aioc direct (ad) memory regions are not coherent with ia caches when accessed from aioc agents. accesses to these memory regions enter the memory system through the memory controller avoiding the imch. memory regions that are not coherent with ia caches need not be accessible to the ia cpu. agent a logical device connected to a bus or shared interconnect that can either initiate accesses or be the target of accesses. alt access mode mode to allow the reading of write-only registers, usually used when saving/restoring register content for power management sleep state implementations. anti-etch any plane-split, void or cutout in a v cc or gnd plane is referred to as an anti-etch. asserted signal is set to a level that represents logical true. asynchronous 1. an event that causes a change in state with no relationship to a clock signal. 2. when applied to transactions or a stream of transactions, a classification for those that do not require service within a fixed time interval.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 99 intel ? ep80579 integrated processor atomic operation a series of two or more transactions to a device by the same initiator which are guaranteed to complete without intervening accesses by a different master. most commonly required for a read-modify-write (rmw) operation. block locking ability to lock the fwh?s blocks to write-protect, read-protect, or open state. buffer 1. a random access memory structure. 2. the term i/o buffer is also used to describe a low- level input receiver and output driver combination. cx states processor power states (cx states) are processor power consumption and thermal management states within the global working state, g0. ? c0: processor power state - while the processor is in this state, it executes instructions. ? c1: processor power state - this power state has the lowest latency. the hardware latency in this state must be low enough that the operating software does not consider the latency aspect of the state when deciding whether to use it. ? c2: processor power state - this state offers improved power savings over the c1 state. the worst-case hardware latency for this state is provided via the acpi system firmware and operating software can use this information to determine when the c1 state should be used instead of the c2 state. ? c3: processor power state - this state is not supported. the c3 state offers improved power savings over the c1 and c2 states. the worst-case hardware latency for this state is provided via the acpi system firmware and the operating software can use this information to determine when the c2 state should be used instead of c3 state. while in the c3 state, the processor?s caches maintain state but ignore any snoops. cache line the unit of memory that is copied to and individually tracked in a cache. specifically, 64 bytes of data or instructions aligned on a 64-byte physical address boundary. cfg used as a qualifier for transactions that target pci configuration address space. character the raw data byte in an encoded system (i.e., the 8b value in a 8b/10b encoding scheme). this is the meaningful quantum of information to be transmitted or that is received across an encoded transmission path. cmi ia-32 c ore interface, m emory controller hub, i /o controller hub coherent (c) transactions that ensure that the processor?s view of memory through the cache is consistent with that obtained through the i/o subsystem. in ep80579 integrated processor, coherent (c) memory regions are coherent with ia caches when accessed from aioc agents. accesses to these memory regions enter the memory system through the imch. memory regions that are coherent with ia caches must be accessible to the ia cpu. command the distinct phases, cycles, or packets that make up a transaction. requests and completions are referred to generically as commands. completion a packet, phase, or cycle used to terminate a transaction on a interface, or within a component. a completion will always refer to a preceding request and may or may not include data and/or other information. core power well main system power, turns off in s3 ? s5 cyclic redundancy check a number derived from, and stored or transmitted with, a block of data in order to detect corruption. by recalculating the crc and comparin g it to the value originally transmitted, the receiver can detect some types of transmission errors. deasserted signal is set to a level that represents logical false. deferred transaction a processor bus split transaction. the requesting agent receives a deferred response which allows other transactions to occur on the bus. later, the response agent completes the original request with a separate deferred reply transaction. delayed transaction a transaction where the target retries an initial request, but unknown to the initiator, forwards or services the request on behalf of the initiato r and stores the completion or the result of the request. the original initiator subsequently reissues the request and receives the stored completion. direct memory access method of accessing memory on a system without interrupting the processors on that system. downstream describes commands or data flowing away from the processor-memory complex and toward i/ o. the terms upstream and downstream are never used to describe transactions as a whole. (e.g. downstream data may be the result of an outbound write, or an inbound read. the completion to an inbound read travels downstream.) table 1-4. glossary table (sheet 2 of 5) term definition
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 100 order number: 320066-003us full duplex a connection or channel that allows data or messages to be transmitted in opposite directions simultaneously. gb/s gigabits per second (10 9 bits per second) gb/s gigabytes per second (10 9 bytes per second) global visibility an operation is said to be globally visible when all side-effects of the operation are visible to every observer in the system. for example, a write to some resource (e.g., memory location, control register, etc.) r achieves global visibility when a read of r by all other agents is guaranteed to return the new value. gx states global system states (gx states) apply to the entire system and are visible to the user. ? g3: mechanical off - a computer state that is entered and left by a mechanical switch. it is implied by the entry of this off state through a mechanical means that no electrical current is running through the circuitry and that it can be worked on without damaging the hardware or endangering service personnel. ? g2/s5: soft off - a computer state where the computer consumes a minimal amount of power. ? g1: sleeping - a computer state where the computer consumes a small amount of power, user mode threads are not being executed, and the system ?appears? to be off (from an end user?s perspective, the display is off, and so on). ? g0: working - a computer state where the system dispatches user mode (application) threads and they execute. in this state, peripheral devices are having their power state changed dynamically. half duplex a connection or channel that allows data or messages to be transmitted in either direction, but not simultaneously. implicit writeback a snoop-initiated data transfer from the bus agent with the modified cache line to the memory controller due to an access to that line. inbound a transaction where the request destination is the processor-memory complex and is sourced from i/o. the terms inbound and outbound refer to transactions as a whole and never to requests or completions in isolation. (e.g., an inbound read generates downstream data, whereas an inbound write has upstream data. even more confusing, the completion to an inbound read travels downstream.) industry standard architecture a 16-bit bus architecture associated with the ibm at motherboard designed to connect motherboard circuitry to expansion card devices that is now considered legacy. initiator the source of requests. [iba] an agent sending a request packet on 3gio is referred to as the initiator for that transaction. the initiator may receive a completion for the request. [3gio] isa regime a special legacy mode to support isa-based devices which have been integrated into the chipset. it opens a dedicated channel from the peripheral device to the processor bus. while in this mode, the legacy device is granted exclus ive accesses to memory and the ability to use tenured transactions. isochronous a classification of transactions or a stream of transactions that require service within a fixed time interval. lane a set of differential signal pairs, one pair for transmission and one pair for reception. a by-n link is composed of n lanes. layer a level of abstraction commonly used in interface specifications as a tool to group elements related to a basic function of the interface within a layer and to identify key interactions between layers. legacy functional requirements handed down from previous chipsets, or pc compatibility requirements from the past. link the collection of two ports and their interconnecting lanes. a link is a dual simplex communications path between two components. lpc bus low pin count connection used to connect to the super i/o device. master a device or logical entity that is capable of initiating transactions. a master is any potential initiator. mbyte/s megabytes per second (10 6 bytes per second) mem used as a qualifier for transactions that target memory space. (for example, a mem read to i/ o.) table 1-4. glossary table (sheet 3 of 5) term definition
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 101 intel ? ep80579 integrated processor metastability a characteristic of flip flops that describes the state where the output becomes non- deterministic. most commonly caused by a setup or hold time violation. multi media timer (mmt) see high precision event timer (hpet) in ta b l e 1 - 3 . non-coherent transactions that may cause the processor?s view of memory through the cache to be different than that obtained through the i/o subsystem. north usually refers to bridges. the bridge or device that is closer to the processor-memory complex. ordering refers to the order in which signals and/or memory accesses to different locations must reach global visibility to ensure some behavior. note that this excludes the ?ordering? necessary to prevent data hazards which are accesses to the same location. outbound a transaction where the request destination is i/o and is sourced from the processor-memory complex. the terms inbound and outbound refer to transactions as a whole and never to requests or completions in isolation. (for example, an outbound read generates upstream data, whereas an outbound write has downstream data. even more confusing, the completion to an outbound read travels upstream.) oword 128 bits of data on a naturally aligned sixteen-byte boundary (e.g., the least significant four bits of the byte address are b?0000?). this is the native size of the imch datapath. packet the indivisible unit of data transfer and routing, consisting of a header, data, and crc. pci reset pcirst#. this is the secondary pci bus reset signal. it is a logical or of the primary interface pltrst# signal and the state of the secondary bus reset bit. peer-to-peer transactions that occur between two devices independent of memory or the processor. platform reset iich asserts pltrst# to reset devices that reside on the primary pci bus. the iich asserts pltrst# during power-up and when a hard reset sequence is initiated through the cf9h register. pltrst# is driven inactive a minimum of 1 ms after both pwrok and vrmpwrgd are driven high. pltrst# is driven for a minimum of 1 ms when initiated through the cf9h register. plesiochronous from greek, meaning almost synchronous. describes signals that have the same nominal digital rate, but are synchronized on different clocks. any variation in rate is constrained within specified limits, which allows a device to process the data signal without buffer underflow or overflow by making periodic compensating adjustments that repeat or delete dummy data bits. however, there is no limit to the phase difference that can accumulate between the signals over time. port 1. logically, an interface between a component and a pci express* link. 2. physically, a group of transmitters and rece ivers located on the same chip that define a link. posted a transaction that is considered complete by the initiating agent or source before it actually completes at the target of the request or de stination. all agents or devices handling the request on behalf of the original initiator must then treat the transaction as being system visible from the initiating interface all the way to the final destination. commonly refers to memory writes. push model method of messaging or data transfer that predominately uses writes instead of reads. queue a first-in first-out (fifo) structure. receiver 1. the agent that receives a packet across an interface regardless of whether it is the ultimate destination of the packet. 2. more narrowly, the circuitry required to convert incoming signals from the physical medium to more perceptible forms. request a packet, phase, or cycle used to initiate a transaction on a interface, or within a component. reserved the contents or undefined states or information that are not defined at this time. using any reserved area is not permitted. reserved register bits must be set to 0. however, when stated, there may be specific instances where a reserved register is either non-zero, or there may be a requirement to make it non-zero. resume power well trickle from power supply, only turns off when power is disconnected from wall. resume reset signal that resets the parts of the iich in the resume power well, generated when the trickle supply turns on. rtc power well powered by a coin cell battery and only turns off when the battery is drained. powers the rtc and some resume events. table 1-4. glossary table (sheet 4 of 5) term definition
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 102 order number: 320066-003us sx states sleeping states (sx states) are types of sleeping states within the global sleeping state, g1. ? s5: soft off state. the main memory power pl ane is shut down in addition to the clock synthesizer and core well power planes for the processor and cmi. the cmi resume well is still powered. ? s4: sleeping state - this state is only used to transition to or from the s5 state. the s4 state is not a supported power management state in cmi. ? s3: suspend to ram (str) state - the clock synthesizer and core well power planes for the processor and cmi are shut down, but the main memory power plane and the cmi resume well remain active. all clocks from synthesizers are shut down during the s3 state. ? s0: awake state - power management state when all power planes are active. simplex a connection or channel that allows data or messages to be transmitted in one direction only. smbus system management bus. a two-wire interface through which various system components may communicate. snooping a means of ensuring cache coherency by monitoring all memory accesses on a common multi- drop bus to determine if an access is to information resident within a cache. south usually refers to bridges. the bridge or device that is further from the processor-memory complex. south port the pci express* downstream root port(s) on the iich. split lock sequence a sequence of transactions that occurs when the target of a lock operation is split across a processor bus data alignment or cache line bound ary, resulting in two read transactions and two write transactions to accomplish a read-modify-write operation. split transaction a transaction that consists of distinct request and completion phases or packets that allow use of bus, or interconnect, by other transactions while the target is servicing the request. symbol an expanded and encoded representation of a data byte in an encoded system (e.g., the 10b value in a 8b/10b encoding scheme). this is th e value that is transmitted over the physical medium. symbol time the amount of time required to transmit a symbol. ta r g e t a device that responds to bus transactions. the agent receiving a request packet is referred to as the target for that transaction. tenured transaction a transaction that holds the bus or interconnect until complete, effectively blocking all other transactions while the target is servicing the request. tra n sa c t i on an overloaded term that represents an operation between two or more agents that can be comprised of multiple phases, cycles, or packets. transaction identifier a multi-bit field used to uniquely identify a transaction. commonly used to relate a completion with its originating request in a split transaction system. transmitter 1. the agent that sends a packet across an interface regardless of whether it was the original generator of the packet. 2. more narrowly, the circuitry required to drive signals onto the physical medium. upstream describes commands or data flowing toward the processor-memory complex and away from i/ o. the terms upstream and downstream are never used to describe transactions as a whole. (for example, upstream data may be the result of an inbound write, or an outbound read. the completion to an outbound read travels upstream.) vcmi ia-32 core, ia-32 c ore interface, m emory controller hub, i /o controller hub table 1-4. glossary table (sheet 5 of 5) term definition
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 103 intel ? ep80579 integrated processor 2.0 architectural overview 2.1 overview this chapter provides an overview of the intel ? ep80579 integrated processor product line architecture. section 2.1.1, ?block summary? gives a high-level summary for each of the major blocks and their internal interfaces. section 2.1.2, ?external interfaces? reviews the ep80579?s external chip interfaces. the block diagrams in figure 2-1 and figure 2-1 show the major ep80579 blocks. 2.1.1 block summary ? the ep80579 ia-32 core runs at 600, 1066, and 1200 mhz with an internal 400 or 533 mhz front-side bus (fsb) interface. the ia-32 core features a 256 kilobyte 2- way level 2 cache (l2). ? the ep80579 imch provides the main path to memory for the ia-32 core and all peripherals that perform coherent i/o (e.g. pci express*, the iich to coherent memory). the imch includes the four channel dma engine as well as a pci express* root complex with 1x8, 2x4, or 2x1 interfaces. the memory controller operates at 200-266-333-400 mhz, depending on external ddr and sku configuration. depending on sku, the ep80579 supports a single channel, 64-bit with ecc, memory controller for external ddr-2 memory (400, 533, 667, and 800 mhz). the ep80579 also supports a 32-bit with ecc mode for cost-sensitive applications. ? the ep80579 iich provides a set of pc platform-compatible i/o devices that include two sata1.0/2.0, one usb1.1/2.0 host controller supporting two usb ports, and two serial 16550 compatible uart interfaces. the iich complex interfaces to the mch through the ?nsi? internal bus interface. ? the ep80579 acceleration and i/o complex (aioc) supports three gigabit ethernet media access controllers, mdio, local expansion bus (leb), two controller area network (can) interfaces, ieee1588 (2-gbe and 2-can ports), and ssp. in addition some sku have three high-speed serial tdm interfaces that provide up to 12 t1/e1. asu and ssu provide the high performance packet processing and accelerate common security capability.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 104 order number: 320066-003us figure 2-1. intel ? ep80579 integrated processor block diagram acceleration and i/o complex imch pci express interface (x1) (gen1, 1x8, 2x4 or 2x1 root complex) ia complex ia-32 core l2 cache (256 kb) iich sata 2.0 (x2) usb 2.0 (x2) uart (x2) gpio (x36) smbus (x2) apic, dma, timers, watch dog timer, rtc, hpet (x3) memory controller hub fsb edma memory controller (ddr-2 400/533/667/800, 64b with ecc) local expansion bus (16b @ 80 mhz) mdio (x1) can (x2) ssp (x1) ieee-1588 gige mac #2 gige mac #0 gi ge mac #1 transparent pci-to-pci bridge spi lpc1.1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 105 intel ? ep80579 integrated processor figure 2-2. intel ? ep80579 integrated processor with intel ? quickassist technology block diagram acceleration and i/o complex ? enabling software required. imch pci express interface (x1) (gen1, 1x8, 2x4 or 2x1 root complex) ia complex ia-32 core l2 cache (256 kb) iich apic, dma, timers, watch dog timer, rtc, hpet (x3) memory controller hub fsb edma memory controller (ddr-2 400/533/667/800, 64b with ecc) tdm interface ? (12 e1/t1) local expansion bus (16b @ 80 mhz) mdio (x1) can (x2) ssp (x1) ieee-1588 acceleration services unit ? security services unit ? (3des, aes, (a)rc4, md5, sha-x, pke, trng) 256 kb asu sram gige mac #2 gige mac #0 gige mac #1 transparent pci-to-pci bridge uart (x2) gpio (x36) smbus (x2) sata 2.0 (x2) usb 2.0 (x2) spi lpc1.1
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 106 order number: 320066-003us 2.1.2 external interfaces ta b l e 2 - 1 summarizes the key features of the external interfaces. table 2-1. ep80579 external interface summary name qty. description external ddr memory 1 single channel memory controller with an ecc enabled 64-bit interface that, depending on sku, supports external ddr-2 memory (400, 533, 667 and 800 mhz). minimum memory size is 128 mb (in 32 bit mode). maximum memory size is 4gb. the ep80579 integrated processor also supports a 32-bit mode (with ecc) for cost-sensitive applications. pci express* (root) 1 supports 1x8, 2x4, or 2x1 configurations as a root complex. gigabit ethernet 3 10/100/1000 gigabit ethernet macs with rgmii/rmii interface. two of the three ports support ieee 1588 hardware assist. tdm 3 8.192 mhz high-speed synchronous serial tdm interfaces that support up to 12 t1/e1 links (sku dependent) with intel software driver provided for hdlc support. local expansion bus 1 25/16-bit 80mhz local expansion bus with 8 programmable chip selects. usb 2.0 1 universal serial bus 2.0 host controller interface, supports two usb ports (shared with usb1.1 ports) usb 1.1 1 universal serial bus 1.1 host controller interface, supports two usb ports (shared with usb2.0 ports) lpc 1 low pin count bus (lpc) interface to attached pc compatible boot flash memory up to 64mb. spi 1 serial peripheral interface (spi). gpio 36 programmable general purpose i/o (gpio) pins. note, intel recomends using this interface to boot from. of the 36pins, many have alternate functions defined. smbus/i2c 2 i2c compatible smbus2.0 connections. uart 2 16550 compatible asynchronous serial ports that support data rate of at least 115kbits/sec. sata 2 sata1.0 or 2.0 used to attached external hard drives. ssp 1 synchronous serial port can 2 controller area network interfaces. mdio 1 mdio interface to support the ethernet interfaces. ieee-1588 1 ieee-1588 hardware assist
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 107 intel ? ep80579 integrated processor 2.1.3 frequencies and gear ratios this section discusses frequencies and gear ratios. the ia core used in the ep80579 is an ia-32 core, and can run at frequencies between 600 and 1200 mhz (actually supported cpu frequencies vary by sku, see chapter 47.0, ?skus, power savings and pre-boot firmware? ). based on divider ratios in its pll design, the ia-32 core imposes a 6:1 minimum core/bus frequency ratio. this limits maximum fsb frequency to 400 or 533 mhz front-side bus (fsb) interface. the ia-32 core/fsb frequency combinations supported are listed in ta bl e 2 - 2 . ta bl e 2 - 3 summarizes the memory controller clock ratios. 2.2 signaling architecture as defined in ta bl e 2 - 4 , the ep80579 supports communication between the ia, aioc devices (asu, ssu, internal i/o devices) and externally attached bus master (pci express* through different memory types using a variety of operations. table 2-2. ia-32 core / fsb frequency ratios (depends on sku and configuration) ia-32 core [mhz] fsb [mhz] ratio 600 400 6:1 1066 533 8:1 1200 533 9:1 table 2-3. memory controller frequencies ddr clock [mhz] ddr technology 200 ddr2-400 266 ddr2-533 333 ddr2-667 400 ddr2-800 table 2-4. summary of communication operation agent targeted memory type a a. ?x? cells are supported with normal or mmio accesses and ?-? cells are not supported. external dram (coherent) external dram (aioc direct) read, write ia x x b asu x x pci-e dma, edma x x b gbe x x atomic ia x - asu x x pci-e dma, edma - - gbe - -
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 108 order number: 320066-003us the ep80579 allows signaling to occur between ia, aioc complex, and externally- attached agents in the appropriate native signaling format. the ep80579 supports basic producer/consumer behavior between agents. because the aioc complex devices are exposed to the ia platform as pci devices, they follow pci ordering semantics when interacting with ia. this enables two fundamental producer/consumer models in coherent memory: the polled and interrupt methods. for the polled method: 1. producer writes data to location ?x? in coherent memory. 2. producer sets flag to location ?y? in coherent memory 3. consumer waits for flag to be set in coherent memory 4. consumer read data from location ?x? in coherent memory to ensure this behavior, agents generating traffic into the imch must ensure that the writes originating from an agent are globally observable in the same order. in the above case x and y must be globally observable in the same order. for the interrupt method: 1. producer writes data to location ?x? in coherent memory. 2. producer generates an interrupt to consumer (asynchronous signal) 3. consumer reads interrupt status from producer?s address space. consumer waits for read to complete before issuing the next transaction. 4. consumer reads data from location ?x? in coherent memory to ensure this behavior, an mmio read issued to the pci device (item 3 above) after a write that originated from this pci device (item 1 above) must not complete out of order. the read completion must push ahead (flush) the write. also the mmio read (item 3 above) should be to a location that is in the device. in the ep80579, it should not be to the pci configuration registers but the device registers pointed to by the pci bar 1 . this ensures that ia device driver software for the ep80579 is not required to include explicit memory fence operations to enable producer-consumer synchronization for interrupt handling. examples: 1. : gige placing received data in coherent dram and interrupting ia, ia issuing a gige csr read, whose read completion must serialize the received dram data stream. 2. : tdm placing received data in coherent dram, then interrupting the ia, then ia gets a pointer to the data. an ia pointer dereference from the ia must see the tdm dram data. 3. : asu placing data in coherent dram, then interrupting the ia, then ia gets a pointer to the data. an ia pointer dereference from the ia must see the asu dram data. b. agents in the ia-32 core may access aioc-direct memory (non-coherent) via uncacheable 1, 2 or 4-byte ia loads/store, ia mmx 8-byte movq instructions or 64-byte dma transfers. while such ia-32 core accesses to aioc-direct memory are not ordered with respect to other asu memory traffic, the aioc-direct memory supports limited one-way communication in which ia agent (or the internal pci agent) is the sole writer and the internal pci agent (or the ia agent) views such me mory locations as read-only. hardware will ensure that self-aligned 1,2, 4, 8 and 64-byte updates will be atomically visible to all readers. 1. the reason for this requirement is that the mch config bus us ed to access the pci configuration registers does not serialize the ep80579 internal pci bus. gige ia ? tdm ia ? asu ia ?
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 109 intel ? ep80579 integrated processor for communication using memory that is not coherent with the ia processor caches, or for direct communication between aioc agents (e.g. between asu, tdm, and gige devices), the ep80579 may require software to insert explicit fencing operations to ensure correct producer/consumer behavior. details are discussed in chapter 4.0, ?signaling? . 2.3 dma and peer-to-peer data transfers the ep80579 provides multiple dma and dma-like features that are summarized here: ? imch edma engine: the four channel imch ?enhanced dma? (edma) engine which supports dword aligned dma. the edma engine supports memory-to- memory and memory-to-pcie transfers. read dma granularity ranges from 1 byte to 4 kilobytes. write dma granularity ranges from 1 to 256 bytes. the edma engine supports different source/target byte alignments that are important for packet processing, and is only programmable via ia pci configuration space with completions signaled via ia interrupts. the edma engine can support burst data movement between ?aioc-direct memory? and ia coherent memory. ? iich dma : supports iich agents to/from memory, this is only used by usb and sata. ? lpc dma: supports lpc agents. see chapter 20.0, ?lpc dma? . ? no peer-to-peer reads: the imch does not support peer-to-peer reads. ta bl e 2 - 5 lists the supported dma and peer-to-peer data transfer options. table 2-5. dma and peer-to-peer data transfer options usage model# operation source destination initiator owner (software) 1 pci dma read dram pci ex device pci ex device ia device driver 2 pci dma write pci ex device dram pci ex device ia device driver 3aioc read dram or aioc device aioc device (ge) device ia, asu 4aioc write aioc device dram or aioc device (ge) device ia, asu 5 aioc 3rd party read dram aioc device (ssu) asu asu 6 aioc 3rd party write aioc device (ssu) dram asu asu 7 peer-to-peer pci read not supported 8 peer-to-peer pci write aioc master or pci ex device pci ex device only aioc master or pci ex device aioc master device driver 9 mem-to-mem dram dram edma engine ia 10 mem-to-memory mapped io dram pci ex or aioc device edma engine ia
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 110 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 111 intel ? ep80579 integrated processor 3.0 platform memory and device configuration 3.1 overview this chapter presents the views of the major address spaces and device configuration structures as seen by various internal and external agents. three related aspects are covered: ? the memory maps seen by various internal and external agents. ? the endianness seen by various agents and mechanisms the ep80579 uses to allow communication between agents with different endianness expectations. ? the pci configuration infrastructure, which the ep80579 exposes through its memory maps. 3.1.1 configuration objectives the ep80579 device and configuration model operates in a system-on-a-chip environment and blends the architectures of many disparate components into a unified whole. the major goals for the device configuration and access architecture include: ? provide a configuration and access model that is aligned with existing ia platform algorithms. ? support a unified address space model. the ia-32 core is the primary agent responsible for device configuration. this is true across all supported skus. to provide device configuration and operation capabilities that are aligned with the ia platform, the ep80579 uses the existing pci infrastructure to expose on-die software- visible sub-blocks as devices on the pci fabric. figure 3-1 presents a logical overview of this organization.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 112 order number: 320066-003us the on-die imch and iich devices materialize on pci bus 0 while the aioc devices materialize on pci bus ?m? that is behind a transparent pci-to-pci bridge on pci bus 0 (the bus that the internal imch and iich devices use). for simplicity, the figure does not show external devices. 3.1.2 terminology and conventions throughout this chapter, we will use the gene ric term ?device? to refer to either a pci device or a function of a pci device. the text will be explicit when the distinction between device and function is important. addresses are always in hexadecimal and broken into 16-bit segments, for example, 0_feed_beef . when the distinction is important and not obvious, addresses are subscripted with ?v?, ?p?, or ?s? for virtual, physical, or system address spaces, respectively. the ep80579 addresses its dram in units of 8-byte quadwords. before assigning byte addresses to the byte lanes in dram, we will refer to the locations as byte lane a through h as ta b l e 3 - 1 illustrates. the byte located in address 0, lane a is refe rred to as 0a, the byte in address 0 lane b is 0b, etc. figure 3-1. device-centric logical view of ep80579 devices ia cpu aioc devices asu ssu gbe imch / iich devices dram edma usb transparent pci-to-pci bridge pci bus 0 pci host bridge pci bus m table 3-1. main memory dram organization address byte lane h byte lane g byte lane f byte lane e byte lane d byte lane c byte lane b byte lane a 00h0g0f0e0d0c0b0a 88h8g8f8e8d8c8b8a 16 16h 16g 16f 16e 16d 16c 16b 16a
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 113 intel ? ep80579 integrated processor 3.2 ia platform infrastructure the imch and iich blocks (which, along with the ia-32 core, are collectively referred to as the vcmi) in the ep80579 provide an ia platform infrastructure with respect to endianness, address spaces and memory maps, configuration, etc. this section focuses on the ia views and expectations around the endianness, address spaces and memory maps, and configuration for a basic ia platform. the ep80579 operates within this framework. these discussions highlight how and where the ep80579 differs from the framework. for a dditional detailed information on the ia infrastructure in the ep80579 specifically, see section 9.0, ?cmi introduction? , which discusses the imch implementation. 3.2.1 ia platform view of endianness all memory in an ep80579 platform is little-endian to match requirements and expectations of an ia platform. the byte lanes (see table 3-1 on page 112 ) are connected from the memory interface to the imch such that little-endian ia-32 core sees ?byte 0? of a quad-word in memory in byte lane a and ?byte 7? of a quad-word in memory in byte lane h. consider the following c code: char c, *cp; // 1 byte short s, *sp; // 2 bytes long l, *lp; // 4 bytes long long ll, *llp; // 8 bytes cp = sp = lp = llp = (void *) 0x8; // qw address 1 c = *cp; s = *sp; l = *lp; ll = *llp; executing this code on the ia-32 core in an ep80579 yields the following results: c == 8a s == 8b8a l == 8d8c8b8a ll == 8h8g8f8e8d8c8b8a where the right-hand values in these results use the notation that ta b l e 3 - 1 o n page 112 in section 3.1.2 describes to identify the byte lanes and address.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 114 order number: 320066-003us 3.2.2 ia platform view of configuration because the imch and iich blocks in the ep80579 come from an ia heritage, the ep80579 exposes much of the functionality in these blocks through a pci infrastructure. the ep80579 extends this pci infrastructure to expose the functionality in the aioc, as section 3.7, ?pci configuration? on page 119 describes. before describing how the aioc integrates with the ia-based imch and iich blocks, it is helpful to consider how the pci exposes imch and iich functionality. logically, the software-visible sub-blocks of the imch and iich materialize as pci devices and functions 1 on pci bus 0 of the system through three independent address spaces: ? configuration space: each function of each device has at least 256b of configuration space that is mapped to a fixed location by the platform (pci express* devices can provide for larger configuration spaces). this space provides system software with basic information on the device and allows for device- independent configuration. ? memory-mapped i/o (mmio) and i/o spaces: each function of each device can request up to six mmio and i/o regions of device-specified sizes to be mapped into physical address space through base address registers in the configuration header. system software selects the base address of each region. these spaces support device-specific operation such as access to device-specific control registers. of the thirty-two possible device slots on bus 0, five slots are reserved for software- visible blocks in the ep80579 imch and iich and remainder are unused. in general, the imch claims configuration accesses (i.e., those accesses that target configuration space) to device numbers 0, 1, 2, and 3 of bus 0 and routes configuration accesses to the remaining devices to the iich over an internal nsi interface using type 0 pci configuration transactions 2 (see section 13.2, ?platform configuration structure conceptual overview? and section 13.3, ?routing configuration accesses? . in the ep80579 design, transactions to bus 0 devices that are sent through nsi to the iich and unclaimed by the iich will master abort. figure 3-2 presents a logical view of the ep80579 infrastructure for the software-visible blocks in the iich and imch. 1. except where the distinction is important, this document uses the term ?device? to refer to both devices and functions in the pci sense of these words. 2. configuration transactions take the type 1 form while in transit through the pci fabric to their destination bus; upon reachi ng their destination bus, they become type 0 transactions.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 115 intel ? ep80579 integrated processor ta bl e 3 - 2 summarizes the address space requirements (both in memory and i/o space) of the imch and iich. figure 3-2. logical overview of the cmi pci infrastructure iich imch ia dev: 0 dev: 1 dev: 2,3 dev: 29 dev: 31 pci bus 0 nsi nsi usb sata, spi, lpc, smbus edma pci-ex imch, ddr table 3-2. basic cmi platform address space requirements for imch and iich devices unit pci block mem, i/o size register dev. fn. imch 0 0 northbridge mem 4kb smrbase (see section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? ) 1 dram, error handling n/a n/a 1 0 edma mem 4kb edmalbar (see section 16.3.1.9, ?offset 10h: edmalbar - edma low base address register? 20 pci-express (hsi a0) 8 or 4 n/a n/a 30 pci-express (hsi a1) 4 n/a n/a iich 29 0 usb 1.1 i/o 32b usbiobar (see section 25.1.1.9, ?usbiobar - base address register? ) 7 usb 2.0 mem 1kb mbar (see section 26.2.1.10, ?offset 10h: mbar - memory base address register? )
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 116 order number: 320066-003us the imch and iich devices in the ep80579 on pci bus 0 allocate 18kb of memory space above and beyond the pci l allocations in figure 3-2 and 72b of i/o space through pci bars (this memory could be allocated in the ?open? regions in figure 3-2 ). this table does not include any memory regions that external devices (i.e., those attached to a imch pci express* port) or aioc devices might allocate. in addition to the imch and iich devices, the ep80579 includes an ia-32 core that provides msrs and other configuration structures. 3.3 high-level views this section presents an overview of some of the general characteristics of the agents that the various ep80579 memory maps expose. 3.3.1 characteristics of external system memory (dram) the address spaces in the ep80579 expose up to 4gb of physical system memory, in the form of dram, to be accessed by both on- and off-die agents. 31 0 lpc/spi n/a n/a 2sata i/o 8b pcmdba (see section 23.1.1.8, ?offset 10h: pcmdba ? primary command block base address register? ) i/o 4b pctlba (see section 23.1.1.9, ?offset 14h: pctlba ? primary control block base address register? ) i/o 8b scmdba (see section 23.1.1.10, ?offset 18h: scmdba ? secondary command block base address register? ) i/o 4b sctlba i/o 16b lbar (see section 23.1.1.12, ?offset 20h: lbar ? legacy bus master base address register? ) mem 1kb abar (see section 23.1.1.13, ?offset 24h: abar ? ahci base address register? ) 3smbusn/an/a table 3-2. basic cmi platform address space requirements for imch and iich devices table 3-3. memory regions region managed by accesses to system memory by aioc agents coherent with ia caches? contents ia o/s ia o/s y ia o/s and application code and data structures ia/asu shared (coherent) ep80579 driver a a. the ep80579 driver includes the ep80579-specific software stacks that run on the ia, asu, etc. y ia and aioc shared data structures ia/asu shared (aioc-direct) ep80579 driver a n aioc data structures; ia-32 core may access a portion via the ep80579 driver
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 117 intel ? ep80579 integrated processor of the regions in ta b l e 3 - 3 , the ?ia/asu shared (coherent)? and ?ia/asu shared (aioc-direct)? regions are not managed by the ia o/s. the ep80579 software expects that the bios carves this memory out of the memory map early in the boot process and sets it aside for use by the intel ? ep80579 integrated processor with intel? quickassist technology software stack. as a result, the ia o/s does not allocate, manage, page, etc. these regions of memory. the regions in ta b l e 3 - 3 fall into one of two categories with respect to ia cache coherency: one that is coherent with ia caches for aioc accesses and one that is not. it is important to note that the coherent/non-coherent category of a region affects only how the aioc hardware handles a dram accesses. the category, in and of itself, does not have any implications on how ia must always access the region. the ep80579 expects that, in general, all agents in the system can access all memory, consistent with their addressing capabilities, in the three regions that ta bl e 3 - 3 lists. exceptions to this general rule may arise due to the size of the address space that an agent supports or due to agent-specific aliasing of dram addresses onto other structures. the following sections on the memory maps outline any agent-specific exceptions. finally, memory accesses that originate from the aioc (or a device attached to the aioc) must honor the coherency requirements in ta bl e 3 - 3 based on the region they target. for consistency, software is expected to configure the ep80579 such that memory that the ia-32 core cannot access is not part of regions that are expected to be coherent with ia caches. 3.3.2 characteristics of internal and external memories ta bl e 3 - 4 defines the supported operations by memory type. the table uses the following notation to indicate the behavior of the ep80579: ? ??? means the operation is not supported by the ep80579. ? ?s? implies that the operation happens as a single atomic 1 update to memory. in other words, either the update is observable in its entirety or not at all. ? ?m? implies that the operation may happen as multiple updates to memory. in other words, other agents can observe different parts of the affected memory location change values in any order but the end state of the memory location will be the desired value. this ?flickering lights? effect makes such memory accesses useless for multi-agent synchronization unless a semaphore or flag variable is used to guard access to the shared location 2 . this table only applies to aligned-to-size operations; that is, a 4-byte operation is aligned to a 4-byte boundary, an 8-byte operation is aligned to an 8-byte boundary, etc.) . 1. in the sense that it cannot be divided into multiple smaller writes. 2. note that in guarding the location, visibility of the new flag must imply that the ?flickering? has stopped.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 118 order number: 320066-003us . 3.3.3 characteristics of device configuration to be able to leverage existing ia bios, o/s, and power management software, the ep80579?s configuration mechanisms follow existing ia platform approaches. of the four major components of the ep80579: ? the ia-32 core can use normal ia platform configuration algorithms. ? the imch and iich can use normal ia platform configuration algorithms. ? to interoperate with normal ia platform configuration algorithms, the aioc must be configured by the ia processor. with the ep80579, the boot and configuration process is: 4. the ia boots from a flash device on the iich spi (lpc) interface. system software discovers and configures the devices on pci bus 0 in the imch/iich. 5. system software discovers and configures the devices behind the transparent pci- to-pci bridge into the aioc. this may amount to allocating memory regions specified by the bars 1 . 6. system software configures other buses on the system. once this process completes, the ep80579 is ready for operation. it may be necessary for software to re-order the devices on bus 0 in the imch/iich/ aioc to ensure that the aioc can obtain the resources it needs. since enumeration involves either a depth-first or a breadth-fi rst traversal of the device tree from device zero (depending on the implementation of the platform pci enumeration and discovery code), the system may not be able to honor a request for a large memory region from an aioc device if this device is enumerated late in the process due to a large device number. this issue is not unique to the ep80579 and is handled in whatever fashion standard ia platform software handles such resource issues. table 3-5. supported operations by memory type operation ia-32 core aioc agents type size bytes coherent (ia wb cacheable) aioc-direct a a. aioc-direct is a feature of the intel ? ep80579 integrated processor with intel? quickassist technology sku. coherent aioc-direct a read, write 1s s ? ? 2s s ? ? 4s s s m 8s s s s 16smmm 32 ? ? m m 64 s ? m m 128 ? ? m m atom read- modify-write (semaphore) 1s m ? ? 2s m ? ? 4s m s s 8s m ? ? 1. a 32-bit bar can request a single memory size that is a power of 2 from 16b to 2gb according to the pci specification.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 119 intel ? ep80579 integrated processor 3.4 memory map for ia-attached agents there are two constraints in the ep80579 cmi and memory controller designs: ? the ia-32 core only supports 32-bit physical addresses. ? the memory controller supports at most 4gb of physical memory. this discussion focuses on the perspective of an ia-attached agent; section 3.5, ?memory map for aioc-attached devices? on page 119 provides similar discussion for aioc-attached agents. 3.5 memory map for aioc-attached devices aioc-attached agents support several independent target ids that provide independent address spaces. ta b l e 3 - 7 summarizes, the addressing capabilities of aioc agents range from 25 to 32-bits. 3.6 endianness the ep80579 operates in an ia platform environment that is little-endian. 3.7 pci configuration this section presents an overview of the implementation that integrates the aioc and memory controller with the ia pci infrastructure for configuration. ? pci mechanisms (configuration spac e, memory-mapped i/o spaces, and i/o spaces) expose state for configuration. ? the ia-32 core performs all system configuration and initialization. table 3-6. device exposure from an ia-attached memory map perspective device to access materializes in region notes pcie gige macs imch/iich aioc devices pci l ? pci bar(s) set by ia o/s or bios specify address mapping(s). ? ia-32 core configures through i/o or pci enhanced config spaces. ? reads, config space access between i/o agents not supported. ? region is at least 128mb per definition of tolm, see section 16.1.1.30, ?offset c4h: tolm - top of low memory register? . dram dram ad ? contains ia/asu shared (aioc-direct) region from ta bl e 3 -3 . ? mencbase and menclimit registers define address range. ? ia caches not coherent with aioc accesses to this region. ? must include all dram that is inaccessible to the ia-32 core. dram c ? contains i/a o/s, ia/asu shared (coherent) regions from ta b l e 3 - 3 . ? ia caches coherent with aioc accesses to this region. ? cannot include any dram that is inaccessible to the ia-32 core. table 3-7. address space sizes of aioc-attached devices address space size [b] devices 32 gigabit ethernet macs 32 asu, ssu, tdm, ssp, can, 1588
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 120 order number: 320066-003us ? the ia-32 core configures the aioc, imch and iich using standard ia platform algorithms (i.e., pci-based discovery, enumeration, and configuration) with modifications for the specific mix of functionality that the ep80579 cpu, imch, and iich instantiations provide. ? ia software configures external pcie devices in the ep80579 using normal pci discovery and configuration algorithms. the device and bus numbers for external devices are assigned by the bios and/or o/s during boot-time enumeration as normal. ? an ep80579-specific user driver handles interaction with external non-pci agents attached to the ep80579 through its aioc-side i/o interfaces. that is, the ep80579 user driver, not bios, will ?discover? and operate any devices attached to the local expansion bus, for example. note that since these devices do not implement pci semantics, it is expected that they will not allocate mmio regions beyond those already allocated for the pci view of the appropriate aioc device. ? the o/s always allocates an aperture in the memory map for any pci device that defines one or more bars, even if the device is unknown to the o/s at discovery. the pci abstraction that the aioc provides for its devices is primarily a software abstraction for the purposes of configuration; the aioc itself does not contain pci devices. 3.7.1 overview the ep80579 integrates the aioc and memory controller into the pci fabric as figure 3-3 describes. this figure presents a logical view of the system. figure 3-3. attaching the aioc to the cmi pci fabric (logical perspective) aioc complex iich imch ia fsb nsi devices pci bus 0 pci bus 0 devices asu/ssu dram (ad) memory controller (in imch) bridge leb, can, ssp, 1588 gige dram (c) pci bus m
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 121 intel ? ep80579 integrated processor in this figure, pci bus 0 originates in the imch and reaches internal imch pci devices through internal paths. bus 0 is bridged into the iich via an nsi interconnect and into the aioc. the memory controller materializes internally to the imch as device 0 of pci bus 0. the internal transparent bridge materializes the devices for the aioc through a bridged hierarchy as figure 3-4 illustrates. in this hierarchy, a transparent pci-to-pci bridge appear on pci bus 0 with the remaining aioc devices materializing behind the bridge on pci bus m 1 . 3.7.2 device tree this section describes how the devices on the ep80579 die map onto the pci device tree. in general, the ep80579 exposes the structures and sub-blocks that section 3.7.1 describes through pci devices that materialize behind a transparent bridge on bus 0. figure 3-4 presents an overview of the device tree for on-die ep80579 software-visible sub-blocks (see also figure 13-1, ?bus 0 device map? on page 348 ). as mentioned earlier, aioc devices materialize on bus ?m? behind a bridge on pci bus 0 where the ia bios or o/s assign the secondary bus number ?m? at discovery. devices can request space in the system memory and i/o address maps through bars in the configuration header. in general, the ep80579 materializes most device control and status registers in memory-mapped regions allocated by a bar. the only exception 1. the ia bios and/or o/s assigns the specific bus number during pci discovery and enumeration. figure 3-4. overview of pci infrastructure for on-die devices aioc iich imch dev: 0 dev: 1 dev: 2, 3 dev: 29 dev: 31 dev: 7 dev: 8 dev: 0,1,2 dev: 3 dev: 4, 5 dev: 6 pci bus m 1588 leb gbe mac 0/1/ 2 mdio can 0/1 ssp usb sata, spi, lpc, smbus edma pci-e pci bus 0 nsi nsi imch ddr (m) transparent pci-to-pci bridge pci bus 0 dev: 12 asu dev: 9 dev: 10 reserved tdm reserved dev: 11
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 122 order number: 320066-003us lies in the standard pci configuration, status, and capability registers that pci requires which materialize only in pci configuration space. the aioc devices that lie behind the bridge allocate by either the bios or os to their regions of address and i/o space within a contiguous region of address space that the bridge claims. it is assumed that system software configures the aperture for the bridge to be large enough to cover all of the address space that the devices behind the bridge request. the remainder of this section summarizes the device tree that the ep80579 implements. this summary includes a mapping between pci devices and the ep80579 blocks along with the value of the device id, class code, and a summary of the resources (i.e., registers, memory, etc.) that each device requests. ta b l e 3 - 9 summarizes the pci devices that the imch and iich materialize. table 3-9. imch and iich pci device summary device name ep80579 units pci sku id number resources a a. ?mbar? is a memory space bar, ?iobar? is an i/o space bar, ?pm? is a power management capability, and ?msi? is an msi capability. b/d/f b b. pci bus number, device number, and function number. bsp c c. pci base class code, subclass code, and programming interface pci configuration register values. device id memory controller hub imch 0 / 0 / 0 060000h 5020h 1,2,3,4,5,6, 7,8 mbar (4kb and 4kb) error reporting imch 0 / 0 / 1 ff0000h 5021h 1,2,3,4,5,6, 7,8 edma edma 0 / 1 / 0 088000h 5023h 1,2,3,4,5,6, 7,8 msi, mbar (4kb) pci-ex port 0 pea0 0 / 2 / 0 060400h 5024h 1,2,3,4,5,6, 7,8 pm, msi pci-ex port 1 pea1 0 / 3 / 0 060400h 5025h 1,2,3,4,5,6, 7,8 pm, msi pci-to-pci bridge imch 0 / 4 / 0 060400h 5037h 1,2,3,4,5,6, 7,8 usb 1.1 controller usb1.1 0 / 29 / 0 0c0300h 5033h 1,2,3,4,5,6, 7,8 iobar (32b) usb 2.0 controller usb2.0 0 / 29 / 7 0c0320h 5035h 1,2,3,4,5,6, 7,8 pm, mbar (1kb) lpc/spi lpc/spi 0 / 31 / 0 060100h 5031h 1,2,3,4,5,6, 7,8 iobar (128b, 64b) sata sata 0 / 31 / 2 01018ah, 010601h, 010401h, 010401h d d. sata sc and pi values depends on the sata mode and map value settings. 5028h, 5029h, 502ah, 502bh e e. sata did value depends on the sata mode settings. 1,2,3,4,5,6, 7,8 pm, msi, iobar (8b, 8b, 4b, 4b, 16b), mbar (1kb) smbus smbus 0 / 31 / 3 0c0500h 5032h 1,2,3,4,5,6, 7,8 iobar (32b)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 123 intel ? ep80579 integrated processor a summary of the registers, memory-mapped, and i/o-mapped resources that ta bl e 3 - 9 and ta b l e 3 - 1 0 identify can be found in section 7.0, ?register summary? . detailed descriptions of these resources can be found in the chapters that cover the relevant block. table 3-10. aioc pci device summary device name ep80579 units pci sku id number resources a a. ?mbar? is a memory space bar, ?iobar? is an i/o space bar, ?pm? is a power management capability, ?msi? is an msi capability, and ?st? is an ep80579 signal target capability. b/d/f b b. pci bus number, device number, and function number. bsp c c. pci base class code, subclass code, and programming interface pci configuration register values. device id gige mac 0 gbe 0 m / 0 / 0 020000h 5040h 2,4,6,8 pm, msi, st, mbar (128kb), iobar (32b) 5041h 1,3,7,5 5042h reserved d d. these device ids are reserved for future skus. 5043h reserved d gige mac 1 gbe 1 m / 1 / 0 020000h 5044h 2,4,6,8 pm, msi, st, mbar (128kb), iobar (32b) 5045h 1,3,7,5 5046h reserved d 5047h reserved d gige mac 2 gbe 2 m / 2 / 0 020000h 5048h 2,4,6,8 pm, msi, st, mbar (128kb), iobar (32b) 5049h 1,3,7,5 504ah reserved d 504bh reserved d mdio mdio m / 3 / 0 ff0000h 503eh 1,2,3,4,5,6,7 ,8 pm, mbar (4kb) can interface 0 can 0 m / 4 / 0 0c0900h 5039h 1,2,3,4,5,6,7 ,8 pm, msi, st, mbar (4kb) can interface 1 can 1 m / 5 / 0 0c0900h 503ah 1,2,3,4,5,6,7 ,8 pm, msi, st, mbar (4kb) ssp ssp m / 6 / 0 078000h 503bh 1,2,3,4,5,6,7 ,8 pm, msi, st, mbar (4kb) ieee 1588 1588 m / 7 / 0 111000h 503ch 1,2,3,4,5,6,7 ,8 pm, msi, st, mbar (4kb) local expansion bus le bus m / 8 / 0 068000h 503dh 1,2,3,4,5,6,7 ,8 pm, msi, st, mbar (4kb and 0-256mb e ) e. the size of the region that the 0-256mb mbar requests is a multiple of 32mb between 0mb and 256mb (inclusive) based on reset-time platform configuration. asu asu m / 9 / 0 0b4000h 502ch 2,4,6,8 pm, msi, st, mbar (8kb, 16kb, 16kb, and 4kb) 502dh 1,3,7,5 502eh reserved d 502fh reserved d reserved reserved m / 10 / 0 088000h 503fh 1,2,3,4,5,6,7 ,8 reserved tdm tdm m / 11 / 0 0b4000h 504ch 1,3,5,7 pm, msi, st, mbar (4kb and 4kb) reserved reserved m / 12 / 0 110100h 5030h 1,2,3,4,5,6,7 ,8 reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 124 order number: 320066-003us 3.7.3 materializing device structures the ep80579 exposes aioc resources through standard pci abstractions: configuration spaces, memory-mapped i/o spaces, and i/o spaces. access to mmio and i/o spaces are accessed through memory and i/o read/write instructions, respectively. the addressing of these spaces for a given device depends on the specific mapping that the pci configuration header establishes through bars. pci defines two mechanisms for accessing the 256b of each device/function configuration registers located in pci configuration space. ? pci mechanism: the header is accessed using 1-, 2-, or 4-byte in and out instructions that access the pci configuration address and data i/o ports at addresses 0cf8h - 0cfbh and 0cfch - 0cffh , respectively, in the ia i/o space. this mechanism allows access only to the 256b pci-compatible configuration space ? pci express* enhanced mechanism: the header is accessed using 1-, 2-, or 4-byte memory accesses to the 256mb region starting at hecbase ( 0_e000_0000 p by default. this mechanism allows access to an expanded 4kb configuration space that pci express* defines (the first 256b are, by definition, the pci-compatible configuration space). these mechanisms differ in the address space they use to access the header. the pci mechanism travels through ia i/o space while the pci express* enhanced mechanism travels through ia memory space. the address format that the mechanisms use is identical to the standard ia platform format that encodes the pci bus, device, and function numbers along with a register offset or number (see section 13.6.0.1, ?offset 0cf8h: config_address - configuration address register? and section 13.8.4, ?enhanced configuration fsb address format? for details). for either access method, the hardware in the aioc that implements the configuration headers must be able to process accesses of the appropriate sizes. 3.7.4 pci configuration headers the pci specification requires each pci device to provide a 256b configuration space. the first 64b of this space contains a standard pci configuration header and the remaining 192b contains any device-specific registers, capabilities records, etc. needed by the function. there are two flavors of configuration headers: ? all non-bridge devices provide a pci type 0 configuration headers. this form of header is used to represent devices on the pci fabric. ? all bridge devices provide a pci type 1 configuration header. this form of header is used to represent bridge devices in the pci fabric. because the aioc devices are not pci devices, they do not fully support all pci configuration header fields 1 . the following tables describe the support in greater detail. ta b l e 3 - 1 1 summarizes the fields in a pci type 0 header (i.e., header for non-bridge devices) and identifies which fields the ep80579 implements for aioc devices. the ep80579 hardware implements the appropriate pci semantics for all supported registers and fields in this table. 1. configuration headers for imch and iich devices follow pci expectations as these devices are pci compliant.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 125 intel ? ep80579 integrated processor table 3-11. pci configuration header support for type 0 headers in aioc devices (sheet 1 of 2) offset register and field bit(s) supt. a acc. b notes 00h - 01h vendor id 15:0 y ro required by pci. 02h - 03h device id 15:0 y ro required by pci. 04h - 05h command register interrupt disable 10 y rw supported in devices that can use intx c . n ro not supported in devices that do not use intx d . fast back-to-back enable 9 n ro not supported. serr# enable 8 n ro not supported. intx/msi signal aioc errors. parity error response 6 n ro not supported. intx/msi signal aioc errors. vga palette snoop 5 n ro not supported. mem. write & inval. enable 4 n ro not supported. special cycles 3 n ro not supported. bus master enable 2 nrw asu, gbe, tdm, leb devices: not supported e , bit is implemented as rw but has no effect yro all devices except asu, gbe, tdm, leb: these devices cannot be bus masters. memory space enable 1 yrw all devices except 1588; these devices each materialize in memory space. nro for ieee1588; ieee1588 does not materialize in memory space. i/o space enable 0 y rw for gbe; gbe materializes in i/o space. nro all devices except gbe; these devices do not materialize in i/o space. 06h - 07h status register detected parity error 15 n ro not supported; intx/msi signal errors. signalled system error 14 n ro not supported. intx/msi signal aioc errors. received master- abort 13 n ro not supported e . received target- abort 12 n ro not supported e . signalled target- abort 11 n ro not supported; aioc devices do not target- abort. devsel timing 10:9 n ro not supported. master data parity error 8 n ro not supported. intx/msi signal aioc errors. fast back-to-back capable 7 n ro not supported. 66mhz capable 5 n ro not supported. capabilities list 4 y ro setup based on capabilities exposure by device. interrupt status 3 y ro supported in devices that can use intx c . n ro not supported in devices that do not use intx d . 08h revision id 7:0 y ro required by pci. 09h - 0bh class code 23:0 y ro required by pci.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 126 order number: 320066-003us ta b l e 3 - 1 2 summarizes the fields in a pci type 1 header (i.e., header for bridge devices) and identifies which fields the ep80579 implements. the ep80579 hardware implements the appropriate pci semantics for all supported registers and fields in this table. 0ch cache line size 7:0 n ro not supported. 0dh latency timer 7:0 n ro not supported. 0eh header type 7:0 y ro required by pci. 0fh bist 7:0 n ro not supported. 10h - 27h base address (x6) 6 x 31:0 yrw devices that materialize in i/o or memory spaces will populate these slots as necessary based on address space needs. 28h - 2bh cis pointer 31:0 n ro not supported. 2ch - 2dh subsystem vid 15:0 y ro required by pci. 2eh - 2fh subsystem id 15:0 y ro required by pci. 34h capability pointer 7:0 y ro setup based on capabilities exposure by device. 3ch interrupt line 7:0 y rw supported in devices that can use intx c . n ro not supported in devices that do not use intx d . 3dh interrupt pin 7:0 y ro supported in devices that can use intx c . n ro not supported in devices that do not use intx d . 3eh min_gnt 7:0 n ro not supported. 3fh max_lat 7:0 n ro not supported. a. supported fields provide appropriate pci semantics. unsupported fields always return zero on reads unless otherwise noted. b. ro and rw access types indicate that the register or field supports read-only access and read/write access, respectively. c. aioc devices that may signal via intx include gbe, can, ssp, and ieee1588. d. aioc devices that cannot signal via intx include leb. e. this behavior is a deviation from the pci specification for only the gbe and a device that can be a bus master. table 3-11. pci configuration header support for type 0 headers in aioc devices (sheet 2 of 2) offset register and field bit(s) supt. a acc. b notes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 127 intel ? ep80579 integrated processor table 3-12. pci configuration header support for type 1 headers in aioc devices (sheet 1 of 3) offset register and field bit(s) supt. a acc. b notes 00h - 01h vendor id 15:0 y ro required by pci. 02h - 03h device id 15:0 y ro required by pci. 04h - 05h command register interrupt disable 10 n rw bridge-generated interrupts not supported. fast back-to-back enable 9 n ro not supported. serr# enable 8 n rw bridge delivers events that would be master aborts (primarily address decode) as serr#. parity error response 6 n rw not supported. intx/msi signal aioc errors. vga palette snoop 5 n ro not supported. mem. write & inval. enable 4 n ro not supported. special cycles 3 n ro not supported. bus master enable 2 n rw not supported c . memory space enable 1nrw bridge itself does not expose any non-standard registers via memory space. i/o space enable 0 n rw bridge itself does not expose any non-standard registers via i/o space. 06h - 07h status register detected parity error 15 n ro not supported. intx/msi signal aioc errors. signalled system error 14 n ro not supported. intx/msi signal aioc errors. received master- abort 13 n ro not supported c . received target- abort 12 n ro not supported c . signalled target- abort 11 n ro not supported; aioc devices do not target- abort. devsel timing 10:9 n ro not supported. master data parity error 8 n ro not supported. intx/msi signal aioc errors. fast back-to-back capable 7 n ro not supported. 66mhz capable 5 n ro not supported. capabilities list 4 y ro setup based on capabilities exposure by bridge. interrupt status 3 n ro bridge-generated interrupts not supported. 08h revision id 7:0 y ro required by pci. 09 - 0bh class code 23:0 y ro required by pci. 0ch cache line size 7:0 n ro not supported. 0dh latency timer 7:0 n ro not supported. 0eh header type 7:0 y ro required by pci. 0fh bist 7:0 n ro not supported. 10h - 17h base address (x2) 2 x 31:0 nro not supported. bridge does not expose non- standard registers via bar. 18h primary bus number 7:0 y rw required by pci.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 128 order number: 320066-003us 19h secondary bus number 7:0 y rw required by pci. 1ah subordinate bus number 7:0 y rw required by pci. 1bh secondary latency timer 7:0 y ro not supported. 1ch i/o base 7:0 y rw supported, aioc devices materialize in i/o space. 1dh i/o limit 7:0 y rw supported, aioc devices materialize in i/o space. 1eh - 1fh secondary status register detected parity error 15 n ro not supported. intx/msi signal aioc errors. received system error 14 n ro not supported. intx/msi signal aioc errors received master- abort 13 n ro not supported c . received target- abort 12 n ro not supported c . signalled target- abort 11 n ro secondary-side devices cannot target-abort. devsel timing 10:9 n ro not supported. master data parity error 8 n ro not supported. intx/msi signal aioc errors. fast back-to-back capable 7 n ro not supported. 66mhz capable 5 n ro not supported. 20h - 21h memory base 15:0 y rw supported, aioc devices materialize in memory space. 22h - 23h memory limit 15:0 y rw supported, aioc devices materialize in memory space. 24h - 25h prefetch memory base 15:0 n rw d prefetchable memory devices not supported. 26h - 27h prefetch memory limit 15:0 n rw d prefetchable memory devices not supported. 28h - 2bh prefetch base (upper 32b) 31:0 n rw d prefetchable memory devices not supported. 2ch - 2fh prefetch limit (upper 32b) 31: 0 n rw d prefetchable memory devices not supported. 30h - 31h i/o base (upper 16b) 15:0 n ro i/o spaces larger than 64kb not supported. 32h - 33h i/o limit (upper 16b) 15:0 n ro i/o spaces larger than 64kb not supported. 34h capability pointer 7:0 y ro setup based on capabilities exposure by bridge. 38h - 3bh expansion rom base 31:0 n ro not supported. 3ch interrupt line 7:0 n ro bridge-generated interrupts not supported. 3dh interrupt pin 7:0 n ro bridge-generated interrupts not supported. table 3-12. pci configuration header support for type 1 headers in aioc devices (sheet 2 of 3) offset register and field bit(s) supt. a acc. b notes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 129 intel ? ep80579 integrated processor for additional details on the headers for aioc devices, see section 35.3.1, ?description of pci configuration header space? . the specific portion of the 256b pci configuration space that is active in a device depends on the needs of the specific device. in general, a device requires far less than 256b of storage to implement a typical configuration space. regions of the 256b configuration space that are not required are reserved and need only support default behavior compliant with the pci specification: all pci devices must treat configuration space write operations to reserved registers as no-ops; that is, the access must be completed normally on the bus and the data discarded. read accesses to reserved or unimplemented registers must be completed normally and a data value of 0 returned. 3eh - 3fh bridge control register discard timer serr# enable 11 n ro not supported. discard timer status 10 n ro not supported. secondary discard timeout 9 n ro not supported. primary discard timeout 8 n ro not supported. fast back-to-back enable 7 n ro not supported. secondary bus reset 6 n rw not supported. master abort mode 5 y ro bridge delivers events that would be master aborts (primarily address decode) as serr#. vga enable 3 n rw not supported. isa enable 2 n rw not supported. serr# enable 1 n rw not supported. parity error response 0 n rw not supported. a. supported fields provide appropriate pci semantics. unsupported fields always return zero on reads unless otherwise noted and need not provide pci semantics. b. ro and rw access types indicate that the register or field supports read-only access and read/write access, respectively. c. this is a known deviation from the pci specification since the bridge can be a bus master. d. this is a deviation from the pci specification since this register should be ro on bridges that do not support prefetchable regions. the registers are rw for compatibility with the base ip. software is expected to set these fields to indicate an empty region since no secondary- side devices (i.e., bus m) request prefethcable memory. table 3-12. pci configuration header support for type 1 headers in aioc devices (sheet 3 of 3) offset register and field bit(s) supt. a acc. b notes
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 130 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 131 intel ? ep80579 integrated processor 4.0 signaling 4.1 overview this chapter presents an overview of the inter-agent signaling mechanisms supported along with the implications on transaction ordering necessary to support producer/ consumer software algorithms. this chapter concentrates primarily signaling for functional, not error, purposes while section 5.0, ?error handling? provides additional discussion on error signaling. the ep80579 signaling model operates in a system-on-a-chip environment and must blend the signaling architectures of many disparate components into a unified whole. ? allow signaling between ia agents (i.e., the ia-32 core, imch, iich, and external pci-express-attached devices) and aioc agents. ? support producer/consumer relationships between agents in the ia or aioc. ? provide compatibility with existing ia signaling mechanisms for internal imch/iich agents and external devices. ? provide compatibility with ia platform signaling semantics and abstractions. there are two tightly related parts to the signaling model: ?the signaling mechanism determines how takes a signal from a source agent, performs any necessary translation, and delivers it to a target agent in a form the target can understand. ?the ordering mechanism determines how orders a given signal from a source agent with respect to the data stream that the source agent produces to meet ordering requirements. figure 4-1. logical overview of signaling architecture aioc ia complex (cpu, imch, iich) signal bridging pci ex pci device(s) internal pci agents ep80579
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 132 order number: 320066-003us the ia complex attaches to the aioc through a transparent pci-to-pci bridge. within the aioc, the ?signal bridge? block in figure 4-1 represents the hardware in the aioc, that converts signaling between the aioc an d ia domains and presents the appropriate abstractions to agents on either side of the bridge. 4.1.1 terminology and conventions throughout this section, we use the following terminology: ? global visibility: an operation is said to be globally visible when all side-effects of the operation are visible to every observer in the system. for example, a write to some resource (e.g., memory location, control register, etc.) r achieves global visibility when a read of r by all other agents is guaranteed to return the new value. ? ordering: ordering refers to the order in which signals and/or memory accesses to different locations must reach global visibility to ensure some behavior. note that this excludes the ?ordering? necessary to prevent data hazards which are accesses to the same location. ? signal: a message sent between agents to indicate some condition of interest. a signal may be an interrupt, a memory write, etc. this section uses the term when the specific transport medium is not important. 4.2 existing signaling capabilities there are several agents in the ep80579 that can be both the source and the target of a ?signal?: the ia-32 core and accelerators in the aioc. in addition, there are several other agents in the ep80579 that can be the source of a signal: devices in the imch or iich, the error reporting hardware, the gigabit ethernet mac, the ssp interface, the can interfaces, the ieee 1588 interface, externally-attached pci-express devices, and externally-attached local expansion bus devices (via gpio or intx interrupts). this section summarizes the existing signaling capabilities of each of these agents. when discussing signaling, this section classifies all signals into one of two general categories: ? ordered signals must maintain a particular relationship with the data stream. for example, a mac signals a cpu with an ordered signal after the mac finishes writing inbound packet data to memory. ? unordered signals need not maintain a particular relationship with the data stream. for example, memory interface hardware signals a cpu with an unordered signal when the interface encounters an uncorrectable memory error. signals of either type may participate in producer/consumer operations between agents; however, the operation can use only ordered signals if the producer/consumer operation involves the data stream 1 . finally, note that this classification refers specifically to the data stream; signals may also be ordered with respect to other events (e.g., data being available in a local device buffer). 1. for producer/consumer operation to work correctly, software and hardware must be able to establish ordering relationships between various events in the operation. such a relationship cannot be established between the data stream and a signal that is unordered with respect to the data stream.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 133 intel ? ep80579 integrated processor 4.2.1 ia-32 core/platform the ia-32 core supports two inbound signaling mechanisms that the ep80579 can use to accept signals from other agents: a legacy interrupt (intx) and a message-signaled interrupt (msi). the intx mechanism encodes an interrupt on one of four out-of-band interrupt signals that drive interrupt controllers in the ia platform. the msi mechanism encodes an interrupt as an in-band 32-bit write to a memory-mapped location. when the platform observes a write to an msi location, it generates an interrupt to the cpu. the operating system or system software specifies, in large part, the data value that travels with an msi; the device has limited ability to change or modify this value in the pci msi model. the ia platform also supports signaling for errors through events that the platform eventually maps onto interrupts, such as serr or smi. section 5.0, ?error handling? discusses these mechanisms in further detail. these mechanisms are not used in functional inter-agent signaling. 4.2.1.1 msi and intx signaling the ep80579 supports both msi and intx mechanisms to interoperate with ia platform system software since not all operating systems or devices support msis. the pci configuration header of each device indicates the capabilities of the device (i.e., if it can generate an msi, which pin it uses in intx mode, etc.) and also allows system software to specify the signaling mechanism the device should use when the device is capable of both msi and intx signaling. further, when signaling the ia platform, software must tolerate ?warts? of the ia signaling model such as spurious interrupts, etc. for outbound signaling from the ia-32 core to other agents, the ep80579 relies on memory writes to mmio locations to transport signals or ia can issue an mmio read to a device csr. 4.2.1.2 gpio signaling the ep80579 provides the ability to configure a subset of its gpio pins as interrupts. gpio pins 16-21, 23-25, 27, 28, 30, 31, 33, 34, and 40 can function in either an interrupt mode or as a gpio. each of these gpio pins can be connected to a single input on the apic when software configures the gpio as an interrupt. these pins are then available to external devices, such as a device attached to the local expansion bus, for use as signals. the ep80579 handles signals arriving through a gpio interrupt are handled like all other interrupts connected to the apic. for additional information, see the gpio material in section 22.0, ?general purpose i/o: bus 0, device 31, function 0? . 4.2.2 other agents the remaining agents that are relevant to the ep80579 signaling model can only signal in the outbound direction; that is, they only generate signals from the agent into ep80579. these agents operate as follows: ? imch, iich, and externally-attached pci devices generate ia platform intx or msi signals based on pci device and platform configuration. pci mechanisms such as serr can also support error reporting (see section 5.0, ?error handling? ). ? gigabit ethernet mac generates a side-band interrupt signal. ? can, ssp, and ieee 1588 interfaces generate side-band interrupt signals. ? externally-attached local expansion bus devices generate side-band interrupt signals. these signals are not carried on the local expansion bus itself but rather are presented to the ia-32 core through gpio pins that the system configures to generate signals.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 134 order number: 320066-003us 4.3 inter-agent signaling signals may originate from a number of sources within the system but may only target one of the on-die agents in the ep80579: the ia-32 core or aioc accelerator. this section considers inter-agent signaling mechanisms available in the ep80579. this material looks at signaling in isolation. because the ep80579 integrates devices from several different fabrics, signaling between different agents may require bridge functionality to convert signals between the various existing capabilities that section 4.2, ?existing signaling capabilities? on page 132 describes. figure 4-2 presents a logical view of the flow of signals through the ep80579. . in this model, a signal originates from a source agent as an in- or side-band signal. depending on the specific situation, the signal may either reach the destination directly or through a signal bridge. the signal bridge in ep80579 does not provide any mechanism to ensure that a destination agent responds to a given inbound signal. as a result, software must be able to keep up with the signaling rates if catching and processing every signal is a requirement. if software is unable to keep up with the signaling rate, one or more signals can be dropped. ta b l e 4 - 1 summarizes the cross product of the combinations of producer and consumer agents that ep80579 supports for signaling between agents. this table identifies the types of signaling allowed as well as any bridging that the ep80579 hardware must provide to support signaling between the indicated agents. table 4-1. supported inter-agent signaling figure 4-2. logical view of signaling flow signal bridge destination agent in- or side-band signal from source agent signal for destination agent in destination format source agent signal bridging on-die signal consumer ia-32 core signal producer ia-32 core not supported a a. support not required since there is only one such agent in an ep80579. imch, iich devices pci msi / intx via pci gige mac side band: pci msi / intx ssp side band: pci msi / intx can side band: pci msi / intx 1588 side band: pci msi / intx errors b b. this includes signaling for errors in the memory controller, local expansion bus, etc. side band: pci msi / intx external pci express* device pci msi / intx via pci external local expansion bus device msi / intx via gpio
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 135 intel ? ep80579 integrated processor in this table, ?:? and ?via? indicates bridged and direct paths for the signaling (see figure 4-2 ), respectively. all ep80579 hardware that inter-operates with ia platform structures for signaling, such as the signal bridge, operate in ia physical address space. this allows it to access ia platform devices, such as the lapic that are accessed via mmio reads and writes in the pci l memory region. the next two sections cover the various signaling scenarios that are represented in the cells of ta bl e 4 - 1 : signaling that travels around the bridge and that is bridged from a side band signal. 4.3.1 signaling that travels around the signal bridge for signaling that does not need to travel through the signal bridge, the ep80579 does not require any specific signaling support. in these cases, the signaling occurs over an existing path. for example, an interrupt from a iich usb controller would travel over the existing iich intx or msi path based on device configuration. 4.3.2 signaling that is bridged from a side-band source signal the majority of signaling scenarios in ta bl e 4 - 1 that require bridging are conversions between side band signals and a signal that targets the ia-32 core. the ep80579 uses a centralized agent, the signal bridge to perform this conversion. one or more side- band signals arrive at the signal bridge from each aioc device that is capable of signaling. the bridge is responsible for generating the appropriate outbound signal to either an asu device or the ia-32 core. figure 4-3 presents an overview of the signal bridge hardware for a subset of the ep80579 aioc devices. figure 4-3. signal bridging logically, the signal bridge consists of the msi and signal target capability records from the pci configuration headers for the aioc devices. the msi capability record for a device includes a message address register (mar in figure 4-3 ) and message data register (mdr in figure 4-3 ) that indicate the address and data for the msi as per the pci definition of this capability. the signal target capability record for a device includes a mask that determines how the bridge steers the signal, data which identifies additional signaling data, and a status that indicates which side-band signal(s) has been asserted 1 . the signal target capability is a vendor-specific capability record whose format the ep80579 defines. in the example show in figure 4-3 , side band signals arrive from gigabit ethernet mac and other aioc agents. these agents correspond to aioc pci devices. here, the gbe agent generates a signal that the signal bridge delivers as an msi to ia based on the 1. the status is not shown in figure 4-3 . msi [c], f (z) ia int signal bridge 0 9 11 intb mar ?, mdr ? mar c, mdr z asu mar a, mdr x msi 10 mask m 11 , data ? mask m 9 , data s mask m 0 , data ? mask m 10 , data ? signal target aioc aioc aioc gbe 0 n n n n
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 136 order number: 320066-003us configuration in the msi and signal target capability records in the pci configuration header. these records allow the signal bridge to determine how to handle an inbound signal from a device. all side band signals from a given source are collected at the signal bridge. for example, a source may provide interrupt lines and error condition lines that cause the ep80579 to send a signal when any one is asserted. sets of side band signals are then associated with each aioc pci device that can signal. when a given side band signal asserts, the signal bridge looks up the msi and signal target capability records in the pci configuration header that corresponds to the device. these resources tell the signal bridge how and where to deliver the outbound signal: ? if the masks in the signal target capability record indicate the signal should be delivered to the ia-32 core, the signal bridge sends an msi or intx signal to the ia- 32 core. ? if the pci configuration header selects msi messaging, the signal bridge generates an msi transaction from the device that generates the signal to the ia-32 core in accordance with the msi capability record. ? if the pci configuration header selects intx messaging, the signal bridge generates an intx transaction to the ia-32 core. the status register in the signal target capability provides the state of the side-band signals associated with a given aioc pci device to help software disambiguate the source of the signal. 4.3.2.1 targeting the ia-32 core with a bridged signal to remain compatible with existing ia software stacks, ep80579 hardware supports the pci msi and legacy intx signaling mechanisms into the cmi in response to signals targeting the ia-32 core. ? msi enable field selects the signaling mechanism an msi-capable device uses: ?intx legacy mode. ?msi mode. ? msi capability record specifies how ia system software wants msi-capable devices to signal the ia-32 core through a message address and message data register. ? interrupt pin and line registers specify the interrupt pin and line that the hardware uses for legacy intx mode. ? interrupt disable bit in the command register specifies whether or not the device generates any signals. based on the pci abstraction, these are per-device fields that are logically associated with a given device and that all devices that can signal the ia-32 core must implement. software is free to mix signal delivery mechanisms at the device level. for example, it may configure the ep80579 such that the gigabit ethernet macs signal through msis while the remaining aioc devices signal through intx. when device x signals the ia-32 core, it consults the pci configuration header for device x to determine how to deliver the signal to ia (i.e., via msi or intx). for signaling via msi, the header identifies the address and data value in the msi transaction. hardware builds the 32-bit data value for the msi transaction from the contents of the pci msi message data register, mdr , according to the pci semantics. specifically, the data value sent in the msi to ia is: ? bits 31:16 are zero. ? bits 15:0 are mdr , the value of the pci msi data register in the pci configuration header of the source device 1 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 137 intel ? ep80579 integrated processor the address is given directly by the pci msi message address register, mar . finally, the source of the msi transaction is set to the bus/device/function number of the device that generates the signal. for signaling via intx, the header identifies the interrupt line and pin that the ep80579 should use. in this case, hardware generates the appropriate transactions for intx upstream into the cmi. since the intx mechanism cannot transport any information beyond the fact that a signal occurred, the ep80579 needs to expose enough device state to the software stack, via device-specific control register(s), to allow software to be able to determine both the source and cause of the interrupt. such state would be in addition to the generic interrupt state that each pci device provides through its pci configuration header as per the pci specification to integrate with the existing imch/iich, the signal bridge in the ep80579 will generate four intx signals that it tracks based on the interrupt state of the blocks from the aioc that can generate signals. these four intx signals are provided to interrupt hardware in the ia platform hardware where they are ored with similar signals from other agents and converted into the appropriate signaling to the ia-32 core. this hardware will also provide a signal back to the imch that indicates when the local intx state can be deasserted. in addition to generating any transaction(s) necessary to send the signal to the ia, the aioc must preserve the semantics of pci interrupts and signals with respect to the state in the pci configuration headers for the aioc devices. ? signaling to the ia-32 core by a device should operate in accordance with the msi mode and configuration in the msi capability record. ? signaling to the ia-32 core by a device must be disabled when the interrupt disable bit in the pci command register is set ? the interrupt status bit in the pci status register should reflect the status of an intx signal. this preserves the pci abstraction for aioc devices. 1. this assumes that the device requests exactly on e message in the pci msi capability record [pci_3].
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 138 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 139 intel ? ep80579 integrated processor 5.0 error handling 5.1 overview this section presents an overview of the error handling mechanisms that the ep80579 provides. the intent of this discussion is to provide a broad background to error handling on the chip. register definitions and other error handling details can be found in the discussions of the relevant units throughout this document. 5.2 ep80579 view of error reporting this section describes the guiding principles on which the error logging and reporting registers are based for the ep80579. for the purposes of this discussion, an ?error? is an exceptional condition that is beyond the control of the ep80579 hardware or software and might result in data corruption or data loss. this definition does not cover ?functional? errors that are not beyond the control of the ep80579. for example, this section discusses double-bit ecc errors as they involves data corruption that occurs through no overt action of the ep80579; it does not cover an underflow error on a ring since this is a functional condition that can be managed in software to avoid data loss. 5.2.1 hardware capabilities with respect to their error handling capabilities, the blocks on the ep80579 can be divided into three groups: the ia blocks (including the ia-32 core, imch exclusive of the memory interface, iich), the memory controller interface, and the aioc blocks. generally speaking, ? the ia blocks (see section 5.3, ?error reporting by the imch? on page 141 and section 5.4, ?error reporting by the iich? on page 149 ) use the ferr/nerr and pci error reporting infrastructures. ? the memory controller block (see section 5.5, ?error reporting by the system memory controller? on page 153 ) uses the ferr/nerr error reporting infrastructure. ? the aioc blocks (see section 5.6, ?error reporting by aioc devices? on page 155 ) use their existing error reporting infrastructures that are ?bridged? into the ia-32 core to report errors to ia through pci signals (i.e., intx or msi depending on device configuration). these blocks do not support other pci error reporting capabilities such as serr or the imch ferr/nerr architecture. this organization allows an ep80579 system to use standard ia platform reporting abstractions and algorithms throughout the ia portion of the chip (including the memory controller). aioc devices then use pci intx or msi signaling to present their error handling within the ia infrastructure. utilizing signaling in this fashion implies that the responsibility for error handling in aioc devices resides with intel provided aioc device drivers in the ep80579 software stack.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 140 order number: 320066-003us the ep80579 hardware, where appropriate, supports two general capabilities for error handling. the first is support for data ?poisoning? to propagate errors through the chip. the second is support for mechanisms to allow software to inspect the cause of the error. to allow software to inspect the error, each unit in the ep80579 that is capable of detecting errors typically provides hardware support to: ? log sufficient information for software to determine what the error was along with relevant details on the error. ? disable error detection and reporting. ? report if more than one error occurred. at a minimum, the unit will note that a second error occurred. optionally, a unit may gather additional information on subsequent errors such as the type(s) of errors or other relevant details. a given unit need not support all of these ca pabilities.to illustrate these capabilities, consider the ep80579 dram interface. dram on the ep80579 is protected by ecc, so, on a read with a double-bit error, the memory controller reports an error. the memory controller can poison the data return value to inform future consumers of the data that the data is bad. for software, registers in the memory controller provide the ability to mask this error along with logging registers that captures the address that was being read when the error was encountered. on an unmasked double-bit error, the logging register captures the address and the memory controller signals the ia-32 core through the ferr/nerr infrastructure. the error address register is locked at this point, so subsequent errors will not overwrite it until software handles the error and unlocks the registers by writing a register to clear the error condition. the memory controller provides a ?next error? register that can capture information on other unmasked errors that occur before software clears the double-bit error condition. in general, the cmi will attempt to route requests based on their understanding of the address space layout of the platform (that is, the amount of installed physical dram, attached pci express* devices, etc.). there are several tables throughout the eas that define how various parts of the chip handle this routing task: ? section 10.1, ?overview? and section 10.2, ?imch responses to edma transactions? describes how the imch responses to transactions from the edma engine. ? the memory controller does not perform bounds checking on addresses, error handling behavior is determined by the upstream agents that pass the request to the memory controller as section 5.5.1, ?handling out-of-bounds addresses? on page 154 describes. the ia portion uses the standard ia mechanisms to handle cases where this routing encounters errors (e.g., accessing an unpopulated region of memory). these cases cause aborts and are escalated through the normal error handling paths. on errors in requests arriving from the memory target, the imch will drop writes (i.e., not forward them into the imch) and poison data returns for reads through the appropriate push/ pull data error signals. these error conditions are reported through imch error reporting registers.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 141 intel ? ep80579 integrated processor 5.2.2 software usage model the software responsibilities for error handling are split between bios and system/ application software. the manner in which the software uses the capabilities that the hardware provides depends on the specific software stack under consideration. in general, bios does not establish a usage model for error handling. its primary responsibility is to configure the error handling registers throughout the ep80579 in a manner consistent with the needs of system and application software. the ep80579 reference bios provides this level of support. however, in general, a bios implementation may also log information on error events reported via smi 1 . in this case, bios populates data structures in smbios 2 that an operating system can later retrieve. generally speaking, the software is more interested in seeing an error rather than the specific location where it is sent. the usage model from the system or application perspective depends on the manner in which the hardware reports the event to the system along with the specific error event. there are two general types of reporting that one can consider: through a kernel-trapped signal and through a non-kernel- trapped signal. a particular error event need be reported through at least one of these mechanisms. when the hardware reports an error event through a signal that the os kernel handles on its own (e.g., mcerr, serr, etc.), the operating system takes whatever corrective action it implements for the signal: bug check, panic, halt, reboot, event logging, clean up and continue, etc. in this case, the os kernel establishes the usage model. this approach is only applicable to the ia and memory controller blocks since the aioc devices can only report error events through intx or msi signals that the os kernel passes off to the appropriate driver softwa re rather than handle in the kernel. when the hardware reports an error event error through a signal that the software outside of the os kernel handles on its own (e.g., intx, msi, etc.), it is the responsibility of driver or other non-kernel software to take corrective action. all aioc agents fall into this category since their hardware uses only intx or msi for error reporting. in this case, it is the responsibility of the driver software to establish the error handling usage model. typically, the action the driver takes in response to an error event will match those taken by the os kernel: panic, clean up and continue, etc. 5.3 error reporting by the imch see section 14.2, ?exception handling? and section 14.3, ?error conditions signaled? for further discussion on imch error handling. 5.3.1 overview of the first and next error architecture the imch provides a ?first? and ?next? error architecture wherein errors accumulate locally in unit-level first/next error registers that the imch aggregates into global first/ next error registers. once a unit records an e rror event in its ?first? error register, it will record all subsequent errors in its ?next? e rror register until software clears the error condition in the first error register. the error events are then classified into ?fatal? and ?non-fatal? groups for reporting through the global first and next error registers. the architecture allows software to mask individual error events at the unit level. in addition, through per-unit registers, software can configure the hardware to report the error event through ia smi, sci, serr, or mcerr signals. 1. this approach only works for error events that the ep80579 can report through smi. specifically, this approach would not work for error events from aioc agents which cannot report through smi in the ep80579. 2. system management bios (smbios) is a specification to lay out data structures and access methods in a bios which provides for storage and retrieval of information about the pc in question
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 142 order number: 320066-003us the actions taken by the hardware in response to an error event depends on the manner in which software has configured the imch to report the error. for unmasked events that the imch signals through smi, sci, or serr, the imch presents the error to the ia-32 core indirectly through the iich. in these cases, the imch sends an error message to the iich (via nsi) that iich interrupt logic handles by signaling the ia-32 core through an interrupt. for unmasked events that the imch signals through mcerr, the imch directly presents the error to the ia-32 core (via fsb). in this case, the imch directly signals the ia-32 core through the mcerr protocol on the fsb. after receiving the message, software will query the global imch error registers (see section 5.3.2, ?global error events? ) to determine which imch unit is responsible for the error. with that information, software can query the unit that generated the event to determine the specific cause. 5.3.2 global error events ta b l e 5 - 1 summarizes the error events that the imch captures in its global_ferr and global_nerr error registers (see section 16.2.1.12, ?offset 40h: global_ferr - global first error register? and section 16.2.1.13, ?offset 44h: global_nerr - global next error register? ). each of these events rolls up one or more unmasked error events from an individual imch unit. to determine the specific error event that causes a signal, software consults the unit-specific error registers that ta b l e 5 - 1 indicates. the global registers provide summary information only; masking takes place at the unit level. . table 5-1. summary of imch global error conditions event fatality a a. fatal versus non-fatal classification for reporting through global_ferr and global_nerr. unit-specific registers notes dram controller fatal error fatal dram_ferr, dram_nerr fatal error in dram interface. fsb fatal error fatal fsb_ferr, fsb_nerr fatal error on internal cpu/imch fsb interface. nsi fatal error fatal nsi_ferr, nsi_nerr fatal error on internal imch/iich nsi interface. dma fatal error fatal edma_ferr, edma_nerr fatal error from dma controller. pci express* port a1, a0 fatal error fatal peaferr, peanerr b b. each port has its own independent peaferr and peanerr registers in the pci configuration space for the port controller device. fatal error from pci express* port a1 (pea1) or a0 (pea0). buffer unit non-fatal error non-fatal buf_ferr, buf_nerr non-fatal error in posted memory write buffer. dram controller non-fatal error non-fatal dram_ferr, dram_nerr non-fatal error in dram interface. fsb non-fatal error non-fatal fsb_ferr, fsb_nerr non-fatal error on internal cpu/imch fsb interface. nsi non-fatal error non-fatal nsi_ferr, nsi_nerr non-fatal error on internal imch/iich nsi interface. dma non-fatal error non-fatal edma_ferr, edma_nerr non-fatal error from dma controller. pci express* port a1, a0 non-fatal error non-fatal peaferr, peanerr b non-fatal error from pci express* port a1 (pea1) or a0 (pea0).
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 143 intel ? ep80579 integrated processor section 5.3.3 , section 5.3.4 , section 5.3.5 , section 5.3.6 , section 5.3.7 , and section 5.3.8 discuss the specific per-unit events that the imch hardware captures and rolls up into the global conditions that ta b l e 5 - 1 lists. 5.3.3 unit-level errors from the buffer unit the imch buffer unit captures error events from the memory system coherent posted memory write buffer (pmwb) in the buf_ferr and buf_nerr registers. the buffer unit reports an error event to the ia-32 core through sci, smi, serr, or mcerr signals based on the settings in the buf_scicmd, buf_smicmd, buf_serrcmd, and buf_mcerrcmd registers. software can independently configure the specific signal that each buffer unit error event uses. ta bl e 5 - 2 summarizes the error conditions that the pmwb can generate. . ta bl e 5 - 3 summarizes the capabilities of the imch buffer unit error handling for each of the features that the unit is expected to provide. 5.3.4 unit-level errors from the dram interface these errors include the error events reported by the memory controller, see section 5.5, ?error reporting by the system memory controller? on page 153 for additional details. table 5-2. summary of imch buffer unit error conditions event type fatality a a. fatal versus non-fatal classification for reporting through global_ferr and global_nerr. reports via b b. based on buf_scicmd, buf_smicmd, buf_serrcmd, and buf_mcerrcmd register values. notes dram to pmwb parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error detected on read from dram agent by pmwb. system bus or i/o to pmwb parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error detected on write to pmwb from system bus or i/o agent. pmwb to system bus parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error detected on data to the system bus. pmwb to dram parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error detected when pmwb is flushed to dram. table 5-3. summary of imch buffer unit error reporting capabilities feature implementation enabling and masking error reporting the buf_emask (see section 16.2.1.29, ?offset 74h: buf_emask - memory buffer error mask register? ), buf_scicmd, buf_smicmd, buf_serrcmd, and buf_mcerrcmd registers enable and mask error reporting. the pcicmd register (see section 16.2.1.3, ?offset 04h: pcicmd - pci command register? ) also enables and masks serr signals. logging details imch does not capture error logging information beyond the event flags in the buf_ferr, buf_nerr and pcists (see section 16.2.1.4, ?offset 06h: pcists - pci status register? ) registers. reporting multiple errors the buf_nerr register captures ?next? errors. this register indicates up to one additional error (beyond the first error) of each type. data poisoning imch passes along error information to poison data.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 144 order number: 320066-003us 5.3.5 unit-level errors from the fsb interface the fsb interface captures error events from the fsb interface that connects the ia-32 core to the imch in the fsb_ferr and fsb_nerr registers. the fsb interface reports an error event to the ia-32 core through sci, smi, serr, or mcerr signals based on the settings in the fsb_scicmd, fsb_smicmd, fsb_serrcmd, and fsb_mcerrcmd registers. software can independently configure the specific signal that each buffer unit error event uses. ta b l e 5 - 4 summarizes the error conditions that the fsb can generate. . ta b l e 5 - 5 summarizes the capabilities of the fsb error handling for each of the features that the unit is expected to provide. although the imch supports all of the errors ta b l e 5 - 4 lists with the features in ta b l e 5 - 5 , the ep80579 implementation does not take full advantage of these capabilities since its fsb implementation does not support all of the features necessary. table 5-4. summary of imch fsb error conditions event type fatality a a. fatal versus non-fatal classification for reporting through global_ferr and global_nerr. reports via b b. based on fsb_scicmd, fsb_smicmd, fsb_serrcmd, and fsb_mcerrcmd register values. notes outgoing i/o data parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error on outgoing data from i/o subsystem. outgoing memory data parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error on outgoing data from memory subsystem. fsb binit# detected uncorrectable fatal n/a c c. although the imch supports these errors, the ep80579 will not ever generate them since its on-die fsb implementation does not support binit# or parity. electrical high-to-low transition of binit#. fsb mcerr# detected uncorrectable non-fatal sci, mcerr, smi, or serr electrical high-to-low transition of mcerr# when cmi is not driving. non-dram lock error uncorrectable non-fatal sci, mcerr, smi, or serr lock detected to memory space that does not map to dram. fsb addr. above tom/tolm uncorrectable non-fatal sci, mcerr, smi, or serr address detected above tom/tolm. fsb data parity uncorrectable non-fatal n/a c parity error on fsb detected. fsb addr. strobe glitch detected uncorrectable fatal n/a c glitch detected on fsb address strobe. fsb data strobe glitch detected uncorrectable fatal n/a c glitch detected on fsb data strobe. fsb request/addr parity uncorrectable fatal n/a c party error on fsb address or request signals. table 5-5. summary of imch fsb error reporting capabilities feature implementation enabling and masking error reporting the fsb_emask fsb_scicmd, fsb_smicmd, fsb_serrcmd, and fsb_mcerrcmd registers enable and mask error reporting. the pcicmd register also enables and masks serr signals. logging details fsb does not capture error logging information beyond the event flags in the fsb_ferr, fsb_nerr and pcists reporting multiple errors the fsb_nerr register captures ?next? errors. this register indicates up to one additional error (beyond the first error) of each type. data poisoning fsb passes along e rror information to poison data.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 145 intel ? ep80579 integrated processor for additional discussion on the imch responses to transactions from the fsb interface, see section 10.1, ?overview? . 5.3.6 unit-level errors from the nsi the imch hardware captures error events from the nsi interface that connects the imch to the iich in the nsi_ferr and nsi_nerr registers. the nsi interface reports an error event to the ia-32 core through ia sci, smi, serr, or mcerr signals based on the settings in the nsi_scicmd, nsi_smicmd, nsi_serrcmd, and nsi_mcerrcmd registers. software can independently configure the specific signal that each buffer unit error event uses. ta bl e 5 - 6 summarizes the error conditions that the nsi can generate. . table 5-6. summary of imch nsi error conditions event type fatality a reports via b notes unsupported request uncorrectable fatal, non- fatal sci, mcerr, smi, or serr unsupported request detected. malformed tlp uncorrectable fatal, non- fatal sci, mcerr, smi, or serr malformed tlp detected. receiver overflow uncorrectable fatal sci, mcerr, smi, or serr overflow detected in posted, non- posted, or completion upstream queue. unexpected completion uncorrectable non-fatal sci, mcerr, smi, or serr completion received that does not correspond to an outstanding request. completer abort uncorrectable non-fatal sci, mcerr, smi, or serr completer abort detected. completion timeout uncorrectable non-fatal sci, mcerr, smi, or serr request not completed within timeout window. poisoned tlp uncorrectable non-fatal sci, mcerr, smi, or serr portion of tlp data payload was corrupt. data link protocol error uncorrectable fatal sci, mcerr, smi, or serr error detected in data link protocol. replay timer timeout uncorrectable non-fatal sci, mcerr, smi, or serr replay timer expired. replay_num rollover uncorrectable non-fatal sci, mcerr, smi, or serr retry buffer replay counter rolled over. bad dllp crc uncorrectable non-fatal sci, mcerr, smi, or serr calculated dllp crc did not equal received value. bad tlp crc uncorrectable non-fatal sci, mcerr, smi, or serr calculated tlp crc did not equal received value. receiver error uncorrectable non-fatal sci, mcerr, smi, or serr packet framing error. received fatal error message uncorrectable fatal sci, mcerr, smi, or serr fatal error message received over nsi link. received non- fatal error message uncorrectable non-fatal sci, mcerr, smi, or serr non-fatal error message received over nsi link.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 146 order number: 320066-003us ta b l e 5 - 7 summarizes the capabilities of the nsi error handling for each of the features that the unit is expected to provide. for additional discussion on the imch responses to transactions from the nsi interface, see section 10.1, ?overview? . 5.3.7 unit-level errors from the edma engine the imch edma unit captures error events from the edma engine in the edma_ferr and edma_nerr registers (the edma unit reports an error event to the ia-32 core through ia sci, smi, serr, or mcerr signals based on the settings in the edma_scicmd, edma_smicmd, edma_serrcmd, and edma_mcerrcmd registers. software can independently configure the specific signal that each edma unit error event uses. ta b l e 5 - 8 summarizes the error conditions that the edma can generate. . received correctable error message correctable non-fatal sci, mcerr, smi, or serr correctable error message received over nsi link. parity error on data from core uncorrectable non-fatal sci, mcerr, smi, or serr parity error detected on data received from core. link down uncorrectable fatal sci, mcerr, smi, or serr link transitioned from dl_up to dl_down. a. fatal versus non-fatal classification for reporting through global_ferr and global_nerr. b. based on nsi_scicmd, nsi_smicmd, nsi_serrcmd, and nsi_mcerrcmd register values. table 5-6. summary of imch nsi error conditions event type fatality a reports via b notes table 5-7. summary of imch nsi error reporting capabilities feature implementation enabling and masking error reporting the nsi_emask, nsi_scicmd, nsi_smicmd, nsi_serrcmd, and nsi_mcerrcmd registers enables and masks error reporting. the pcicmd register also enables and masks serr signals. logging details nsi captures error logging information in the following registers: ? all errors: nsi_ferr, nsi_nerr, and pcists capture event flags. ? poisoned tlp: pcists captures event flags. ? received fatal/non-fatal/correctable error messages: nsi_errsid. all of the logging information that the nsi ca ptures relates to the ?first? error with the exception of nsi_nerr. reporting multiple errors the nsi_nerr register captures ?next? errors. this register indicates up to one additional error (beyond the first error) of each type. data poisoning nsi passes along error information to poison data. table 5-8. summary of imch edma error conditions event type fatality a reports via b notes ndar addressing error uncorrectable non-fatal sci, mcerr, smi, or serr descriptor pointer is of incorrect type or range for channels 0-3. ndar alignment error uncorrectable non-fatal sci, mcerr, smi, or serr descriptor pointer is not aligned to an 8 dw boundary for channels 0-3. source address error uncorrectable non-fatal sci, mcerr, smi, or serr source address does not comply with source type or range for channels 0-3.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 147 intel ? ep80579 integrated processor ta bl e 5 - 9 summarizes the capabilities of the edma error handling for each of the features that the unit is expected to provide. for additional discussion on the imch responses to transactions from the edma engine, see section 10.1, ?overview? and section 10.2, ?imch responses to edma transactions? . 5.3.8 unit-level errors from pci express* ports a0 and a1 the imch pci express* port controllers capture error events from the port a0 and a1 controllers in per-port registers. the register set provides two parallel error reporting mechanisms, one that reports standard errors defined by the pci express* specification and a second that reports errors that are specific to the ep80579 pci express* implementation (and thus, outside of the standard pci express* errors). the pci express* controllers capture errors required by the pci express* base specification in the uncerrsts and corerrsts registers. the controllers capture ep80579-specific errors in the peauniterr register. the errors from both sets of errors are aggregated in the peaferr and peanerr registers. the pci express* controllers report an error event to the ia-32 core through ia sci, smi, serr, or mcerr signals based on the settings in the peaerrdocmd register. ta bl e 5 - 1 0 summarizes the error conditions that the pci-express can generate. destination address error uncorrectable non-fatal sci, mcerr, smi, or serr destination address does not comply with destination type or range for channels 0-3. parity error uncorrectable non-fatal sci, mcerr, smi, or serr parity error during read of source data from system memory for channels 0-3. write error uncorrectable non-fatal sci, mcerr, smi, or serr write to ro descriptor registers when dma in normal mode for channels 0-3. a. fatal versus non-fatal classification for reporting through global_ferr and global_nerr. b. based on edma_scicmd, edma _smicmd, edma_serrcmd, and ed ma_mcerrcmd register values. table 5-8. summary of imch edma error conditions event type fatality a reports via b notes table 5-9. summary of imch edma error reporting capabilities feature implementation enabling and masking error reporting the edma_emask, edma_scicmd, edma_smicmd, edma_serrcmd, and edma_mcerrcmd registers enables and masks error reporting. the pcicmd register also enables and masks serr signals. logging details edma does not capture error logging information beyond the event flags in the edma_ferr, edma_nerr and pcists. reporting multiple errors the edma_nerr register captures ?next? errors. this register indicates up to one additional error (beyond the first error) of each type. data poisoning edma passes along error information to poison data.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 148 order number: 320066-003us . table 5-10. summary of imch pci-express error conditions event type fatality a a. fatal versus non-fatal classification for reporting through global_ferr and global_nerr. reports via b b. based on peaerrdocmd register value. notes unsupported request uncorrectable uncerrsev c c. severity is set by the uncerrsev register. sci, mcerr, smi, or serr request type unsupported. ecrc error uncorrectable uncerrsev c sci, mcerr, smi, or serr error in ecrc. malformed tlp uncorrectable uncerrsev c sci, mcerr, smi, or serr malformed tlp, like it says... receiver overflow uncorrectable uncerrsev c sci, mcerr, smi, or serr overflow on upstream queue. unexpected completion uncorrectable uncerrsev c sci, mcerr, smi, or serr received completion that does not match any outstanding requests. completer abort uncorrectable uncerrsev c sci, mcerr, smi, or serr received request violates programming model. completion timeout uncorrectable uncerrsev c sci, mcerr, smi, or serr timeout. flow control protocol error uncorrectable uncerrsev c sci, mcerr, smi, or serr poisoned tlp uncorrectable uncerrsev c sci, mcerr, smi, or serr tlp data payload corrupt. data link protocol uncorrectable uncerrsev c sci, mcerr, smi, or serr ack/nack has incorrect sequence number. unsupported request uncorrectable uncerrsev c sci, mcerr, smi, or serr unsupported request uncorrectable uncerrsev c sci, mcerr, smi, or serr unsupported request uncorrectable uncerrsev c sci, mcerr, smi, or serr replay timer correctable non-fatal sci, mcerr, smi, or serr replay timer expired. replay_num rollover correctable non-fatal sci, mcerr, smi, or serr retry buffer counter rolled over. bad dllp status correctable non-fatal sci, mcerr, smi, or serr computed dllp crc does not match received value. bad tlp status correctable non-fatal sci, mcerr, smi, or serr computed tlp crc does not match received value. receiver error correctable non-fatal sci, mcerr, smi, or serr received 8b/10b error. lle protocol error uncorrectable non-fatal sci, mcerr, smi, or serr transaction layer detected protocol error. link down error uncorrectable fatal sci, mcerr, smi, or serr link transitions from dl_up to dl_down. downstream data queue parity uncorrectable non-fatal sci, mcerr, smi, or serr parity error occurred in downstream data queue. smb clock timeout uncorrectable non-fatal sci, mcerr, smi, or serr smb clk low greater than 25ms. unexpected nak on smb uncorrectable non-fatal sci, mcerr, smi, or serr unexpected nak on smb. smb arbitration uncorrectable non-fatal sci, mcerr, smi, or serr smb lost bus arbitration.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 149 intel ? ep80579 integrated processor ta bl e 5 - 1 1 summarizes the capabilities of the pci-express error handling for each of the features that the unit is expected to provide. see section 16.4, ?pci express* port a standard and enhanced registers: bus 0, devices 2 and 3, function 0? for additional details. for additional discussion on the imch responses to transactions from the pci express* ports, see section 10.1, ?overview? . 5.4 error reporting by the iich the ep80579 iich devices rely on the pci error reporting architecture to reporting errors. in this architecture, details on the e rrors are logged in the pci status register from the per-device pci configuration header. a parity or other severe system error causes the device to generate an ia serr signal. errors that occur on the nsi bus between the imch and iich report through the nsi_ferr and nsi_nerr infrastructure as section 5.3.1, ?overview of the first and next error architecture? on page 141 and section 5.3.6, ?unit-level errors from the nsi? on page 145 describe. on the iich backbone, iich devices must rely entirely on the serr signal that the device generates on an error event to report the error. the iich does not provide any other capability (such as data poisoning) that would allow a consumer of iich data to note an error. as a result, an iich devi ce can return erroneous data on a request. the remainder of this section describes the error handling capabilities of the units in the iich. 5.4.1 smbus interface the iich provides a smbus controller that can generate an interrupt or smi on error events and can also use the pci serr infrastructure to report errors. the hcfg register selects either smi or interrupt signaling; parity and system errors always signal through serr. ta b l e 5 - 1 2 summarizes the error conditions that the controller reports. table 5-11. summary of imch pci-ex press error reporting capabilities feature implementation enabling and masking error reporting the uncerrmsk, uncedmask, corerrmsk, coredmask, rpmerrsts, peamaskerr, rperrcmd, and peaerrdocmd registers enables and masks error reporting. the pcicmd register also enables and masks serr signals. logging details pci express* controllers captures error loggi ng information in th e following registers: ? rpmerrsts errors: errsid captures requester ids. ? errors with header capture: hdrlog0, hdrlog1, hdrlog2, and hdrlog3 captures the first four 32-bit words of the headers. this information is in addition to the st atus information in uncerrsts, corerrsts, rpmerrsts, peaferr, and peanerr. reporting multiple errors the peanerr and rperrmsts registers captures ?next? errors. this register indicates up to one additional error (beyond the first error) of each type. data poisoning pci express* controllers pa ss along error information to poison data.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 150 order number: 320066-003us . ta b l e 5 - 1 3 summarizes the capabilities of the smbus controller error handling for each of the features that the unit is expected to provide. for additional details on error handling in the smbus controller, see section 24.0, ?smbus controller functional description: bus 0, device 31, function 3? . 5.4.2 lpc interface the iich provides a lpc interface that uses the pci serr infrastructure to report errors. ta bl e 5 - 1 4 summarizes the error conditions that the controller reports. . ta b l e 5 - 1 5 summarizes the capabilities of the lpc interface error handling for each of the features that the unit is expected to provide. table 5-12. summary of smbus interface error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes device error uncorrectable fatal interrupt, smi b b. based on hcfg register values. device error. bus error uncorrectable fatal interrupt, smi b bus error. failed bus tra n sa c t i on uncorrectable fatal interrupt, smi b bus transaction failed. parity error uncorrectable fatal serr parity error detected. system error uncorrectable fatal serr system error detected. table 5-13. summary of smbus controller error reporting capabilities feature implementation enabling and masking error reporting the cmd and usbintr registers enables and masks error reporting. logging details the usb 1.1 interface captures the type of event detected in the dsr, hsts, and auxs registers. reporting multiple errors the smbus interface does not capture multiple events. data poisoning iich backbone does not support data poisoning. table 5-14. summary of lpc interface error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes parity error uncorrectable fatal serr parity error detected. system error uncorrectable fatal serr system error detected. table 5-15. summary of lpc interface error reporting capabilities feature implementation enabling and masking error reporting the cmd register supports error enabling and masking.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 151 intel ? ep80579 integrated processor for additional details on error handling in the lpc interface, see section 19.0, ?lpc interface: bus 0, device 31, function 0? . 5.4.3 usb 1.1 interface the iich provides a usb 1.1 controller that can generate an interrupt on error events and can also use the pci serr infrastructure to report errors. ta b l e 5 - 1 6 summarizes the error conditions that the controller reports. . ta bl e 5 - 1 7 summarizes the capabilities of the usb 1.1 controller error handling for each of the features that the unit is expected to provide. for additional details on error handling in the usb 1.1 controller, see section 25.0, ?usb (1.1) controller: bus 0, device 29, function 0? . 5.4.4 usb 2.0 interface the iich provides a usb 2.0 controller that can generate an interrupt on error events and can also use the pci serr infrastructure to report errors. ta b l e 5 - 1 8 summarizes the error conditions that the controller reports. logging details the lpc interface captures the type of event detected in the sts register. reporting multiple errors the lpc interface does not capture multiple events. data poisoning iich backbone does not support data poisoning. table 5-15. summary of lpc interface error reporting capabilities feature implementation table 5-16. summary of usb 1.1 interface error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes host controller process error uncorrectable fatal interrupt consistency check by host controller fails while processing a td. host system error uncorrectable fatal interrupt serious error during host system access involving hc module. usb error uncorrectable fatal interrupt usb transaction completion ended in error. parity error uncorrectable fatal serr parity error on read completion returned to host controller or uhci register write. table 5-17. summary of usb 1.1 interface error reporting capabilities feature implementation enabling and masking error reporting the cmd and usbintr registers supports error enabling and masking. logging details the usb 1.1 interface captures the type of event detected in the dsr and usbsts registers. reporting multiple errors the usb 1.1 interface does not capture multiple events, error events cause the interface to halt operation until serviced by software. data poisoning iich backbone does not support data poisoning.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 152 order number: 320066-003us . ta b l e 5 - 1 9 summarizes the capabilities of the usb 2.0 controller error handling for each of the features that the unit is expected to provide. for additional details on error handling in the usb 2.0 controller, see section 26.0, ?usb 2.0 host controller: bus 0, device 29, function 7? . 5.4.5 sata interface the iich provides a sata interface that can generate an interrupt on error events and can also use the pci perr infrastructure to report errors. ta b l e 5 - 2 0 summarizes the error conditions that the controller reports. . ta b l e 5 - 2 1 summarizes the capabilities of the sata controller error handling for each of the features that the unit is expected to provide. table 5-18. summary of usb 2.0 interface error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes host system error uncorrectable fatal interrupt serious error during host system access involving hc module. usb error uncorrectable fatal interrupt usb transaction completion ended in error. parity error uncorrectable fatal serr parity error on usb read completion. system error uncorrectable fatal serr parity error on address, command, or data, or unsuccessful completion of ech-initiated read. table 5-19. summary of usb 2.0 interface error reporting capabilities feature implementation enabling and masking error reporting the cmd and usb20intr registers supports error enabling and masking. logging details the usb 2.0 interface captures the type of event detected in the dsr and usb20sts registers. reporting multiple errors the usb 2.0 interface does not capture multiple events, error events cause the interface to halt operation until serviced by software. data poisoning iich backbone does not support data poisoning. table 5-20. summary of sata interface error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes host bus fatal error uncorrectable fatal interrupt unrecoverable host bus error host bus data error uncorrectable fatal interrupt uncorrectable data error. interface fatal error uncorrectable fatal interrupt fatal error on sata interface. interface non- fatal error uncorrectable non-fatal interrupt non-fatal error on sata interface. parity error uncorrectable fatal serr parity error detected on interface.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 153 intel ? ep80579 integrated processor for additional details on error handling in the sata interface, see section 23.0, ?sata: bus 0, device 31, function 2? . 5.4.6 serial i/o interface the iich provides a serial i/o interface that can generate an interrupt on error events. ta bl e 5 - 2 2 summarizes the error conditions that the serial i/o interface captures. . ta bl e 5 - 2 3 summarizes the capabilities of the thermal sensor error handling for each of the features that the unit is expected to provide. for additional details on error handling in the serial i/o interface, see section 33.0, ?serial i/o unit and watchdog timer? . 5.5 error reporting by the system memory controller the memory controller interfaces with memory to provide data movement to and from dram along the aioc-direct and coherent paths to memory. the memory controller is designed to conform to the imch first and next error handling architecture that section 5.3.1, ?overview of the first and next error architecture? on page 141 describes. the memory controller reports its unit-level first/next error events through the dram_ferr and dram_nerr registers in the memory controller (see section 11.5, ?error handling? ). the flow of memory controller errors matches the imch behavior for its other errors as section 5.3.1 describes. table 5-21. summary of sata interface error reporting capabilities feature implementation enabling and masking error reporting the cmd and pie[0-3] registers support error enabling and masking. logging details the sata interface captures the type of event detected in the sts and pis[0-3] registers. reporting multiple errors the sata interface does not capture multiple events. data poisoning iich backbone does not support data poisoning. table 5-22. summary of serial i/o interface error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes framing error uncorrectable fatal interrupt received character missing stop bit. parity error uncorrectable fatal interrupt received character has parity error. overrun error uncorrectable fatal interrupt receive buffer over-written. table 5-23. summary of serial i/o interface error reporting capabilities feature implementation enabling and masking error reporting the ier and lcr registers supports error enabling and masking. logging details the serial i/o interface captures the type of event detected in the iir and lsr registers. reporting multiple errors the serial i/o interface does not capture multiple events. data poisoning n/a
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 154 order number: 320066-003us 5.5.1 handling out-of-bounds addresses the memory controller does not perform any bounds checking on system addresses that it receives from other agents. as a result, the behavior of the ep80579 in response to an access to a dram location that is outside the range of populated memory depends on the source of the transaction and the path it takes through the device. there are two paths of relevance to this discussion: the coherent path through the imch and the aioc-direct path directly to the memory controller. accesses to locations above top of memory along the coherent path (from either aioc agents via the aioc-interface, the ia-32 core, or other agents attached to the cmi through pci express*, etc.) will be aborted by the imch. the specific manner of the abort depends on whether the transaction originates from the ia-32 core or a aioc agent. access to locations above top of memory along the aioc-direct path (from the aioc memory target) are not aborted or otherwise trapped by default. the results of such transactions are undefined and may alias onto populated memory regions. as a result, software must program the ep80579 so that it can never generate an aioc-direct system address above tom. the memory target provides the ability to log range errors (and optionally halt the aioc master that generated the transaction). 5.5.2 imch - memory controller the memory controller can notify the ia-3 2 core of memory-related error events through sci, smi, serr, or mcerr signals based on the settings in the dram_scicmd, dram_smicmd, dram_serrcmd, and dram_mcerrcmd registers (see section 11.0, ?system memory controller? ). software can configure the specific signal used for each error event independently. ta b l e 5 - 2 4 summarizes the error conditions that the memory controller captures. note that the memory controller always reports errors through the non-fatal classification in the error reporting registers. . ta b l e 5 - 2 5 summarizes the capabilities of the memory controller error handling for each of the features that the unit is expected to provide. table 5-24. summary of memory controller error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. this can differ from the fatal/non-fatal classification for reporting through global_ferr and global_nerr. reports via b b. based on dram_scicmd, dram_smicmd, dram_s errcmd, and dram_mcerrcmd register values. notes uncorrectable write error uncorrectable fatal sci, mcerr, smi, or serr write of poisoned data to dram. uncorrectable read error uncorrectable fatal sci, mcerr, smi, or serr error during normal demand reads. uncorrectable scrubber data error uncorrectable fatal sci, mcerr, smi, or serr memory scrubber encountered an uncorrectable error. correctable read error correctable non-fatal sci, mcerr, smi, or serr hardware will correct and report if appropriately configured error threshold detect status non-fatal sci, mcerr, smi, or serr count of single- or double-bit errors exceeds a programmable threshold. memory test complete status non-fatal sci, mcerr, smi, or serr status event to indicate when memory test hardware completes testing.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 155 intel ? ep80579 integrated processor for additional details on error handling in the memory controller, see section 11.5, ?error handling? . 5.6 error reporting by aioc devices the aioc devices continue to use the native error reporting infrastructure that each unit provides. primarily, this infrastructu re relies on one or more side-band error signals from each aioc device that can signal an error along with parity protection on key interfaces. the aioc native error reporting mechanisms are then bridged into the pci framework that the ep80579 uses to expose aioc devices to ia. although aioc devices present a pci interface to ia, they do not implement pci error reporting capabilities such as serr. as a result, the native signals from the aioc devices are bridged onto pci intx or msi signals. this implies that the driver software provides all error handling for aioc units 1 . the following sections describe the error reporting for each of the aioc units along with transaction responses. the per-unit presentations are organized by the pci device in which the units materialize. 5.6.1 gigabit ethernet mac the gigabit ethernet mac units each signal error conditions through three interrupt signals: functional 0, functional 1, and error. software uses the ims0, ims1, and ims2 configuration registers in a gigabit ethernet mac to map error conditions onto the functional 0, functional 1, and error interrupt signals, respectively. depending on the configuration, error and functional events may share an interrupt (e.g., software may configure the functional 1 interrupt to signal both error and functional events); typically, software will configure a mac to deliver its error events separately through only the error interrupt. ta bl e 5 - 2 6 summarizes the error conditions that the gigabit ethernet mac captures. table 5-25. summary of memory controller error reporting capabilities feature implementation enabling and masking error reporting the dram_emask, dram_scicmd, dram_smicmd, dram_serrcmd, and dram_mcerrcmd registers enable and mask error reporting. logging details memory controller captures additional error logging information in the following registers: ? uncorrectable read errors: dram_ded_add. ? uncorrectable scrubber data errors: dram_scrb_add. ? correctable read errors: dram_secf_add, dram_secf_syndrome, dram_secn_add, dram_secn_syndrome. ? error threshold detect: rankthrex, thresh_sec0, thresh_sec1, thresh_ded, dram_sec_r0, dram_sec_r1, dram_ded_r0, dram_ded_r1. additional logging information is not captured for the remaining errors in ta bl e 5 -2 4 . with the exception of dram_secn_add and dram_secn_syndrome, all of the logging information that the memory controller captures relates to the ?first? error. reporting multiple errors the dram_nerr register captures the ?next? errors seen by the memory controller. this register indicates up to one additional error (beyond the first error) of each type. data poisoning memory controller passes along error information to poison data both on inbound (from memory) data and outbound (to memory) data. 1. if pci abstractions such as serr were used, this would not be the case. platform and/or o/s software would also be involved in error handling for the devices even if the involvement is limited to generating a blue screen.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 156 order number: 320066-003us ta b l e 5 - 2 7 summarizes the capabilities of the gigabit ethernet mac error handling for each of the features that the unit is expected to provide. see section 37.6, ?gbe controller register summary? and section 37.5.12, ?error handling? for additional details. 5.6.2 can interface the can units signal error conditions through two interrupt signals. the can unit shares one interrupt between functional signaling duties (e.g., signaling that a message was received) and error reporting, while the se cond interrupt reports only parity errors. status and enable registers in the can operate and control signaling functionality in the can such as error reporting. ta b l e 5 - 2 8 summarizes the error conditions that the can captures. table 5-26. summary of gigabit ethernet mac error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via b b. based on settings in ims0, ims1, and ims2 registers. notes statistic register ecc error uncorrectable fatal err, fn0, or fn1 interrupts double-bit ecc error in a statistic register. internal memory error uncorrectable fatal err, fn0, or fn1 interrupts parity or double-bit ecc error in an internal memory. dma packet buffer error uncorrectable fatal err, fn0, or fn1 interrupts double-bit ecc error during read from dma packet buffer on tx or rx. dma tx desc. ecc error uncorrectable fatal err, fn0, or fn1 interrupts double-bit ecc error during read from dma transmit descriptor. dma rx desc. ecc error uncorrectable fatal err, fn0, or fn1 interrupts double-bit ecc error during read from dam receive descriptor. table 5-27. summary of gigabit ethernet mac error reporting capabilities feature implementation enabling and masking error reporting the ims0, ims1, and ims2 interrupt mask set registers and the imc0, imc1, and imc2 interrupt mask clear registers support error enabling and masking. when software configures the gbe to deliver errors on their own interrupt, the smia and smme registers from the signal target capab ility in the pci configur ation header for a gbe mac can also support error enabling and masking. logging details the sint register from the signal target ca pability in the pci configuration header for a gbe mac provides read-only access to the state of the interrupt signals from a gbe mac. additional logging information is not captured for the other errors in ta b l e 5 - 2 6 . reporting multiple errors individual status bits in the gbe icr0, icr1, and icr2 interrupt cause registers are set as conditions occur. the unit can indicate at most one outstanding error at any time. data poisoning gbe passes along e rror information to poison data.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 157 intel ? ep80579 integrated processor ta bl e 5 - 2 9 summarizes the capabilities of the can error handling for each of the features that the unit is expected to provide. see section 39.6, ?register summary? and section 39.5.2, ?error handling? for additional details. 5.6.3 ssp interface the ssp unit signals error conditions through a single interrupt signal. the ssp block shares this interrupt between functional duties (e.g., transmit fifo service request) and error reporting duties. software is expected to use status registers in the ssp to determine the cause of a signal. ta bl e 5 - 3 0 summarizes the error condition that the ssp captures. table 5-28. summary of can error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes crc check error uncorrectable fatal can system interrupt mismatch between received and computed crc. acknowledge error uncorrectable fatal can system interrupt improperly formatted ack slot. form error uncorrectable fatal can system interrupt improperly formatted fixed-form field. bit error uncorrectable fatal can system interrupt mismatch between monitored and sent bit value. stuff error uncorrectable fatal can system interrupt improperly formatted message from start of frame to crc delimiter. can sram parity error uncorrectable fatal can parity interrupt parity error in interface sram. clearing the parity error requires a reset of the can interface. please see section on can interrupts in section 39.2, ?feature list? on page 1569 for more details. table 5-29. summary of can error reporting capabilities feature implementation enabling and masking error reporting the can interrupt enable register supports error enabling and masking. the smia and smme registers from the signal target capability in the pci configuration header for the can units also supports error enabling and masking. using these registers to mask the can system interrupt masks both error and functional events since the can units use this interrupt to signal both error and functional conditions. logging details the sint register from the signal target capability in the pci configuration header for a can unit provides read-only access to the state of the interrupt signals from a can unit. can does not log additional details on errors. reporting multiple errors individual status bits in can interrupt status register are set as conditions occur. the unit can indicate at most one outstanding error of each type at any time. data poisoning can does not require support for data poisoning. errors during transactions cause the transaction to abort and an error event to be signaled.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 158 order number: 320066-003us ta b l e 5 - 3 1 summarizes the capabilities of the ssp error handling for each of the features that the unit is expected to provide. see section 40.4, ?register summary? and section 40.3.2, ?error handling? for additional details. 5.6.4 local expansion bus the local expansion bus unit signals error conditions from the interface into the ep80579 through a single interrupt signal that is used exclusively for errors. in addition, this unit signals errors from the internal bridge through a separate interrupt. ta b l e 5 - 3 2 summarizes the error conditions that the local expansion bus captures. . ta b l e 5 - 3 3 summarizes the capabilities of the local expansion bus error handling for each of the features that the unit is expected to provide. table 5-30. summary of ssp error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes functional receiver overrun (ror) uncorrectable fatal ssp interrupt receive fifo is full, any incoming data is discarded. table 5-31. summary of ssp error reporting capabilities feature implementation enabling and masking error reporting ssp does not provide the ability to enable or mask the interrupt from an ror error condition. the smia and smme registers from the signal target capability in the pci configuration header for the ssp unit also support error enabling and masking. using these registers to mask the ssp interrupt masks both error and functional events since the ssp unit uses this interrupt to signal both error and functional conditions. logging details the sint register from the signal target capa bility in the pci configuration header for the ssp unit provides read-only access to the state of the interrupt signals from ssp. ssp does not log additional details on its errors. reporting multiple errors ssp can only generate a single error. the unit can indicate at most one outstanding error at any time. data poisoning ssp error conditions result in loss of data an d system interrupt. there is no need to poison in these cases. table 5-32. summary of local expansion bus error conditions event type fatality a a. ?fatal? events result in data loss or data corruption that the unit cannot repair, ?non-fatal? events do not. reports via notes parity error uncorrectable fatal leb parity error interrupt parity error on outbound read from the ep80579.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 159 intel ? ep80579 integrated processor see section 42.5, ?register summary? . 5.6.5 ieee 1588, and gcu the ieee 1588 and gcu in the aioc do not signal any non-functional error conditions. table 5-33. summary of local expansion bus error reporting capabilities feature implementation enabling and masking error reporting leb device provides the following registers to support error enabling and masking: ? errors from leb: exp_timing_cs[0-7]. the smia and smme registers from the signal target capability in the pci configuration header for the leb also support error masking and enabling. logging details the sint register from the signal target capability in the pci configuration header for the leb provides read-only access to the state of the interrupt signals from the leb. leb device captures additional error logging information in the following registers: ? leb parity errors: exp_parity_status. reporting multiple errors leb device reports additional errors as follows: ? leb errors data poisoning leb pass along error information to poison data.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 160 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 161 intel ? ep80579 integrated processor 6.0 reset and power management this chapter describes the intel ? ep80579 integrated processor reset and power management. 6.1 reset and powergood distribution this section discusses the detailed sequencing of how power and clocking signals must be applied to bring the ep80579 out of reset. 6.1.1 types of reset the ep80579 has four types of reset: power-good (cold) reset, hard reset, cpu-only reset, and targeted i/o subsystem reset(s). each of these reset subclasses have unique effects and is described in ta bl e 6 - 1 . 6.1.1.1 powergood implementation the initial boot from when the power supplies are energized is facilitated by the powergood mechanism. the voltage sources from all platform power supplies are routed to a system component which tracks them as they ramp-up, asserting platform powergood (cpu_vrd_pwr_gd and sys_pwr_ok) after a fixed interval (nominally 99 ms) after the last voltage reference has stabilized. powergood signals are propagated asynchronously to dedicated iich, imch, and ia-32 core inputs. generally, the devices on aioc fabric including the aioc reset block do not receive a powergood signal. the exception is the gbe mac devices (see section 6.1.2.3.5, ?gbe mac? ). ta bl e 6 - 2 summarizes the power wells and external voltages required by the ep80579. more detailed power supply pin information can be found in ta b l e 6 - 3 . table 6-1. types of reset and wake-up from power saving states type mechanism effect of reset on following blocks cpu imch/ iich aioc pci-e ddr power-good input pin reset reset reset reset reset hard input pin reset reset reset reset reset software (sw) controlled write to i/o port cf9 reset reset reset reset reset cpu-only internal to the ep80579. generated by imch reset -n/a -n/a -n/a -n/a s3 -> s0 wake event reset reset reset reset -n/a s4/s5->s0 wake event reset reset reset reset reset
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 162 order number: 320066-003us 6.1.1.2 hard reset implementation a hard reset is initiated by the iich via the pltrst# as a result various s-state wake events or other reset signal assertions. pltrst# is driven to the imch and is propagated from there to the reset block for aioc fabric. the reset block in the aioc fabric is responsible for resetting the individual blocks. imch propagates a hard reset to the fsb and subordinate pci express* subsystems. the fsb components are reset via the cpurst# (internal signal) signal, while the pci express* subsystems through pcirst#. 6.1.1.3 software controlled reset software may cause a full system reset through a write to the reset control register located at i/o port cf9. see also section 6.1.1.4, ?cpu only reset implementation? for software controlled cpu only reset mechanisms. 6.1.1.4 cpu only reset implementation for power management, error conditions and other reasons, the ep80579 supports a targeted cpu only reset semantic. this mechanism eliminates system reset at large when the cpu function (such as clock gearing selection) must be updated during initialization. it only affects the ia-32 core. other blocks such as iich, imch, aioc complex are not reset. it is controlled by imch. the ia-32 core can also be reset via the assertion of its init# pin which may be accomplished by several conditions including a software write to the reset control register in iich. asserting the init# pin on the ia-32 core invokes a response similar to that of asserting cpurst#. the major difference is that during an init, the internal caches, msrs, mtrrs, and fpu state are left unchanged (although, the tlbs and btb are invalidated as with a hardware reset). when init is signaled while the processor is in virtual-8086 mode, the processor leaves virtual-8086 mode and enters real-address mode. an init provides a method for switching from protected to real-address mode while maintaining the contents of the internal caches. table 6-2. power wells and external voltages power well nominal voltage components core 1.0-1.3 v ia processor: ia-cpu 1.2 v core logic (imch, iich, asu, ssu, tdm, gbe mac1, gbe mac2), sata pads, pci-e pads, local expansion bus 1.8 v pci-e pll, ddr2 pads. note: 0.9v are generated from 1.8v 2.5 v rmii/rgmii 3.3 v sata, pci-e 5.0v 5v tolerance reference suspend 1.2 v iich, usb pads, ddr2 core logic, gbe mac0, usb core logic and pads 2.5 v rmii/rgmii 3.3 v usb pads, rmii/rgmii pads 5.0v 5v sustain reference rtc 3.3 v rtc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 163 intel ? ep80579 integrated processor 6.1.1.5 s-state wake events wake events for the various acpi sleep states cause a hard reset to the ep80579 (see section 27.6.3, ?exiting sleep states? ). wake on lan, supported by the gbe macs, leverages mechanisms provided for gpi and pme wake events. 6.1.1.6 targeted reset implementation the targeted reset is provided for hot-plug events, as well as for port specific error handling under mca or smi software control. a targeted reset may be requested by setting bit six (secondary bus reset) of the bridge control register (d2, f0, offset 3eh) in the target root port device. setting this bit crashes the link training and status state machine (ltssm) of the target port to the reset state, where it issues at least 1024 ts1 ordered sets with the reset bit asserted. this propagates an in-band ?h ot? reset to the downstream device, and consequently force an equivalent reset to an y devices further downst ream. this reset is identical to a general hard reset from the perspective of destination pci express* device. 6.1.2 platform reset and powergood this section describes the reset and powergood external platform interfaces. 6.1.2.1 platform powergood the ep80579 receives two powergood signals from the platform. the first is cpu_vrd_pwr_gd and the other is sys_pw r_ok. sys_pwr_ok is asserted after a fixed delay from the time that cpu_vrd_pwr_gd goes active and indicates that power has been stable for at least 99 ms. the ep80579 inputs pwrgd, pwrok, and sys_pwr_ok are connected to the sys_pwr_ok platform signal. cpu_vrd_pwr_gd and sys_pwr_ok distribution inside the ep80579 is discussed in section 6.1.2.3, ?reset and powergood distribution? . refer to figure 6-1 for the block diagram showing cpu_vrd_pwr_gd and sys_pwr_ok interfaces. 6.1.2.2 platform reset the ep80579 receives two reset signals from the platform. the first one is sys_reset which includes the reset button on the platform. the second is resume reset which is used for resetting the iich resume well afte r power is restored from a power failure. reset distribution inside the ep80579 is discussed in section 6.1.2.3, ?reset and powergood distribution? . refer to the figure 6-1 , for a block diagram showing the reset interface.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 164 order number: 320066-003us 6.1.2.3 reset and powergood distribution the ep80579 reset follows a general path through the iich to the imch and out to the rest of the chip. 6.1.2.3.1 iich iich plays the central role in reset and powergood distribution to the whole chip. iich receives two powergood signals from the platform (cpu_vrd_pwr_gd and sys_pwr_ok). the assertion of these signals starts the reset sequence for the ep80579. iich generates the central reset signal (known as pltrst#) that initiates the reset of the rest of the chip. pltrst# is received by imch. iich also generates pcirst# signal for resetting the pci device. pcirst# is similar to pltrst# except that pcirst# can be asserted using a csr. iich also generates the powergood (cpupwrgd#) signal for ia-32 core. figure 6-1. powergood and reset interface ep80579 wdt_n pwrbtn_n rsmrst_n sys_rest_n pcirst_n pltrst_n pwrok vrmpwrgd pwrgd rstin_n nc8 rtest_n pwron_btn fp_pwron# rtcrst# rtc reset_btn fp_reset# rsmrst# glue 4 cpu_vrd_pwr_gd sys_pwr_ok fwh lai sio lpc p80 pci-e x4 conn pci -e x8 conn itp/xdp 1k sys_pwr_ok gbe_aux_pwr_good gbe_pme_wake gbe_aux_pwr_good wake signal tpm 1.0v/1.3v ia-32 core ready ck410 2.5v for gbe 1.2v logic core ready silverbox_pwrok gbe powergood 2ms delay 100ms del ay pwrgd ddr2 1.8v pme_n 0 ohm empty pci-e switch vccsus25 2.5v vccpsus 3.3v vccsus1 1.2v en en db800 inverter vsby3_3
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 165 intel ? ep80579 integrated processor iich signals inputs vrmpwrgd - voltage regulator powergood: this signal is directly connected to the platform signal, cpu_vrd_pwr_gd and signifies that the voltage regulator is stable. pwrok - iich power okay: this signal is directly connected to the platform signal, sys_pwr_ok. when asserted, pwrok is an indication to the iich that power has been stable for at least 99 ms and that pciclk has been stable for at least 1 ms. pwrok can be driven asynchronously. when pwrok is inactive, the iich asserts pltrst#. sys_reset# - system reset: this signal initiates a system reset and causes pltrst# to go active. sys_reset# must be asserted for at least 100ms. system reset cannot occur again until sys_reset# has been detected inactive, and the system is back to a full s0 state with pltrst# inactive. if bit 3 of the reset control register is set then the assertion of sys_reset# will result in a full power cycle reset. rsmrst# - resume well reset: this signal resets the iich resume power plane logic when power is reapplied after a power failure. if the afterg3_en bit in the general power management configuration 3 register (d31 f0 offset a4) is set to 0, iich transitions the system from g3 (mechanical off) to s0 state and causes the assertion of the pltrst# output. if afterg3_en is 1, the system will transition to s5 state. rtest# - rtc well test: this signal is tied to the platform rtcrst# signal. normally it is held high (to vccrtc), but can be driven low on the tester or motherboard to test the rtc well. rtest# resets some bits in the rtc well that are otherwise not reset by pltrst# or rsmrst#. an external rc circuit on the rtcrst# signal creates a time delay such that rtcrst# will go high some time after the battery voltage is valid. the rc time delay must be in the 10-20 ms range. this allows detection when a new battery has been installed. unless entering a xor chain test mode, the rtest# input must always be high when all other non-rtc power planes are on. outputs cpupwrgd - cpu powergood: this signal is the logical and of the iich vrmpwrgd and pwrok input signals. this signal is connected to the processor's powergood input to indicate when the processor power is valid. pltrst# - platform reset: this signal is asserted by sys_reset#, rsmreset#, or software. the iich asserts pltrst# to reset devices on the platform (e.g., sio, fwh, lan, imch, ide, tpm, etc.) during power-up (cpu_pwrgd de-asserted) and when software initiates a hard reset sequence through the reset control register. the iich drives pltrst# active a minimum of 1 ms when initiated through the reset control register. the iich de-asserts pltrst# a minimum of 1 ms after cpu_pwrgd is driven high. pcirst# - pci reset: this is the secondary pci bus reset signal. this signal is asserted a small number of pci clocks after pltrst# or can be asserted independently by the secondary bus reset bit. 6.1.2.3.2 imch imch plays a crucial role in the reset sequence for ia-32 core. imch receives the powergood signal (sys_pwr_ok) from the platform. the iich pltrst# drives the imch rstin# input. imch drives the cpurst# (internal signal) while it is in the reset. imch works with iich to initialize the nsi link between iich and imch. once the central reset (pltrst#) is de-asserted, imch de-asserts the cpurst# (internal signal).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 166 order number: 320066-003us imch can also configure some aspects of the ia-32 core at power on. imch drives these configuration settings before cpurst# (internal signal) assertion based on the contents of its power-on configuration register (d8, f0, offset c0h). imch signals inputs pwrgd - imch powergood: this signal is directly connected to the platform signal, sys_pwr_ok. when asserted, pwrgd is an indication to the imch that power has been stable for at least 99 ms. when pwrgd is inactive, the imch asserts its cpurst# (internal signal) outputs. rstin# - imch reset: this signal is directly connected to the iich pltrst# output. when rstin is active, the imch asserts its cpurst# (internal signal) output. 6.1.2.3.3 ia-32 core early in the cold reset (powergood) sequence, the ia-32 core voltage regulator drives a default voltage to the ia-32 core to read the fuses containing the ia-32 core fsb frequency requirements. the ep80579 then drives its bsel pin to the appropriate value which is latched by the platform when it is known to be stable. the platform uses the bsel information to update the ia-32 core voltage regulator to the appropriate operating voltage prior to the assertion of cpu_vrd_pwr_gd. the platform also uses the value of bsel to drive the clock generator to the correct reference clock (bclk) frequency. reset and configuration for ia-32 core is do ne by iich and imch. reset for ia-32 core starts when imch asserts cpurst# (internal signal) and iich asserts cpupwrgd. the assertion of both of these signals initiates the pll locking process for the ia-32 core. all the flops and internal states are reset during the reset process. the processor?s pll locks before cpurst# (internal signal) is de-asserted. cpurst# (internal signal) needs to be asserted for at least 1ms and not more than 10ms (processor spec).the ia-32 core receives power-on configuration values on its address pins during cpurst# (internal signal). 6.1.2.3.4 imch the imch receives the central reset (pltrst#) from iich. clocks to dimms are disconnected till bios configures the dimms. memory controller core logic boots at the default frequency as driven by the bsel pin. based on the ddr type and frequency memory controller needs to re-lock itself at the ddr frequency once bios has read the ddr. 6.1.2.3.5 gbe mac there are three gbe mac devices. each gbe receives the internal system reset. each gbe also receives a power ok signal from the platform that is also used as a reset. gbe0 receives this signal via the gbe_aux_pwr_good external pin. gbe1 and gbe2 receive this signal via the sys_pwr_ok external pin. the sys_pwr_ok pin is connected to the sys_pwr_ok platform signal which is also connected to the pwrok and pwrgd pins. the gbe_aux_pwr_good pin should be connected to sys_pwr_ok when no auxiliary power supply is used. if an auxiliary supply is used for gbe0, then gbe_aux_pwr_good should be connected to the power good signal from that power supply (this signal is subject to the timing requirements documented in figure 6-4, ?power rail sequence timings (sustain well power management)? on page 170 ). under all circumstances, gbe0 must be powered by either the system supply or the auxiliary supply. likewise, gbe_aux_pwr_good must be connected to the corresponding power good signal. gbe0 must be powered to enable operation of either gbe1 or gbe2.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 167 intel ? ep80579 integrated processor 6.1.3 ep80579 power sequencing and reset sequence the following diagrams show the reset sequencing. 1. the ep80579 receives power and drives its bsel and v_sel pins. cpu_vrd_pwr_gd, sys_pwr_ok (platform signals) are not asserted. pltrst#, and cpurst# (internal signal) are asserted. 2. cpu_vrd_pwr_gd is asserted (platform signal). internal signal name is vrmpwrgd. 3. external reference clock provided from platform is stable, and is supplied to the ep80579 internal plls to generate required internal clocks. voltage regulator output is modified to correspond to bsel and v_sel values. 4. the ep80579 cru pll locks. 5. sys_pwr_ok (platform signal) == pwrok/pwrgd internal signal asserted 6. io and core plls lock on the cpu. 7. iich de-asserts pltrst# 8. imch de-asserts udrstb (internal reset unit). all ep80579 blocks except the ia-32 core come out of reset. 9. imch de-asserts cpurst# (internal signal) cpu executes the reset micro-code figure 6-2. reset sequence 1 3 4 5 6 7 8 10 power applied to ep80579 reference clock stable (from clock generator) pwrok pwrgd sys_pwr_ok cpu_vrd_pwr_gd (from platform) cru clock pltrst# de-asserted all the blocks except the ia cpu come out of reset udrst cpurst# de-asserted de-asserted reset microcode execution re-steer to bios memory controller initialization ddr initialization iich imch cpu ep80579 imch 2 (from platform) vrmpwrgd stable 5 iich cpu_pwrgd asserted cpu fsb and core clocks stable 9
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 168 order number: 320066-003us table 6-3. ep80579 power supply pins nominal voltage voltage tolerance package pin supply types description well = core 0.9 v (ddr2) +/-5% vttddr ddr ddr termination voltage 1.0v@600mhz 1.3v@1066/ 1200mhz +/-2% vccvc ia-32 core ia-32 core power 1.2 v +/-5% vcca[1] ia-32 core ia-32 core pll1 power vcca[2] ia-32 core ia-32 core pll2 power vcc cru, cru_pad, ddr, expansion, bus, gbe, imch_pad, misc io, pci, express, sata core power vccusb12 usb2 digital power vccausb12 usb2 analog power vccahpll cru analog pll power vccape0pll12 pci-express pll digital power vccapll sata analog pll power vccape pci-express receiver analog power vccape pci-express receiver analog power vccape pci-express transmitter analog power vccarx sata analog receiver power vccatx sata analog transmitter power vccrpe pci-express receiver digital power vccsata sata sata power 1.8 v (ddr2) +/-5% vcc18 ddr ddr io power vcc18 trng trng power vcctmp18 thermal sensor thermal sensor power vccape0pll18 pci-express pll vrm power 2.5 v +/-5% vcc25 gbe gbe io 3.3 v +/-5% vcc33 cru_pad, expansion bus, imch_pad, misc io io power vccgbe33 gbe 3.3v tolerance reference vccsata33 sata sata power vccabg3p3_usb usb2 analog bandgap power vccabgp033 pci-express bandgap analog power vccasatabg3p3 sata analog bandgap power 5 v +/-5% vcc50 expansion bus, misc io, cru_pad, imch_pad 5v tolerance reference well = suspend
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 169 intel ? ep80579 integrated processor figure 6-3 illustrates the sequence that power rails should follow as they are brought up at power on. figures 6-4 , 6-5 , 6-6 , and 6-7 accompanied by ta b l e 6 - 4 , ta b l e 6 - 5 , and ta b l e 6 - 6 show the relationship between the power supply rails and key reset signals upon ep80579 power-up. in figures 6-4 and 6-5 , the terms ?core? and ?suspend? refer to the power wells that table 6-2 on page 162 describes. 1.2 v +/-5% vcc1p2_usbsus usb2 1.2v usb sustain power vccsus1 imch_pad rtc core sustain power vccsus1 gbe core gbe sustain power 2.5 v +/-5% vccsus25 gbe sustain gbe power 3.3 v +/-5% vccpsus usb2, imch_pad usb and rtc io sustain power vccgbepsus gbe sustain 3.3v tolerance reference 5 v +/-5% vcc50_sus imch_pad, usb2 5v sustain reference well = rtc 3.3 +/-5% vccprtc imch_pad real time clock power table 6-3. ep80579 power supply pins nominal voltage voltage tolerance package pin supply types description figure 6-3. ep80579 rail power on sequence suspend 3.3v suspend 5.0v suspend 1.2v ia-32 core 1.0v - 1.3v core 3.3v core 2.5v core 1.8v vttddr core 1.2v core 5.0v ps_on# 2 suspend 2.5v vccprtc 1
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 170 order number: 320066-003us figure 6-4. power rail sequence timings (sustain well power management) vccprtc core 2. 5 v suspend 3. 3 v rtcrst # rsmrst # t 200 t 201 suspend 5 v core 5 v sys_ pwr_ok core 3. 3 v suspend 1. 2 v t205 t204 t 209 t 213 t202 t 212 vrmpwrgd/ cpu_vrd_pwr_gd t 210 ia- 32 core 1.0-1. 3 v core 1. 2 v t211 suspend 2. 5 v t 203 core 1. 8 v , vttddr t206 g b e_ a u x_ p wr_ go od
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 171 intel ? ep80579 integrated processor figure 6-5. power rail sequence timing (no sustain well power management) vrmpwrgd/ cpu_vrd_pwr_gd sys_pwrok gbe_aux_pwr_good table 6-4. power rail sequence signal timings sym parameter min max units notes t200 vccprtc active to rtcrst# inactive 18 ? ms t201 suspend 5 v active to suspend 3.3 v active 0 ? ms 1 t202 suspend 3.3 v active to suspend 2.5 v active 0 ? ms 2 t203 suspend 2.5 v active to suspend 1.2 v active 0 ? ms 3 t204 suspend supplies active to rsmrst# inactive 10 ? ms t205 vccprtc supply active to suspend supplies active 0 ? ms 4 t209 core 5 v active to core 3.3 v active 0 ? ms 1 notes: 1. the 5 v supply must power up before its associated 3.3 v supply within 0.3 v, and must power down after the 3.3 v supply within 0.3v. 2. ensure the following: a) suspend 3.3 v must power up before suspend 2.5 v or after suspend 2.5 within 0.3 v, b) suspend 2.5 v must power down before suspend 3.3 v or after suspend 3.3 v within 0.3 v. 3. ensure the following: a) suspend 2.5 v must power up before suspend 1.2 v or after suspend 1.2 v within 0.3 v, b) suspend 1.2 v must power down before suspend 2.5 v or after suspend 2.5 v within 0.3 v. 4. the vccsus supplies must never be active while the vccprtc supply is inactive. 5. ensure the following a) core 3.3 v must power up before core 2.5 v or after core 2.5 v within 0.3 v, b) core 2.5 v must power down before core 3.3 v or after core 3.3 v within 0.3 v. 6. ensure the following: a) core 2.5 v must power up before vcc1.2 v or after core 1.2 v within 0.3 v, b) core 1.2 v must power down before core 2.5 v or after core 2.5 v within 0.3 v.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 172 order number: 320066-003us t210 core 3.3 v active to core 2.5 v active 0 ? ms 5 t211 core 2.5 v active to core 1.2 v active 0 ms 6 t212 suspend supplies active to core supplies active 0 ? ms 4 t213 all core supplies active to sys_pwr_ok (platform signal) active 99 ? ms table 6-4. power rail sequence signal timings sym parameter min max units notes notes: 1. the 5 v supply must power up before its associated 3.3 v supply within 0.3 v, and must power down after the 3.3 v supply within 0.3v. 2. ensure the following: a) suspend 3.3 v must power up before suspend 2.5 v or after suspend 2.5 within 0.3 v, b) suspend 2.5 v must power down before suspend 3.3 v or after suspend 3.3 v within 0.3 v. 3. ensure the following: a) suspend 2.5 v must power up before suspend 1.2 v or after suspend 1.2 v within 0.3 v, b) suspend 1.2 v must power down before suspend 2.5 v or after suspend 2.5 v within 0.3 v. 4. the vccsus supplies must never be active while the vccprtc supply is inactive. 5. ensure the following a) core 3.3 v must power up before core 2.5 v or after core 2.5 v within 0.3 v, b) core 2.5 v must power down before core 3.3 v or after core 3.3 v within 0.3 v. 6. ensure the following: a) core 2.5 v must power up before vcc1.2 v or after core 1.2 v within 0.3 v, b) core 1.2 v must power down before core 2.5 v or after core 2.5 v within 0.3 v. figure 6-6. powergood reset sequence b6548-01 power rails bsel cpu+vrd_pwr_gd/ vrmpwrgd reference clock sys_pwr_ok/ pwrok/pwrgd cpu_pwrgd pltrst#/rstin# pcirst# cpu power-on configuration cpurst# ab cd f i j
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 173 intel ? ep80579 integrated processor table 6-5. powergood reset timings timing description value t ab vrmpwrgd/ cpu_vrd_pwr_gd assertion to reference clock stable 2 ms t ac vrmpwrgd/ cpu_vrd_pwr_gd assertion to sys_pwr_ok (platform signal) assertion 99 ms t cd sys_pwr_ok (platform signal) assertion to cpu_pwrgd assertion (cpu_pwrgd is logical and of vrmpwrgd/ cpu_vrd_pwr_gd and sys_pwr_ok) logic delay tdf cpu_pwrgd assertion to pltrst# de-assertion 1 ms tfi rstin# deassertion to cpurst# (internal signal) de-assertion 1 ms + cpu_rst_done transaction delay (max 10,000 pci- e clocks) + cpu_rst_done capture timer (min 2000 reference clocks) tij cpurst# (internal signal) de-assertion to poc invalid 2 reference clocks figure 6-7. hard reset sequence b6549-01 reference clock sys_pwr_ok/pwrok/ pwrgd/cpu_pwrgd sys_reset# pltrst#/rstin# cpu power-on configuration cpurst# adgh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 174 order number: 320066-003us table 6-6. hard reset timings timing description value t ad minimum sys_reset assertion duration 100 ms t dg rstin# deassertion to cpurst# (internal signal) de-assertion 1 ms + cpu_rst_done transaction delay (max 10,000 pci-e clocks) + cpu_rst_done capture timer (min 2000 reference clocks) t gh cpurst# (internal signal) de-assertion to poc invalid 2 reference clocks
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 175 intel ? ep80579 integrated processor 6.2 bios boot flow (initialization) after hardware reset of the ep80579 and once ia -32 core has executed the reset micro-code, the ia 32 core resteers to reset vector (0xffff_fff0) and starts fetching from bios code boot rom. bios starts execution from the reset vector regardless of whether wake is from s3, s4, or s5. to determine that it is s3 resume, bios checks the sus_typ field in the power management controller. if it is not s3, then normal boot occurs. if it is s3, then bios also chec ks the power failure bits (pwrbtnor_sts, pwr_flr, pwrok_flr). if these are set to one, then memory contents cannot be relied on and normal boot is followed. if it is an s3 resume and the power failure bits are not set, then the s3 boot path is followed. the normal boot path is that used for cold reset and for s4/s5 resume. from a bios perspective there is no difference between s4 and s5. the following steps describe the boot sequence after reset before handover to os. figure 6-8. bios boot flow (cold boot, s3/s4->s0) 1) select bsp hard reset this step is automatic and precedes any software influence on chipset configuration. power-on-configuration is propagated across the fsb, breq0# is asserted to select a boot-strap cpu, and mch strapping options are sampled. 5) configure pci- express ports. * for cold reset, bios reads the pci-express port configuration register and configure ports which are successfully trained. * for s3/s4->s0, bios retrieves the expected pci-express port configuration from nvram/disk. bios must then read the pci-express port status registers, configure the ports which successfully trained, and update the mch configuration map (device present bits) to reflect mch environment. 3) initialize memory * on cold reset, bios calibrates and configures imch and ddr. bios may also run diagnostic tests on populated memory at this point to verify no ill-effects from reset. initialize all populated memory to all "0"s with good ecc codes. if desired, bios may also run diagnostic tests on populated memory at this point to verify no ill-effects from reset. * on s3->s0, bios retrieves the prior configuration. 4) shadow bios bios copies required bios code up from the fwh via ich to the desired location in main memory. program the pam registers to reflect the correct shadowing settings. 6) enumerate pci bios execute a standard pci scan in incrementing bus and device number order, program primary/secondary/subordinate bus# registers, and aggregate the total memory required for each logical pci-express port. at the end of this step, the pci io, m, pm, tolm, and hpcim registers should be properaly configured to reflect allocated i/o and mmio space. 8) interrogate and clear error regs at this point bios has access to all the error reporting information in the system. 10) enable smm bios programs the desired smm size, location, and configuration. at the end of this step, set the mch control register bit to lock-down the memory map. this prevents viruses from reprogramming the memory confi guration to compromise smm space. 9) apic configuration bios programs the apic configuration registers in the mch to allocate message space in the processor/chipset reserved space. identical configuration must be propagated to all capable expander devices found during enumeration. pass to os (cold reset) or context recovery (s3/s4- >s0) 2) read/retrieve memory cfg * on cold reset, bios reads the spd registers in dimm via smbus. bios finds the ddr type, ddr frequency and configures the gearing ratio. bios uses the information to programdra, drb, drc and drt registers in imch. bios enables the ddr clock. * on s3->s0, bios retrieves the memory table intact from non-volatile memory, and uses that information directly to program dra, drb, drc, and drt registers. cpu poc .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 176 order number: 320066-003us 6.2.1 memory configuration as described in the flow chart, one of the first actions of the bios is to configure main memory. this section describes the memory configuration sequence of bios. at reset the memory controller disables the output clock reference drivers for all dimm slots, which prevents them from locking at the wrong frequency, and then relocking after this step in the initialization process. memory controller core logic boots at a factory set default frequency as is indicated by the bsel pin. the bios must first set the ddr frequency and ratio via the drc register because the memory controller needs to re-lock itself at the desired ddr frequency. bios configures the ddr frequency by reading the fsb frequency value from a processor internal msr and ddr2 circuitry and sets the ddr speed bits [3:0] of the drc register (d0, f0, offset 7ch). once the correct frequencies have been selected bios updates ckdis (d0, f0, offset 8ch), such that only populated ranks of populated dimm slots receive output clocks from the memory controller. using the ddr spd data, bios programs the imch dra and drb registers for proper translation of physical addresses to ddr row, bank, and column addresses. bios further configures the ddr configuration, timing, and impedance compensation settings to enable reliable communication between the imch and the ddr dimm devices. the drt registers (d0, f0, offsets 78h and 64h) defaults settings can be found in section 11.0, ?system memory controller? . bios further performs ddr calibration, memory initialization, and optional membist. at this stage bios is aware of the total amount of memory populated in the system, and may generate the starting value for the top of memory (tom) register setting. bios will generally want to complete at least a rudimentary memory test sequence (next step) prior to finalizing the memory size information reported to the operating system. for memory initialization details refer to section 11.0, ?system memory controller? . wake from s3/s4/s5 are also described in the figure 6-8 6.2.2 memory initialization at this point in the boot sequence memory contains random data from power-on, and would therefore generate non-deterministic ecc errors on read accesses. to zero-out memory and initialize all locations with good ecc, the memory controller provides a hardware engine which will walk all populated dram space issuing cache-line sized writes with all zeroes as data. 6.2.3 boot from network booting from network on intel platforms is supported by pxe. pxe (preboot execution environment) is an existing open industry specification for network clients to automatically download software images and configuration parameters. the pxe client software is typically implemented as a bios option rom that is executed during the preboot phase of the client system. this option rom (oprom) implements a sufficient network stack to perform all of the necessary network operations to boot an operating system. this oprom image is written assuming ia-32 architecture and instruction set. also, each oprom image is modified specifically for a given network interface controller (nic).
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 177 intel ? ep80579 integrated processor the bios must first establish an environment suitable for execution of the pxe oprom. this environment must provide the following: ? system memory sufficient for c-code execution. this memory will be used to load/ execute oprom code, implement a call stack and data storage. in addition system memory must be available for loading/execution of os. ? bios runtime services sufficient for oprom execution. these services are typically provided by system bios and allow the pxe oprom to be implemented for platform independence. ? the pci sub-system is enumerated with allocation of system memory space, io space and interrupts completed. this will establish the address location of resources accessed by the oprom code during execution. after oprom initialization, the code remains in memory and waits until the bios reaches the point at which the os-boot process begins. when a gbe is selected for boot, code in the oprom will be used to initiate communication with a server to supply the images required for boot. after these images are loaded execution control passes from the bios to the images loaded in memory. this transition concludes the preboot phase and enters in to the os-boot phase. 6.3 power management 6.3.1 power management states from a user-visible level, the system can be thought of as being in one of the states shown in figure 6-9 . in general use, computers alternate between the working and sleeping states. in the working state, the computer is used to do work. user-mode application threads are dispatched and running. individual devices can be in low-power (dx) states and processors can be in low-power (cx) states if they are not being used. figure 6-9. global system power states and transitions
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 178 order number: 320066-003us any device the system turns off because it is not actively in use can be turned on with short latency. (what ?short? means depends on the device. an lcd display needs to come on in sub-second times, while it is generally acceptable to wait a few seconds for a printer to wake.) precise definitions for gx, dx, sx and cx states are given in ta bl e 6 - 7 , ta b l e 6 - 8 , ta b l e 6 - 9 , and ta bl e 6 - 1 0 . table 6-7. global power states global power state description g3 mechanical off a computer state that is entered and left by a mechanical means (for example, turning off the system's power through the movement of a large red switch). various government agencies and countries require this operating mode. it is implied by the entry of this off state through a mechanical means that no electrical current is running through the circuitry and that it can be worked on without damaging the hardware or endangering service personnel. the os must be restarted to return to the working state. no hardware context is retained. except for the real- time clock, power consumption is zero. g2/s5 soft off a computer state where the computer consumes a minimal amount of power. no user mode or system mode code is run. this state requires a large latency in order to return to the working state. the system's context will not be preserved by the hardware. the system must be restarted to return to the working state. it is not safe to disassemble the machine in this state. g1 sleeping a computer state where the computer consumes a small amount of power, user mode threads are not being executed, and the system ?appears? to be off (from an end user's perspective, the display is off, and so on). latency for retu rning to the working state varies on the wake environment selected prior to entry of this state (for example, whether the system should answer phone calls). work can be resumed without rebooting the os because large elements of system context are saved by the hardware and the rest by system software. it is not safe to disassemble the machine in this state. g0 working a computer state where the system dispatches user mode (application) threads and they execute. in this state, peripheral devices (peripherals) are having their power state changed dynamically. the user can select, through some ui, various performance/power characteristics of the system to have the software optimize for performance or battery life. the system responds to external events in real time. it is not safe to disassemble the machine in this state. table 6-8. device states device state description d3 off power has been fully removed from the device. the device context is lost when this state is entered, so the os software will reinitialize the device when powering it back on. since device context and power are lost, devices in this state do not decode their address lines. devices in this state have the longest restore times. all classes of devices define this state. d2 the meaning of the d2 device state is defined by each device class. many device classes may not define d2. in general, d2 is expected to save more power and preserve less device context than d1 or d0. buses in d2 may cause the device to lose some context (for example, by reducing power on the bus, thus forcing the device to turn off some of its functions). d1 the meaning of the d1 device state is defined by each device class. many device classes may not define d1. in general, d1 is expected to save less power and preserve more device context than d2. d0 fully-on this state is assumed to be the highest level of power consumption. the device is completely active and responsive, and is expected to remember all relevant context continuously.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 179 intel ? ep80579 integrated processor 6.3.2 power management support as a system on a chip with embedded i/o devices and many skus, the ep80579 power management needs to perform multiple functions (typically under acpi and/or bios system software control): ? minimize power consumption of software-disabled interfaces/units. ? transition between defined acpi states as defined in ta b l e 6 - 1 1 . ? support system wake-up from gpio, pci express* devices and gbe mac ports (wake-on-lan). table 6-9. sleeping states sleeping state description s0 fully active s1 the s1 sleeping state is a low wake latency sleeping state. in this state, no system context is lost (cpu or chip set) and hardware maintains all system context. s2 the s2 sleeping state is a low wake latency sleeping state. this state is similar to the s1 sleeping state except that the cpu and system cache context is lost (the os is responsible for maintaining the caches and cpu context). control starts from the processor's reset vector after the wake event. s3 the s3 sleeping state is a low wake latency sleeping state where all system context is lost except system memory. cpu, cache, and chip set context are lost in this state. hardware maintains memory context and restores some cpu and l2 configuration context. control starts from the processor's reset vector after the wake event. s4 the s4 sleeping state is the lowest power, longest wake latency sleeping state supported by acpi. in order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. platform context is maintained. s5 soft off the s5 state is similar to the s4 state except that the os does not save any context. the system is in the ?soft? off state and requires a complete boot when it wakes. software uses a different state value to distinguish between the s5 state and the s4 state to allow for initial boot operations within the bios to distinguish whether or not the boot is going to wake from a saved memory image. table 6-10. cpu states processor power state description c0 - full on processor core is active. all clocks are running. processor can maintain cache coherency via snoops. processor responds to interrupt. c1 - auto halt processor core is not active after executing an auto-halt instruction. processor core clock is internally gated. processor can maintain cache coherency via snoops. processor responds to interrupts. aside from putting the processor in a non-executing power state, this state has no other software-visible effects. c2 - stop grant processor core is not active after its stpclk# input is asserted. processor core clock is internally gated. processor can maintain cache coherency via snoops. processor responds to interrupts. aside from putting the processor in a non-executing power state, this state has no other software-visible effects. c3 - deep sleep processor core is not active after its slp# input is asserted. processor core clock is gated and plls are disabled. processor does not respond to snoops or interrupts. while in the c3 state, the processor's caches maintain state but ignore any snoops. the operating software is responsible for ensuring that the caches maintain coherency. the ep80579 does not support c3 while functioning in s0 state, however, while in s1 state, the ep80579 will put the processor in deep sleep state through the assertion on the slp# signal.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 180 order number: 320066-003us ? support cold and warm reset for the whole chip. table 6-11. acpi states acpi state iich imch ia-32 core aioc s0 full on full on c0, c1, c2 full on s1 full on full on deep sleep full on s2 not supported not supported not supported not supported s3-hot not supported not supported not supported not supported s3-cold (suspend to ram) sections stay on, standby wells ddr io power on but interface not active power down d3 (stop clock and power down, except gbe mac wake-on lan) s4 (suspend to disk) sections stay on, standby wells sections stay on, standby wells power down power down s5 soft off sections stay on, standby wells sections stay on, standby wells power down power down table 6-12. power wells status for su pported acpi states* (sheet 1 of 2) power well supply pin(s) s0 s1 s3-cold s4 s5 core vttddr on on on a off off vccvc vcca[1] vcca[2] on on off off off vcc vccusb12 vccausb12 vccahpll vccape0pll12 vccapll vccape vccarx vccatx vccrpe vccsata on on off off off vcc18 vcctmp18 vccape0pll18 on on on b off off vcc25 on on off off off vcc33 vccgbe33 vccsata33 vccabg3p3_usb vccabgp033 vccasatabg3p3 on on off off off vcc50 on on off off off
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 181 intel ? ep80579 integrated processor 6.3.2.1 transitioning between power states the ep80579 uses a cooperative power-down that is driven by software. to transition from s0 into the s3 or s4 state under acpi/bios/os/device driver control, system software is required to: 1. suspend acceleration and security service application-level threads. 2. place asu and ssu devices into quiescent idle state, by completing all outstanding work requests, saving internal state to memory, then disabling asu/ssu interrupts. 3. quiesce i/o interfaces by disabling rx of new traffic, finalizing outstanding tx operations, disabling interrupts, and saving snap-shot of internal state to memory. 4. save internal imch and iich state to memory. 5. if transitioning to s4, move dram image to disk. 6. drain all outstanding imch updates to dram. 7. signal iich to power-down the ia-32 core, the aioc, the imch and the iich. in case of s3, the memory interface is placed into self-refresh mode. in s3/s4 state, the gbe mac, gpio and lpc interfaces remain powered to process wake events. an external wake event from gpio, gbe mac (received wake-on-lan packet) or pci express* signals the iich to initiate a complete reset sequence that transitions the ep80579 back into the s0 state as follows: 1. all internal states outside of the iich resume well are fully reset. 2. on resume from s3, bios does not reinitialize memory. please refer to section 6.2, ?bios boot flow (initialization)? for details. 3. on resume from s3 or s4, all ep80579 device drivers (including asu and ssu drivers) are expected to restore internal device state from their memory resident save area. 4. on resume from s3 or s4, resume acceleration and security service application- level threads. note: there is no support for wake from usb when in s3/s4/s5. 6.3.2.2 power state transition timing diagrams for power state transition timing details, refer to section 49.5.1.2, ?power management ac characteristics? . suspend vcc1p2_usbsus vccsus1 on on on on on vccsus25 on on on on on vccpsus vccgbepsus on on on on on vcc50_sus on on on on on rtc vccprtc ononononon a. vttdr, can optionally be powered off during s3, but typically is derived from and tracks ddr io voltage, vcc18, to avoid the complexity involved in timing the vttddr power up with the exit of s3. b. vcctmp18 and vccape0pll18 can optionally be powered off in s3 state. they are feed areas that consume very little power and are grouped with vcc18, which must be on in s3, to avoid requiring an additional power supply to support them. table 6-12. power wells status for supported acpi states* (sheet 2 of 2) power well supply pin(s) s0 s1 s3-cold s4 s5
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 182 order number: 320066-003us 6.3.3 thermal sensor the ep80579 has an on-die thermal sensor. it helps to control the silicon temperature by monitoring the silicon thermal status and activating the thermal control sequence when the silicon reaches its maximum operating temperature. see chapter 50.0, ?thermal specifications and design considerations? for details. 6.3.4 acpi implementation the pci device tree for the ep80579 is shown in figure 3-4, ?overview of pci infrastructure for on-die devices? on page 121 . the ep80579 follows the acpi specification (http://www.acpi.info/downloads/acpispec30a.pdf) which implies that all the pci devices implement the standard pci/acpi registers: 1. pci power management block 2. capability id 3. next item pointer 4. power management capabilities (pmc) 5. power management control and status register (pmcsr)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 183 intel ? ep80579 integrated processor 7.0 register summary 7.1 overview of register descriptions and summaries this chapter presents summary tables for the registers and mmio spaces that the components of the ep80579 define. in addition, this chapter describes how to read the standard register description that is used throughout this document to describe the functionality of individual registers. the register summaries in this document follow a general formatting structure that includes, for each register, its name, default value, offsets, and a cross-reference to its detailed register description. locations that are not associated with a register in the summary table should be assumed to be reserved. the summaries in this chapter are organized by functional unit and describe the ep80579 registers that are visible from the ia platform perspective (e.g., pci registers, pci memory-mapped i/o registers, fixed ia i/o space registers, etc.). 7.1.1 register description tables in addition to the summaries in this chapter, this document uses a standard tabular format to describe the operation of each register in the device. these descriptions are cross-referenced from summary tables and cover the specific content and functionality of a register. the information in a register description table can be broken down into three major areas: ? materialization information that establishes how the register appears to software. ? global information that lists the size, default, value, power well, etc. for the register. ? field definitions that list the name, description, default value, and attributes of all the fields in the register. the register definition can describe a unique register entity in the design or serve as a template that describes several register entities are instantiated in the design. the materialization information in the register description table can handle common scenarios with minimal duplication of content: ? a single physical register that materializes at multiple ?addresses? in the system (i.e., a double- or triple-mapped register). ? multiple physical registers that share the same definition but materialize within different ?device? instances. ? multiple physical registers that share the same definition but materialize repeatedly within a single ?device?. the register description table format handles the first two scenarios through ?views? that make up the bulk of the materialization information in a register description table and handles the final scenario through a set of ?repeated register? conventions.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 184 order number: 320066-003us the materialization information in a table includes specification of one or more ?views?. each view consists of a view ?type? along with several type-specific fields that serve to specify the ?address? of the register in the system from a particular perspective. for example, a pci ?view? includes, in part, the pci bus number as a parameter since this information is necessary to specify the location of the register. in a register description table, each view specification occupies one row of the table. a register description table includes one or more views depending on how the register materializes to software. there are a number of different views that this document uses to describe how ep80579 registers materialize to software. ta b l e 7 - 1 defines the views that this document uses along with the type-specific fields that each view includes. table 7-1. definition of the views used in register description tables view type describes registers in type-specific fields name description pci pci configuration space or memory/ io spaces that are mapped via pci bars b:d:f pci bus, device, and function number that the register is associated with through pci configuration, memory-mapped, or i/o-mapped spaces (see bar). bar pci base address register in b:d:f that the register is referenced from. this field is ?configuration? for registers that materialize in pci configuration space. otherwise, the field is the name of the bar register in b:d:f that provides the base address. the register materializes in memory space unless the bar field contains ?(io)?; i.e., views with a bar of ?foobar? and ?foobar (io)? materialize in memory and i/o spaces, respectively. offset start starting offset from bar. the offset is in bytes unless the field contains ?(2b)?, ?(4b)?, and ?(8b)? to indicate a single-, double-, or quad-word offset, respectively a . offset end ending offset of register from bar. the offset is in bytes unless the field contains ?(2b)?, ?(4b)?, and ?(8b)? to indicate a single-, double-, or quad-word offset, respectively a . ia f general ?fixed? location in ia memory or i/o spaces base address base address. typically, this field contains a number or register name. it may contain a comma-separated list if the register can materialize at one of several possible bases (for example, ?100h, 200h based on fooreg?). the register materializes in memory space unless the base address field contains ?(io)?; i.e., views with a base address of ?0000h? and ?0000h (io)? are in memory and i/o space, respectively. offset start starting address or offset from base address field. the offset is in bytes unless the field contains ?(2b)?, ?(4b)?, and ?(8b)? to indicate a single-, double-, or quad-word offset, respectively a . offset end ending address or offset from base address field. the offset is in bytes unless the field contains ?(2b)?, ?(4b)?, and ?(8b)? to indicate a single-, double-, or quad-word offset, respectively a .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 185 intel ? ep80579 integrated processor the register description tables adopt the convention that ta b l e 7 - 2 and ta b l e 7 - 3 describe for view and register name information to distinguish the three scenarios mentioned above (single physical register, multiple physical registers in the same device, and multiple physical registers in different devices). ta bl e 7 - 2 describes how to interpret the combination of register views and name. this table elides the type-specific fields and simply lists the types of views for brevity. ia i indirect location accessed via index/window register pair win:idx name of the window and index registers that expose the indirect register(s). for example, w:i of ?foo:bar? indicates that accesses to foo indirectly access the register that is located at the index (i.e., offset) in bar. offset start starting offset to put in the index register to access the indirect register. the index is in bytes unless the field contains ?(2b)?, ?(4b)?, and ?(8b)? to indicate a single-, double-, or quad-word offset, respectively a . offset end ending address or offset from base address field. the offset is in bytes unless the field contains ?(2b)?, ?(4b)?, and ?(8b)? to indicate a single-, double-, or quad-word offset, respectively a . a. in this usage, words, double words, and quad words are 16-, 32-, and 64-bits, respectively. table 7-1. definition of the views used in register description tables view type describes registers in type-specific fields name description table 7-2. view convention to describe single versus multiple physical registers scenario register name example views from register table interpretation single foo pci pci ia f ia f this example shows a single physical register foo. foo materializes in two different pci devices and at two different ?fixed? memory locations that the pci and ia m views describe.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 186 order number: 320066-003us when describing multiple physical registers of the same ?format? that materialize in the same device, the tables use the convention that ta b l e 7 - 3 describes to denote the offsets 1 . the remainder of this section presents several examples that illustrates how to read register definition tables. these examples are intended to illustrate how to interpret a register definition table, not describe actual registers in the ep80579. as a result, some of the examples may be contrived from the perspective of an implementation. multiple (different devices, same name) baz pci 1 pci 2 ia f 1 ia f 2 all views for the register include a numeric suffix that corresponds to the physical instance of the register. views with the same suffix address the same physical register. this example shows two physical registers matching the description of baz. the first instance of baz materializes in the pci device and at the memory location that the pci 1 and ia f 1 views describe, while the second instance of baz materializes in pci 2 and at ia f 2. multiple (different devices and names) baz{2:0} pci 0 pci 1 pci 2 ia f 0 ia f 1 ia f 2 like the multiple scenario above, the views also include a numeric suffix that, in this case, maps to different register names. the {m:n} notation in the register name indicates that each physical instance of the register has a different name that includes the instance number. an instance number i is an integer such that . this implies that there are m - n + 1 distinct instances of the register. this example shows three physical registers matching the description of baz: baz0, baz1, and baz2. baz0 materializes in the pci device and at the memory location that the pci 0 and ia f 0 views describe, baz1 materializes in pci 1 and at ia f 1, and baz2 materializes in pci 2 and at ia f 2. multiple (same device) bleh[1-3] pci pci ia f ia f the register name has a suffix indicating the number of physical instances of the register. the format of the suffix is ?[m-n]? where m and n are integers and implies that there are n - m + 1 distinct instances of the register. this example shows three physical registers matching the description of bleh: bleh[1], bleh[2], and bleh[3]. each register materializes in two different pci devices and at two different ?fixed? memory locations that the pci and ia m views describe. table 7-2. view convention to describe single versus multiple physical registers scenario register name example views from register table interpretation nim ? 1. in this scenario, it is the offset that distinguishes the different materialization points of the registers; the remaining vi ew fields should be the same since this scenario applies to registers in the same ?device?. table 7-3. offset convention to describe multiple physical registers in the same device register name offset in view(s) (start or end) interpretation bleh[1-3] 10h, 38h, 70h three bleh registers whose offsets match the elements of the comma- separated list. the offsets are bleh[1] = 10h, bleh[2] = 38h, bleh[3] = 70h. baz[1-2] 103h at 2h two baz registers whose offsets stride by 2h starting from 103h. the offsets are baz[1] = 103h, baz[2] = 105h.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 187 intel ? ep80579 integrated processor given the conventions outlined above, ta b l e 7 - 4 presents an example definition for the register eg_single which corresponds to a single physical register. this register materializes at offset e0h in the configuration space for pci device 4, at double-word (i.e., 32-bit) offset 100h in the memory region defined by foobar of pci device 12, and at the fixed offset 0a0h in ia i/o space 1 . in the table, the materialization information includes the rows starting with ?view? and the title; the field definitions includes all rows below the row starting with ?bit range?, and the rows beginning ?description? and ?size? encompass the global information. ta bl e 7 - 5 presents an example definition for the register eg_multi_diff which corresponds to two physical registers that materialize in different ?devices?. the first instance materializes at offset d0h in the configuration space for pci device 20 and at the fixed offset ffef01b0h in ia memory space. the second instance materializes at offset d0h in the configuration space for pci device 21 and at the fixed offset ffef11c0h in ia memory space. both registers have the same name, eg_multi_diff. 1. recall that offsets are in bytes unless otherwise specified with ?(2b)?, ?(4b)?, or ?(8b)?. table 7-4. eg_single: example single register with different views description: a single physical register that materializes at multiple locations. view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: e0h e1h view: pci bar: foobar bus:device:function: 0:12:0 offset start: offset end: 100h (4b) 101h (4b) view: ia f base address: 0000h (io) offset start: offset end: a0h a1h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 magic magic stuff: this field contains a magic number, 8086h. 8086h ro table 7-5. eg_multi_diff: example multiple registers in different devices with different views description: a set of two physical registers that materialize in different devices. view: pci 1 bar: configuration bus:device:function: 0:20:0 offset start: offset end: d0h d3h view: pci 2 bar: configuration bus:device:function: 0:21:0 offset start: offset end: d0h d3h view: ia f 1 base address: 00000000h offset start: offset end: ffef01b0h ffef01b3h view: ia f 2 base address: 00000000h offset start: offset end: ffef11c0h ffef11c3h size: 32 bit default: deadbeefh power well: core, reset bit range bit acronym bit description sticky bit reset value bit access 31 : 00 bmagic black magic stuff: this field contains a magic number. deadbeefh ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 188 order number: 320066-003us this table illustrates how the global information can be tied to a particular register in multiple register cases. in this table, the first and second instances of eg_mult_diff are in the ?core? and ?reset? power wells, respectively. typically, this notation is only be used for the power well. it is also possible to incorporate the instance number in the name as ta bl e 7 - 2 describes. using the name eg_multi{2:1}_diff in ta b l e 7 - 5 would identify two physical registers with different names. the first, eg_multi2_diff, materializes according to the pci 2 and ia f 2 views, while the second, eg_multi1_diff, materializes according to the pci 1 and ia f 1 views. ta b l e 7 - 6 presents an example definition for the register eg_multi_same which corresponds to two physical registers that materialize in the same ?device?. the instance eg_mult_same[1] materializes at offset ace0h in the i/o region defined by blahbar of pci device 16 and at the fixed offset 100h in ia i/o space. the instance eg_mult_same[2] materializes at offset ace4h in the i/o region defined by blahbar of pci device 16 and at the fixed offset 120h in ia i/o space. note that in this example, the strides do not need to be the same across the different views. finally, ta b l e 7 - 7 presents an example definition for the register eg_index which corresponds to a physical registers that materialize indirectly. to access the eg_index register, the starting offset 0100h (in double words of 32-bits) is written to the apic_idx index register to select eg_index which is then accessed through the apic_wnd window registers. the offsets should always fit within the index register. table 7-6. eg_multi_same[1-2]: example multiple registers in same device with different views description: a set of two physical registers that materialize in the same device. view: pci bar: blahbar (io) bus:device:function: 0:16:0 offset start: offset end: ace0h at 4h ace3h at 4h view: ia f base address: 0000h (io) offset start: offset end: 100h, 120h 103h, 123h size: 32 bit default: dead8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 brmagic blacker magic stuff: this field contains a magic number. dead8086h ro table 7-7. eg_index: example single indexed register description: a single indexed register. view: ia i win:idx apic_wnd:apic_idx offset start: offset end: 0100h (4b) 0100h (4b) size: 32 bit default: 0acefaceh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 magic magic stuff: this field contains a magic number. 0acefaceh ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 189 intel ? ep80579 integrated processor 7.1.2 register field access attributes ta bl e 7 - 8 describes the register field access attribute acronyms that this document uses in its summaries and descriptions. in some cases, the access attribute for a field may depend on a setting of a fuse or a value in another register. in this case, the access types for the field will be of the form ?x or y?. readers should consult the description of the field for additional information on the conditions that enable the various access types. for example, a field foo that is either ro or rw based on the setting of a fuse bit would have an access type of ?ro or rw?. 7.1.3 register nomenclature and values the summary and description tables also includ e register and field values. in general, a number is given by a string of digits followed by a single-character that identifies the base as decimal, ?d?, hexadecimal, ?h?, or bi nary, ?b?. both the digits and base pieces of a number are always case-insensitive 1 . that is, beefh and beefh represent the same hexadecimal number. a value of 0 (zero) does not require a base character. if a value is non-zero, the default base is assumed to be binary unless stated otherwise. all hexadecimal and decimal numbers must always have a base character. in addition to the legal digits for the base, the digit string can contain ?x? to denote undefined values. typically, xh is equivalent to xxxxb, xxh is equivalent to xxxxxxxxb. however, a 5-bit wide field that is undefined can be represented as both xxh and xxxxxb; that is, a nibble in a hex representation must be ?x? if any of its bits are ?x?. table 7-8. register field access attributes attribute description rv reserved ? a reserved field. ro read-only ? software/bios can only read this bit. contents are either hardwired or set by hardware. wo write-only ? not supported as a bit. the write causes a hardware event to take place. wrc write/read to clear ? writes and reads clear. see bit descriptions. rc read to clear ? cleared automatically when read. rw read/write ? software/bios can read and write this bit. rwc read/write-clear ? software/bios can read this bit and must write to a 1 to clear this bit. rcwc read-clear/write-clear ? cleared when read or write one to clear. rw0c read/write zero to clear ? software/bios can read this bit, and must write to a 0 to clear this bit. r0/w read zero/write ? this register will only read 0. must read register description for write actions. ro/rwc read only/read-write-clear ? attribute de pendent on configuration. see bit description rs/w1c read-set/write-clear ? read to set, write 1 to clear rws read/write-set ? software/bios can read this bit and write it to a 1. hardware clears this bit. rwl read/write-lock ? software/bios can read and write this bit. hardware or another configuration bit can lock this bit and prevent it from being updated. rwo read/write-once ? software/bios can read this bit, but can only write this bit once. it is a special form of rwl. once any byte within a register with rwo bits has been written, the rwo bits are locked and only a reset can clear its contents. any exceptions are clearly documented. 1. the ?suggested? convention is that digits are always upper case while the base is always lower case.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 190 order number: 320066-003us there are three special values that can be used in place of numbers to indicate cases where the value of a register or field is not fixed at design time and depends on other parameters: ? fuse: the setting of one or more fuses determines the value of the register or field. ? strap: the setting of a strap pin determines the value of the register or field. ? variable: the setting of other on-die state determines the value of the register or field. in these cases, the description of the register or field that is not fixed should contain additional information that describes how the ep80579 arrives at the value. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. 7.1.4 ?sticky? register fields for each field in a register, the description tables include an indication of whether or not the bits that make up the field are ?sticky? or not. sticky bits in registers will retain their value across a hard reset. resetting field in a register that is designated as ?sticky? to its default/reset value requires a cold reset. unless explicitly noted, all register fields are assumed to not be sticky. 7.2 ia-32 core registers the ia-32 core registers are described in the related documentation for the intel? pentium? m processor .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 191 intel ? ep80579 integrated processor 7.3 imch and iich registers this section summarizes the registers found in the imch and the iich. 7.3.1 imch registers: bus 0, device 0, function 0 the imch includes the registers listed in ta b l e 7 - 9 through ta b l e 7 - 1 1 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 16.1, ?imch registers: bus 0, device 0, function 0? , and section 16.7, ?memory mapped i/o for nsi registers? for detailed discussion of these registers. table 7-9. bus 0, device 0, function 0: summary of imch pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid ? vendor identification register? on page 391 8086h 02h 03h ?offset 02h: did ? device identification register? on page 391 5020h 04h 05h ?offset 04h: pcicmd: pci command register? on page 392 0006h 06h 07h ?offset 06h: pcists: pci status register? on page 393 0010h 08h 08h ?offset 8h: rid - revision identification register? on page 394 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 394 00h 0bh 0bh ?offset 0bh: bcc ? base class code register? on page 394 06h 0eh 0eh ?offset 0eh: hdr - header type register? on page 395 80h 14h 17h ?offset 14h: smrbase - system memory rcomp base address register? on page 396 00000000h 2ch 2dh ?offset 2ch: svid - subsystem vendor identification register? on page 396 0000h 2eh 2fh ?offset 2eh: sid - subsystem identification register? on page 397 0000h 4ch 4fh ?offset 4ch: nsibar - root complex block address register? on page 397 00000000h 50h 50h ?offset 50h: cfg0- imch configuration 0 register? on page 398 0ch 51h 51h ?offset 51h: imch_cfg1 ? imch configuration 1 register? on page 399 00000h 53h 53h ?offset 53h: cfgns1 - configuration 1 (non-sticky) register? on page 399 00h 58h 58h ?offset 58h: fdhc - fixed dram hole control register? on page 400 00h 59h 59h ?offset 59h: pam0 - programmable attribute map 0 register? on page 401 00h 5ah 5ah ?offset 5ah: pam1: programmable attribute map 1 register? on page 402 00h 5bh 5bh ?offset 5bh: pam2 - programmable attribute map 2 register? on page 403 00h 5ch 5ch ?offset 5ch: pam3 - programmable attribute map 3 register? on page 404 00h 5dh 5dh ?offset 5dh: pam4 - programmable attribute map 4 register? on page 405 00h 5eh 5eh ?offset 5eh: pam5 - programmable attribute map 5 register? on page 406 00h 5fh 5fh ?offset 5fh: pam6 - programmable attribute map 6 register? on page 407 00h 9ch 9ch ?offset 9ch: devpres - device present register? on page 408 33h 9dh 9dh ?offset 9dh: exsmrc - extended system management ram control register? on page 409 00h 9eh 9eh ?offset 9eh: smram - system management ram control register? on page 411 02h 9fh 9fh ?offset 9fh: exsmramc - expansion system management ram control register? on page 413 07h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 192 order number: 320066-003us b8h bbh ?offset b8h: imch_mencbase: ia/asu shared non-coherent (aioc-direct) memory base address register? on page 413 000fffffh bch bfh ?offset bch: imch_menclimit - ia/asu shared non-coherent (aioc-direct) memory limit address register? on page 414 00000000h c4h c5h ?offset c4h: tolm - top of low memory register? on page 415 0800h c6h c7h ?offset c6h: remapbase - remap base address register? on page 416 03ffh c8h c9h ?offset c8h: remaplimit ? remap limit address register? on page 416 0000h cah cbh ?offset cah: remapoffset - remap offset register? on page 417 0000h cch cdh ?offset cch: tom - top of memory register? on page 417 0000h ceh cfh ?offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register? on page 418 e000h d8h d8h ?offset d8h: cachectl0 - write cache control 0 register? on page 418 00h deh dfh ?offset deh: skpd - scratchpad data register? on page 419 0000h f6h f6h ?offset f6h: imch_tst2 - imch test byte 2 register? on page 419 00h 60h at 1h 60h at 1h ?offset 60h: drb[0-3] - dram row [3:0] boundary register? on page 421 ffh 70h at 4h 73h at 4h ?offset 70h: dra[0-1] - dram row [0:1] attribute register? on page 422 00000515h 78h 7bh ?offset 78h: drt0 - dram timing register 0? on page 424 242ad280h 64h 67h ?offset 64h: drt1 - dram timing register 1? on page 431 12110000h 7ch 7fh ?offset 7ch: drc - dram controller mode register? on page 435 00000002h 84h 87h ?offset 84h: eccdiag - ecc detection/correction diagnostic register? on page 437 00000000h 88h 8bh ?offset 88h: sdrc - ddr sdram secondary control register? on page 439 00000002h 8ch 8ch ?offset 8ch: ckdis - ck/ck# clock disable register? on page 441 00h 8dh 8dh ?offset 8dh: ckedis - cke clock enable register? on page 442 00h 90h 93h ?offset 90h: sparectl - spare control register? on page 443 00000000h b0h b3h ?offset b0h: ddr2odtc - ddr2 odt control register? on page 444 00000000h table 7-9. bus 0, device 0, function 0: summary of imch pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-10. bus 0, device 0, function 0: summary of imch configuration registers mapped through nsibar memory bar (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: snsivcech - nsi virtual channel enhanced capability header register? on page 680 04010002h 04h 07h ?offset 04h: nsipvccap1 - nsi port vc capability register 1? on page 680 00000000h 08h 0bh ?offset 08h: nsipvccap2 - port vc capability register 2? on page 681 00000001h 0ch 0dh ?offset 0ch: nsipvcctl - nsi port vc control register? on page 682 0000h 10h 13h ?offset 10h: nsivc0rcap - nsi vc0 resource capability register? on page 682 00000001h 14h 17h ?offset 14h: nsivc0rctl - nsi vc0 resource control register? on page 683 800000ffh 1ah 1bh ?offset 1ah: nsivc0rsts - nsi vc0 resource status register? on page 684 0002h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 193 intel ? ep80579 integrated processor 80h 83h ?offset 80h: nsircilcech - nsi root complex internal link control enhanced capability header register? on page 684 00010006h 84h 87h ?offset 84h: nsilcap - nsi link capabilities register? on page 685 0003a041h table 7-10. bus 0, device 0, function 0: summary of imch configuration registers mapped through nsibar memory bar (sheet 2 of 2) offset start offset end register id - description default value table 7-11. bus 0, device 0, function 0: summary of imch smrbase registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: notespad - note (sticky) pad for bios support register? on page 601 0000h 02h 03h ?offset 02h: notepad - note pad for bios support register? on page 601 0000h 40h 43h ?offset 40h: dcalcsr ? dcal control and status register? on page 602 00000000h 44h 47h ?offset 44h: dcaladdr - dcal address register? on page 606 00000000h 48h at 1h 48h at 1h ?offset 48h: dcaldata[0-71] - dram calibration data register? on page 607 00000000h 94h 96h ?offset 94h: rcvenac - receiver enable algorithm control register? on page 611 180810h 98h 9bh ?offset 98h: dsretc - dram self-refresh (sr) extended timing and control register? on page 611 5c141400h 9ch 9ch ?offset 9ch: dqsfail1 - dqs failure configuration register 1? on page 612 00h a0h a3h ?offset a0h: dqsfail0 - dqs failure configuration register 0? on page 613 00000000h a4h a7h ?offset a4h: drrtc00 - receive enable reference output timing control register? on page 615 06060606h a8h abh ?offset a8h: drrtc01 - receive enable reference output timing control register? on page 616 06060606h c4h c4h ?offset c4h: drrtc02 - receive enable reference output timing control register? on page 616 06h b4h b7h ?offset b4h: dqsofcs00 - dqs calibration register? on page 617 00000000h b8h bbh ?offset b8h: dqsofcs01 - dqs calibration register? on page 617 00000000h c6h c6h ?offset c6h: dqsofcs02 - dqs calibration register? on page 618 00h bch bfh ?offset bch: dqsofcs10 - dqs calibration register? on page 618 00000000h c0h c3h ?offset c0h: dqsofcs11 - dqs calibration register? on page 619 00000000h c7h c7h ?offset c7h: dqsofcs12 - dqs calibration register? on page 619 00h cch cfh ?offset cch: wptrtc0 - write pointer timing control register? on page 620 00000000h d0h d0h ?offset d0h: wptrtc1 - write pointer timing control 1 register? on page 621 00h d4h d7h ?offset d4h: ddqscvdp0 - dqs delay calibration victim pattern 0 register? on page 621 aaaa0a05h d8h dbh ?offset d8h: ddqscvdp1 - dqs delay calibration victim pattern 1 register? on page 622 5b339c5dh dch dfh ?offset dch: ddqscadp0 - dqs delay calibration aggressor pattern 0 register? on page 622 aaabffffh e0h e3h ?offset e0h: ddqscadp1 - dqs delay calibration aggressor pattern 1 register? on page 623 db339ce1h f0h f3h ?offset f0h: diomon - ddr i/o monitor register? on page 623 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 194 order number: 320066-003us f8h fbh ?offset f8h: dramisctl - miscellaneous dram ddr cluster control register? on page 624 1011h c8h cah ?offset c8h: dramdllc - ddr i/o dll control register? on page 625 0db6c0h e8h ebh ?offset e8h: fivesreg - fixed 5s pattern register? on page 625 55555555h ech efh ?offset ech: aaaareg - fixed a pattern register? on page 626 aaaaaaaah 140h 143h ?offset 140h: mbcsr - membist control register? on page 626 00000000h 144h 147h ?offset 144h: mbaddr - memory test address register? on page 629 00h 148h at 4h 14ch at 4h ?offset 148h: mbdata[0:9] - memory test data register? on page 629 00h 19ch 19fh ?offset 19ch: mb_start_addr - memory test start address register? on page 632 00h 1a0h 1a3h ?offset 1a0h: mb_end_addr - memory test end address register? on page 632 00h 1a4h 1a7h ?offset 1a4h: mblfsrsed - memory test circular shift and lfsr seed register? on page 633 00h 1a8h 1abh ?offset 1a8h: mbfaddrptr - memory test failure address pointer register? on page 633 00h 1b0h 1b3h ?offset 1b0h: mb_err_data00 - memory test error data 0? on page 634 00h 1b4h 1b7h ?offset 1b4h: mb_err_data01 - memory test error data 0? on page 634 00h 1b8h 1bbh ?offset 1b8h: mb_err_data02 - memory test error data 0? on page 634 00h 1bch 1bfh ?offset 1bch: mb_err_data03 - memory test error data 0? on page 635 00h 1c0h 1c1h ?offset 1c0h: mb_err_data04 - memory test error data 0? on page 635 00h 1c4h 1c7h ?offset 1c4h: mb_err_data10 - memory test error data 1? on page 635 00h 1c8h 1cbh ?offset 1c8h: mb_err_data11 - memory test error data 1? on page 636 00h 1cch 1cfh ?offset 1cch: mb_err_data12 - memory test error data 1? on page 636 00h 1d0h 1d3h ?offset 1d0h: mb_err_data13 - memory test error data 1? on page 636 00h 1d4h 1d5h ?offset 1d4h: mb_err_data14 - memory test error data 1? on page 637 00h 1d8h 1dbh ?offset 1d8h: mb_err_data20 - memory test error data 2? on page 637 00h 1dch 1dfh ?offset 1dch: mb_err_data21 - memory test error data 2? on page 637 00h 1e0h 1e3h ?offset 1e0h: mb_err_data22 - memory test error data 2? on page 638 00h 1e4h 1e7h ?offset 1e4h: mb_err_data23 - memory test error data 2? on page 638 00h 1e8h 1e9h ?offset 1e8h: mb_err_data24 - memory test error data 2? on page 638 00h 1ech 1efh ?offset 1ech: mb_err_data30 - memory test error data 3? on page 639 00h 1f0h 1f4h ?offset 1f0h: mb_err_data31 - memory test error data 3? on page 639 00h 1f4h 1f7h ?offset 1f4h: mb_err_data32 - memory test error data 3? on page 639 00h 1f8h 1fbh ?offset 1f8h: mb_err_data33 - memory test error data 3? on page 640 00h 1fch 1fdh ?offset 1fch: mb_err_data34 - memory test error data 3? on page 640 00h 260h 263h ?offset 260h: ddriomc0 - ddrio mode register control register? on page 641 00000078h 264h 267h ?offset 264h: ddriomc1 - ddrio mode register control register 1? on page 642 52520000h 268h 26bh ?offset 268h: ddriomc2 - ddrio mode control register 2? on page 645 039e6000h 284h at 4h 294h at 4h ?offset 284h: wl_cntl[4:0] - write levelization control register? on page 647 00000000h 298h 29bh ?offset 298h: wdll_misc - dll miscellaneous control? on page 649 00000000h table 7-11. bus 0, device 0, function 0: summary of imch smrbase registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 195 intel ? ep80579 integrated processor 7.3.2 imch error reporting registers: bus 0, device 0, function 1 the imch includes the registers listed in ta b l e 7 - 1 2 . these registers materialize in pci configuration space. see section 16.2, ?dram controller error reporting registers: bus 0, device 0, function 1? for detailed discussion of these registers. table 7-12. bus 0, device 0, function 1: summary of imch error reporting pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 447 8086h 02h 03h ?offset 02h: did - device identification register? on page 447 5021h 04h 05h ?offset 04h: pcicmd - pci command register? on page 448 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 448 0000h 08h 08h ?offset 08h: rid - revision identification register? on page 449 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 449 00h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 449 ffh 0dh 0dh ?offset 0dh: mlt - master latency timer register? on page 450 00h 0eh 0eh ?offset 0eh: hdr - header type register? on page 450 00h 2ch 2dh ?offset 2ch: svid - subsystem vendor identification register? on page 450 0000h 2eh 2fh ?offset 2eh: sid - subsystem identification register? on page 451 0000h 40h 43h ?offset 40h: global_ferr - global first error register? on page 451 00000000h 44h 47h ?offset 44h: global_nerr - global next error register? on page 453 00000000h 48h 4bh ?offset 48h: nsi_ferr - nsi first error register? on page 454 00000000h 4ch 4fh ?offset 4ch: nsi_nerr - nsi next error register? on page 457 00000000h 50h 53h ?offset 50h: nsi_scicmd - nsi sci command register? on page 459 00000000h 54h 57h ?offset 54h: nsi_smicmd: nsi smi command register? on page 461 00000000h 58h 5bh ?offset 58h: nsi_serrcmd - nsi serr command register? on page 464 00000000h 5ch 5fh ?offset 5ch: nsi_mcerrcmd - nsi mcerr command register? on page 466 00000000h 60h 61h ?offset 60h: fsb_ferr - fsb first error register? on page 468 0000h 62h 63h ?offset 62h: fsb_nerr - fsb next error register? on page 469 0000h 64h 65h ?offset 64h: fsb_emask - fsb error mask register? on page 470 0009h 68h 69h ?offset 68h: fsb_scicmd - fsb sci command register? on page 471 0000h 6ah 6bh ?offset 6ah: fsb_smicmd - fsb smi command register? on page 472 0000h 6ch 6dh ?offset 6ch: fsb_serrcmd - fsb serr command register? on page 473 0000h 6eh 6fh ?offset 6eh: fsb_mcerrcmd - fsb mcerr command register? on page 474 0000h 70h 70h ?offset 70h: buf_ferr - memory buffer first error register? on page 475 00h 72h 72h ?offset 72h: buf_nerr - memory buffer next error register? on page 475 00h 74h 74h ?offset 74h: buf_emask - memory buffer error mask register? on page 476 00h 78h 78h ?offset 78h: buf_scicmd - memory buffer sci command register? on page 477 00h 7ah 7ah ?offset 7ah: buf_smicmd - memory buffer smi command register? on page 478 00h 7ch 7ch ?offset 7ch: buf_serrcmd - memory buffer serr command register? on page 479 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 196 order number: 320066-003us 7eh 7eh ?offset 7eh: buf_mcerrcmd - memory buffer mcerr command register? on page 480 00h e4h e7h ?offset e4h: nsierrinjctl - nsi error injection control register? on page 481 00040000h e8h ebh ?offset e8h: berrinjctl - buffer error injection control register? on page 482 00000000h 80h 81h ?offset 80h: dram_ferr - dram first error register? on page 483 0000h 82h 83h ?offset 82h: dram_nerr - dram next error register? on page 484 0000h 84h 84h ?offset 84h: dram_emask - dram error mask register? on page 486 00h 88h 88h ?offset 88h: dram_scicmd - dram sci command register? on page 487 00h 8ah 8ah ?offset 8ah: dram_smicmd - dram smi command register? on page 488 00h 8ch 8ch ?offset 8ch: dram_serrcmd - dram serr command register? on page 489 00h 8eh 8eh ?offset 8eh: dram_mcerrcmd - dram mcerr command register? on page 490 00h 98h 99h ?offset 98h: thresh_sec0 - rank 0 sec error threshold register? on page 491 0000h 9ah 9bh ?offset 9ah: thresh_sec1 - rank 1 sec error threshold register? on page 491 0000h a0h a3h ?offset a0h: dram_secf_add - dram first single bit error correct address register? on page 492 00000000h a4h a7h ?offset a4h: dram_ded_add - dram double bit error address register? on page 492 00000000h a8h abh ?offset a8h: dram_scrb_add - dram scrub error address register? on page 493 00000000h b0h b1h ?offset b0h: dram_sec_r0 - dram rank 0 sec error counter register? on page 494 0000h b2h b3h ?offset b2h: dram_ded_r0 - dram rank 0 ded error counter register? on page 494 0000h b4h b5h ?offset b4h: dram_sec_r1 - dram rank 1 sec error counter register? on page 494 0000h b6h b7h ?offset b6h: dram_ded_r1 - dram rank 1 ded error counter register? on page 495 0000h c2h c3h ?offset c2h: thresh_ded - ded error threshold register? on page 495 0000h c4h c5h ?offset c4h: dram_secf_syndrome - dram first single error correct syndrome register? on page 496 0000h c6h c7h ?offset c6h: dram_secn_syndrome - dram next single error correct syndrome register? on page 496 0000h c8h cbh ?offset c8h: dram_secn_add - dram next single bit error correct address register? on page 497 00000000h dch ddh ?offset dch: rankthrex - rank error threshold exceeded register? on page 498 0000h ech efh ?offset ech: derrinjctl - dram error injection control register? on page 499 00000000h table 7-12. bus 0, device 0, function 1: summary of imch error reporting pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 197 intel ? ep80579 integrated processor 7.3.3 edma engine registers: bus 0, device 1, function 0 the edma engine includes the registers listed in ta b l e 7 - 1 3 and ta b l e 7 - 1 4 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 16.3, ?edma registers: bus 0, device 1, function 0? and section 16.6, ?memory mapped i/o for edma registers? for detailed discussion of these registers. table 7-13. bus 0, device 1, function 0: summary of edma pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 502 8086h 02h 03h ?offset 02h: did - device identification register? on page 502 5023h 04h 05h ?offset 04h: pcicmd - pci command register? on page 503 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 504 0010h 08h 08h ?offset 08h: rid - revision identification register? on page 504 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 505 80h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 505 08h 0eh 0eh ?offset 0eh: hdr - header type register? on page 505 00h 10h 13h ?offset 10h: edmalbar - edma low base address register? on page 506 00000000h 2ch 2dh ?offset 2ch: svid - subsystem vendor identification register? on page 506 0000h 2eh 2fh ?offset 2eh: sid - subsystem identification register? on page 507 0000h 34h 34h ?offset 34h: capptr - capabilities pointer register? on page 507 b0h 3ch 3ch ?offset 3ch: intrline - interrupt line register? on page 507 00h 3dh 3dh ?offset 3dh: intrpin - interrupt pin register? on page 508 01h 40h 40h ?offset 40h: edmactl - edma control register? on page 508 08h 80h 83h ?offset 80h: edma_ferr - edma first error register? on page 509 00000000h 84h 87h ?offset 84h: edma_nerr - edma next error register? on page 511 00000000h 88h 88h ?offset 88h: edma_emask - edma error mask register? on page 513 00h a0h a0h ?offset a0h: edma_scicmd - edma sci command register? on page 514 00h a4h a4h ?offset a4h: edma_smicmd - edma smi command register? on page 515 00h a8h a8h ?offset a8h: edma_serrcmd - edma serr command register? on page 516 00h ach ach ?offset ach: edma_mcerrcmd - edma mcerr command register? on page 517 00h b0h b3h ?offset b0h: msicr - msi control register? on page 518 00020005h b4h b7h ?offset b4h: msiar - msi address register? on page 519 fee00000h b8h b9h ?offset b8h: msidr - msi data register? on page 520 0000h table 7-14. bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar (sheet 1 of 3) offset start offset end register id - description default value 00h 03h ?offset 00h: ccr0 - channel 0 channel control register? on page 653 00000000h 04h 07h ?offset 04h: csr0 - channel 0 channel status register? on page 656 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 198 order number: 320066-003us 08h 0bh ?offset 08h: cdar0 - channel 0 current descriptor address register? on page 657 00000000h 0ch 0fh ?offset 0ch: cduar0 - channel 0 current descriptor upper address register? on page 658 00000000h 10h 13h ?offset 10h: sar0 - channel 0 source address register? on page 658 00000000h 14h 17h ?offset 14h: suar0 - channel 0 source upper address register? on page 659 00000000h 18h 1bh ?offset 18h: dar0 - channel 0 destination address register? on page 659 00000000h 1ch 1fh ?offset 1ch: duar0 - channel 0 destination upper address register? on page 660 00000000h 20h 23h ?offset 20h: ndar0 - channel 0 next descriptor address register? on page 661 00000000h 24h 27h ?offset 24h: nduar0 - channel 0 next descriptor upper address register? on page 662 00000000h 28h 2bh ?offset 28h: tcr0 - channel 0 transfer count register? on page 662 00000000h 2ch 2fh ?offset 2ch: dcr0 - channel 0 descriptor control register? on page 663 00000000h 40h 43h ?offset 40h: ccr1 - channel 1 channel control register? on page 665 00000000h 44h 47h ?offset 44h: csr1 - channel 1 channel status register? on page 665 00000000h 48h 4bh ?offset 48h: cdar1 - channel 1 current descriptor address register? on page 665 00000000h 4ch 4fh ?offset 4ch: cduar1 - channel 1 current descriptor upper address register? on page 666 00000000h 50h 53h ?offset 50h: sar1 - channel 1 source address register? on page 666 00000000h 54h 57h ?offset 54h: suar1 - channel 1 source upper address register? on page 666 00000000h 58h 5bh ?offset 58h: dar1 - channel 1 destination address register? on page 667 00000000h 5ch 5fh ?offset 5ch: duar1 - channel 1 destination upper address register? on page 667 00000000h 60h 63h ?offset 60h: ndar1 - channel 1 next descriptor address register? on page 667 00000000h 64h 67h ?offset 64h: nduar1 - channel 1 next descriptor upper address register? on page 668 00000000h 68h 6bh ?offset 68h: tcr1 - channel 1 transfer count register? on page 668 00000000h 6ch 6fh ?offset 6ch: dcr1 - channel 1 descriptor control register? on page 668 00000000h 80h 83h ?offset 80h: ccr2 - channel 2 channel control register? on page 669 00000000h 84h 87h ?offset 84h: csr2 - channel 2 channel status register? on page 669 00000000h 88h 8bh ?offset 88h: cdar2: channel 2 current descriptor address register? on page 669 00000000h 8ch 8fh ?offset 8ch: cduar2 - channel 2 current descriptor upper address register? on page 670 00000000h 90h 93h ?offset 90h: sar2 - channel 2 source address register? on page 670 00000000h 94h 97h ?offset 94h: suar2 - channel 2 source upper address register? on page 670 00000000h 98h 9bh ?offset 98h: dar2 - channel 2 destination address register? on page 671 00000000h 9ch 9fh ?offset 9ch: duar2 - channel 2 destination upper address register? on page 671 00000000h a0h a3h ?offset a0h: ndar2 - channel 2 next descriptor address register? on page 671 00000000h a4h a7h ?offset a4h: nduar2 - channel 2 next descriptor upper address register? on page 672 00000000h a8h abh ?offset a8h: dcr2 - channel 2transfer control register? on page 672 00000000h ach afh ?offset ach: dcr2 - channel 2 descriptor control register? on page 672 00000000h c0h c3h ?offset c0h: ccr3 - channel 3 channel control register? on page 673 00000000h c4h c7h ?offset c4h: csr3 - channel 3 channel status register? on page 673 00000000h table 7-14. bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar (sheet 2 of 3) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 199 intel ? ep80579 integrated processor c8h cbh ?offset c8h: cdar3 - channel 3 current descriptor address register? on page 673 00000000h cch cfh ?offset cch: cduar3 - channel 3 current descriptor upper address register? on page 674 00000000h d0h d3h ?offset d0h: sar3 - channel 3 source address register? on page 674 00000000h d4h d7h ?offset d4h: suar3 - channel 3 source upper address register? on page 674 00000000h d8h dbh ?offset d8h: dar3 - channel 3 destination address register? on page 675 00000000h dch dfh ?offset dch: duar3 - channel 3 destination upper address register? on page 675 00000000h e0h e3h ?offset e0h: ndar3 - channel 3 next descriptor address register? on page 675 00000000h e4h e7h ?offset e4h: nduar3 - channel 3 next descriptor upper address register? on page 676 00000000h e8h ebh ?offset e8h: tcr3 - channel 3 transfer count register? on page 676 00000000h ech efh ?offset ech: dcr3 - channel 3 descriptor control register? on page 677 00000000h 100h 103h ?offset 100h: dcgc - edma controller global command? on page 677 00000000h 104h 107h ?offset 104h: dcgs - edma controller global status? on page 678 00000000h table 7-14. bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar (sheet 3 of 3) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 200 order number: 320066-003us 7.3.4 pci express* port a registers: bus 0, device 2, function 0 the pci express* port a includes the registers listed in ta b l e 7 - 1 5 . these registers materialize in pci configuration spaces. see section 16.4, ?pci express* port a standard and enhanced registers: bus 0, devices 2 and 3, function 0? for detailed discussion of these registers. table 7-15. bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers (sheet 1 of 3) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 527 8086h 02h 03h ?offset 02h: did - device identification register? on page 527 5024h 04h 05h ?offset 04h: pcicmd - pci command register? on page 528 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 530 0010h 08h 08h ?offset 08h: rid - revision identification register? on page 531 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 532 04h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 532 06h 0ch 0ch ?offset 0ch: cls - cache line size register? on page 533 00h 0eh 0eh ?offset 0eh: hdr - header type register? on page 533 01h 18h 18h ?offset 18h: pbusn - primary bus number register? on page 534 00h 19h 19h ?offset 19h: sbusn - secondary bus number register? on page 534 00h 1ah 1ah ?offset 1ah: subusn: subordinate bus number register? on page 535 00h 1ch 1ch ?offset 1ch: iobase - i/o base address register? on page 535 f0h 1dh 1dh ?offset 1dh: iolimit - i/o limit address register? on page 536 00h 1eh 1fh ?offset 1eh: secsts - secondary status register? on page 536 0000h 20h 21h ?offset 20h: mbase - memory base address register? on page 538 fff0h 22h 23h ?offset 22h: mlimit - memory limit address register? on page 539 0000h 24h 25h ?offset 24h: pmbase - prefetchable memory base address register? on page 540 fff1h 26h 27h ?offset 26h: pmlimit - prefetchable memory limit address register? on page 540 0001h 28h 28h ?offset 28h: pmbasu - prefetchable memory base upper address register? on page 541 0fh 2ch 2ch ?offset 2ch: pmlmtu - prefetchable memory limit upper address register? on page 541 00h 34h 34h ?offset 34h: capptr - capabilities pointer register? on page 542 50h 3ch 3ch ?offset 3ch: intrline - interrupt line register? on page 542 00h 3dh 3dh ?offset 3dh: intrpin - interrupt pin register? on page 543 01h 3eh 3eh ?offset 3eh: bctrl - bridge control register? on page 543 00h 44h 44h ?offset 44h: vscmd0 - vendor specific command byte 0 register? on page 545 00h 45h 45h ?offset 45h: vscmd1 - vendor specific command byte 1 register? on page 546 00h 46h 46h ?offset 46h: vssts0 - vendor specific status byte 0 register? on page 547 00h 47h 47h ?offset 47h: vssts1 - vendor specific status byte 1 register? on page 547 00h 48h 48h ?offset 48h: vscmd2 - vendor specific command byte 2 register? on page 548 00h 50h 50h ?offset 50h: pmcapid - power management capabilities structure register? on page 548 01h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 201 intel ? ep80579 integrated processor 51h 51h ?offset 51h: pmnptr - power management next capabilities pointer register? on page 549 58h 52h 53h ?offset 52h: pmcapa - power management capabilities register? on page 549 c822h 54h 55h ?offset 54h: pmcsr - power management status and control register? on page 550 0000h 56h 56h ?offset 56h: pmcsrbse - power management status and control bridge extensions register? on page 551 00h 58h 58h ?offset 58h: msicapid - msi capabilities structure register? on page 551 05h 59h 59h ?offset 59h: msinptr - msi next capabilities pointer register? on page 552 64h 5ah 5bh ?offset 5ah: msicapa - msi capabilities register? on page 553 0002h 5ch 5fh ?offset 5ch: msiar - msi address for pci express register? on page 553 fee00000h 60h 61h ?offset 60h: msidr - msi data register? on page 554 0000h 64h 64h ?offset 64h: peacapid - pci express features capabilities id register? on page 555 10h 65h 65h ?offset 65h: peanptr - pci express next capabilities pointer register? on page 556 00h 66h 67h ?offset 66h: peacapa - pci express features capabilities register? on page 556 0041h 68h 6bh ?offset 68h: peadevcap - pci express device capabilities register? on page 557 00000001h 6ch 6dh ?offset 6ch: peadevctl - pci express device control register? on page 558 0000h 6eh 6fh ?offset 6eh: peadevsts - pci express device status register? on page 560 0000h 70h 73h ?offset 70h: pealnkcap - pci express link capabilities register? on page 561 0203e481h 74h 75h ?offset 74h: pealnkctl - pci express link control register? on page 562 0001h 76h 77h ?offset 76h: pealnksts - pci express link status register? on page 564 1001h 78h 7bh ?offset 78h: peasltcap - pci express slot capabilities register? on page 565 00000000h 7ch 7dh ?offset 7ch: peasltctl - pci express slot control register? on page 568 01c0h 7eh 7fh ?offset 7eh: peasltsts - pci express slot status register? on page 569 0040h 80h 83h ?offset 80h: pearpctl - pci express root port control register? on page 570 00000000h 84h 87h ?offset 84h: pearpsts - pci express root port status register? on page 571 00000000h 100h 103h ?offset 100h: enhcapst - enhanced capability structure register? on page 571 00010001h 104h 107h ?offset 104h: uncerrsts - uncorrectable error status register? on page 572 00000000h 108h 10bh ?offset 108h: uncerrmsk - uncorrectable error mask register? on page 574 00000000h 10ch 10fh ?offset 10ch: uncerrsev - uncorrectable error severity register? on page 575 00062010h 110h 113h ?offset 110h: corerrsts - correctable error status register? on page 576 00000000h 114h 117h ?offset 114h: corerrmsk - correctable error mask register? on page 578 00000000h 118h 11bh ?offset 118h: aercacr - advanced error capabilities and control register? on page 579 00000000h 11ch 11fh ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? on page 580 00000000h 120h 123h ?offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register? on page 580 00000000h 124h 127h ?offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register? on page 581 00000000h 128h 12bh ?offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register? on page 581 00000000h 12ch 12fh ?offset 12ch: rperrcmd - root (port) error command register? on page 582 00000000h table 7-15. bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers (sheet 2 of 3) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 202 order number: 320066-003us 130h 133h ?offset 130h: rperrmsts - root (port) error message status register? on page 583 00000000h 134h 137h ?offset 134h: errsid - error source id register? on page 585 00000000h 140h 143h ?offset 140h: peauniterr - pci express unit error register? on page 586 00000000h 144h 147h ?offset 144h: peamaskerr - pci express unit mask error register? on page 588 0000e000h 148h 14bh ?offset 148h: peaerrdocmd - pci express error do command register? on page 589 00000000h 14ch 14fh ?offset 14ch: uncedmask - uncorrectable error detect mask register? on page 591 00000000h 150h 153h ?offset 150h: coredmask - correctable error detect mask register? on page 592 00000000h 158h 15bh ?offset 158h: peaunitedmask - pci express unit error detect mask register? on page 594 00000000h 160h 163h ?offset 160h: peaferr - pci express first error register? on page 595 00000000h 164h 167h ?offset 164h: peanerr - pci express next error register? on page 597 00000000h 168h 16bh ?offset 168h: peaerrinjctl - error injection control register? on page 597 00000000h table 7-15. bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers (sheet 3 of 3) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 203 intel ? ep80579 integrated processor 7.3.5 pci express* port a1 registers: bus 0, device 3, function 0 the pci express* port a1 includes the registers listed in ta bl e 7 - 1 6 . these registers materialize in pci configuration space. see section 16.4, ?pci express* port a standard and enhanced registers: bus 0, devices 2 and 3, function 0? for detailed discussion of these registers. table 7-16. bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers (sheet 1 of 3) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 527 8086h 02h 03h ?offset 02h: did - device identification register? on page 528 5025h 04h 05h ?offset 04h: pcicmd - pci command register? on page 528 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 530 0010h 08h 08h ?offset 08h: rid - revision identification register? on page 531 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 532 04h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 532 06h 0ch 0ch ?offset 0ch: cls - cache line size register? on page 533 00h 0eh 0eh ?offset 0eh: hdr - header type register? on page 533 01h 18h 18h ?offset 18h: pbusn - primary bus number register? on page 534 00h 19h 19h ?offset 19h: sbusn - secondary bus number register? on page 534 00h 1ah 1ah ?offset 1ah: subusn: subordinate bus number register? on page 535 00h 1ch 1ch ?offset 1ch: iobase - i/o base address register? on page 535 f0h 1dh 1dh ?offset 1dh: iolimit - i/o limit address register? on page 536 00h 1eh 1fh ?offset 1eh: secsts - secondary status register? on page 536 0000h 20h 21h ?offset 20h: mbase - memory base address register? on page 538 fff0h 22h 23h ?offset 22h: mlimit - memory limit address register? on page 539 0000h 24h 25h ?offset 24h: pmbase - prefetchable memory base address register? on page 540 fff1h 26h 27h ?offset 26h: pmlimit - prefetchable memory limit address register? on page 540 0001h 28h 28h ?offset 28h: pmbasu - prefetchable memory base upper address register? on page 541 0fh 2ch 2ch ?offset 2ch: pmlmtu - prefetchable memory limit upper address register? on page 541 00h 34h 34h ?offset 34h: capptr - capabilities pointer register? on page 542 50h 3ch 3ch ?offset 3ch: intrline - interrupt line register? on page 542 00h 3dh 3dh ?offset 3dh: intrpin - interrupt pin register? on page 543 01h 3eh 3eh ?offset 3eh: bctrl - bridge control register? on page 543 00h 44h 44h ?offset 44h: vscmd0 - vendor specific command byte 0 register? on page 545 00h 45h 45h ?offset 45h: vscmd1 - vendor specific command byte 1 register? on page 546 00h 46h 46h ?offset 46h: vssts0 - vendor specific status byte 0 register? on page 547 00h 47h 47h ?offset 47h: vssts1 - vendor specific status byte 1 register? on page 547 00h 48h 48h ?offset 48h: vscmd2 - vendor specific command byte 2 register? on page 548 00h 50h 50h ?offset 50h: pmcapid - power management capabilities structure register? on page 548 01h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 204 order number: 320066-003us 51h 51h ?offset 51h: pmnptr - power management next capabilities pointer register? on page 549 58h 52h 53h ?offset 52h: pmcapa - power management capabilities register? on page 549 c822h 54h 55h ?offset 54h: pmcsr - power management status and control register? on page 550 0000h 56h 56h ?offset 56h: pmcsrbse - power management status and control bridge extensions register? on page 551 00h 58h 58h ?offset 58h: msicapid - msi capabilities structure register? on page 551 05h 59h 59h ?offset 59h: msinptr - msi next capa bilities pointer register? on page 552 64h 5ah 5bh ?offset 5ah: msicapa - msi capabilities register? on page 553 0002h 5ch 5fh ?offset 5ch: msiar - msi address for pci express register? on page 553 fee00000h 60h 61h ?offset 60h: msidr - msi data register? on page 554 0000h 64h 64h ?offset 64h: peacapid - pci express features capabilities id register? on page 555 10h 65h 65h ?offset 65h: peanptr - pci express next capabilities pointer register? on page 556 00h 66h 67h ?offset 66h: peacapa - pci express features capabilities register? on page 556 0041h 68h 6bh ?offset 68h: peadevcap - pci express device capabilities register? on page 557 00000001h 6ch 6dh ?offset 6ch: peadevctl - pci express device control register? on page 558 0000h 6eh 6fh ?offset 6eh: peadevsts - pci express device status register? on page 560 0000h 70h 73h ?offset 70h: pea1lnkcap - pci express link capabilities register? on page 561 0303e441h 74h 75h ?offset 74h: pealnkctl - pci express link control register? on page 562 0001h 76h 77h ?offset 76h: pealnksts - pci express link status register? on page 564 1001h 78h 7bh ?offset 78h: pea1sltcap - pci express slot capabilities register? on page 566 00000000h 7ch 7dh ?offset 7ch: peasltctl - pci express slot control register? on page 568 01c0h 7eh 7fh ?offset 7eh: peasltsts - pci express slot status register? on page 569 0040h 80h 83h ?offset 80h: pearpctl - pci express root port control register? on page 570 00000000h 84h 87h ?offset 84h: pearpsts - pci express root port status register? on page 571 00000000h 100h 103h ?offset 100h: enhcapst - enhanced capability structure register? on page 571 00010001h 104h 107h ?offset 104h: uncerrsts - uncorrectable error status register? on page 572 00000000h 108h 10bh ?offset 108h: uncerrmsk - uncorrectable error mask register? on page 574 00000000h 10ch 10fh ?offset 10ch: uncerrsev - uncorrectable error severity register? on page 575 00062010h 110h 113h ?offset 110h: corerrsts - correctable error status register? on page 576 00000000h 114h 117h ?offset 114h: corerrmsk - correctable error mask register? on page 578 00000000h 118h 11bh ?offset 118h: aercacr - advanced error capabilities and control register? on page 579 00000000h 11ch 11fh ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? on page 580 00000000h 120h 123h ?offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register? on page 580 00000000h 124h 127h ?offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register? on page 581 00000000h 128h 12bh ?offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register? on page 581 00000000h 12ch 12fh ?offset 12ch: rperrcmd - root (port) error command register? on page 582 00000000h table 7-16. bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers (sheet 2 of 3) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 205 intel ? ep80579 integrated processor 130h 133h ?offset 130h: rperrmsts - root (port) error message status register? on page 583 00000000h 134h 137h ?offset 134h: errsid - error source id register? on page 585 00000000h 140h 143h ?offset 140h: peauniterr - pci express unit error register? on page 586 00000000h 144h 147h ?offset 144h: peamaskerr - pci express unit mask error register? on page 588 0000e000h 148h 14bh ?offset 148h: peaerrdocmd - pci express error do command register? on page 589 00000000h 14ch 14fh ?offset 14ch: uncedmask - uncorrectable error detect mask register? on page 591 00000000h 150h 153h ?offset 150h: coredmask - correctable error detect mask register? on page 592 00000000h 158h 15bh ?offset 158h: peaunitedmask - pci express unit error detect mask register? on page 594 00000000h 160h 163h ?offset 160h: peaferr - pci express first error register? on page 595 00000000h 164h 167h ?offset 164h: peanerr - pci express next error register? on page 597 00000000h 168h 16bh ?offset 168h: peaerrinjctl - error injection control register? on page 597 00000000h table 7-16. bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers (sheet 3 of 3) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 206 order number: 320066-003us 7.3.6 usb (1.1) controller: bus 0, device 29, functions 0 the usb 1.1 controller includes the registers listed in ta b l e 7 - 1 7 and ta b l e 7 - 1 8 . these registers materialize in pci configuration and i/o spaces (via pci i/o bar), respectively. see chapter 25.0, ?usb (1.1) controller: bus 0, device 29, function 0? for detailed discussion of these registers. table 7-17. bus 0, device 29, functions 0, summary of usb (1.1) controller pci configuration registers offset start offset end register id - description default value 00h 03h ?id - identifiers register? on page 942 50338086h 04h 05h ?pcicmd - command register? on page 942 0000h 06h 07h ?pcists - device status register? on page 943 0280h 08h 08h ?rid - revision id register? on page 944 variable 0ah 0ah ?subc - sub class code register? on page 945 03h 0bh 0bh ?bcc - base class code register? on page 945 0ch 0dh 0dh ?mlt - master latency timer register? on page 945 00h 0eh 0eh ?hdr - header type register? on page 946 variable 20h 23h ?usbiobar - base address register? on page 946 00000001h 2ch 2dh ?usbx_svid - usb subsystem vendor id register? on page 947 0000h 2eh 2fh ?usbx_sid - usb subsystem id register? on page 947 0000h 3ch 3ch ?intl - interrupt line register? on page 948 00h 3dh 3dh ?intp - interrupt pin register? on page 948 variable 60h 60h ?sbrn - serial bus release number register? on page 948 10h c0h c1h ?usblkmcr - usb legacy keyboard/mouse control register? on page 949 2000h c4h c4h ?usbren - usb resume enable register? on page 951 00h c8h c8h ?usbcwp - usb core well policy register? on page 951 00h f8h fbh ?manid - manufacturer id register? on page 952 00010f90h table 7-18. summary of usb (1.1) controller configuration registers mapped through usbiobar i/o bar offset start offset end register id - description default value 00h 01h ?usbcmd: usb command register? on page 954 0000h 02h 03h ?usbsts: usb status register? on page 957 0020h 04h 05h ?usbintr: usb interrupt enable register? on page 959 0000h 06h 07h ?frnum: frame number register? on page 959 0000h 08h 0bh ?frbaseadd: frame list base address register? on page 960 xxxxx000h 0ch 0ch ?sofmod: start of frame modify register? on page 961 40h 10h 11h ?pscr - port status and control register? on page 962 0080h 12h 13h ?pscr - port status and control register? on page 962 0080h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 207 intel ? ep80579 integrated processor 7.3.7 usb (2.0) controller: bus 0, device 29, function 7 the usb 2.0 controller includes the registers listed in ta bl e 7 - 1 9 and ta b l e 7 - 2 0 . these registers materialize in pci configuration and i/o spaces (via pci i/o bar), respectively. see chapter 26.0, ?usb 2.0 pci configuration registers? for detailed discussion of these registers. table 7-19. bus 0, device 29, function 7: summary of usb (2.0) controller pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor id register? on page 979 8086h 02h 03h ?offset 02h: did - device identification register? on page 979 5035h 04h 05h ?offset 04h: cmd - command register? on page 980 0000h 06h 07h ?offset 06h: dsr - device status register? on page 981 0290h 08h 08h ?offset 08h: rid - revision id register? on page 983 variable 09h 09h ?offset 09h: pi - programming interface register? on page 983 20h 0ah 0ah ?offset 0ah: scc - sub class code register? on page 983 03h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 984 0ch 0dh 0dh ?offset 0dh: mlt - master latency timer register? on page 984 00h 10h 13h ?offset 10h: mbar - memory base address register? on page 985 00000000h 2ch 2dh ?offset 2ch: ssvid - usb 2.0 subsystem vendor id register? on page 985 xxxxh 2eh 2fh ?offset 2eh: ssid - usb 2.0 subsystem id register? on page 986 xxxxh 34h 34h ?offset 34h: cap_ptr - capabilities pointer register? on page 986 50h 3ch 3ch ?offset 3ch: iline - interrupt line register? on page 987 00h 3dh 3dh ?offset 3dh: ipin - interrupt pin register? on page 987 variable 50h 50h ?offset 50h: pm_cid - pci power management capability id register? on page 987 01h 51h 51h ?offset 51h: pm_next - next item pointer #1 register? on page 988 58h 52h 53h ?offset 52h: pm_cap - power management capabilities register? on page 989 c9c2h 54h 55h ?offset 54h: pm_cs - power management control/status register? on page 990 0000h 58h 58h ?offset 58h: dp_cid - debug port capability id register? on page 991 0ah 59h 59h ?offset 59h: dp_next - next item pointer #2 register? on page 991 00h 5ah 5bh ?offset 5ah: dp_base - debug port base offset register? on page 991 20a0h 60h 60h ?offset 60h: sbrn - serial bus release number register? on page 992 20h 61h 61h ?offset 61h: fla - frame length adjustment register? on page 992 20h 62h 63h ?offset 62h: pwc - port wake capability register? on page 993 01ffh 64h 65h ?offset 64h: cuo - classic usb override register? on page 994 0000h 68h 6bh ?offset 68h: ulsec - usb 2.0 legacy support extended capability register? on page 994 00000001h 6ch 6fh ?offset 6ch: ulscs - usb 2.0 legacy support control/status register? on page 995 00000000h 70h 73h ?offset 70h: isu2smi - intel specific usb 2.0 smi register? on page 997 00000000h 80h 80h ?offset 80h: ac - access control register? on page 999 00h f8h fbh ?offset f8h: manid - manufacturer id register? on page 1000 00010f90h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 208 order number: 320066-003us table 7-20. bus 0, device 29, function 7: summary of usb (2.0) controller configuration registers mapped through mbar memory bar offset start offset end register id - description default value 00h 00h ?offset 00h: caplength - capability length register? on page 1002 20h 02h 03h ?offset 02h: hciversion - host controller interface version number register? on page 1003 0100h 04h 07h ?offset 04h: hcsparams - host controller structural parameters register? on page 1003 01001202h 08h 0bh ?offset 08h: hccparams - host controller capability parameters register? on page 1004 00006871h 20h 23h ?offset 20h: usb2cmd - usb 2.0 command register? on page 1007 00080000h 24h 27h ?offset 24h: usb2sts - usb 2.0 status register? on page 1009 00001000h 28h 2bh ?offset 28h: usb2intr - usb 2.0 interrupt enable register? on page 1012 00000000h 2ch 2fh ?offset 2ch: frindex - frame index register? on page 1013 00000000h 30h 33h ?offset 30h: ctrldssegment - control data structure segment register? on page 1014 00000000h 34h 37h ?offset 34h: periodiclistbase - periodic frame list base address register? on page 1014 00000xxxh 38h 3bh ?offset 38h: asynclistaddr - current asynchronous list address register? on page 1015 00000000h 60h 63h ?offset 60h: configflag - configure flag register? on page 1015 00000000h 64h 67h ?offset 64h: portsc - port n status and control register? on page 1016 00003000h 68h 6bh ?offset 64h: portsc - port n status and control register? on page 1016 00003000h a0h a3h ?offset a0h: cntl_sts - control/status register? on page 1037 00000000h a4h a4h ?offset a4h: usbpid - usb pids register? on page 1039 00000000h a8h afh ?offset a8h: databuf - data buffer bytes 7:0? on page 1039 00000000000 00000h b0h b0h ?offset b0h: config - configuration register? on page 1040 00007f01h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 209 intel ? ep80579 integrated processor 7.3.8 root complex: bus 0, device 31, function 0 the root complex includes the registers listed in ta bl e 7 - 2 1 . these registers materialize in memory space (via pci memory bar), respectively. see chapter 17.0, ?bridging and configuration? for detailed discussion of these registers. table 7-21. bus 0, device 31, function 0: summary of root complex configuration registers mapped through rcba memory bar offset start offset end register id - description default value 0000h 0003h ?offset 0000h: vch - virtual channel capability header register? on page 691 10010002h 0004h 0007h ?offset 0004h: vcap1 - virtual channel capability 1 register? on page 691 0801h 0008h 000bh ?offset 0008h: vcap2 - virtual channel capability 2 register? on page 692 0001h 000ch 000dh ?offset 000ch: pvc - port virtual channel control register? on page 692 0h 000eh 000fh ?offset 000eh: pvs -port virtual channel status register? on page 693 0h 0010h 0013h ?offset 0010h: v0cap - virtual channel 0 resource capability register? on page 693 00000001h 0014h 0017h ?offset 0014h: v0ctl - virtual channel 0 resource control register? on page 694 800000ffh 001ah 001bh ?offset 001ah: v0sts - virtual channel 0 resource status register? on page 695 0h 0100h 0103h ?offset 0100h: rctcl - root complex topology capabilities list register? on page 696 1a010005h 0104h 0107h ?offset 0104h: esd - element self description register? on page 696 00000102h 0110h 0113h ?offset 0110h: uld - upstream link description register? on page 697 0001h 0118h 011fh ?offset 0118h: ulba - upstream link base address register? on page 697 00000000000 00000h 01a0h 01a3h ?offset 01a0h: ilcl - internal link capabilities list register? on page 698 00010006h 01a4h 01a7h ?offset 01a4h: lcap - link capabilities register? on page 698 0012441h 01a8h 01a9h ?offset 01a8h: lctl - link control register? on page 699 0h 01aah 01abh ?offset 01aah: lsts - link status register? on page 700 0041h 3108h 310bh ?offset 3108h: d29ip - device 29 interrupt pin register? on page 702 10004321h 3140h 3141h ?offset 3140h: d31ir - device 31 interrupt route register? on page 702 3210h 3144h 3145h ?offset 3144h: d29ir - device 29 interrupt route register? on page 703 3210h 31ffh 31ffh ?offset 31ffh: oic - other interrupt control register? on page 704 0h 3400h 3403h ?offset 3400h: rc - rtc configuration register? on page 704 0h 3404h 3407h ?offset 3404h: hptc - high performance precision timer configuration register? on page 705 0h 3410h 3413h ?offset 3410h: gcs - general control and status register? on page 706 variable 3414h 3417h ?offset 3414h: buc - backed up control register? on page 708 variable 3418h 341bh ?offset 3418h: fd - function disable register? on page 709 00000080h 341ch 341fh ?offset 341ch: prc - power reduction control register clock gating? on page 711 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 210 order number: 320066-003us 7.3.9 lpc interface: bus 0, device 31, function 0 the lpc interface includes the registers listed in ta bl e 7 - 2 2 through ta bl e 7 - 2 6 . these registers materialize in pci configuration and i/o spaces (via pci i/o bar). see chapter 19.0, ?lpc interface: bus 0, device 31, function 0? , chapter 27.0, ?power management? , chapter 18.0, ?system management? , and chapter 22.0, ?general purpose i/o: bus 0, device 31, function 0? for detailed discussion of these registers. table 7-22. bus 0, device 31, function 0: summary of lpc interface pci configuration registers offset start offset end register id - description default value 00h 03h ?offset 00h: id: vendor identification register? on page 734 50318086h 04h 05h ?offset 04h: cmd: device command register? on page 735 0007h 06h 07h ?offset 06h: sts: status register? on page 736 0200h 08h 08h ?offset 08h: rid: revision id register? on page 737 variable 09h 0bh ?offset 09h: cc: class code register? on page 737 060100h 0dh 0dh ?offset 0dh: mlt: master latency timer register? on page 737 00h 0eh 0eh ?offset 0eh: htype: header type register? on page 738 80h 2ch 2fh ?offset 2ch: sid: subsystem identifiers register? on page 738 00000000h 40h 43h ?offset 40h: abase: acpi base address register? on page 739 00000001h 44h 47h ?offset 44h: actl: acpi control register? on page 739 00h 48h 48h ?offset 48h: gba: gpio base address register? on page 740 00000001h 4ch 4ch ?offset 4ch: gc: gpio control register? on page 741 00h 60h 60h ?offset 60h: parc: pirqa routing control register? on page 741 80h 61h 61h ?offset 61h: pbrc: pirqb routing control register? on page 742 80h 62h 62h ?offset 62h: pcrc: pirqc routing control register? on page 742 80h 63h 63h ?offset 63h: pdrc: pirqdq routing control register? on page 743 80h 64h 64h ?offset 64h: scnt: serial irq control register? on page 744 10h 68h 68h ?offset 68h: perc: pirqeq routing control register? on page 745 80h 69h 69h ?offset 69h: pfrc: pirqf routing control register? on page 745 80h 6ah 6ah ?offset 6ah: pgrc: pirqg routing control register? on page 746 80h 6bh 6bh ?offset 6bh: phrc: pirqh routing control register? on page 747 80h 80h 81h ?offset 80h: iod: i/o decode ranges register? on page 747 0000h 82h 83h ?offset 82h: ioe: i/o enables register? on page 749 0000h 84h 85h ?offset 84h: lg1: lpc generic decode range 1 register? on page 750 0000h 88h 88h ?offset 88h: lg2: lpc generic decode range 2 register? on page 751 0000h d0h d3h ?offset d0h: fs1: fwh id select 1 register? on page 752 00112233h d4h d5h ?offset d4h: fs2: fwh id select 2 register? on page 753 4567h d8h dbh ?offset d8h: fde: fwh decode enable register? on page 754 ffcfh dch dch ?offset dch: bc: bios control register? on page 756 00h f0h f3h ?offset f0h: rcba: root complex base address register? on page 757 00000000h f8h fbh ?offset f8h: manid: manufacturer id register? on page 757 00010f90h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 211 intel ? ep80579 integrated processor table 7-23. bus 0, device 31, function 0: summary of lpc interface power management pci configuration registers offset start offset end register id - description default value a0h a0h ?offset a0h: gen_pmcon_1 - general pm configuration 1 register? on page 1048 0200h a2h a2h ?offset a2h: gen_pmcon_2 - general pm configuration 2 register? on page 1049 00h a4h a4h ?offset a4h: gen_pmcon_3 - general pm configuration 3 register? on page 1051 00h b8h bbh ?offset b8h: gpi_rout - gpi routing control register? on page 1053 00000000h table 7-24. bus 0, device 31, function 0: summary of tco configuration registers mapped through tcobase i/o bar? offset start offset end register id - description default value 00h 01h ?offset 00h: trld - tco timer reload and current value register? on page 715 0000h 02h 02h ?offset 02h: tdi - tco data in register? on page 715 00h 03h 03h ?offset 03h: tdo - tco data out register? on page 716 00h 04h 04h ?offset 04h: tsts1 - tco 1 status register? on page 716 0000h 06h 07h ?offset 06h: tsts2 - tco 2 sts register? on page 718 0000h 08h 09h ?offset 08h: tctl1 - tco 1 control register? on page 720 0000h 0ah 0bh ?offset 0ah: tctl2 - tco 2 control register? on page 721 0008h 0ch at 01h 0ch at 01h ?offset 0ch: tmsg[1-2] - tco message register? on page 721 00h 0eh 0eh ?offset 0eh: twds - tco watchdog status register? on page 722 00h 10h 10h ?offset 10h: le - legacy elimination register? on page 722 03h 12h 13h ?offset 12h: ttmr - tco timer initial value register? on page 723 0004h table 7-25. bus 0, device 31, function 0: summary of lpc interface power management general configuration registers mapped through pmbase i/o bar (sheet 1 of 2) offset start offset end register id - description default value 00h 00h ?offset 00h: pm1_sts ? power management 1 status register? on page 1056 0000h 02h 02h ?offset 02h: pm1_en - power management 1 enables register? on page 1058 0000h 04h 04h ?offset 04h: pm1_cnt - power management 1 control register? on page 1059 0000h 08h b8h ?offset 08h: pm1_tmr - power management 1 timer register? on page 1060 00000000h 10h 10h ?offset 10h: proc_cnt - processor control register? on page 1060 00000000h 14h 14h ?offset 14h: lv2 - level 2 register? on page 1063 00h 28h 28h ?offset 28h: gpe0_sts - general purpose event 0 status register? on page 1063 00000000h 2ch 2ch ?offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register? on page 1067 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 212 order number: 320066-003us 30h 30h ?offset 30h: smi_en - smi control and enable register? on page 1068 00000000h 34h 34h ?offset 34h: smi_sts - smi status register? on page 1071 00000000h 38h 38h ?offset 38h: alt_gpi_smi_en - alternate gpi smi enable register? on page 1073 0000h 3ah 3ah ?offset 3ah: alt_gpi_smi_sts - alternate gpi smi status register? on page 1074 0000h 44h 44h ?offset 44h: devtrap_sts - devtrap_sts register? on page 1074 0000h table 7-25. bus 0, device 31, function 0: summary of lpc interface power management general configuration registers mapped through pmbase i/o bar (sheet 2 of 2) offset start offset end register id - description default value table 7-26. bus 0, device 31, function 0: summary of general purpose i/o configuration registers mapped through gba bar io bar offset start offset end register id - description default value 00h 03h ?offset 00h: gpio_use_sel1 - gpio use select 1 {31:0} register? on page 807 variable 04h 07h ?offset 04h: gp_io_sel1 - gpio input/output select 1 {31:0} register? on page 808 e400ffffh 0ch 0fh ?offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register? on page 809 ff3f0000h 18h 1bh ?offset 18h: gpo_blink - gpio blink enable register? on page 810 00040000h 2ch 2fh ?offset 2ch: gpi_inv - gpio signal invert register? on page 812 00000000h 30h 33h ?offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register? on page 813 variable 34h 37h ?offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register? on page 813 00000300h 38h 3bh ?offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register? on page 814 00030207h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 213 intel ? ep80579 integrated processor 7.3.10 sata controller: bus 0, device 31, function 2 the sata controller includes the registers listed in ta b l e 7 - 2 7 , ta b l e 7 - 2 8 , and ta bl e 7 - 2 9 . these registers materialize in pci configuration, i/o, and memory spaces (via pci i/o and memory bars). see chapter 23.0, ?sata: bus 0, device 31, function 2? for detailed discussion of these registers. table 7-27. bus 0, device 31, function 2: summary of sata controller pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: id ? identifiers register? on page 819 variable 04h 05h ?offset 04h: cmd - command register? on page 819 0000h 06h 07h ?offset 06h: sts - device status register? on page 820 02b0h 08h 08h ?offset 08h: rid - revision id register? on page 821 variable 0ah 0bh ?offset 0ah: cc - class code register? on page 823 variable 0dh 0dh ?offset 0dh: mlt ? master latency timer register? on page 823 00h 10h 13h ?offset 10h: pcmdba ? primary command block base address register? on page 824 00000001h 14h 17h ?offset 14h: pctlba ? primary control block base address register? on page 824 00000001h 18h 1bh ?offset 18h: scmdba ? secondary command block base address register? on page 825 00000001h 1ch 1fh ?offset 1ch: sctlba ? secondary control block base address register? on page 825 00000001h 20h 23h ?offset 20h: lbar ? legacy bus master base address register when scc is sata with ahci pi? on page 826 00000001h 24h 27h ?offset 24h: abar ? ahci base address register? on page 826 00000000h 2ch 2fh ?offset 2ch: ss - sub system identifiers register? on page 827 00000000h 34h 34h ?offset 34h: cap ? capabilities pointer register? on page 827 80h 3ch 3dh ?offset 3ch: intr - interrupt information register? on page 828 variable 40h 41h ?offset 40h: ptim ? primary timing register? on page 829 0000h 44h 44h ?offset 44h: d1tim ? device 1 ide timing register? on page 830 00h 48h 48h ?offset 48h: syncc ? synchronous dma control register? on page 831 00h 4ah 4bh ?offset 4ah: synctim ? synchronous dma timing register? on page 832 0000h 54h 57h ?offset 54h: iioc ? ide i/o configuration register? on page 833 00000000h 70h 71h ?offset 70h: pid ? pci power management capability id register? on page 834 variable 72h 73h ?offset 72h: pc ? pci power management capabilities register? on page 834 4002h 74h 77h ?offset 74h: pmcs ? pci power management control and status register? on page 835 0000h 80h 81h ?offset 80h: mid ? message signaled interrupt identifiers register? on page 836 7005h 82h 83h ?offset 82h: mc ? message signaled interrupt message control register? on page 837 0000h 84h 87h ?offset 84h: ma ? message signaled interrupt message address register? on page 838 00000000h 88h 89h ?offset 88h: md ? message signaled interrupt message data register? on page 838 0000h 90h 90h ?offset 90h: map ? port mapping register? on page 839 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 214 order number: 320066-003us 92h 92h ?offset 92h: pcs ? port control and status register? on page 840 00h a8h abh ?offset a8h: satacr0 ? serial ata capability register 0? on page 841 00100012h ach afh ?offset ach: satacr1 ? serial ata capability register 1? on page 841 00000048h c0h c0h ?offset c0h: atc ? apm trapping control register? on page 842 00h c4h c4h ?offset c4h: ats ? atm trapping status register? on page 843 00h d0h d3h ?offset d0h: sp ? scratch pad register? on page 844 00000000h e0h e3h ?offset e0h: bfcs ? bist fis control/status register? on page 844 00000000h e4h e7h ?offset e4h: bftd1 ? bist fis transmit data 1 register? on page 846 00000000h e8h ebh ?offset e8h: bftd2 ? bist fis transmit data 2 register? on page 846 0h f8h fbh ?offset f8h: manid ? manufacturing id register? on page 847 variable table 7-27. bus 0, device 31, function 2: summary of sata controller pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-28. bus 0, device 31, function 2: summary of sata controller configuration registers mapped through lbar i/o bar offset start offset end register id - description default value 00h 00h ?offset 00h: pcmd ? primary command register? on page 848 00h 02h 02h ?offset 02h: psts ? primary status register? on page 849 00h 04h 07h ?offset 04h: pdtp ? primary descriptor table pointer register? on page 849 variable 10h 13h ?offset 10h: index ? ahci index register? on page 850 00000000h 14h 17h ?offset 14h: data ? ahci data register? on page 851 variable table 7-29. bus 0, device 31, function 2: summary of sata controller configuration registers mapped through abar memory bar (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: hcap ? hba capabilities register? on page 853 variable 04h 07h ?offset 04h: ghc ? global hba control register? on page 855 00000000h 08h 0bh ?offset 08h: is ? interrupt status register? on page 856 00000000h 0ch 0fh ?offset 0ch: pi ? ports implemented register? on page 856 00000000h 10h 13h ?offset 10h: vs ? ahci version register? on page 857 00010100h a0h a3h ?offset a0h: sgpo -spgio control register? on page 857 00000000h 100h, 180h 17fh, 1ffh ?offset 100h: pxclb[0-1] ? port [0-1] command list base address register? on page 858 variable 104h, 184h 107h, 187h ?offset 104h: pxclbu[0-1] ? port [0-1] command list base address register? on page 858 variable 108h, 188h 10bh, 18bh ?offset 108h: pxfb[0-1] ? port [0-1] fis base address register? on page 859 variable
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 215 intel ? ep80579 integrated processor 10ch, 18ch 10fh, 18fh ?offset 10ch: pxfbu[0-1] ? port [0-1] fis base address upper 32-bits register? on page 859 variable 110h, 190h 113h, 193h ?offset 110h: pxis[0-1] ? port [0-1] interrupt status register? on page 860 00000000h 114h, 194h 117h, 197h ?offset 114h: pxie[0-1] ? port [0-1] interrupt enable register? on page 861 00000000h 118h, 198h 11bh, 19bh ?offset 118h: pxcmd[0-1] ? port [0-1] command register? on page 863 variable 120h, 1a0h 123h, 1a3h ?offset 120h: pxtfd[0-1] ? port [0-1] task file data register? on page 866 0000007fh 124h, 1a4h 127h, 1a7h ?offset 124h: pxsig[0-1] ? port [0-1] signature register? on page 867 ffffffffh 128h, 1a8h 12bh, 1abh ?offset 128h: pxssts[0-1] ? port [0-1] serial ata status register? on page 868 variable 12ch, 1ach 12fh, 1afh ?offset 12ch: pxsctl[0-1] ? port [0-1] serial ata control register? on page 869 00000000h 130h, 1b0h 133h, 1b3h ?offset 130h: pxserr[0-1] ? port [0-1] serial ata error register? on page 870 00000000h 134h, 1b4h 137h, 1b7h ?offset 134h: pxsact[0-1] ? port [0-1] serial ata active register? on page 872 00000000h 138h, 1b8h 13bh, 1bbh ?offset 138h: pxci[0-1] ? port [0-1] command issue register? on page 872 00000000h 13ch, 1bch 13fh, 1bfh ?offset 13ch: pxsntf[0-1] ? port [0-1] snotification register? on page 873 00000000h table 7-29. bus 0, device 31, function 2: summary of sata controller configuration registers mapped through abar memory bar (sheet 2 of 2) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 216 order number: 320066-003us 7.3.11 smbus controller: bus 0, device 31, function 3 the smbus controller includes the registers listed in ta b l e 7 - 3 0 and ta b l e 7 - 3 1 . these registers materialize in pci configuration and i/o spaces (via pci i/o bar), respectively. see chapter 24.0, ?smbus controller functional description: bus 0, device 31, function 3? for detailed discussion of these registers. table 7-30. bus 0, device 31, function 3: summary of smbus controller pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor id register? on page 897 8086h 02h 03h ?offset 02h: did: device id register? on page 897 5032h 04h 05h ?offset 04h: cmd: command register? on page 897 0000h 06h 07h ?offset 06h: ds ? device status register? on page 898 0280h 08h 08h ?offset 08h: rid: revision id register? on page 899 variable 09h 09h ?offset 09h: pi: programming interface register? on page 900 00h 0ah 0ah ?offset 0ah: scc: sub class code register? on page 900 05h 0bh 0bh ?offset 0bh: bcc: base class code register? on page 900 0ch 20h 23h ?offset 20h: sm_base: smb base address register? on page 901 00000001h 2ch 2dh ?offset 2ch: svid: svid register? on page 901 0000h 2eh 2fh ?offset 2eh: sid: subsystem identification register? on page 902 0000h 3ch 3ch ?offset 3ch: intln: interrupt line register? on page 902 00h 3dh 3dh ?offset 3dh: ntpn: interrupt pin register? on page 903 variable 40h 40h ?offset 40h: hcfg: host configuration register? on page 903 00h f8h fbh ?offset f8h: manid: manufacturer id register? on page 904 00010f90h table 7-31. bus 0, device 31, function 3: summary of smbus controller configuration registers mapped through sm_base i/o bar offset start offset end register id - description default value 00h 00h ?offset 00h: hsts: host status register? on page 906 00h 02h 02h ?offset 02h: hctl: host control register? on page 908 00h 03h 03h ?offset 03h: hcmd: host command register? on page 912 00h 04h 04h ?offset 04h: tsa: transmit slave address register? on page 912 00h 05h 05h ?offset 05h: hd0: data 0 register? on page 913 00h 06h 06h ?offset 06h: hd1: data 1 register? on page 913 00h 07h 07h ?offset 07h: hbd: host block data register? on page 914 00h 08h 08h ?offset 08h: pec: packet error check data register? on page 915 00h 0ch 0ch ?offset 0ch: auxs: auxiliary status register? on page 915 00h 0dh 0dh ?offset 0dh: auxc: auxiliary control register? on page 916 00h 0eh 0eh ?offset 0eh: smlc: smlink_pin_ctl register? on page 916 07h 0fh 0fh ?offset 0fh: smbc: smbus_pin_ctl register? on page 917 07h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 217 intel ? ep80579 integrated processor 7.3.12 ia-32 core interface i/o-mapped register 7.3.13 imch pci configuration the pci configuration interface includes the registers listed in ta b l e 7 - 3 3 . these registers materialize at fixed locations in i/o space. 7.3.14 apic the apic includes the registers listed in ta b l e 7 - 3 4 and ta b l e 7 - 3 5 these registers materialize at fixed locations in memory space and are indexed, respectively. see chapter 30.0 for detailed discussion of these registers. table 7-32. summary of ia-32 core interface registers mapped in i/o space offset start offset end register id - description default value 61h 61h ?offset 61h: nmi_sts_cnt - nmi status and control register? on page 1098 00h 70h 70h ?offset 70h: nmi_en - nmi enable (and real time clock index) register? on page 1099 80h 92h 92h ?offset 92h: port92 - fast a20 and init register? on page 1100 00h f0h f0h ?offset f0h: coproc_err - coprocessor error register? on page 1100 00h cf9h cf9h ?offset cf9h: rst_cnt - reset control register? on page 1101 00h table 7-33. summary of imch pci configuration registers mapped in i/o space offset start offset end register id - description default value 0cf8h 0cf8h ?offset 0cf8h: config_address: configuration address register? on page 354 00000000h 0cfch 0cfch ?offset 0cfch: config_data: configuration data register? on page 355 00000000h table 7-34. summary of apic registers mapped in memory space? offset start offset end register id - description default value 0000h (4b) 0000h (4b) ?apic_idx - index register? on page 1135 00h 0010h (4b) 0010h (4b) ?apic_dat ? data register? on page 1136 00h 0040h (4b) 0040h (4b) ?apic_eoi - eoi register? on page 1136 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 218 order number: 320066-003us table 7-35. summary of apic indexed registers offset start offset end register id - description default value 00h (4b) 00h (4b) ?apic_id ? identification register? on page 1138 0000h 01h (4b) 01h (4b) ?apic_vs - version register? on page 1138 00170020h 10h at 02h (4b) 11h at 02h (4b) ?apic_rte[0-39] - redirection table entry? on page 1139 xxxx0000000 1xxxxh
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 219 intel ? ep80579 integrated processor 7.3.15 8259 interrupt controller (pic) the 8259 interrupt controller includes the registers listed in ta b l e 7 - 3 6 . these registers materialize at fixed locations in i/o space. see chapter 30.0, ?interrupts? for detailed discussion of these registers. 7.3.16 apm power management the apm power management includes the registers listed in ta b l e 7 - 3 7 . these registers materialize at fixed locations in i/o space. see chapter 27.0, ?power management? for detailed discussion of these registers. table 7-36. summary of 8259 interrupt controller (pic) registers mapped in i/o space offset start offset end register id - description default value 020h, 0a0h 020h, 0a0h ?icw1[0-1] - initialization command word 1 register? on page 1119 0001x0xxb 021h, 0a1h 021h, 0a1h ?icw2[0-1] - initialization command word 2 register? on page 1120 xxh 21h 21h ?micw3 - master initialization command word 3 register? on page 1121 04h a1h a1h ?sicw3 - slave initialization command word 3 register? on page 1121 00h 21h, 0a1h 21h, 0a1h ?icw4[0-1] - initialization command word 4 register? on page 1122 01h 021h, 0a1h 021h, 0a1h ?ocw1[0-1]- operational control word 1 (interrupt mask) register? on page 1122 00h 020h, 0a0h 020h, 0a0h ?ocw2[0-1] - operational control word 2 register? on page 1123 001xxxxxb 020h, 0a0h 020h, 0a0h ?ocw3[0-1] - operational control word 3 register? on page 1124 001xx10b 4d0h 4d0h ?elcr1 - master edge/level control register? on page 1125 00h 4d1h 4d1h ?elcr2 - slave edge/level control register? on page 1126 00 table 7-37. summary of apm registers mapped in i/o space offset start offset end register id - description default value b2h b2h ?offset b2h: apm_cnt - advanced power management control port register? on page 1054 00h b3h b3h ?offset b3h: apm_sts - advanced power management status port register? on page 1054 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 220 order number: 320066-003us 7.3.17 lpc dma the lpc dma interface includes the registers listed in ta b l e 7 - 3 8 through ta b l e 7 - 4 0 . these registers materialize at fixed locations in i/o space. see chapter 20.0, ?lpc dma? for detailed discussion of these registers. table 7-38. summary of lpc dma registers mapped in i/o space offset start offset end register id - description default value 00h at 02h 10h at 02h ?offset 00h: dma_bca[0-3] - dma base and current address registers for channels 0-3? on page 766 xxxx c4h at 04h c5h at 04h ?offset c4h: dma_bca[5-7] - dma base and current address registers for channels 5-7? on page 767 xxxx 01h at 02h 11h at 02h ?offset 01h: dma_bcc[0-3] - dma base and current count registers for channels 0-3? on page 768 xxxx c6h at 04h c7h at 04h ?offset c6h: dma_bcc[5-7] - dma base and current count registers for channels 5-7? on page 769 xxxx 87h, 83h, 81h, 82h 97h, 93h, 91h, 82h ?offset 87h: dma_mpl[0-3] - dma memory low page registers for channels 0-3? on page 771 xxxxxxx 8bh, 89h, 8ah 9bh, 99h, 9ah ?offset 8bh: dma_mpl[5-7]: dma memory low page registers for channels 5-7? on page 771 xxxxxxx table 7-39. 0000h (io) base address registers in the ia f1 view offset start offset end register id - description default value 08h 08h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b 18h 18h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b 08h 08h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh 18h 18h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh 0ah 0ah ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb 1ah 1ah ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb 0bh 0bh ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh 1bh 1bh ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh 0ch 0ch ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh 1ch 1ch ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh 0dh 0dh ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh 1dh 1dh ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh 0eh 0eh ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh 1eh 1eh ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh 0fh 0fh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b 1fh 1fh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 221 intel ? ep80579 integrated processor 7.3.18 8254 timers the 8254 timers include the registers listed in ta b l e 7 - 4 1 . these registers materialize at fixed locations in i/o space. see chapter 31.0, ?8254 timers? for detailed discussion of these registers. table 7-40. 0000h (io) base address registers in the ia f2 view offset start offset end register id - description default value d0h d0h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b d1h d1h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b d0h d0h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh d1h d1h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh d4h d4h ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb d5h d5h ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb d6h d6h ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh d7h d7h ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh d8h d8h ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh d9h d9h ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh dah dah ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh dbh dbh ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh dch dch ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh ddh ddh ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh deh deh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b dfh dfh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b table 7-41. summary of 8254 timer registers mapped in i/o space offset start offset end register id - description default value 43h 43h ?offset 43h: tcw - timer control word register? on page 1146 xxh 40h at 01h 40h at 01h ?offset 40h: tsb[0-2] - interval timer status byte format register? on page 1147 0xxxxxxxb 40h at 01h 40h at 01h ?offset 40h: tcap[0-2] - interval timer counter access ports register? on page 1148 xxh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 222 order number: 320066-003us 7.3.19 high precision event timers the high precision event timers includes the registers listed in ta bl e 7 - 4 2 . these registers materialize at fixed locations in memory space. see chapter 32.0, ?high precision event timers? for detailed discussion of these registers. 7.3.20 watchdog timer and serial i/o the watchdog timers and serial i/o units includes the registers listed in ta bl e 7 - 4 3 and ta b l e 7 - 4 4 . these registers materialize at fixed locations in i/o space. see chapter 33.0, ?serial i/o unit and watchdog timer? for detailed discussion of these registers. table 7-42. summary of hpet registers mapped in memory space offset start offset end register id - description default value 000h 007h ?offset 000h: gcap_id - general capabilities and id register? on page 1155 0429b17f808 6a201h 010h 017h ?offset 010h: gen_conf - general configuration register? on page 1156 00000000000 00000h 020h 027h ?offset 020h: gintr_sta - general interrupt status register? on page 1157 00000000000 00000h 0f0h 0f7h ?offset 0f0h: main_cnt - main counter value register? on page 1158 xh 100h at 20h 107h at 20h ?offset 100h: hptcc[0-2] - timer n configuration and capabilities register? on page 1159 xh 108h at 20h 10fh at 20h ?offset 108h: hptcv[0-2] - timer n comparator value register? on page 1163 xh table 7-43. summary of uart timer registers in i/o space offset start offset end register id - description default value 02h 02h ?offset 02h: iir - interrupt identification register? on page 1179 01h 02h 02h ?offset 02h: fcr - fifo control register? on page 1180 00h 03h 03h ?offset 03h: lcr - line control register? on page 1182 00h 04h 04h ?offset 04h: mcr - modem control register? on page 1184 00h 05h 05h ?offset 05h: lsr - line status register? on page 1186 60h 06h 06h ?offset 06h: msr - modem status register? on page 1189 00h 07h 07h ?offset 07h: scr - scratchpad register? on page 1190 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 223 intel ? ep80579 integrated processor 7.3.21 real time clock the real time clock include the registers listed in ta bl e 7 - 4 5 . these registers materialize at indexed locations. see chapter 29.0, ?real time clock? for detailed discussion of these registers. table 7-44. summary of watchdog timer registers in i/o space offset start offset end register id - description default value 00h 00h ?offset 00h: pv1r0 - preload value 1 register 0? on page 1194 ffh 01h 01h ?offset 01h: pv1r1 - preload value 1 register 1? on page 1195 ffh 02h 02h ?offset 02h: pv1r2 - preload value 1 register 2? on page 1195 0fh 04h 04h ?offset 04h: pv2r0 - preload value 2 register 0? on page 1196 ffh 05h 05h ?offset 05h: pv2r1 - preload value 2 register 1? on page 1196 ffh 06h 06h ?offset 06h: pv2r2 - preload value 2 register 2? on page 1197 0fh 08h 08h ?offset 08h: gisr - general interrupt status register? on page 1197 00h 0ch 0ch ?offset 0ch: rr0 - reload register 0? on page 1198 00h 0dh 0dh ?offset 0dh: rr1 - reload register 1? on page 1199 00h 10h 10h ?offset 10h: wdtcr - wdt configuration register? on page 1199 00h 18h 18h ?offset 18h: wdtlr - wdt lock register? on page 1201 00h table 7-45. summary of real time clock indexed registers offset start offset end register id - description default value 0ah 0ah ?offset 0ah: rtc_rega - register a (general configuration)? on page 1107 xxh 0bh 0bh ?offset 0bh: rtc_regb - register b (general configuration)? on page 1109 x0x00xxxb 0ch 0ch ?offset 0ch: rtc_regc - register c (flag register)? on page 1110 00x00000b 0dh 0dh ?offset 0dh: rtc_regd - register d (flag register)? on page 1111 10xxxxxxb
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 224 order number: 320066-003us 7.4 aioc registers this section summarizes the registers in the aioc. the registers are presented as they materialize from a pci perspective. 7.4.1 pci-to-pci bridge: bus 0, device 4, function 0 the pci-to-pci bridge includes the registers listed in ta b l e 7 - 4 6 . these registers materialize in pci configuration space. see chapter 34.0, ?pci-to-pci bridge detailed register descriptions? for detailed discussion of these registers along with alternative materializations. table 7-46. bus 0, device 4, function 0: summary of pci-to-pci bridge pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 0h 1h ?offset 0h: vid: vendor identification register? on page 1217 8086h 2h 3h ?offset 2h: did: device identification register? on page 1217 5037h 4h 5h ?offset 4h: pcicmd: device command register? on page 1217 0h 6h 7h ?offset 6h: pcists: pci device status register? on page 1218 10h 8h 8h ?offset 8h: rid: revision id register? on page 1219 variable 9h bh ?offset 9h: cc: class code register? on page 1219 060400h ch ch ?offset ch: cls: cacheline size register? on page 1219 00h dh dh ?offset dh: lt: latency timer register? on page 1220 00h eh eh ?offset eh: hdr: header type register? on page 1220 1h 10h 14h ?offset 10h: csrbar0: control and status registers base address register? on page 1220 00h 14h 17h ?offset 14h: csrbar1: control and status registers base address register? on page 1221 00h 18h 18h ?offset 18h: pbnum: primary bus number register? on page 1221 00h 19h 19h ?offset 19h: secbnm: secondary bus number register? on page 1221 00h 1ah 1ah ?offset 1ah: subbnm: subordinate bus number register? on page 1222 00h 1bh 1bh ?offset 1bh: seclt: secondary latency timer register? on page 1222 00h 1ch 1ch ?offset 1ch: iob: i/o base register? on page 1222 f0 1dh 1dh ?offset 1dh: iol: i/o limit register? on page 1223 0 1eh 1fh ?offset 1eh: secsta: secondary status register? on page 1223 0h 20h 21h ?offset 20h: memb: memory base register? on page 1224 fff0 22h 23h ?offset 22h: meml: memory limit register? on page 1224 0 24h 25h ?offset 24h: pmase: prefetchable memory base register? on page 1225 fff1h 26h 27h ?offset 26h: pmlimit: prefetchable memory limit register? on page 1225 1h 28h 28h ?offset 28h: pmbasu: memory limit register? on page 1226 fh 2ch 2ch ?offset 2ch: pmlmtu: prefetchable memory limit upper register? on page 1226 0 30h 31h ?offset 30h: iobu: i/o base upper register? on page 1227 0 32h 33h ?offset 32h: iolu: i/o limit upper register? on page 1227 0 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1227 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1228 0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 225 intel ? ep80579 integrated processor 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1228 0 3eh 3fh ?offset 3eh: bctl: bridge control register? on page 1228 0000h dch dch ?offset dch: pcid: power management capability id register? on page 1229 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1230 00h deh dfh ?offset deh: pmcap: power management capability register? on page 1230 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1231 0008h e2h e2h ?offset e2h: pmcse: power management control and status extension register? on page 1232 0000h table 7-46. bus 0, device 4, function 0: summary of pci-to-pci bridge pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 226 order number: 320066-003us 7.4.2 gigabit ethernet mac: bus m, devices 0, 1, and 2, function 0 the gigabit ethernet mac includes the registers listed in ta b l e 7 - 4 7 through ta b l e 7 - 4 4 . these registers materialize in pci configuration, i/o (via pci bar), and memory (via pci bar) spaces. see section 35.6, ?gigabit ethernet mac configuration spaces: bus m, device 0-2, function 0? , section 35.7, ?gigabit ethernet mac i/o spaces: bus m, device 0-2, function 0? , and section 37.6, ?gbe controller register summary? for detailed discussion of these registers along with alternative materializations. table 7-47. bus m, device 0, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1241 8086h 02h 03h ?offset 02h: did: device identification register? on page 1241 5040h 04h 05h ?offset 04h: pcicmd: device command register? on page 1243 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1244 10h 08h 08h ?offset 08h: rid: revision id register? on page 1245 variable 09h 0bh ?offset 09h: cc: class code register? on page 1245 020000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1246 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1246 00000000h 14h 17h ?offset 14h: iobar: csr i/o mapped bar register? on page 1247 00000001h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1248 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1248 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1249 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1249 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1250 01h dch dch ?offset dch: pcid: power management capability id register? on page 1251 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1251 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1252 x023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1253 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1254 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1254 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1255 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1255 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1256 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1257 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1258 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1258 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1259 0000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 227 intel ? ep80579 integrated processor f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1259 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1260 0000h table 7-47. bus m, device 0, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-48. bus m, device 1, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1241 8086h 02h 03h ?offset 02h: did: device identification register? on page 1242 5044h 04h 05h ?offset 04h: pcicmd: device command register? on page 1243 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1244 10h 08h 08h ?offset 08h: rid: revision id register? on page 1245 variable 09h 0bh ?offset 09h: cc: class code register? on page 1245 020000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1246 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1246 00000000h 14h 17h ?offset 14h: iobar: csr i/o mapped bar register? on page 1247 00000001h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1248 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1248 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1249 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1249 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1250 01h dch dch ?offset dch: pcid: power management capability id register? on page 1251 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1251 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1252 x023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1253 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1254 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1254 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1255 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1255 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1256 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1257 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1258 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1258 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1259 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 228 order number: 320066-003us f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1259 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1260 0000h table 7-48. bus m, device 1, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-49. bus m, device2, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1241 8086h 02h 03h ?offset 02h: did: device identification register? on page 1242 5048h 04h 05h ?offset 04h: pcicmd: device command register? on page 1243 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1244 10h 08h 08h ?offset 08h: rid: revision id register? on page 1245 variable 09h 0bh ?offset 09h: cc: class code register? on page 1245 020000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1246 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1246 00000000h 14h 17h ?offset 14h: iobar: csr i/o mapped bar register? on page 1247 00000001h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1248 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1248 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1249 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1249 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1250 01h dch dch ?offset dch: pcid: power management capability id register? on page 1251 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1251 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1252 x023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1253 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1254 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1254 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1255 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1255 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1256 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1257 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1258 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1258 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1259 0000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 229 intel ? ep80579 integrated processor f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1259 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1260 0000h table 7-49. bus m, device2, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-50. bus m, device 0, function 0: gigabit ethernet mac i/o spaces registers offset start offset end register id - description default value 0000h 0003h ?offset 0000h: ioaddr - ioaddr register? on page 1263 0000000h 0004h 0007h ?offset 0004h: iodata - iodata register? on page 1264 0000000h table 7-51. bus m, device 1, function 0: gigabit ethernet mac i/o spaces registers offset start offset end register id - description default value 0000h 0003h ?offset 0000h: ioaddr - ioaddr register? on page 1263 0000000h 0004h 0007h ?offset 0004h: iodata - iodata register? on page 1264 0000000h table 7-52. bus m, device 2, function 0: gigabit ethernet mac i/o spaces registers offset start offset end register id - description default value 0000h 0003h ?offset 0000h: ioaddr - ioaddr register? on page 1263 0000000h 0004h 0007h ?offset 0004h: iodata - iodata register? on page 1264 0000000h table 7-53. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 1 of 4) offset start offset end register id - description default value 0000h 0003h ?ctrl: device control register? on page 1438 00000a09h 0008h 000bh ?status: device status register? on page 1441 0000xxxxh 0018h 001bh ?ctrl_ext: extended device control register? on page 1442 00000000h 00e0h 00e3h ?ctrl_aux: auxiliary device control register? on page 1444 00000100h 0010h 0013h ?eeprom_ctrl - eeprom control register? on page 1446 00000x1xh 0014h 0017h ?eeprom_rr ? eeprom read register? on page 1448 xxxxxx00h 0028h 002bh ?fcal: flow control address low register? on page 1449 00c28001h 002ch 002fh ?fcah: flow control address high register? on page 1450 00000100h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 230 order number: 320066-003us 0030h 0033h ?fct: flow control type register? on page 1451 00008808h 0038h 003bh ?vet: vlan ethertype register? on page 1452 00008100h 0170h 0173h ?fcttv: flow control transmit timer value register? on page 1452 00000000h 1000h 1003h ?pba: packet buffer allocation register? on page 1453 00100030h 00c0h 00c3h ?icr0: interrupt 0 cause read register? on page 1454 00000000h 00c4h 00c7h ?itr0: interrupt 0 throttling register? on page 1457 00000000h 00c8h 00cbh ?ics0: interrupt 0 cause set register? on page 1458 00000000h 00d0h 00d3h ?ims0: interrupt 0 mask set/read register? on page 1459 00000000h 00d8h 00dbh ?imc0: interrupt 0 mask clear register? on page 1460 00000000h 08c0h 08c3h ?icr1: interrupt 1cause read register? on page 1462 00000000h 08c8h 08cbh ?ics1: interrupt 0 cause set register? on page 1464 00000000h 08d0h 08d3h ?ims1: interrupt 1 mask set/read register? on page 1466 00000000h 08d8h 08dbh ?imc1: interrupt 1 mask clear register? on page 1467 00000000h 08e0h 08e3h ?icr2: error interrupt cause read register? on page 1469 00000000h 08e8h 08ebh ?ics2: error interrupt cause set register? on page 1471 00000000h 08f0h 08f3h ?ims2: error interrupt mask set/read register? on page 1472 00000000h 08f8h 08fbh ?imc2: error interrupt mask clear register? on page 1473 00000000h 0100h 0103h ?rctl: receive control register? on page 1474 00000000h 2160h 2163h ?fcrtl: flow control receive threshold low register? on page 1478 00000000h 2168h 216bh ?fcrth: flow control receive threshold high register? on page 1479 00000000h 2800h 2803h ?rdbal: receive descriptor base address low register? on page 1480 xxxxxxx0h 2804h 2807h ?rdbah: receive descriptor base address high register? on page 1480 xxxxxxxxh 2808h 280bh ?rdlen: receive descriptor length register? on page 1481 00000000h 2810h 2813h ?rdh: receive descriptor head register? on page 1481 00000000h 2818h 281bh ?rdt: receive descriptor tail register? on page 1482 00000000h 2820h 2823h ?rdtr: rx interrupt delay timer (packet timer) register? on page 1483 00000000h 2828h 282bh ?rxdctl: receive descriptor control register? on page 1483 00010000h 282ch 282fh ?radv: receive interrupt absolute delay timer register? on page 1485 00000000h 2c00h 2c03h ?rsrpd: receive small packet detect interrupt register? on page 1486 00000000h 5000h 5003h ?rxcsum: receive checksum control register? on page 1487 00000000h 5200h at 4h 5203h at 4h ?mta[0-127] ? 128 multicast table array registers? on page 1488 xxxx_xxxxh 5400h at 8h 5403h at 8h ?ral[0-15] - receive address low register? on page 1488 xxxxxxxxh 5404h at 8h 5407h at 8h ?rah[0-15] - receive address high register? on page 1489 000xxxxxh 5600h at 4h 5603h at 4h ?vfta[0-127] - 128 vlan filter table array registers? on page 1490 xxxxxxxxh 0400h 0403h ?tctl: transmit control register? on page 1491 00000008h 0410h 0413h ?tipg: transmit ipg register? on page 1493 00602008h 0458h 045bh ?ait: adaptive ifs throttle register? on page 1495 00000000h 3800h 3803h ?tdbal: transmit descriptor base address low register? on page 1496 xxxxxxx0h 3804h 3807h ?tdbah: transmit descriptor base address high register? on page 1496 xxxxxxxxh table 7-53. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 2 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 231 intel ? ep80579 integrated processor 3808h 380bh ?tdlen: transmit descriptor length register? on page 1497 00000000h 3810h 3813h ?tdh: transmit descriptor head register? on page 1497 00000000h 3818h 381bh ?tdt: transmit descriptor tail register? on page 1498 00000000h 3820h 3823h ?tidv: transmit interrupt delay value register? on page 1499 00000000h 3828h 382bh ?txdctl: transmit descriptor control register? on page 1500 00000000h 382ch 382fh ?tadv: transmit absolute interrupt delay value register? on page 1502 00000000h 3830h 3833h ?tspmt: tcp segmentation pad and minimum threshold register? on page 1504 01000400h 4000h 4003h ?crcerrs: crc error count register? on page 1505 00000000h 4004h 4007h ?algnerrc: alignment error count register? on page 1506 00000000h 400ch 400fh ?rxerrc: receive error count register? on page 1506 00000000h 4010h 4013h ?mpc: missed packet count register? on page 1507 00000000h 4014h 4017h ?scc: single collision count register? on page 1507 0000h 4018h 401bh ?ecol: excessive collisions count register? on page 1508 00000000h 401ch 401fh ?mcc: multiple collision count register? on page 1508 00000000h 4020h 4023h ?latecol: late collisions count register? on page 1509 00000000h 4028h 402bh ?colc: collision count register? on page 1509 00000000h 4030h 4033h ?dc: defer count register? on page 1510 00000000h 4034h 4037h ?tncrs: transmit with no crs count register? on page 1510 00000000h 403ch 403fh ?cexterr: carrier extension error count register? on page 1511 00000000h 4040h 4043h ?rlec: receive length error count register? on page 1511 00000000h 4048h 404bh ?xonrxc: xon received count register? on page 1512 00000000h 404ch 404fh ?xontxc: xon transmitted count register? on page 1512 00000000h 4050h 4053h ?xoffrxc: xoff received count register? on page 1513 00000000h 4054h 4057h ?xofftxc: xoff transmitted count register? on page 1513 00000000h 4058h 405bh ?fcruc: fc received unsupported count register? on page 1514 00000000h 405ch 405fh ?prc64: good packets received count (64 bytes) register? on page 1514 00000000h 4060h 4063h ?prc127: good packets received count (65-127 bytes) register? on page 1515 00000000h 4064h 4067h ?prc255: good packets received count (128-255 bytes) register? on page 1515 00000000h 4068h 406bh ?prc511 - good packets received count (256-511 bytes) register? on page 1516 00000000h 406ch 406fh ?prc1023: good packets received count (512-1023 bytes) register? on page 1516 00000000h 4070h 4073h ?prc1522: good packets received count (1024 to max bytes) register? on page 1517 00000000h 4074h 4077h ?gprc: good packets received count (total) register? on page 1518 00000000h 4078h 407bh ?bprc: broadcast packets received count register? on page 1518 00000000h 407ch 407fh ?mprc: multicast packets received count register? on page 1519 00000000h 4080h 4083h ?gptc: good packets transmitted count register? on page 1519 00000000h 4088h 408ah ?gorcl: good octets received count low register? on page 1520 00000000h 408ch 408fh ?gorch: good octets received count high register? on page 1521 00000000h 4090h 4093h ?gotcl: good octets transmitted count low register? on page 1522 00000000h table 7-53. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 3 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 232 order number: 320066-003us 4094h 4097h ?gotch: good octets transmitted count high register? on page 1522 00000000h 40a0h 40a3h ?rnbc: receive no buffers count register? on page 1523 00000000h 40a4h 40a7h ?ruc: receive undersize count register? on page 1523 00000000h 40a8h 40abh ?rfc: receive fragment count register? on page 1524 00000000h 40ach 40afh ?roc: receive oversize count register? on page 1524 00000000h 40b0h 40b3h ?rjc: receive jabber count register? on page 1525 00000000h 40c0h 40c3h ?torl: total octets received low register? on page 1526 00000000h 40c4h 40c7h ?torh: total octets received high register? on page 1526 00000000h 40c8h 40cfh ?totl: total octets transmitted low register? on page 1527 00000000h 40cch 40cfh ?toth: total octets transmitted high register? on page 1528 00000000h 40d0h 40d3h ?tpr: total packets received register? on page 1528 00000000h 40d4h 40d7h ?tpt: total packets transmitted register? on page 1529 00000000h 40d8h 40dbh ?ptc64 - packets transmitted count (64 bytes) register? on page 1529 00000000h 40e0h 40e3h ?ptc255: packets transmitted count (128-255 bytes) register? on page 1530 00000000h 40e4h 40e7h ?ptc511: packets transmitted count (256-511 bytes) register? on page 1530 00000000h 40e8h 40ebh ?ptc1023: packets transmitted count (512-1023 bytes) register? on page 1531 00000000h 40ech 40efh ?ptc1522: packets transmitted count (1024-1522 bytes) register? on page 1531 00000000h 40f0h 40f3h ?mptc: multicast packets transmitted count register? on page 1532 00000000h 40f4h 40f7h ?bptc: broadcast packets transmitted count register? on page 1532 00000000h 40f8h 40fbh ?tsctc: tcp segmentation context transmitted count register? on page 1533 00000000h 40fch 40ffh ?tsctfc: tcp segmentation context transmit fail count register? on page 1533 00000000h 5800h 5803h ?wuc - wake up control register (0x05800; rw)? on page 1534 00000000h 5808h 580bh ?wufc - wake up filter control register (0x05808; rw)? on page 1535 00000000h 5810h 5813h ?wus - wake up status register (0x05810; rw)? on page 1536 00000000h 5838h 583bh ?ipav - ip address valid register (0x05838; rw)? on page 1537 00000000h 5840h at 8h 5843h at 8h ?ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers? on page 1538 xxxxxxxxh 5880h 5883h ?ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4? on page 1539 xxxxxxxxh 05884h 5887h ?ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8? on page 1539 xxxxxxxxh 5888h 588bh ?ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12? on page 1540 xxxxxxxxh 588ch 588fh ?ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16? on page 1541 xxxxxxxxh 5f00h at 8h 5f03h at 8h ?fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw)? on page 1542 00000000h 9000h at 8h 9003h at 8h ?ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1543 0000000xh 9800h at 8h 9803h at 8h ?ffvt[0-127]: flexible filter value table registers? on page 1544 xxxxxxxxh 0510h 0513h ?intbus_err_stat - internal bus error status register? on page 1544 00000000h 0900h 0903h ?mem_tst - memory error test register? on page 1546 00000000h 0904h 0907h ?mem_sts - memory error status register? on page 1547 007f0000h table 7-53. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 4 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 233 intel ? ep80579 integrated processor table 7-54. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 1 of 4) offset start offset end register id - description default value 0000h 0003h ?ctrl: device control register? on page 1438 00000a09h 0008h 000bh ?status: device status register? on page 1441 0000xxxxh 0018h 001bh ?ctrl_ext: extended device control register? on page 1442 00000000h 00e0h 00e3h ?ctrl_aux: auxiliary device control register? on page 1444 00000100h 0010h 0013h ?eeprom_ctrl - eeprom control register? on page 1446 00000x1xh 0014h 0017h ?eeprom_rr ? eeprom read register? on page 1448 xxxxxx00h 0028h 002bh ?fcal: flow control address low register? on page 1449 00c28001h 002ch 002fh ?fcah: flow control address high register? on page 1450 00000100h 0030h 0033h ?fct: flow control type register? on page 1451 00008808h 0038h 003bh ?vet: vlan ethertype register? on page 1452 00008100h 0170h 0173h ?fcttv: flow control transmit timer value register? on page 1452 00000000h 1000h 1003h ?pba: packet buffer allocation register? on page 1453 00100030h 00c0h 00c3h ?icr0: interrupt 0 cause read register? on page 1454 00000000h 00c4h 00c7h ?itr0: interrupt 0 throttling register? on page 1457 00000000h 00c8h 00cbh ?ics0: interrupt 0 cause set register? on page 1458 00000000h 00d0h 00d3h ?ims0: interrupt 0 mask set/read register? on page 1459 00000000h 00d8h 00dbh ?imc0: interrupt 0 mask clear register? on page 1460 00000000h 08c0h 08c3h ?icr1: interrupt 1cause read register? on page 1462 00000000h 08c8h 08cbh ?ics1: interrupt 0 cause set register? on page 1464 00000000h 08d0h 08d3h ?ims1: interrupt 1 mask set/read register? on page 1466 00000000h 08d8h 08dbh ?imc1: interrupt 1 mask clear register? on page 1467 00000000h 08e0h 08e3h ?icr2: error interrupt cause read register? on page 1469 00000000h 08e8h 08ebh ?ics2: error interrupt cause set register? on page 1471 00000000h 08f0h 08f3h ?ims2: error interrupt mask set/read register? on page 1472 00000000h 08f8h 08fbh ?imc2: error interrupt mask clear register? on page 1473 00000000h 0100h 0103h ?rctl: receive control register? on page 1474 00000000h 2160h 2163h ?fcrtl: flow control receive threshold low register? on page 1478 00000000h 2168h 216bh ?fcrth: flow control receive threshold high register? on page 1479 00000000h 2800h 2803h ?rdbal: receive descriptor base address low register? on page 1480 xxxxxxx0h 2804h 2807h ?rdbah: receive descriptor base address high register? on page 1480 xxxxxxxxh 2808h 280bh ?rdlen: receive descriptor length register? on page 1481 00000000h 2810h 2813h ?rdh: receive descriptor head register? on page 1481 00000000h 2818h 281bh ?rdt: receive descriptor tail register? on page 1482 00000000h 2820h 2823h ?rdtr: rx interrupt delay timer (packet timer) register? on page 1483 00000000h 2828h 282bh ?rxdctl: receive descriptor control register? on page 1483 00010000h 282ch 282fh ?radv: receive interrupt absolute delay timer register? on page 1485 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 234 order number: 320066-003us 2c00h 2c03h ?rsrpd: receive small packet detect interrupt register? on page 1486 00000000h 5000h 5003h ?rxcsum: receive checksum control register? on page 1487 00000000h 5200h at 4h 5203h at 4h ?mta[0-127] ? 128 multicast table array registers? on page 1488 xxxx_xxxxh 5400h at 8h 5403h at 8h ?ral[0-15] - receive address low register? on page 1488 xxxxxxxxh 5404h at 8h 5407h at 8h ?rah[0-15] - receive address high register? on page 1489 000xxxxxh 5600h at 4h 5603h at 4h ?vfta[0-127] - 128 vlan filter table array registers? on page 1490 xxxxxxxxh 0400h 0403h ?tctl: transmit control register? on page 1491 00000008h 0410h 0413h ?tipg: transmit ipg register? on page 1493 00602008h 0458h 045bh ?ait: adaptive ifs throttle register? on page 1495 00000000h 3800h 3803h ?tdbal: transmit descriptor base address low register? on page 1496 xxxxxxx0h 3804h 3807h ?tdbah: transmit descriptor base address high register? on page 1496 xxxxxxxxh 3808h 380bh ?tdlen: transmit descriptor length register? on page 1497 00000000h 3810h 3813h ?tdh: transmit descriptor head register? on page 1497 00000000h 3818h 381bh ?tdt: transmit descriptor tail register? on page 1498 00000000h 3820h 3823h ?tidv: transmit interrupt delay value register? on page 1499 00000000h 3828h 382bh ?txdctl: transmit descriptor control register? on page 1500 00000000h 382ch 382fh ?tadv: transmit absolute interrupt delay value register? on page 1502 00000000h 3830h 3833h ?tspmt: tcp segmentation pad and minimum threshold register? on page 1504 01000400h 4000h 4003h ?crcerrs: crc error count register? on page 1505 00000000h 4004h 4007h ?algnerrc: alignment error count register? on page 1506 00000000h 400ch 400fh ?rxerrc: receive error count register? on page 1506 00000000h 4010h 4013h ?mpc: missed packet count register? on page 1507 00000000h 4014h 4017h ?scc: single collision count register? on page 1507 0000h 4018h 401bh ?ecol: excessive collisions count register? on page 1508 00000000h 401ch 401fh ?mcc: multiple collision count register? on page 1508 00000000h 4020h 4023h ?latecol: late collisions count register? on page 1509 00000000h 4028h 402bh ?colc: collision count register? on page 1509 00000000h 4030h 4033h ?dc: defer count register? on page 1510 00000000h 4034h 4037h ?tncrs: transmit with no crs count register? on page 1510 00000000h 403ch 403fh ?cexterr: carrier extension error count register? on page 1511 00000000h 4040h 4043h ?rlec: receive length error count register? on page 1511 00000000h 4048h 404bh ?xonrxc: xon received count register? on page 1512 00000000h 404ch 404fh ?xontxc: xon transmitted count register? on page 1512 00000000h 4050h 4053h ?xoffrxc: xoff received count register? on page 1513 00000000h 4054h 4057h ?xofftxc: xoff transmitted count register? on page 1513 00000000h 4058h 405bh ?fcruc: fc received unsupported count register? on page 1514 00000000h 405ch 405fh ?prc64: good packets received count (64 bytes) register? on page 1514 00000000h 4060h 4063h ?prc127: good packets received count (65-127 bytes) register? on page 1515 00000000h 4064h 4067h ?prc255: good packets received count (128-255 bytes) register? on page 1515 00000000h table 7-54. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 2 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 235 intel ? ep80579 integrated processor 4068h 406bh ?prc511 - good packets received count (256-511 bytes) register? on page 1516 00000000h 406ch 406fh ?prc1023: good packets received count (512-1023 bytes) register? on page 1516 00000000h 4070h 4073h ?prc1522: good packets received count (1024 to max bytes) register? on page 1517 00000000h 4074h 4077h ?gprc: good packets received count (total) register? on page 1518 00000000h 4078h 407bh ?bprc: broadcast packets received count register? on page 1518 00000000h 407ch 407fh ?mprc: multicast packets received count register? on page 1519 00000000h 4080h 4083h ?gptc: good packets transmitted count register? on page 1519 00000000h 4088h 408ah ?gorcl: good octets received count low register? on page 1520 00000000h 408ch 408fh ?gorch: good octets received count high register? on page 1521 00000000h 4090h 4093h ?gotcl: good octets transmitted count low register? on page 1522 00000000h 4094h 4097h ?gotch: good octets transmitted count high register? on page 1522 00000000h 40a0h 40a3h ?rnbc: receive no buffers count register? on page 1523 00000000h 40a4h 40a7h ?ruc: receive undersize count register? on page 1523 00000000h 40a8h 40abh ?rfc: receive fragment count register? on page 1524 00000000h 40ach 40afh ?roc: receive oversize count register? on page 1524 00000000h 40b0h 40b3h ?rjc: receive jabber count register? on page 1525 00000000h 40c0h 40c3h ?torl: total octets received low register? on page 1526 00000000h 40c4h 40c7h ?torh: total octets received high register? on page 1526 00000000h 40c8h 40cfh ?totl: total octets transmitted low register? on page 1527 00000000h 40cch 40cfh ?toth: total octets transmitted high register? on page 1528 00000000h 40d0h 40d3h ?tpr: total packets received register? on page 1528 00000000h 40d4h 40d7h ?tpt: total packets transmitted register? on page 1529 00000000h 40d8h 40dbh ?ptc64 - packets transmitted count (64 bytes) register? on page 1529 00000000h 40e0h 40e3h ?ptc255: packets transmitted count (128-255 bytes) register? on page 1530 00000000h 40e4h 40e7h ?ptc511: packets transmitted count (256-511 bytes) register? on page 1530 00000000h 40e8h 40ebh ?ptc1023: packets transmitted count (512-1023 bytes) register? on page 1531 00000000h 40ech 40efh ?ptc1522: packets transmitted count (1024-1522 bytes) register? on page 1531 00000000h 40f0h 40f3h ?mptc: multicast packets transmitted count register? on page 1532 00000000h 40f4h 40f7h ?bptc: broadcast packets transmitted count register? on page 1532 00000000h 40f8h 40fbh ?tsctc: tcp segmentation context transmitted count register? on page 1533 00000000h 40fch 40ffh ?tsctfc: tcp segmentation context transmit fail count register? on page 1533 00000000h 5800h 5803h ?wuc - wake up control register (0x05800; rw)? on page 1534 00000000h 5808h 580bh ?wufc - wake up filter control register (0x05808; rw)? on page 1535 00000000h 5810h 5813h ?wus - wake up status register (0x05810; rw)? on page 1536 00000000h 5838h 583bh ?ipav - ip address valid register (0x05838; rw)? on page 1537 00000000h 5840h at 8h 5843h at 8h ?ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers? on page 1538 xxxxxxxxh 5880h 5883h ?ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4? on page 1539 xxxxxxxxh table 7-54. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 3 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 236 order number: 320066-003us 05884h 5887h ?ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8? on page 1539 xxxxxxxxh 5888h 588bh ?ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12? on page 1540 xxxxxxxxh 588ch 588fh ?ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16? on page 1541 xxxxxxxxh 5f00h at 8h 5f03h at 8h ?fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw)? on page 1542 00000000h 9000h at 8h 9003h at 8h ?ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1543 0000000xh 9800h at 8h 9803h at 8h ?ffvt[0-127]: flexible filter value table registers? on page 1544 xxxxxxxxh 0510h 0513h ?intbus_err_stat - internal bus error status register? on page 1544 00000000h 0900h 0903h ?mem_tst - memory error test register? on page 1546 00000000h 0904h 0907h ?mem_sts - memory error status register? on page 1547 007f0000h table 7-54. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 4 of 4) offset start offset end register id - description default value table 7-55. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 1 of 4) offset start offset end register id - description default value 0000h 0003h ?ctrl: device control register? on page 1438 00000a09h 0008h 000bh ?status: device status register? on page 1441 0000xxxxh 0018h 001bh ?ctrl_ext: extended device control register? on page 1442 00000000h 00e0h 00e3h ?ctrl_aux: auxiliary device control register? on page 1444 00000100h 0010h 0013h ?eeprom_ctrl - eeprom control register? on page 1446 00000x1xh 0014h 0017h ?eeprom_rr ? eeprom read register? on page 1448 xxxxxx00h 0028h 002bh ?fcal: flow control address low register? on page 1449 00c28001h 002ch 002fh ?fcah: flow control address high register? on page 1450 00000100h 0030h 0033h ?fct: flow control type register? on page 1451 00008808h 0038h 003bh ?vet: vlan ethertype register? on page 1452 00008100h 0170h 0173h ?fcttv: flow control transmit timer value register? on page 1452 00000000h 1000h 1003h ?pba: packet buffer allocation register? on page 1453 00100030h 00c0h 00c3h ?icr0: interrupt 0 cause read register? on page 1454 00000000h 00c4h 00c7h ?itr0: interrupt 0 throttling register? on page 1457 00000000h 00c8h 00cbh ?ics0: interrupt 0 cause set register? on page 1458 00000000h 00d0h 00d3h ?ims0: interrupt 0 mask set/read register? on page 1459 00000000h 00d8h 00dbh ?imc0: interrupt 0 mask clear register? on page 1460 00000000h 08c0h 08c3h ?icr1: interrupt 1cause read register? on page 1462 00000000h 08c8h 08cbh ?ics1: interrupt 0 cause set register? on page 1464 00000000h 08d0h 08d3h ?ims1: interrupt 1 mask set/read register? on page 1466 00000000h 08d8h 08dbh ?imc1: interrupt 1 mask clear register? on page 1467 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 237 intel ? ep80579 integrated processor 08e0h 08e3h ?icr2: error interrupt cause read register? on page 1469 00000000h 08e8h 08ebh ?ics2: error interrupt cause set register? on page 1471 00000000h 08f0h 08f3h ?ims2: error interrupt mask set/read register? on page 1472 00000000h 08f8h 08fbh ?imc2: error interrupt mask clear register? on page 1473 00000000h 0100h 0103h ?rctl: receive control register? on page 1474 00000000h 2160h 2163h ?fcrtl: flow control receive threshold low register? on page 1478 00000000h 2168h 216bh ?fcrth: flow control receive threshold high register? on page 1479 00000000h 2800h 2803h ?rdbal: receive descriptor base address low register? on page 1480 xxxxxxx0h 2804h 2807h ?rdbah: receive descriptor base address high register? on page 1480 xxxxxxxxh 2808h 280bh ?rdlen: receive descriptor length register? on page 1481 00000000h 2810h 2813h ?rdh: receive descriptor head register? on page 1481 00000000h 2818h 281bh ?rdt: receive descriptor tail register? on page 1482 00000000h 2820h 2823h ?rdtr: rx interrupt delay timer (packet timer) register? on page 1483 00000000h 2828h 282bh ?rxdctl: receive descriptor control register? on page 1483 00010000h 282ch 282fh ?radv: receive interrupt absolute delay timer register? on page 1485 00000000h 2c00h 2c03h ?rsrpd: receive small packet detect interrupt register? on page 1486 00000000h 5000h 5003h ?rxcsum: receive checksum control register? on page 1487 00000000h 5200h at 4h 5203h at 4h ?mta[0-127] ? 128 multicast table array registers? on page 1488 xxxx_xxxxh 5400h at 8h 5403h at 8h ?ral[0-15] - receive address low register? on page 1488 xxxxxxxxh 5404h at 8h 5407h at 8h ?rah[0-15] - receive address high register? on page 1489 000xxxxxh 5600h at 4h 5603h at 4h ?vfta[0-127] - 128 vlan filter table array registers? on page 1490 xxxxxxxxh 0400h 0403h ?tctl: transmit control register? on page 1491 00000008h 0410h 0413h ?tipg: transmit ipg register? on page 1493 00602008h 0458h 045bh ?ait: adaptive ifs throttle register? on page 1495 00000000h 3800h 3803h ?tdbal: transmit descriptor base address low register? on page 1496 xxxxxxx0h 3804h 3807h ?tdbah: transmit descriptor base address high register? on page 1496 xxxxxxxxh 3808h 380bh ?tdlen: transmit descriptor length register? on page 1497 00000000h 3810h 3813h ?tdh: transmit descriptor head register? on page 1497 00000000h 3818h 381bh ?tdt: transmit descriptor tail register? on page 1498 00000000h 3820h 3823h ?tidv: transmit interrupt delay value register? on page 1499 00000000h 3828h 382bh ?txdctl: transmit descriptor control register? on page 1500 00000000h 382ch 382fh ?tadv: transmit absolute interrupt delay value register? on page 1502 00000000h 3830h 3833h ?tspmt: tcp segmentation pad and minimum threshold register? on page 1504 01000400h 4000h 4003h ?crcerrs: crc error count register? on page 1505 00000000h 4004h 4007h ?algnerrc: alignment error count register? on page 1506 00000000h 400ch 400fh ?rxerrc: receive error count register? on page 1506 00000000h 4010h 4013h ?mpc: missed packet count register? on page 1507 00000000h 4014h 4017h ?scc: single collision count register? on page 1507 0000h 4018h 401bh ?ecol: excessive collisions count register? on page 1508 00000000h table 7-55. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 2 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 238 order number: 320066-003us 401ch 401fh ?mcc: multiple collision count register? on page 1508 00000000h 4020h 4023h ?latecol: late collisions count register? on page 1509 00000000h 4028h 402bh ?colc: collision count register? on page 1509 00000000h 4030h 4033h ?dc: defer count register? on page 1510 00000000h 4034h 4037h ?tncrs: transmit with no crs count register? on page 1510 00000000h 403ch 403fh ?cexterr: carrier extension error count register? on page 1511 00000000h 4040h 4043h ?rlec: receive length error count register? on page 1511 00000000h 4048h 404bh ?xonrxc: xon received count register? on page 1512 00000000h 404ch 404fh ?xontxc: xon transmitted count register? on page 1512 00000000h 4050h 4053h ?xoffrxc: xoff received count register? on page 1513 00000000h 4054h 4057h ?xofftxc: xoff transmitted count register? on page 1513 00000000h 4058h 405bh ?fcruc: fc received unsupported count register? on page 1514 00000000h 405ch 405fh ?prc64: good packets received count (64 bytes) register? on page 1514 00000000h 4060h 4063h ?prc127: good packets received count (65-127 bytes) register? on page 1515 00000000h 4064h 4067h ?prc255: good packets received count (128-255 bytes) register? on page 1515 00000000h 4068h 406bh ?prc511 - good packets received count (256-511 bytes) register? on page 1516 00000000h 406ch 406fh ?prc1023: good packets received count (512-1023 bytes) register? on page 1516 00000000h 4070h 4073h ?prc1522: good packets received count (1024 to max bytes) register? on page 1517 00000000h 4074h 4077h ?gprc: good packets received count (total) register? on page 1518 00000000h 4078h 407bh ?bprc: broadcast packets received count register? on page 1518 00000000h 407ch 407fh ?mprc: multicast packets received count register? on page 1519 00000000h 4080h 4083h ?gptc: good packets transmitted count register? on page 1519 00000000h 4088h 408ah ?gorcl: good octets received count low register? on page 1520 00000000h 408ch 408fh ?gorch: good octets received count high register? on page 1521 00000000h 4090h 4093h ?gotcl: good octets transmitted count low register? on page 1522 00000000h 4094h 4097h ?gotch: good octets transmitted count high register? on page 1522 00000000h 40a0h 40a3h ?rnbc: receive no buffers count register? on page 1523 00000000h 40a4h 40a7h ?ruc: receive undersize count register? on page 1523 00000000h 40a8h 40abh ?rfc: receive fragment count register? on page 1524 00000000h 40ach 40afh ?roc: receive oversize count register? on page 1524 00000000h 40b0h 40b3h ?rjc: receive jabber count register? on page 1525 00000000h 40c0h 40c3h ?torl: total octets received low register? on page 1526 00000000h 40c4h 40c7h ?torh: total octets received high register? on page 1526 00000000h 40c8h 40cfh ?totl: total octets transmitted low register? on page 1527 00000000h 40cch 40cfh ?toth: total octets transmitted high register? on page 1528 00000000h 40d0h 40d3h ?tpr: total packets received register? on page 1528 00000000h 40d4h 40d7h ?tpt: total packets transmitted register? on page 1529 00000000h 40d8h 40dbh ?ptc64 - packets transmitted count (64 bytes) register? on page 1529 00000000h table 7-55. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 3 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 239 intel ? ep80579 integrated processor 40e0h 40e3h ?ptc255: packets transmitted count (128-255 bytes) register? on page 1530 00000000h 40e4h 40e7h ?ptc511: packets transmitted count (256-511 bytes) register? on page 1530 00000000h 40e8h 40ebh ?ptc1023: packets transmitted count (512-1023 bytes) register? on page 1531 00000000h 40ech 40efh ?ptc1522: packets transmitted count (1024-1522 bytes) register? on page 1531 00000000h 40f0h 40f3h ?mptc: multicast packets transmitted count register? on page 1532 00000000h 40f4h 40f7h ?bptc: broadcast packets transmitted count register? on page 1532 00000000h 40f8h 40fbh ?tsctc: tcp segmentation context transmitted count register? on page 1533 00000000h 40fch 40ffh ?tsctfc: tcp segmentation context transmit fail count register? on page 1533 00000000h 5800h 5803h ?wuc - wake up control register (0x05800; rw)? on page 1534 00000000h 5808h 580bh ?wufc - wake up filter control register (0x05808; rw)? on page 1535 00000000h 5810h 5813h ?wus - wake up status register (0x05810; rw)? on page 1536 00000000h 5838h 583bh ?ipav - ip address valid register (0x05838; rw)? on page 1537 00000000h 5840h at 8h 5607h at 8h ?ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers? on page 1538 xxxxxxxxh 5880h 5883h ?ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4? on page 1539 xxxxxxxxh 05884h 0588fh ?ipv6_addr0bytes_5_8 ? ipv6 address tabl e register, bytes 5 - 8? on page 1539 xxxxxxxxh 5888h 588bh ?ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12? on page 1540 xxxxxxxxh 588ch 588fh ?ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16? on page 1541 xxxxxxxxh 5f00h at 8h 5f03h at 8h ?fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw)? on page 1542 00000000h 9000h at 8h 9003h at 8h ?ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1543 0000000xh 9800h at 8h 9803h at 8h ?ffvt[0-127]: flexible filter value table registers? on page 1544 xxxxxxxxh 0510h 0513h ?intbus_err_stat - internal bus error status register? on page 1544 00000000h 0900h 0903h ?mem_tst - memory error test register? on page 1546 00000000h 0904h 0907h ?mem_sts - memory error status register? on page 1547 007f0000h table 7-55. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 4 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 240 order number: 320066-003us 7.4.3 gcu: bus m, device 3, function 0 the gcu includes the registers listed in ta b l e 7 - 5 6 and ta bl e 7 - 5 7 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 35.8, ?gcu configuration space: bus m, device 3, function 0? and chapter 38.0, ?register summary? for detailed discussion of these registers along with alternative materializations. table 7-56. bus m, device 3, function 0: summary of gcu pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1265 8086h 02h 03h ?offset 02h: did: device identification register? on page 1266 503eh 04h 05h ?offset 04h: pcicmd: device command register? on page 1266 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1267 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1268 variable 09h 0bh ?offset 09h: cc: class code register? on page 1268 ff0000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1268 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1269 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1269 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1270 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1270 dch dch dch ?offset dch: pcid: power management capability id register? on page 1270 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1271 00h deh dfh ?offset deh: pmcap: power management capability register? on page 1271 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1272 0000h table 7-57. bus m, device 3, function 0: summary of gcu registers mapped through csrbar memory bar (sheet 1 of 2) offset start offset end register id - description default value 00000010h 00000013h ?offset 0x00000010h: mdio_status - mdio status register? on page 1562 00000000h 00000014h 00000017h ?offset 0x00000014h: mdio_command - mdio command register? on page 1562 00000000h 00000018h 0000001bh ?offset 0x00000018h: mdio_drive - mdio drive register? on page 1563 03030107h 00000020h 00000023h ?offset 0x00000020h: mdc_drive - mdc drive register? on page 1563 0303030fh 00000024h 00000027h ?offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register? on page 1564 0031f31fh 00000044h 00000047h ?offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register? on page 1564 00000000h 00000050h 00000053h ?offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register? on page 1565 63000300h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 241 intel ? ep80579 integrated processor 00000054h 00000057h ?offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register? on page 1566 000030f301h 00000060h 00000063h ?offset 0x00000060h: ssp_drive - ssp drive register? on page 1566 02000200h 00000064h 00000067h ?offset 0x00000064h: tdm_drive_3 - tdm drive register for tdm ports 3? on page 1567 02000200h 00000068h 0000006bh ?offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2? on page 1567 02000200h 00000028h 0000002bh ?offset 0x00000028h: can_drive - can drive register? on page 1568 02000200h table 7-57. bus m, device 3, function 0: summary of gcu registers mapped through csrbar memory bar (sheet 2 of 2) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 242 order number: 320066-003us 7.4.4 can interface: bus m, device 4 and 5, function 0 the can interface includes the registers listed in ta b l e 7 - 5 8 through ta bl e 7 - 6 1 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 35.9, ?can controller configuration spaces: bus m, device 4-5, function 0? and chapter 39.0, ?detailed register descriptions? for detailed discussion of these registers along with alternative materializations. table 7-58. bus m, device 4, function 0: summary of can interface pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1275 8086h 02h 03h ?offset 02h: did: device identification register? on page 1275 5039h 04h 05h ?offset 04h: pcicmd: device command register? on page 1276 0h 06h 07h ?offset 06h: pcists: pci device status register? on page 1277 10h 08h 08h ?offset 08h: rid: revision id register? on page 1278 variable 09h 0bh ?offset 09h: cc: class code register? on page 1278 0c0900h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1279 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1279 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1280 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1280 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1281 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1281 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1282 01h 40h 40h ?offset 40h: canctl - can control register? on page 1282 00h dch dch ?offset dch: pcid: power management capability id register? on page 1283 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1283 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1284 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1284 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1285 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1285 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1286 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1286 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1287 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1287 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1288 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1288 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1289 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1289 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1290 0000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 243 intel ? ep80579 integrated processor table 7-59. bus m, devices 5, function 0: summary of can interface pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1275 8086h 02h 03h ?offset 02h: did: device identification register? on page 1276 503ah 04h 05h ?offset 04h: pcicmd: device command register? on page 1276 0h 06h 07h ?offset 06h: pcists: pci device status register? on page 1277 10h 08h 08h ?offset 08h: rid: revision id register? on page 1278 variable 09h 0bh ?offset 09h: cc: class code register? on page 1278 0c0900h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1279 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1279 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1280 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1280 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1281 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1281 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1282 01h 40h 40h ?offset 40h: canctl - can control register? on page 1282 00h dch dch ?offset dch: pcid: power management capability id register? on page 1283 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1283 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1284 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1284 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1285 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1285 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1286 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1286 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1287 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1287 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1288 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1288 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1289 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1289 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1290 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 244 order number: 320066-003us table 7-60. bus m, device 4, function 0: summary of can registers mapped through csrbar memory bar offset start offset end register id - description default value 00000000h 00000003h ?offset 00000000h: int_status - interrupt status register? on page 1587 00000000h 00000004h 00000007h ?offset 00000004h: int_ebl - interrupt enable register? on page 1588 00000000h 00000008h 0000000ah ?offset 00000008h: buffer status indicators? on page 1589 00000000h 0000000ch 0000000fh ?offset 0000000ch: errorstatus - error status indicators? on page 1590 00000000h 00000010h 00000013h ?offset 00000010h: command - operating modes? on page 1591 00000000h 00000014h 00000017h ?offset 00000014h: config - can configuration register? on page 1592 00000000h 00000020h at 10h 00000023h at 10h ?offset 00000020h: txmessagecontrol[0-7] - transmit message control and command? on page 1593 xxxxxxxxh 00000024h at 10h 00000027h at 10h ?offset 00000024h: txmessageid[0-7] - transmit message id? on page 1595 xxxxxxxxh 00000028h at 10h 0000002ah at 10h ?offset 00000028h: txmessagedatahigh[0-7] - transmit message data high? on page 1596 xxxxxxxxh 0000002ch at 10h 0000002fh at 10h ?offset 0000002ch: txmessagedatalow[0-7] - transmit message data low? on page 1597 xxxxxxxxh 000000a0h at 20h 000000a3h at 20h ?offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control? on page 1598 xxxxxxxxh 000000a4h at 20h 000000a7h at 20h ?offset 000000a4h: rxmessageid[0-15] - receive message id? on page 1600 xxxxxxxxh 000000a8h at 20h 000000abh at 20h ?offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high? on page 1600 xxxxxxxxh 000000ach at 20h 000000afh at 20h ?offset 000000ach: rxmessagedatalow[0-15] - receive message data low? on page 1601 xxxxxxxxh 000000b0h at 20h 000000b3h at 20h ?offset 000000b0h: rxmessageamr[0-15] - receive message amr? on page 1601 xxxxxxxh 000000b4h at 20h 000000b7h at 20h ?offset 000000b4h: rxmessageacr[0-15] - receive message acr? on page 1602 xxxxxxxxh 000000b8h at 20h 000000bbh at 20h ?offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data? on page 1603 xxxxxxxxh 000000bch at 20h 000000bfh at 20h ?offset 000000bch: rxmessageacr_data[0-15] - receive message acr data? on page 1604 xxxxxxxxh table 7-61. bus m, device 5, function 0: summary of can registers mapped through csrbar memory bar (sheet 1 of 2) offset start offset end register id - description default value 00000000h 00000003h ?offset 00000000h: int_status - interrupt status register? on page 1587 00000000h 00000004h 00000007h ?offset 00000004h: int_ebl - interrupt enable register? on page 1588 00000000h 00000008h 0000000ah ?offset 00000008h: buffer status indicators? on page 1589 00000000h 0000000ch 0000000fh ?offset 0000000ch: errorstatus - error status indicators? on page 1590 00000000h 00000010h 00000013h ?offset 00000010h: command - operating modes? on page 1591 00000000h 00000014h 00000017h ?offset 00000014h: config - can configuration register? on page 1592 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 245 intel ? ep80579 integrated processor 7.4.5 ssp interface: bus m, device 6, function 0 the ssp interface includes the registers listed in ta b l e 7 - 6 2 and ta b l e 7 - 6 3 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 35.10, ?ssp controller configuration space: bus m, device 6, function 0? and table 40.4, ?register summary? on page 1606 for detailed discussion of these registers along with alternative materializations. 00000020h at 10h 00000023h at 10h ?offset 00000020h: txmessagecontrol[0-7] - transmit message control and command? on page 1593 xxxxxxxxh 00000024h at 10h 00000027h at 10h ?offset 00000024h: txmessageid[0-7] - transmit message id? on page 1595 xxxxxxxxh 00000028h at 10h 0000002ah at 10h ?offset 00000028h: txmessagedatahigh[0-7] - transmit message data high? on page 1596 xxxxxxxxh 0000002ch at 10h 0000002fh at 10h ?offset 0000002ch: txmessagedatalow[0-7] - transmit message data low? on page 1597 xxxxxxxxh 000000a0h at 20h 000000a3h at 20h ?offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control? on page 1598 xxxxxxxxh 000000a4h at 20h 000000a7h at 20h ?offset 000000a4h: rxmessageid[0-15] - receive message id? on page 1600 xxxxxxxxh 000000a8h at 20h 000000abh at 20h ?offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high? on page 1600 xxxxxxxxh 000000ach at 20h 000000afh at 20h ?offset 000000ach: rxmessagedatalow[0-15] - receive message data low? on page 1601 xxxxxxxxh 000000b0h at 20h 000000b3h at 20h ?offset 000000b0h: rxmessageamr[0-15] - receive message amr? on page 1601 xxxxxxxh 000000b4h at 20h 000000b7h at 20h ?offset 000000b4h: rxmessageacr[0-15] - receive message acr? on page 1602 xxxxxxxxh 000000b8h at 20h 000000bbh at 20h ?offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data? on page 1603 xxxxxxxxh 000000bch at 20h 000000bfh at 20h ?offset 000000bch: rxmessageacr_data[0-15] - receive message acr data? on page 1604 xxxxxxxxh table 7-61. bus m, device 5, function 0: summary of can registers mapped through csrbar memory bar (sheet 2 of 2) offset start offset end register id - description default value table 7-62. bus m, device 6, function 0: summary of ssp controller pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1292 8086h 02h 03h ?offset 02h: did: device identification register? on page 1292 503bh 04h 05h ?offset 04h: pcicmd: device command register? on page 1292 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1293 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1294 variable 09h 0bh ?offset 09h: cc: class code register? on page 1295 078000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1295 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 246 order number: 320066-003us 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1295 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1296 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1296 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1297 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1297 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1297 01h dch dch ?offset dch: pcid: power management capability id register? on page 1298 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1298 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1298 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1299 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1300 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1300 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1300 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1301 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1301 00h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1302 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1302 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1302 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1303 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1303 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1304 0000h table 7-62. bus m, device 6, function 0: summary of ssp controller pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-63. bus m, device 6, function 0: summary of ssp csrs offset start offset end register id - description default value 00h 03h ?offset 00h: sscr0 - ssp control register 0 details? on page 1607 00000000h 04h 07h ?offset 04h: sscr1 - ssp control register 1 details? on page 1610 00000000h 08h 0bh ?offset 08h: sssr - ssp status register details? on page 1614 0000f004h 0ch 0fh ?offset 0ch: ssitr - ssp interrupt test register details? on page 1617 00000000 10h 13h ?offset 10h: ssdr - ssp data register details? on page 1618 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 247 intel ? ep80579 integrated processor 7.4.6 ieee 1588 timestamp unit: bu s m, device 7, function 0 the ieee 1588 timestamp unit includes the registers listed in ta bl e 7 - 6 4 and ta bl e 7 - 6 5 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 35.11, ?ieee 1588 hardware assist unit configuration space: bus m, device 7, function 0? and chapter 41.0, ?register summary? for detailed discussion of these registers along with alternative materializations. table 7-64. bus m, device 7, function 0: summary of ieee 1588 timestamp unit pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1306 8086h 02h 03h ?offset 02h: did: device identification register? on page 1306 503ch 04h 05h ?offset 04h: pcicmd: device command register? on page 1306 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1307 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1308 variable 09h 0bh ?offset 09h: cc: class code register? on page 1308 111000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1309 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1309 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1310 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1310 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1310 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1311 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1311 01h dch dch ?offset dch: pcid: power management capability id register? on page 1312 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1312 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1313 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1313 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1314 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1314 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1314 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1315 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1315 00h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1316 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1316 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1317 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1317 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1318 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1318 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 248 order number: 320066-003us table 7-65. bus m, device 7, function 0: summary of ieee 1588 tsync csrs (sheet 1 of 2) offset start offset end register id - description default value 00000000h 00000003h ?offset 0000h: ts_control register? on page 1639 00000000h 00000004h 00000007h ?offset 0004h: ts_event register? on page 1641 0022h 00000008h 0000000bh ?offset 0008h: ts_addend register? on page 1643 0000h 0000000ch 0000000fh ?offset 000ch: ts_accum register? on page 1643 0000h 00000010h 00000013h ?offset 0010h: ts_test register? on page 1644 0000h 00000014h 00000017h ?offset 0014h: ts_pps_compare register? on page 1646 ffffffffh 00000018h 0000001bh ?offset 0018h: ts_rsystimelo register? on page 1647 0000h 0000001ch 0000001fh ?offset 001ch: ts_rsystimehi register? on page 1648 0000h 00000020h 00000023h ?offset 0020h: ts_systimelo register? on page 1649 0000h 00000024h 00000027h ?offset 0024h: ts_systimehi register? on page 1650 0000h 00000028h 0000002bh ?offset 0028h: ts_trgtlo register? on page 1650 0000h 0000002ch 0000002fh ?offset 002ch: ts_trgthi register? on page 1651 0000h 00000030h 00000033h ?offset 0030h: ts_asmslo register? on page 1652 0000h 00000034h 00000037h ?offset 0034h: ts_asmshi register? on page 1653 0000h 00000038h 0000003bh ?offset 0038h: ts_ammslo register? on page 1654 0000h 0000003ch 0000003fh ?offset 003ch: ts_ammshi register? on page 1655 0000h 0040h at 20h 0043h at 20h ?offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel)? on page 1656 0000h 0044h at 20h 0047h at 20h ?offset 0044h: ts_ch_event[0-7] - time synchronization channel event register per ethernet channel)? on page 1658 0000h 0048h at 20h 004bh at 20h ?offset 0048h: ts_txsnaplo[0-7] - transmit snapshot low register (per ethernet channel)? on page 1659 0000h 004ch at 20h 004fh at 20h ?offset 004ch: ts_txsnaphi[0-7] - transmit snapshot high register (per ethernet channel)? on page 1660 0000h 0050h at 20h 0053h at 20h ?offset 0050h: ts_rxsnaplo[0-7] - receive snapshot low register (per ethernet channel)? on page 1661 0000h 0054h at 20h 0057h at 20h ?offset 0054h: ts_rxsnaphi[0-7] - receive snapshot high register (per ethernet channel)? on page 1662 0000h 0058h at 20h 005bh at 20h ?offset 0058h: ts_srcuuidlo[0-7] - source uuid0 low register (per ethernet channel)? on page 1663 0000h 005ch at 20h 005fh at 20h ?offset 005ch: ts_srcuuidhi[0-7] - sequenceid/sourceuuid high register (per ethernet channel)? on page 1664 0000h 0140h at 10h 0143h at 10h ?offset 0140h: ts_canx_status[0-1] - time synchronization channel event register (per can channel)? on page 1665 0000h 0144h at 10h 0147h at 10h ?offset 0144h: ts_cansnaplo[0-1] - transmit snapshot low register (per can channel)? on page 1666 0000h 0148h at 10h 014bh at 10h ?offset 0148h: ts_cansnaphi[0-1] - transmit snapshot high register (per can channel)? on page 1667 0000h 000001f0h 000001f3h ?offset 01f0h: ts_aux_trgtlo register? on page 1668 0000h 000001f4h 000001f7h ?offset 01f4h: ts_aux_trgthi register? on page 1668 0000h 00000200h 00000203h ?offset 0200h: l2 ethertype register? on page 1669 000088f7h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 249 intel ? ep80579 integrated processor 7.4.7 local expansion bus interface: bus m, device 8, function 0: the local expansion bus interface includes the registers listed in ta bl e 7 - 6 6 and ta bl e 7 - 6 7 . these registers materialize in pci configuration and memory (via pci bar) spaces. see section 35.12, ?expansion bus configuration space: bus m, device 8, function 0? , and table 42.5, ?register summary? on page 1696 for detailed discussion of these registers along with alternative materializations. 0000204h 0000207h ?offset 0204h: user defined ethertype register? on page 1669 00000000h 00000208h 0000020bh ?offset 0208h:user defined header offset register? on page 1670 00000000h 0000020ch 0000020fh ?offset 020ch:user defined header register? on page 1670 00000000h table 7-65. bus m, device 7, function 0: summary of ieee 1588 tsync csrs (sheet 2 of 2) offset start offset end register id - description default value table 7-66. bus m, device 8, function 0: summary of local expansion bus pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1320 8086h 02h 03h ?offset 02h: did: device identification register? on page 1320 503dh 04h 05h ?offset 04h: pcicmd: device command register? on page 1321 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1321 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1322 variable 09h 0bh ?offset 09h: cc: class code register? on page 1323 068000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1323 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1323 00000000h 14h 17h ?offset 14h: mmbar: expansion bus base address register? on page 1324 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1325 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1325 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1326 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1326 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1326 01h 40h 43h ?offset 40h: lebctl: leb control register? on page 1327 00h dch dch ?offset dch: pcid: power management capability id register? on page 1327 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1328 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1328 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1329 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1329 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1330 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1330 09h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 250 order number: 320066-003us e7h e7h ?offset e7h: styp: signal target capability type register? on page 1330 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1331 00h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1331 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1332 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1332 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1333 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1333 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1334 0000h table 7-66. bus m, device 8, function 0: summary of local expansion bus pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 7-67. bus m, device 8, function 0: summary of local expansion bus registers mapped through csrbar pci memory bar" offset start offset end register id - description default value 00000000h 00000003h ?exp_timing_cs0 - expansion bus timing register? on page 1698 bfff3c40h 00000004h at 4h 00000007h at 4h ?exp_timing_cs[1-7] - expansion bus timing registers? on page 1700 00000000h 00000020h 00000020h ?exp_cnfg0 -configuration register 0? on page 1702 00000040h 00000120h 00000123h ?exp_parity_status - expansion bus parity status register? on page 1703 00000000h
order number: 320066-003us ia-32 core and integrated memory controller hub, volume 2 of 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 252 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 253 intel ? ep80579 integrated processor 8.0 ia-32 core 8.1 overview the ep80579system-on-a-chip (soc) uses an ia-32 core, which is based on the intel ? pentium ? m processor (90 nm). major features include: ? 600 mhz, 1066 mhz and 1200 mhz operating frequencies ? fsb frequency of 400 mhz and 533 mhz. ? uni-directional fsb interface (on-chip) for soc applications ? 32 kbyte l1 split instruction and data caches ? 256 kbyte 2-way l2 cache with 64b lines ? soft error protection on l2 cache data and tags (via ecc), soft error protection on l1 cache data and tags (via parity) ? new cpu identifier (cpuid) note the differences between the ia-32 core and the intel ? pentium ? m processor (90 nm) are: ? core and fsb operating frequencies ? uni-directional fsb instead of bi-directional ? different cpu identifier (cpuid) ? reduced l2 cache size and ways ? de-featured intel speedstep ? technology (no vrm specification required) 8.2 theory of operation this section discusses several operational areas of ia-32 core. 8.2.1 l2 cache size the ia-32 core reduces the size and associativity of the l2 cache on the pentium m processor (90 nm)from 2mb 8-way to 256kb 2-way. 8.2.2 platform and jtag identifiers the platform id is a project-specific value. it is used solely for selecting a microcode update (i.e., patch) and is tightly-couple d to a specific cpuid number. bios and os software are aware of the platform id convention and automatically pick up the appropriate patch. there are two views to the platform id: the msr view and the patch view: the msr view is a 3-bit value read out of the processor?s fuse_msr[52:50]. this value is determined by three fuses and is unique per cpuid sku. the patch view is the binary value which represents two raised to the power of the msr view value. a microcode update is considered applicable to a specific processor if, and only if, the following condition is true:
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 254 order number: 320066-003us (((patch.header.cpuid == processor?s cpuid) && ((patch.header.platformid & 2^fuse_msr[52:50]) != 0)) the msr view of the ep80579 platform id is 100b . ta b l e 8 - 1 summarizes the format of the processor version identification signature (cpuid). 8.2.3 fsb physical interface the ia-32 core replaces the standard bi-directional, tri-state fsb interface found on the pentium m processor (90nm) with a uni-directional interface. this uni-directional interface is better suited for soc applications that use a single core. this modification replaces a single bi-directional wire with two uni-directional wires. 8.2.4 ia-32 core and fsb frequency the ep80579 is targeted to operate with ia-32 core frequencies of 600 mhz, 1066 mhz and 1200 mhz and fsb frequencies of 400 mhz (600 mhz sku) and 533 mhz (1066 mhz and 1200 mhz skus). table 8-1. processor version identification signature (cpuid) 31 28 27 20 19 16 1 5 1 4 1 3 1 2 11 8 7 4 3 0 extended family extended model typ e family model number stepping id 00000000000000010000011001010000
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 255 intel ? ep80579 integrated processor 9.0 cmi introduction this section details the system architecture supported by the memory controller hub and i/o controller hub complex. the memory controller hub and i/o controller hub are referred to collectively as the cmi (imch and ich). subsequent chapters cover the following aspects of the mch and the ich: ? description of the cmi architecture. ? descriptions of internal registers. ? descriptions of all external interfaces. the ep80579 is a single chip that integrates the functionality of an ia-32 core, memory controller hub, and an i/o controller hub (see figure 9-1 ). in this document the memory controller hub and i/o controller hub in cmi are referred to as imch (integrated memory controller hub) and iich (integrated i/o controller hub) respectively. the imch and iich units are connected internally through the nsi (north south interface). the nsi is an internal bus that is not externally accessible. figure 9-1. cmi block diagram iich 1x8 pci express configurable as 2x4, 2x1 lpc bus smbus interrupts 2 uart?s 2 ch sata 36 gpios rtc wdt nsi 2 usb-2.0 x8 smbus ddr2 ? (400, 533, 667, 800 ) unbuffered and registered ecc imch 4 channel edma 2 dimm max , 2 ranks max memory controller spi
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 256 order number: 320066-003us 9.1 system architecture cmi implements numerous rasum (reliability, availability, serviceability, usability and manageability) features on multiple interfaces. the imch and iich consist of: ? a memory controller. ? a four-channel, descriptor-chain-based enhanced dma (edma) controller. ? several i/o devices such as usb, sata, etc. ? one x8 pci express* interface, which may be split into a pair of independent x4 or x1 pci express* interfaces. desired i/o controller hub (iich) functions are integrated eliminating the requirement for a legacy i/o bridge. cmi also supports: ? two usb 2.0/1.1 ports ?two sata ports gen1/gen2 ?one lpc bus ?one spi port ?two uart port ?two smbus ports for additional information see section 11.3, ?configurations? on page 291 . 9.2 pci express* cmi provides one configurable x8 pci express interface with a maximum theoretical bandwidth of 4 gbyte/s (aggregate). the x8 pci express interface may alternatively be configured as two independent x4 or x1 pci express interfaces. cmi is a root-class component as defined in the pci express* interface specification, rev 1.0a . the pci express interfaces support connection of cmi to a variety of other bridges compliant with the same revision of the pci express* interface specification, rev 1.0a . for example, the intel ? 82571eb gigabit ethernet adaptor and the intel pci express i/o processor are directly supported on any of these pci express ports. other compatible pci express devices implement functionality such as graphics, hardware raid controllers and tcp/ip off-load engines. these devices are available from intel and/or third-party vendors. as required by the interface specification, cmi will automatically negotiate for and train a single lane (x1) link if an attached device on any logical port fails to establish a viable x4 or x8 connection. this does not imply a capability for cmi to support more than two independent pci express ports of any width simultaneously on the x8 port, nor does it imply that the remaining three lanes of a potential x4 port are useful once the associated link has been established for x1 operation. similarly, cmi will automatically negotiate for and train a single lane (x1) link if an attached device on any logical port fails to establish a viable x4 connection. external bridge devices such as pci or pci-x gigabit ethernet or raid storage devices are directly supported on the pci express ports. this does not preclude connection of the imch to other bridges compliant with the same revision of the pci express interface specification .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 257 intel ? ep80579 integrated processor 9.2.1 supported pci express configurations cmi pci express ports are setup using a configuration register. this register is ?devpres? bdf 000, offset 9ch, bits 2 and 3 which control device 2 and device 3 present. ta bl e 9 - 1 shows all of the valid combinations of this register. 9.2.1.1 low power sku with pci express ports removed to enable low power sku for configurations that do not utilize the pci express ports, the user can disable pci express ports and configuration bits for power savings. 9.3 supported debug and management interfaces the imch supports a target smbus interface for access and control of the imch through its configuration registers. a test access port (tap) interface is also supported for imch system debug purposes. the tap is capable of full read/write access to the entire internal imch register space. platforms based on cmi may also make use of the inter-chassis management bus (icmb) architecture to extend smbus based management throughout a desegregate multi-chassis platform solution. 9.4 supported imch integrated features this section provides a brief overview of internal imch features. the subsections are intended for use as an introduction and a quick reference. see section 9.5 for more detailed descriptions of these features. 9.4.1 edma controller the imch includes an integrated four-channel enhanced direct memory access (edma) controller to perform background data transfers between locations in main memory, or from main memory to a memory-mapped i/o destination. these transfers may be table 9-1. supported pci express configurations devpres dev2 en, dev3 en dev2 en, dev3 dis dev2 dis, dev3 en dev2 dis, dev3 dis strap auto negotiate 1x8, 2x4, lower 1x4, upper 1x4 1x8, lower 1x4 not supported all disabled 2x4 2x4 lower 1x4 upper 1x4 all disabled 1x8 1x8 1x8 not supported all disabled
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 258 order number: 320066-003us individually designated to be coherent (snooped on the fsb) or non-coherent (not snooped on the fsb), providing improvements in system performance and utilization when cache coherence is managed by software rather than hardware. each of the four channels implements an independent set of configuration and status registers, and is capable of fully independent operation. each channel may operate in a single block transfer mode, or a hardware traversed linked-list scatter/gather mode. the internal edma controller only supports transfers between main memory locations, and transfers from a main memory source to an i/o subsystem destination. the internal edma controller supports neither transfers between i/o interfaces, nor transfers from an i/o interface source to a main memory destination. 9.4.2 integrated memory init/test engine the imch provides hardware-managed ecc memory auto-initialization and testing of all populated dram space under software control. once internal configuration has been updated to reflect the type and size of populated dimm, the imch can traverse the populated address space issuing line-sized writes of all zero data, thereby initializing all locations with good ecc memory. this greatly speeds up the mandatory memory initialization step and frees the cpu to pursue other machine initialization and configuration tasks. additional features have been added to the initialization engine to support high-speed population and verification of a programmable memory range with one of eight known data patterns, random data, a wa lking data pattern, or an explicitly specified cache line (data plus ecc). this function facilitates a limited high-speed memory test and provides bios-accessible memory testing capability for potential use by management code or by the operating system. for additional information see section 11.2, ?memory controller feature list? on page 289 . 9.4.3 coherent memory write buffer the imch includes an integrated coherent write buffer sized for 16 64-byte cache lines (a total of 1 kbyte of storage). this feature enables the imch to optimize memory read latency, allowing reads to pass less critical writes en-route to the main memory store. the write buffer includes a cam structure to enforce ordering among conflicting accesses to the same cache line, as well as to provide for read service from the write cache. in the latter case, the access to the main memory store never occurs, which both improves latency and conserves bandwidth on the memory interface. the write buffer is capable of servicing processor read requests directly via a ?hit? to the internal location containing the data without initiation of any ddr subsystem accesses. inbound read requests such as pci express, i.e. not processor, which ?hit? the write buffer result in a flush of the target data, followed by retrieval via an external read request. processor writes to shared non-coherent address space with the asu result in a flush of the current cacheline to main memory. asu atomics will result in a dw write to the asu out of the write cache. 9.4.4 rasum features the imch is designed to bring enterprise-level reliability, availability, serviceability, usability, and manageability to the embedded platform. all internal sram memory arrays are covered by parity. cmi?s pci express interface supports detection and automatic recovery for all transient signaling errors. all imch internal configuration
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 259 intel ? ep80579 integrated processor register space is accessible from the system management bus (smbus) to facilitate system management. the imch supports acpi power management, pci express native hot-plug, and wake-from-lan to maximize platform stand-by flexibility. 9.4.4.1 sec-ded ecc the imch supports a standard (72-bit, non-interleaved) single error correction (sec) and double error detection (ded) ecc mechanism for the ddr memory. the imch supports both ecc and non-ecc dimms. for additional information see section 11.2, ?memory controller feature list? on page 289 . 9.4.4.2 integrated memory scrub engine the imch includes an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem. this hardware detects, logs, and corrects any single-bit ecc errors it encounters, and logs any uncorrectable errors it encounters. both types of errors may be reported via multiple alternate mechanisms under configuration control. the scrub hardware will also execute ?demand scrub? writes when correctable errors are encountered during normal operation (on demand reads, rather than scrub-initiated reads). this functionality provides incremental protection against time-based deterioration of soft memory errors from correctable to uncorrectable. an uncorrectable error encountered by the memory scrub engine is a ?speculative error.? this designation is applied because no system agent has specifically requested use of the corrupt data, and no real error condition exists in the system until that occurs. it is possible that the error resides in an unmodified page of memory that is simply dropped on a swap back to disk. if that were to occur, the speculative error would simply ?vanish? from the system without any adverse consequences. 9.5 imch feature list this section provides an overview of the major imch architectural features. detailed usage information and operational flows, internal register bit information and other specific details of the implementation are provided later in this document. 9.5.1 memory interface for additional information see section 11.2, ?memory controller feature list? on page 289 . 9.5.2 pci express interface in imch ? support for one x8 pci express dual-simplex, high-speed serial i/o interface with eight striped differential pairs in each direction (outbound and inbound) ? the interface may be unpopulated; connected to pci, ethernet, i/o processor, infiniband* bridge devices, external bridge devices (pci or pci-x gigabit ethernet or raid storage devices); or connected to any other device compliant with the same revision of the pci express specification as cmi. ? the x8 interface is capable of bifurcation into two logically independent x4 interfaces with full specification compliance at half the bandwidth capability ? this interface is referred to throughout this document as the pci express port a (pea). when configured as x8, the reference is pea. when in x4 mode there are two available x4 ports referred to as pea0 and pea1.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 260 order number: 320066-003us ? raw bit-rate on the data pins of 2.5 gbit/s. ? maximum theoretical realized bandwidth on the x8 pci express interface of 2 gbyte/s in each direction simultaneously, for an aggregate of 4 gbyte/s. ? maximum theoretical realized bandwidth on the x4 pci express interface of 1 gbyte/s in each direction simultaneously, for an aggregate of 2 gbyte/s per port. ? x8 sustainable data bandwidth is approximately 1.6 gbyte/s in each direction simultaneously ? plesiochronous operation with automatic clock extraction and phase correction at the receiver. ? hierarchical pci-compliant configuration mechanism for downstream devices ? support for pci express memory-mapped enhanced configuration mechanism, up to 4 kbyte per device. ? 64 bit addressing support. ? 64 bit upstream addressing (full dac support), limited to 32 bits internally to/ from system memory (external ddr). ? 32 bit downstream addressing support. ? full 36 bit support for peer segment accesses. note: only 32-bit addresses can be snooped. addresses larger than 32 bits will be truncated. e.g. if a 36-bit address is snooped the upper 4 bits are ignored. ? full-speed interface self-test and diagnostic (ibist) functionality. ? automatic discovery, negotiation, and training of pci express ports out of reset. ? automatic detection of widest operational link; x8, x4 or x1. ? no support for hot-plug via an external smbus connected device. ? run-time detection and recovery for loss of link synchronization. ? 32 bit crc (cyclic redundancy checking) on all transaction layer packets with link- level retry on error (recovery from transien t errors without software-visible system failure). ? 16 bit crc on all link message information ? no support for the optional extended crc (ecrc) mechanism ? aggressive transceiver design to facilitate flexible system topologies ?target ber of 10 -12 for physical signaling interface ? support for peer segment destination write traffic (no peer-to-peer read traffic) ? support for coherent and non-coherent transactions through edma to pea to external agent ? support for both coherent and non-coherent traffic to memory within vc#0 ? non-coherent implies a combination of snoop-not-required and relaxed- ordering attributes ? coherent traffic implies a combination of snoop-required and strong-ordering attributes. ? support for lane reversal at all native widths, and for reversed x4 training on any x8 port ? support for peer segment pci interrupt forwarding to the iich for boot from i/o ? legacy mode support for level-sensitive interrupt emulation without ioxapic support
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 261 intel ? ep80579 integrated processor ? apic and msi interrupt messaging support dma internal score-boarding to translate messages into level-sensitive iich pin semantics ? xtpr-based interrupt redirection for apic messages with lowest priority tie breaking ? support for up to 256b read completion combining ? support for link messaging to facilitate active link and device power state management ? support for aspm l0s entry, no support for optional l1 aspm support ? no support for inbound configuration or i/o traffic ? no support for inbound special cycles or writes requiring completions ? no support for downstream special cycle messages requiring completions 9.5.3 edma controller ? four independent channels ? dedicated data transfer queue per channel ? full register set for descriptor and transfer handling per channel ? support for transfer between main memory locations, and from memory to the i/o subsystem ? supports pci express traffic class to allow external prioritization of traffic ? supports transfers only between two physical addresses ? 32 bit (4 gb) addressing range on the local system memory interface ? 32 bit addressing range on the memory mapped i/o subsystem interface ? maximum transfer of 16 mbyte transfers per block ? fully programmable by the host cpu ? configuration space mapping for dma engine capability and control ? memory-mapped space for dma channel-specific register sets ? chain mode dma transfer with automatic data chaining for scattering/gathering of data blocks ? dma chaining continued until a ?null? descriptor pointer is encountered ? support for appending a block to the end of current dma chain ? automated descriptor retrieval from ddr during chaining ? single read ? programmable independent alignment between source and destination ? byte aligned transfer on the ddr memory interface ? byte aligned transfer on the i/o subsystem interface ? support for non-coherent transfers both to and from system memory on a per descriptor basis ? independent control of coherency for source and destination ? programmable support for interrupt generation on block?by-block basis ? selectable msi or legacy level-sensitive interrupt function ? end of current block transfer ? end of current chain ? for any error causing a transfer to abort
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 262 order number: 320066-003us ? increment of the source and destination address for standard transfers ? increment of the destination and decrement of the source address to enable byte stream reversal. ? constant address mode for the destination address based on the transfer granularity to enable targeting of memory mapped i/o fifo devices ? buffer/memory initialization mode 9.5.4 coherent memory write buffer ? support for 16 64-byte cache-lines of write data ? fully associative conflict detection for accesses targeting memory ? read around write support (non-conflicting) for all traffic to memory ? read-hit support for cpu traffic to memory ? direct data service from buffer without generation of memory traffic ? write-hit support for memory traffic with address conflicts ? hardware-based merging to collapse down to a single memory write ? opportunistic and demand (buffer full) mode processing of pending writes ? configurable ?watermark? mechanism for hardware-based prioritization ? flush on demand via software configuration mechanism ? parity protection on all data ? data poisoning capability in the main store for data received with errors ? processor writes to shared non-coherent address space with the asu result in a flush of the current cacheline to main memory ? asu atomics will result in a dw write to the asu out of the write cache 9.5.5 integrated memory scrub engine for additional information see section 11.2, ?memory controller feature list? on page 289 . ? periodic (programmable) read-modify-write algorithm ? support for the sec-ded mode of operation ? automatic correction of encountered sec errors ? logging of detected errors with granularity to isolate dram device ? support for logging of both first and next subsequent error ? count of errors beyond the first two which are logged ? support for on-demand hardware scrub of sec errors detected during normal operation ? programming interface permits software suspend/resume of scrub in progress 9.5.6 hardware memory initialization engine ? available via bios for hardware memory initialization and/or test ? provides fast whql initialization of all populated dram space to ?0? with good ecc ? target region may be a single location, an entire rank, or all populated ranks ? algorithm optimized for speed, runs at ddr channel saturation rate
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 263 intel ? ep80579 integrated processor ? test extensions permit high-speed population of a target range with a known pattern ? selectable hardware-generated fixed patterns: 0, 3, 5, 6, 9, a, c, f ? hardware generated random pattern capability ? explicitly stipulated data pattern including ecc ? high speed verification capability ? selectable write-only, verify-only, or write-read-verify per location ? logs error location, optional stop and escalate on error detection ? may be made available to the operating system via bios for security ?clear to 0? function 9.5.7 system management functions ? full smbus target support ? support for remote chassis management via the icmb architecture ? serial presence detect of memory devices via standard i 2 c protocol (accessed via iich) ? acpi and pci-pm compatible power management ? includes pme support comprehending pci express extensions ? msi interrupt messaging and redirection support ? hardware relay of pci express legacy mode pci interrupt messages to iich ? supports boot from i/o when ioxapic functions are unavailable 9.5.8 rasum ? sec/ded ecc protection of external memory dram data ? parity protection on internal data propagated through the imch ? crc on data packets and hardware link-level retry on nsi to the iich ? 32-bit crc on data packets and hardware link-level retry on pci express ports ? hardware memory initialization ? true ?clear-to-zero? via hardware writes to all populated devices ? support for hardware-based fast initialization of memory with selectable patterns ? support for hardware-based fast verification of memory via accelerated scrub ? hardware periodic memory scrubbing, including demand scrub support ? flexible extended error reporting capabilities ? configurable error containment at i/o interfaces (poison/propagate or stop/ escalate) ? partial access to internal configuration registers via the tap port ? full access to internal configuration registers via smbus port
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 264 order number: 320066-003us 9.6 iich feature list this section provides a listing of architectural functionality for the major features of the iich. detailed usage information and operational flows, internal register bit information, and other specific details of the implementation are provided later in this document. 9.6.1 low-pin count (lpc) interface and firmware hub (fwh) interface ? allows connection of devices such as super i/o, micro controllers, customer asics. ? supports two master/dma devices. ?memory size up to 8 mbit. 9.6.2 serial peripheral interface (spi) note: intel recommends using the spi as your boot interface. ? supports multiple spi flash vendors. ? simplified hardware. ? equivalent to lpc-based firmware hubs. 9.6.3 integrated serial ata host controllers ? independent dma operation on two ports. ? two ports in sata 1.0a and ahci mode. ? two ports in ahci mode only. ? data transfer rates up to 300 mbyte/s. ? support gen2m electrical spec (cable not exceeding 2m). 9.6.4 usb ? one ehci usb 2.0 host controller with a total of two ports (shared with the uhci ports). ? one uhci host controller for a total of two ports (shared with the ehci ports). ? supports a debug port at usb 2.0 transfer rates. 9.6.5 interrupt controller ? supports up to 8 pci interrupt pins. ? two cascaded 82c59 with 15 interrupts. ? integrated i/o apic supports a total of 40 interrupts (24 interrupts only, when etr3.gpio_irq_strap_sts is 0). ? serial interrupt input for isa legacy-compatible and pci interrupts. ? supports pci scheme for delivering interrupts as write cycles (rather than via pirq[a-h]#). ? front-side message interrupt delivery. ? supports eoi message.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 265 intel ? ep80579 integrated processor 9.6.6 power management logic power management logic for various environments require updates. ? acpi 2.0 compliant. ? support for apm-based legacy power management for non-acpi implementations. ? supports acpi defined power states s0, s1, s3 cold, s4 and s5 (soff). ? acpi power management timer. ?smi# generation. ?pci pme#. 9.6.7 dma controller ? two cascaded 8237 dma controllers. ?supports lpc dma. 9.6.8 timers based on 82c54 ? system timer, refresh request, speaker tone output. 9.6.9 high precision event timers (hpet) ? three timer comparators provided. ? one-shot and periodic interrupts supported. 9.6.10 real-time clock with 256-byte battery-backed cmos ram ? integrated components for the oscillator to reduce problems with incorrect external selections. ? lower power dc/dc converter implementation. 9.6.11 system tco reduction circuits ? timers to detect improper cpu reset and to generate smi# and reset upon detection of stuck cpu. ? interrupt capability to os-specific manageability extension and os capability to call tco bios. ?supports cpu bist. ? ability to disable external devices. 9.6.12 smbus ? host interface allows cpu to communicate via smbus. ? compatible with most 2-wire components that are also i 2 c compatible. ? slave interface allows internal or external microcontroller to access system resources. ? smbus 2.0 compliant. ? no asf support.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 266 order number: 320066-003us 9.6.13 watchdog timer ? selectable prescaler: ? approximately 1 mhz (1 s to 1 s). ? approximately 1 khz (1 ms to 10 min.) ? 33 mhz clock (30 ns clock ticks). ? multiple modes (wdt and free-running). ? free-running mode: ?one stage timer. ? toggles wdt_tout# after programmable time. ?wdt mode: ? two stage timer (first stage generates interrupt, second stage drives wdt_tout# low). ? first stage generates an serirq, nmi or smi interrupt after programmable time. ? second stage drives wdt_out# low or inverts the previous value. ? used only after first timeout occurs. ? status bit preserved in rtc well for possible error detection and correction. ? drives wdt_tout# if output is enabled. ? timer can be disabled (default state) or locked (hard reset required to disable wdt). ? wdt automatic reload of preload value when wdt reload sequence is performed. 9.6.14 serial port ? two full function 16550 compatible serial ports. ? configurable i/o addresses and interrupts. ? 16-byte fifos. ? supports up to 115 kbps. ? programmable baud rate generator. ? modem control circuitry. ? 14.7456 mhz and 48 mhz supported for uart baud clock input. 9.6.15 gpio ? general purpose i/os . ? there are 36 gpio pins of which 5 have alternate power on functions.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 267 intel ? ep80579 integrated processor 10.0 system address map 10.1 overview the ia-32 core addressable memory map is 32 bits or up to 4 gbytes and has 64 kbytes+3 of addressable i/o space. the i/o and memory spaces are divided by system configuration software into non-overlapping regions. the memory ranges are useful either as system memory or as specialized memory, while the i/o regions are used solely to control the operation of devices in the system. there are five basic regions of memory in the system. the regions are shown in ta bl e 1 0 - 1 . figure 10-1 illustrates the basic memory regions. table 10-1. regions of memory ranges range description between top of main memory and 64 gbytes high pci memory range between 4 gbytes and top of main memory between tolm register and 4 gbytes low pci memory address range between 1 mbyte and the tolm register main memory address range below 1 mbyte dos legacy address range figure 10-1. basic memory regions 1 mb top of low memory 4 gb 64 gb apic, pci express, and nsi, non overlapping windows additional main memory address range lo pci memory address range main memory address range dos legacy address range additional main memory address range
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 268 order number: 320066-003us 10.1.1 system memory spaces ta b l e 1 0 - 2 ?s address ranges are always mapped to system memory, regardless of the system configuration. the top of low memory (tolm) register (see section 16.1.1.30, ?offset c4h: tolm - top of low memory register? ) provides a mechanism to carve memory out of the mainmem segment for use by system management mode (smm) hardware and software, pci add-in devices, and other functions. the address of the highest 128 mbyte quantity of populated dram memory in the system is placed into the drb3 register, which will match the value in the top of memory (tom) register (see section 16.1.1.34, ?offset cch: tom - top of memory register? . 10.1.2 vga and mda memory spaces ta b l e 1 0 - 3 lists the vga and mda memory spaces. figure 10-2 illustrates the dos legacy region. these legacy address ranges are used on behalf of video cards to map a frame buffer or a character-based video buffer into a dedicated location. by default, accesses to these ranges are forwarded to the nsi. however, if the vgaen bit is set in one of the bctrl configuration registers (see section 16.4.1.26, ?offset 3eh: bctrl - bridge control register? ), then transactions within the vga and mda spaces are sent to one of the pci express interfaces in imch. note: the vgaen bit may be set in one and only one of the bctrl registers. software must not set more than one vgaen bit. table 10-2. system memory space from to dosmem 0_0000_0000 0_0009_ffff mem1_15 0_0010_0000 0_00ef_ffff mainmem 0_0100_0000 tolm highmem 1_0000_0000 7_ffff_ffff table 10-3. imch vga and mda memory spaces from to vgaa 0_000a_0000 0_000a_ffff mda 0_000b_0000 0_000b_7fff vgab 0_000b_8000 0_000b_ffff
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 269 intel ? ep80579 integrated processor if the configuration bit exsmrc.mdap (see section 16.1.1.25, ?offset 9dh: exsmrc - extended system management ram control register? ) is set, then accesses that fall within the mda range are sent to nsi without regard for the vgaen bits. legacy support requires the ability to have a second graphics controller (monochrome display adapter) in the system. in a cmi system with pci graphics installed via a pcie to pci bridge like pxh, accesses in the standard vga range may be forwarded to any of the logical pci express ports (depending on configuration bits). since the monochrome adapter may be on the nsi (or logical isa) bus, the imch must decode cycles in the mda range and forward them to nsi. this capability is controlled via the mdap configuration bit. in addition to the memory range b0000h to b7fffh, the imch decodes i/o cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh and forwards them to nsi. an optimization allows the system to reclaim the memory displaced by these regions. if smm memory space is enabled by exsmrc.g_smrame and either the smram.d_open bit (see section 16.1.1.25, ?offset 9dh: exsmrc - extended system management ram control register? and section 16.1.1.26, ?offset 9eh: smram - system management ram control register? ) is set or the processor bus receives an smm-encoded request for code (not data), then the transaction is steered to system memory rather than nsi. under these conditions, both the vgaen bits and the mdap bit are overridden. if any vgaen bit is set, then all isaen bits (see section 16.4.1.26, ?offset 3eh: bctrl - bridge control register? ) must be set. the pci specification defines vgaen to be 10- bit decode. therefore the other peer bridges must also be 10-bit decodes (isaen), so that two or more devices don't claim same access. (bridge c doesn't know bridge b has its vgaen bit set.) figure 10-2. dos legacy region upper, lower, expansion card bios and buffer area vgab 1mb 640 kb 768 kb 0c0000h 0a0000h controlled by pam[6:0]. monchrome display adapter space vgaa standard pci/isa video memory (smm memory) 0b8000h 0b0000h 736 kb 704 kb controlled by vga enable and mda enable. = dram key = optionally dram 10 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 270 order number: 320066-003us the mda bit may only be set when one of the vgaen bits is set. if no vgaen bit is set, then mda must not be set either. when the vga range is already mapped onto the nsi interface, the mda range is included as a subset, and the mda enable is meaningless. 10.1.3 pam memory spaces the address range for the pam memory space is defined in ta bl e 1 0 - 4 . the 256 kbyte programmable access memory (pam) region is divided into three parts: ? isa expansion region, a 128 kbyte area between 0_000c_0000h ? 0_000d_ffffh. ? extended bios region, a 64 kbyte area between 0_000e_0000h ? 0_000e_ffffh. ? system bios region, a 64 kbyte area between 0_000f_0000h ? 0_000f_ffffh. specialized programmable hardware in the imch supports routing of read and write accesses within the pam region independently to memory or to nsi. non-snooped transactions are treated accordingly: ? non-snoop reads: memory address 0h. the result is an unsupported request (ur) completion. ? non-snoop writes: memory address 0h with byte enables deasserted. the isa expansion region is divided into eight 16 kbyte segments. each segment can be assigned one of four read/write memory states: read-only, write-only, read/write, or disabled. these segments are typically set to disabled for memory access, which leaves them routed to nsi for isa space. table 10-4. imch pam memory address ranges from to access region pamc0 0_000c_0000 0_000c_3fff isa expansion (16kb/each) pamc4 0_000c_4000 0_000c_7fff pamc8 0_000c_8000 0_000c_bfff pamcc 0_000c_c000 0_000c_ffff pamd0 0_000d_0000 0_000d_3fff pamd4 0_000d_4000 0_000d_7fff pamd8 0_000d_8000 0_000d_bfff pamdc 0_000d_c000 0_000d_ffff pame0 0_000e_0000 0_000e_3fff extended bios (16kb/each) pame4 0_000e_4000 0_000e_7fff pame8 0_000e_8000 0_000e_bfff pamec 0_000e_c000 0_000e_ffff pamf0 0_000f_0000 0_000f_ffff system bios (64kb)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 271 intel ? ep80579 integrated processor the extended system bios region is divided into four 16 kbyte segments. each segment can be assigned independent read and write attributes so it can be mapped either to main dram or to nsi. typically, this area is used for ram or rom. the system bios region is a single 64 kbyte segment. this segment can be assigned independent memory read and write attributes. it is by default (after reset) read/write disabled and cycles are forwarded to nsi. by manipulating the read/write attributes, the imch can ?shadow? bios into the main dram. the term ?shadow? is used to describe the condition where rom memory has been duplicated into main memory; such that reads are serviced from memory, while writes are directed back to the original rom device. such a configuration allows low-latency reads of bios information from the rom while preventing malicious or inadvertent alteration of the bios information in use. note: the pam regions are generally inaccessible from the logical pci express ports. all inbound writes from any port that hit the pa m regions are sent to nsi, which prevents corruption of non-volatile data shadowed in main memory. all inbound reads from any port that hit the pam regions are harmlessly terminated internally; data is returned, but not necessarily from the requested address. transaction routing is not hardware enforced based on the settings in the pam configuration registers. note: the pam regions are inaccessible from the logical aioc port. all inbound reads/writes from any port that hit the pam regions are master aborted by the aioc preventing them from ever pushed into the imch. figure 10-3. memory region from 1 mbyte through 4 gbytes key 1_0000_0000 (4gb) local apic space fef0_0000 fee0_0000 pea i/o apic space fec8_6000 top of low memory (tolm) fec0_0000 nsi i/o apic space fec8_0000 high bios, optional extended smram ff00_0000 = region allowed for mmio below 4gb pci express enanced config. aperture = dram region 00f0_0000 (15 mb) isa hole 0100_0000 (16 mb) 0010_0000 (1mb) = optional dram region =nsi (always) tseg smram space tolm - tseg e000_0000 f000_0000 fec8_2000 unused i/o apic space
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 272 order number: 320066-003us the imch allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kbyte to 1 mbyte (c0000h ? fffffh) and 640 kbytes to 1 mbyte address range. seven programmable attribute map (pam) registers are used to support these features. not all seven of these registers are identical. pam0 controls only one segment (high), while pam[1:6] each control two segments (high and low). cache ability of these areas is controlled via the mtrr registers in the processor. the following two bits apply to both host accesses and pci initiator accesses to the pam areas and are used to specify the memory attributes for each memory segment: these bits apply to both host accesses and pci initiator accesses to the pam areas re read enable. when re = 1, the ia-32 core read accesses to the corresponding memory segment are claimed by the imch and directed to main memory. conversely, when re = 0, the host read accesses are directed to the iich?s pci bus. we write enable. when we = 1, the host write accesses to the corresponding memory segment are claimed by the imch and directed to main memory. conversely, when we = 0, the host write accesses are directed to the iich?s pci bus. together, these two bits specify memory attributes (read-only, write only, read/write and disabled) for each memory segment. these bits only apply to host-initiated access to the pam areas. the imch forwards to main memory any pci express initiated accesses to the pam areas. at the time such pci express accesses to the pam region may occur, the targeted pam segment must be programmed to read/write. it is illegal to issue a pci express initiated transaction to a pam region with the associated pam register not set to read/write. as an example, consider a bios that is implemented on the expansion bus. during the initialization process, bios can be shadowed to main memory to increase system performance. when bios is shadowed to main memory it must be copied to the same address location. to shadow the bios, the attributes for that address range must be set to write-only. the bios is shadowed by first doing a read of that address, which is forwarded to the expansion bus. the host then writes the same address, which is directed to main memory. after bios is completely shadowed, the attributes for that memory area are changed to read-only so that all writes are forwarded to the expansion bus. figure 10-4 and ta bl e 1 0 - 5 show the pam registers and the associated attribute bits.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 273 intel ? ep80579 integrated processor figure 10-4. pam associated attribute bits table 10-5. pam associated attribute bits pam reg attribute bits memory segment comments d0:f0 offset pam0 03:00, 07:06 reserved ? reserved 59h pam0 05:04 we re 0f0000h?0fffffh bios area 59h pam1 03:02, 07:06 reserved ? reserved 5ah pam1 01:00 we re 0c0000h?0c3fffh bios area 5ah pam1 05:04 we re 0c4000h?0c7fffh bios area 5ah pam2 03:02, 07:06 reserved ? reserved 5bh pam2 01:00 we re 0c8000h?0cbfffh bios area 5bh pam2 05:04 we re 0cc000h?0cffffh bios area 5bh pam3 03:02, 07:06 reserved ? reserved 5ch pam3 01:00 we re 0d0000h?0d3fffh bios area 5ch pam3 05:04 we re 0d4000h?0d7fffh bios area 5ch pam4 03:02, 07:06 reserved ? reserved 5dh pam4 01:00 we re 0d8000h?0dbfffh bios area 5dh pam4 05:04 we re 0dc000h?0dffffh bios area 5dh pam5 03:02, 07:06 reserved ? reserved 5eh pam5 01:00 we re 0e0000h?0e3fffh bios extension 5eh pam5 05:04 we re 0e4000h?0e7fffh bios extension 5eh pam6 03:02, 07:06 reserved ? reserved 5fh pam6 01:00 we re 0e8000h?0ebfffh bios extension 5fh pam6 05:04 we re 0ec000h?0effffh bios extension 5fh pam6 5fh pam1 pam2 pam3 pam4 pam5 5ah 5bh 5ch 5dh 5eh offset we r r re r we re r 70 1 2 3 4 5 6 reserved reserved w rite enable (r/w ) 1 = enable 0 = disable read enable (r/w ) 1 = enable 0 = disable reserved reserved w rite enable (r/w ) 1 = enable 0 = disable read enable (r/w ) 1 = enable 0 = disable 59h pam0 hi segment lo segment reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 274 order number: 320066-003us see section 16.1.1.17, ?offset 59h: pam0 - programmable attribute map 0 register? through section 16.1.1.23, ?offset 5fh: pam6 - programmable attribute map 6 register? for more register information on pam memory space registers. 10.1.4 tseg smm memory space the tseg smm space allows system management software to partition a region of main memory just below the top of low memory (tolm) that is accessible only by system management software. size 128kb, 256kb, 512kb, or 1 mbyte in size, depending upon the exsmrc.tseg_sz field (see section 16.1.1.25 ).this space must be below 4 gbytes, so it is specified relative to tolm and not relative to the top of physical memory. enabling smm memory is globally enabled by exsmrc.g_smrame (see section 16.1.1.25 ). requests may access smm system memory when either smm space is open (see smram.d_open in section 16.1.1.26 ) or the imch receives an smm code request on its processor bus. access in order to access the tseg smm space, the tseg must be enabled by exsmrc.t_en ( section 16.1.1.25 ). when all of these conditions are met, then a processor bus access to the tseg space (between tolm-tseg and tolm) is sent to system memory. if the high smram is not enabled or if the tseg is not enabled, then all memory requests from all interfaces are forwarded to system memory. if the tseg smm space is enabled, and an agent attempts a non-smm access to tseg space, then the transaction is specially terminated. inbound accesses from nsi or pci express ports are not allowed to access smm space. 10.1.5 pci express enhanced configuration aperture pci express defines a memory-mapped aperture mechanism through which to access 4 kbyte of pci configuration register space for each possible bus, device, and function number. this 4 kbyte space includes the compatible 256 b of register offsets that are traditionally accessed via the legacy cf8/cfc configuration aperture mechanism in i/o address space, making the enhanced configuration mechanism a full superset of the legacy mechanism. the enhanced mechanism has the advantage that full destination and type of access is specified in a single memory-mapped uncacheable transaction on the fsb, which is both faster and more robust than the historical i/o-mapped address and data register access pair. table 10-6. tseg smm memory space from to tsegsmm tolm - tseg tolm table 10-7. pci express enhanced configuration aperture from to hecregion 0_e000_0000 0_efff_ffff
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 275 intel ? ep80579 integrated processor cmi places the enhanced configuration aperture at e000_0000h by default, as this is the first contiguous 256 mbyte location below the 4 gbyte boundary available for such usage. cmi provides for relocation of this aperture via the hecbase register (see section 16.1.1.35, ?offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register? , although validation of moving the region is minimal. 10.1.6 ioapic memory space the ioapic spaces are used to communicate with ioapic interrupt controllers that may be populated on nsi through pci-express port a (pea). since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. processor accesses to the ioapic0 region are always sent to nsi. processor accesses to the ioapic2 region are always sent to pea. these regions are subject to the apic disable, which are cleared by bios after the allocated regions have been reflected down to the base registers of apic controllers discovered during standard enumeration. until this step of the initialization sequence has been performed, accesses to these regions are treated as subtractive decode and routed to nsi. the imch does not support an ioapic range for the edma controller or the aioc, since there is no ioxapic device or corresponding register set integrated into the edma controller or the aioc. 10.1.7 fsb interrupt memory space the fsb interrupt space is the address range used to deliver interrupts to the fsb. any device below aioc, nsi or a pci express port may issue a memory write to 0feex_xxxxh. the imch will forward this memory write along with its associated data to the fsb as a message signaled interrupt (msi) transaction. the imch terminates the fsb transaction by asserting trdy# and providing the response. this memory write cycle does not go to dram. reads to this address range are aborted by the imch. table 10-8. ioapic memory space from to ioapic0 (nsi) 0_fec0_0000 0_fec7_ffff ioapic2 (pea0) 0_fec8_0000 0_fec8_0fff ioapic3 (pea1) 0_fec8_1000 0_fec8_1fff table 10-9. fsb interrupt memory space from to fsbintr 0_fee0_0000 0_feef_ffff
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 276 order number: 320066-003us 10.1.8 high smm memory space the highsmm space allows cacheable access to the compatible smm space by remapping valid smm accesses between 0_feda_0000 and 0_fedb_ffff to physical accesses between 0_000a_0000 and 0_000b_ffff. the accesses are remapped when smram space is enabled, an appropriate access is detected on the processor bus, and when exsmrc.h_smrame ( section 16.1.1.25 ) allows access to high smram space. inbound smm memory accesses from any port are specially terminated; reads are provided with data retrieved from address 0, while writes are ignored entirely (all byte enables deasserted). 10.1.9 pci device memory (mmio) the imch provides two distinct regions of memory that may be mapped to populated pci devices. the first is the traditional (non-prefetchable) mmio range, which must lie below the 4 gbyte boundary. the registers associated with non-prefetchable mmio (mbase/mlimit, see section 16.4.1.17, ?offset 20h: mbase - memory base address register? / section 16.4.1.18, ?offset 22h: mlimit - memory limit address register? ) are unchanged from historical 32-bit architecture imch implementations. the second is the prefetchable mmio range, which has been extended in cmi such that it may lie on either side of the 4 gbyte boundary. the registers associated with prefetchable mmio (pmbase/pmlimit, see section 16.4.1.19, ?offset 24h: pmbase - prefetchable memory base address register? / section 16.4.1.20, ?offset 26h: pmlimit - prefetchable memory limit address register? ) have been augmented by the pci defined upper 32- bit base/limit register pair (pmbasu/pmlmtu, see section 16.4.1.21, ?offset 28h: pmbasu - prefetchable memory base upper address register? / section 16.4.1.22, ?offset 2ch: pmlmtu - prefetchable memory limit upper address register? ), although only the first nibble of each register is implemented in the imch. the mbase/mlimit pair must be programmed to lie between tolm and 4 gbytes. the pmbase/pmlimit and pmbasu/pmlmtu registers must be programmed to lie between tolm and 4 gbytes. because these registers define a pci memory space, they are subject to the memory access enable (mae) control bit in the standard pci command register (see section 16.4.1.4, ?offset 04h: pcicmd - pci command register? ). note: using the same address space as both cacheable and non cacheable is discouraged. also, assigning and writing the same host address space to two independent downstream devices is also discouraged. although not illegal, both of the above conditions are very difficult to setup intelligently and validate. if 2 devices decide to use the same memory space, and they both send write cycles to it (both either cacheable or uncacheable), there are no guarantees that device 1 data (being older) will get there before device 2 data (being newer) if they do not use a flagging mechanism. table 10-10. high smm memory space from to highsmm 0_feda_0000 0_fedb_ffff
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 277 intel ? ep80579 integrated processor 10.1.9.1 device 2 memory and prefetchable memory plug-and-play software configures the pea a memory window in order to provide enough memory space for the devices behind this virtual pci-to-pci bridge. accesses whose addresses fall within these windows are decoded and forwarded to pea0 for completion. note that neither region should overlap with any other fixed or relocate- able area of memory. also note that pcicmd2 refers to pcicmd for device 2. 10.1.9.2 device 3 memory and prefetchable memory plug-and-play software configures the pea1 memory window in order to provide enough memory space for the devices behind this virtual pci-to-pci bridge. accesses whose addresses fall within this window are decoded and forwarded to pea1 for completion. note that neither region should overlap with any other fixed or relocate- able area of memory. also note that pcicmd3 refers to pcicmd for device 3. note: if pci express port a0 is configured to operate in x8 mode, all functional space for pea1 disappears; effectively collapsing m3/pm3 to match the limit addresses of m2/pm2. 10.1.9.3 device 4 memory and prefetchable memory plug-and-play software configures the pci memory window in order to provide enough memory space for the devices behind this virtual pci-to-pci bridge. accesses whose addresses fall within this window are decoded and forwarded to pci for completion. note that neither region should overlap with any other fixed or relocate-able area of memory. also note that pcicmd4 refers to pcicmd for device 4. table 10-11. device 2 memory and prefetchable memory from to m2 mbase2 mlimit2 pm2 pmbase2/pmbasu2 pmlimit2/pmlmtu2 table 10-12. device 3 memory and prefetchable memory from to m3 mbase3 mlimit3 pm3 pmbase3/pmbasu3 pmlimit3/pmlmtu3 table 10-13. device 4 memory and prefetchable memory from to m4 mbase4 mlimit4 pm4 pmbase4/pmbasu4 pmlimit4/pmlmtu4
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 278 order number: 320066-003us 10.2 imch responses to edma transactions in the following tables, the term ?abort? implies that the edma engine will immediately stop the transfer in progress. the offending access will not be forwarded to the inbound/outbound arbiter at all, an error bit will be set accordingly, and the error will be escalated as specified by the configurat ion bits controlling interrupts and errors. note: this behavior is quite different from the and pci express inbound ports, as in the latter cases the transaction in question was requested by some other initiator elsewhere in the platform. the edma engine is a source of traffic all by itself, which makes error containment much simpler in the case of edma traffic. 10.2.1 fixed address spaces (edma) ta b l e 1 0 - 1 4 summarizes imch responses to edma accesses to the various fixed address spaces. 10.2.2 relocatable address spaces (edma) ta b l e 1 0 - 1 5 summarizes imch responses to edma accesses to the various relocatable address spaces. table 10-14. edma accesses to fixed address spaces address space conditions destination imch response dosmem - mainmem transaction is sent to memory system vgaa vgab mda pamc0? pamf0 -abort programmer?s responsibility not to target edma accesses in the legacy region between 640kb and 1 mbyte mem1_15 - mainmem transaction is sent to memory system isa15 fdhc.hen = 0 mainmem hole disabled: transaction is sent to memory system fdhc.hen = 1 abort hole enabled: edma will abort on accesses directed to the isa hole when enabled mainmem - mainmem transaction is sent to memory system (unless address hits an enabled tseg smm range. see tsegsmm) tsegsmm - variable refer to table 10-16, ?supported smm ranges? . ioapic[0,2-3] - abort programmer?s responsibility to avoid the apic ranges fsbintr - abort programmer?s responsibility to avoid the fsb interrupt messaging range highsmm - variable refer to table 10-16, ?supported smm ranges? . highmem address is below the top of memory space defined by tom and the remap registers mainmem transaction is sent to memory system. address is above the top of memory abort hardware will detect an attempt to access above the populated dram space, and will abort.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 279 intel ? ep80579 integrated processor note: edma access is not permitted to the port, thus any address mapping to the legacy interface will cause an abort. 10.3 i/o address space the imch generates outbound transactions on behalf of all ia-32 core i/o accesses. the imch contains two internal registers in the ia-32 core i/o space dedicated to the configuration access mechanism; the configuration address register (config_address) and the configuration data register (config_data). the behavior of the imch in response to accesses to these registers is described in chapter 13.0, ?platform configuration.? the ia-32 core allows 64 k+3 bytes to be addressed within the i/o space. the imch propagates the ia-32 core i/o address without any translation to the targeted destination bus. note that the upper three locations can be accessed only during i/o address wrap-around; when signal a16# is asserted on the processor bus. a16# is asserted on the processor bus whenever a dword i/o access is made from address 0fffdh, 0fffeh, or 0ffffh. in addition, a16# is asserted when software attempts a two-byte i/o access from address 0ffffh. all i/o accesses (read or write) which do not map to internal imch registers will receive a defer response on the fsb, and be forwarded to the appropriate outbound port. the imch never posts an i/o write. the imch never responds to inbound transactions to i/o or configuration space initiated on any port. inbound i/o or configuration transactions requiring a completion are terminated with ?master abort? completion packets on the originating port interface. inbound i/o or configuration write transactions not requiring completion are dropped. 10.3.1 configuration window the i/o addresses 0cf8h and 0cfch are treated specially, as they define the compatible configuration window. dword accesses to 0cf8h address the internal imch configuration address register. accesses from 1 to 4 bytes in size to the region from 0cfc-0cffh are treated as configuration data accesses if configuration space is enabled (bit31 of the configuration address register is set). refer to chapter 13.0, ?platform configuration.? for further details. table 10-15. edma accesses to relocatable address spaces address space conditions destination imch response nsi: m nsi: pm - abort no support for edma destination on nsi pea: m[n] pea: pm[n] write, mae = 1 pea[n] transaction forwarded to destination pea port. write, mae = 0 abort abort. memory access disabled. read transaction abort abort. no support for peer segment reads. nsi_sub - abort no support for edma destination on nsi pea: pm[n] write, mae = 1 pea[n] transaction forwarded to destination pea port. write, mae = 0 abort abort. memory access disabled. read transaction abort abort. no support for peer segment reads.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 280 order number: 320066-003us 10.3.2 vga and mda regions along with the memory space address regions described in section 10.1.2, ?vga and mda memory spaces? , there are fixed i/o locations associated with both the vga and the mda regions. accesses to these addresses are routed to nsi by default, but this behavior may be modified via the vgaen, mdap and mae configuration settings. refer to the prior sections for the rules associated with the configuration settings of vgaen, mdap and mae. the mda region includes i/o space addresses 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh. the vga region includes i/o space ranges 3b0-3bbh, and 3c0-3dfh. the pci specification defines both mda and vga to be 10-bit address decode, thus all accesses with a[9:0] matching any of these addresses are subject to the associated routing rules. address bits a[15:10] are ignored when the check against these fixed addresses are applied. the order of precedence for the routing checks is as follows: ? mae = 0, mda addresses will route to nsiif mdap is set, overriding any vgaen. ? mae = 1, mda addresses will route to the peer device if mdap is set, overriding any vgaen. ? mae = 0, vga addresses will route to the nsi . ? mae = 1, vga addresses will route to the pci express port with its vgaen set, if any. ? mae = 0, mda addresses which fall within vga regions will route to the nsi if mdap is clear. ? mae = 1, mda addresses which fall within vga regions will follow vgaen if mdap is clear. ? both vga and mda addresses default to nsi if mdap and all vgaen bits are clear. note: setting of mdap or any of the vgaen bits implies that the isaen bit is also set in all virtual p2p bridges, because of the 10-bit decode requirement. note: aioc access to this space is not supported. upstream attempted accesses to this space are programming errors and will result in a master abort.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 281 intel ? ep80579 integrated processor 10.4 main memory addressing the ?high memory? and ?extended memory? address regions are together called ?main memory.? main memory is composed of ad dress segments that refer to ddr sdram system memory. main memory addresses are mapped to ddr sdram channels, devices, banks, rows, and columns in different ways depending upon the type of memory being used and upon the density or organization of the memory. the process for determining the device and channel ids for addressed devices is as follows: ? the requested address is compared agains t the values of all eight drb registers. the number of the register whose programmed value is greater than the address and whose previous register is less than the address is the output of the comparison. ? the value of the drb register ?below? is subtracted from the address in order to determine the offset into the group. ? the offset determines the manner in whic h the row, column, and bank address bits are extracted from the address. 10.5 system management mode (smm) space cmi supports the use of main memory as system management ram (smm ram) enabling the use of system management mode. the imch supports three smm options: ? compatible smram (c_smram) ?high segment (hseg) ? top of memory segment (tseg) system management ram space provides an access protected memory area that is available for smi handler code and data storage. this memory resource is normally hidden from the operating system so that the processor has immediate access to this memory space upon entry to smm (cannot be swapped-out). 10.5.1 smm addressing ranges imch provides three smram options: ? below 1 mbyte option that supports compatible smi handlers. ? above 1 mbyte option that allows new smi handlers to execute with write-back cacheable smram. ? optional larger write-back cacheable t_seg area from 128 kbyte to 1 mbyte in size. the above 1 mbyte solutions require changes to compatible smram handler code to properly execute above 1 mbyte. note: the first two options both map legal accesses to the same physical range of memory, while the third defines an independent region of addresses. 10.5.1.1 smm space restrictions if any of the following conditions are violated, the results of smm accesses are unpredictable and may cause the system to hang: ? the compatible smm space must not be set-up as cacheable. ? both d_open and d_close must not be set to 1 at the same time. ? when tseg smm space is enabled, the tseg space must not be reported to the os as available dram. this is a bios responsibility.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 282 order number: 320066-003us bios and smm code must cooperate to properly configure the imch in order to ensure reliable operation of the smm function. 10.5.1.2 smm space definition smm space is defined by both its addressed smm space and its dram smm space. the addressed smm space is defined as the range of fsb addresses used by the ia-32 core to access smm space. dram smm space is defined as the range of physical dram memory locations containing smm information. the smm space can be accessed at one of three transaction address ranges: ?compatible ?high ?tseg the compatible and tseg smm space is not remapped and therefore the addressed and dram smm physical addresses are iden tical. the high smm space is remapped; thus the addressed and dram smm locations are different. note that the high dram space is the same as the compatible transaction address space. ta b l e 1 0 - 1 6 describes all three unique addressing combinations: ? compatible transaction address ? high transaction address ? tseg transaction address table 10-16. supported smm ranges smm space enabled transaction address space (adr) dram space (dram) compatible (c) a0000h to bffffh a0000h to bffffh high (h) 0feda0000h to 0fedbffffh a0000h to bffffh tseg (t) (tolm-tseg_sz) to tolm (tolm-tseg_sz) to tolm notes: 1. high smm: this implementation is consistent with the intel e7500 and intel e7501 designs. in prior mch designs the high segment was the 384 kbyte region from a_0000h to f_ffffh. however c_0000h to f_ffffh was not useful, so it has been deleted in the imch design. 2. tseg smm: this implementation is consistent with the intel e7500 and intel e7501 designs. in prior mch designs the tseg address space was offset by 256 mbytes to allow for simpler decoding and the tseg was remapped to just under the tolm. in the imch the tseg region is not offset by 256 mbytes and it is not remapped. 3. in cases where dram tolm is less than tom tseg cannot be used for smm. for this case menc memory spans consecutive space from above tolm to below tolm and will conflict with tseg space
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 283 intel ? ep80579 integrated processor 10.6 memory reclaim background the following memory mapped i/o devices an d ranges are typically located below 4 gbytes: ?high bios ?h-seg ?xapic ?local apic ? fsb interrupts ? pea0 through pea1 m, pm and bar regions in previous generation mch architectures, the physical dram memory overlapped by the logical address space allocated to these memory mapped i/o devices was unusable. in server systems the memory allocated to memory mapped i/o devices could easily exceed 1 gbyte. this creates the possibility of a large amount of physical memory populated in the system becoming unusable. the imch provides the capability to reclaim the physical memory overlapped by the memory mapped i/o logical address space via remapping physical memory from the top of low memory (tolm) boundary up the 4 gbytes boundary (or tom if less than 4 gbytes) to an equivalent sized logical address range located just above the top of physical memory 10.6.1 memory remapping algorithm note: the ia-32 core is not capable of using the re map capability and care must be taken to ensure that no addresses sent to the ia-32 core are greater than tolm in that it will cause aliasing. the remap capability can be utilized by the aioc, iich and pcie ports. terminology clarification: physical address the address presented to the imch is traditionally called a ?physical address,? because intel architecture processors contain both segmentation and paging hardware, and all compatible software differentiates between logical addresses, virtual addresses, and physical addresses. the algorithm for remapping addresses presented to the imch to reclaim dram address space must be implemented such that the mechanism is invisible to compatible software. system address the system address applies to the internal imch interface to physical dram memory, and is not directly visible to software, other than through certain internal logging registers used to store decoded dram address information for error isolation. an incoming address (referred to as a physical address) is checked to see if it falls in the memory remap window. the bottom of the remap window is defined by the value in the remapbase register (see section 16.1.1.31, ?offset c6h: remapbase - remap base address register? ). the top of the remap window is defined by the value in the remaplimit register ( section 16.1.1.32, ?offset c8h: remaplimit ? remap limit address register? ). an address that falls within this window is remapped to the physical memory starting at the address defined by the tolm register.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 284 order number: 320066-003us 10.7 iich register and memory mappings this section covers cmi?s iich various address decoding ranges. this section is for background purposes, and must not to be considered by implementers and validators as part of the behavioral definition of cmi. each decode range is described elsewhere in the section associated with the corresponding function. 10.7.1 i/o map the i/o map is divided into separate types. fixed ranges cannot be moved, but in some cases can be disabled. variable ranges can be moved and can also be disabled. 10.7.1.1 fixed i/o address ranges ta b l e 1 0 - 1 7 shows the fixed i/o decode ranges from the ia-32 core perspective. note that for each i/o range, there may be separate behavior for reads and writes. cycles that go to target ranges that are marked as reserved will not be decoded, and are passed to pci to pci bridge where they are dropped. address ranges that are not listed or marked reserved are not positively decoded by the iich (unless assigned to one of the variable ranges). in subtractive mode, i/o ranges that are not otherwise decoded are forwarded to pci to pci bridge where they are dropped. table 10-17. fixed i/o ranges decoded by iich (sheet 1 of 3) i/o address read target write target internal unit separate enable/ disable 00h ? 08h dma controller dma controller dma none 09h ? 0eh reserved dma controller dma none 0fh dma controller dma controller dma none 10h ? 18h dma controller dma controller dma none 19h ? 1eh reserved dma controller dma none 1fh dma controller dma controller dma none 20h ? 21h interrupt controller interrupt controller interrupt none 24h ? 25h interrupt controller interrupt controller interrupt none 28h ? 29h interrupt controller interrupt controller interrupt none 2ch ? 2dh interrupt controller interrupt controller interrupt none 2e ? 2f lpc sio lpc sio forwarded to lpc yes 30h ? 31h interrupt controller interrupt controller interrupt none 34h ? 35h interrupt controller interrupt controller interrupt none 38h ? 39h interrupt controller interrupt controller interrupt none 3ch ? 3dh interrupt controller interrupt controller interrupt none 40h ? 42h timer/counter timer/counter pit (8254) none 43h reserved timer/counter pit none 4e ? 4f lpc sio lpc sio forwarded to lpc yes 50h ? 52h timer/counter timer/counter pit none 53h reserved timer/counter pit none 60h microcontroller microcontrolle r forwarded to lpc yes w/ 64h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 285 intel ? ep80579 integrated processor 61h nmi controller nmi controller ia-32 core interface none 62h microcontroller microcontroller forwarded to lpc yes w/ 66h 63h nmi controller 1 nmi controller 1 ia-32 core interface yes, alias to 61h 64h micocontroller microcontroller forwarded to lpc yes w/ 60h 65h nmi controller 1 nmi controller 1 ia-32 core interface yes, alias to 61h 66h microcontroller microcontroller forwarded to lpc yes w/ 62h 67h nmi controller 1 nmi controller 1 ia-32 core interface yes, alias to 61h 70h reserved nmi and rtc controller rtc none 71h rtc controller rtc controller rtc none 72h rtc controller nmi and rtc controller rtc yes, w/ 73h 73h rtc controller rtc controller rtc yes, w/ 72h 74h rtc controller nmi and rtc controller rtc none 75h rtc controller rtc controller rtc none 76h rtc controller nmi and rtc controller rtc none 77h rtc controller rtc controller rtc none 80h dma controller, or lpc dma controller, or lpc dma none 81h ? 83h dma controller dma controller dma none 84h ? 86h dma controller dma controller and lpc dma none 87h dma controller dma controller dma none 88h dma controller dma controller and lpc dma none 89h ? 8bh dma controller dma controller dma none 8ch ? 8eh dma controller dma controller and lpc dma none 8fh dma controller dma controller dma none 90h ? 91h dma controller dma controller dma yes, alias to 8xh 92h reset generator reset generator ia-32 core interface none 93h ? 9fh dma controller dma controller dma yes, alias to 8xh a0h ? a1h interrupt controller interrupt controller interrupt none a4h ? a5h interrupt controller interrupt controller interrupt none a8h ? a9h interrupt controller interrupt controller interrupt none ach ? adh interrupt controller interrupt controller interrupt none b0h ? b1h interrupt controller interrupt controller interrupt none b2h ? b3h power management power management power management none b4h ? b5h interrupt controller interrupt controller interrupt none b8h - b9h interrupt controller interrupt controller interrupt none bch ? bdh interrupt controller interrupt controller interrupt none c0h ? d1h dma controller dma controller dma none d2h ? ddh reserved dma controller dma none deh ? dfh dma controller dma controller dma none 170h ? 177h sata sata sata yes table 10-17. fixed i/o ranges decoded by iich (sheet 2 of 3) i/o address read target write target internal unit separate enable/ disable
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 286 order number: 320066-003us 10.7.1.2 variable i/o decode ranges ta b l e 1 0 - 1 8 shows the variable i/o decode ranges. they are set using base address registers (bars) or other configuration bits in the various configuration spaces. the pnp software (pci or acpi) can use their configuration mechanisms to set and adjust these values. warning: the variable i/o ranges must not be set to conflict with the fixed i/o ranges. if the configuration software allows conflicts to occur, it may produce unpredictable results. there are no checks for conflicts. 1f0h ? 1f7h sata sata sata yes 200 ? 207h gameport low gameport low forwarded to lpc yes 208 ? 20fh gameport high gameport high forwarded to lpc yes 376h sata sata sata yes 3f6h sata sata sata yes 4d0h ? 4d1h interrupt controller interrupt controller interrupt none cf9h reset generator reset generator ia-32 core interface none notes: 1. only if the port 61 alias enable bit (gcs.p61ae) bit is set. otherwise, the target is dropped. 2. table 10-17. fixed i/o ranges decoded by iich (sheet 3 of 3) i/o address read target write target internal unit separate enable/ disable table 10-18. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64k i/o space 64 power management usb #1 anywhere in 64k i/o space (see note 1 ) 32 usb1 host controller 1 smbus anywhere in 64k i/o space 32 smb unit tco 96 bytes above acpi base 32 tco unit gpio anywhere in 64k i/o space 64 gpio unit parallel port 3 ranges in 64k i/o space 8 2 lpc peripheral serial port 1 8 ranges in 64k i/o space 8 lpc peripheral serial port 2 8 ranges in 64k i/o space 8 lpc peripheral floppy disk controller 2 ranges in 64k i/o space 8 lpc peripheral lpc generic 1 anywhere in 64k i/o space 128 lpc peripheral lpc generic 2 anywhere in 64k i/o space 16 lpc peripheral i/o trapping ranges anywhere in 64k i/o space 1 to 256 bytes trap on internal i/o data bus notes: 1. these ranges are decoded directly. 2. there is also an alias 400h above the parallel port range that is used for ecp parallel ports.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 287 intel ? ep80579 integrated processor 10.7.2 memory map table 10-19 shows (from the ia-32 core perspective) the memory ranges that are decoded. cycles that arrive that are not directed to any of the internal memory targets that decode (see table 10-19 )are dropped. software must not attempt locks to the iich?s memory-mapped i/o ranges for usb 2.0, and hpet (high precision event timer). if attempted, the lock is not honored which means potential deadlock conditions may occur. table 10-19. iich memory decode ranges (from ia-32 core perspective) memory range target dependency/comments 000e0000 - 000effff fwh bit 6 in fwh decode enable register is set. 000f0000 - 000fffff fwh bit 7 in fwh decode enable register is set fec00000 - fec0 0040 i/o(x)apic inside iich ffc0 0000 - ffc7 ffff ff80 0000 - ff87 ffff fwh bit 8 in fwh decode enable register ffc8 0000 ? ffcf ffff ff88 0000 - ff8f ffff fwh bit 9 in fwh decode enable register ffd0 0000 - ffd7 ffff ff90 0000 - ff97 ffff fwh bit 10 in fwh decode enable register is set ffd8 0000 ? ffdf ffff ff98 0000 - ff9f ffff fwh bit 11 in fwh decode enable register is set ffe0 000 - ffe7 ffff ffa0 0000 - ffa7 ffff fwh bit 12 in fwh decode enable register is set ffe8 0000 ? ffef ffff ffa8 0000 ? ffaf ffff fwh bit 13 in fwh decode enable register is set fff0 0000 - fff7 ffff ffb0 0000 - ffb7 ffff fwh bit 14 in fwh decode enable register is set fff8 0000 ? ffff ffff ffb8 0000 ? ffbf ffff fwh always enabled. the top two 64kb blocks in this range can be swapped by the iich. see section 10.5 for details. ff70 0000 - ff7f ffff ff30 0000 - ff3f ffff fwh bit 3 in fwh decode enable 2 register is set ff60 0000 - ff6f ffff ff20 0000 - ff2f ffff fwh bit 2 in fwh decode enable 2 register is set ff50 0000 - ff5f ffff ff10 0000 - ff1f ffff fwh bit 1 in fwh decode enable 2 register is set ff40 0000 - ff4f ffff ff00 0000 - ff0f ffff fwh bit 0 in fwh decode enable 2 register is set 1kb anywhere in 4gb range usb 2.0 host controller enable via standard pci mechanism (device 29, function 7) fed0 x000h-fed0 x3ffh hpet bios determines ?fixed? location which is one of four 1kb ranges where x (in the first column) is 0h, 1h, 2h, or 3h. all other n/a master aborted
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 288 order number: 320066-003us 10.7.3 boot-block update scheme the iich supports a ?top-block swap? mode that swaps the top block in the fwh (the boot block) with another location. this allows for safe update of the boot block (even if a power failure occurs). when the ?top-swap? enable bit is set, inverts a16 for cycles going to the upper two 64 kbyte blocks in the fwh. specifically, in this mode, accesses to ffff_0000h-ffff_ffffh are directed to fffe_0000h-fffe_ffffh and vice versa. when the top swap enable bit is 0, the iich will not invert a16. this bit is automatically set to 0 by rtest#, but not by pltrst#. the scheme is based on the concept that the top block is reserved as the ?boot? block, and the block immediately below the top block is reserved for doing boot-block updates. the algorithm is: 1. software copies the top block to the block immediately below the top. 2. software checks that the copied block is correct. this could be done by performing a checksum calculation. 3. software sets the ?top-block swap? bit. this will invert a16 for cycles going to the fwh. 4. software erases the top block. 5. software writes the new top block. 6. software checks the new top block. 7. software clears the top-block swap bit. 8. software sets the top_swap lock-down bit. if a power failure occurs at any point after step 3, the system is able to boot from the copy of the boot block that is stored in the block below the top. this is because the top- swap bit is backed in the rtc well. note: the top-block swap mode may be forced by an external strapping option (see chapter 16.0, ?imch registers.? ). when top-block swap mode is forced in this manner, the top_swap bit cannot be cleared by software. a reboot with the strap removed will be required to exit a forced top-block weap mode. note: top-block swap mode only affects accesses to the firmware hub space, not feature space. note: the top-block swap mode has no effect on accesses below fffe_0000h.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 289 intel ? ep80579 integrated processor 11.0 system memory controller 11.1 overview the memory controller is responsible for controlling the off-chip dram devices. the unit scheduler, control and protocol state machines access dram devices over a wide range of speed bins using ddr2 dram technology. the ep80579 supports one memory channel. 11.2 memory controller feature list the memory controller supports the following features ? supports 1 dimm ? ddr2 ? 64 and 32-bit mode. ? single rank (64 or 32-bit mode) or dual rank (64 bit mode) device. ? ddr2-400, ddr2-533, ddr2-667, ddr2-800. ? see to ?rules for populating dimm slots? for more details. ? supports dual dimms ? ddr2 and 64 bit mode only ? registered dual dimm support with 1t command/address timing. unbuffered dual dimm support with 2t command/address timing. please refer to ?2t timing mode? for details. ? 32-bit mode dual dimm is not supported ? restrictions on speed, number of ranks and modes in 2 dimm mode, refer to ?rules for populating dimm slots? for details. ? ddr2-400 is supported. ? ddr2-533 and ddr2-667 are also supported with special design guidelines. refer to table 11-5 for more details. ? supports 32-bit mode ? 32-bit mode is for memory-down configuration, thus the following modes are not supported: dual dimm, dual rank, registered ? supports 256 mb, 512 mb, 1 gb and 2 gb density parts in the x8 configuration. ta bl e 1 1 - 1 shows the various ddr2 device densities and widths supported. ta bl e 1 1 - 2 and ta bl e 1 1 - 3 shows the various memory capacity configurations supported using these parts in the 64 bit and 32-bit modes. ? memory controller does not support 4 gb density ? see section 11.3, ?configurations? for more details. ? supports 4-bank devices ? 256 mb and 512 mb ddr2 parts
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 290 order number: 320066-003us ? supports 8-bank devices. ? 1 gb and 2 gb ddr2 parts ? supports unbuffered and registered dimms ? supports discrete memory components soldered on the board ? supports 2 dq loads similar to the double sided dimm configuration. ? one 72b wide dram interface, 64b data + 8b ecc. ? the 64b data interface can optionally configured to be a 32b interface with 8b ecc. the 32b option provides half the total bandwidth compared to the 64b interface, and meets the requirements for systems that are cost sensitive and want to populate small memory footprint soldered on the mother board. ? supports burst-of-4 mode with a minimum access size of 32b for the 64b interface. ? on the 64b interface accesses longer than 32b are serviced as multiple burst- of-4 transactions without closing the page. ? on the 32b interface, the controller supports burst-of-8 for a minimum access size that is still 32b. ? optional error protection using ecc bits and error code that supports sec/ded (single bit error correction/double bit error detection). please see ?offset 7ch: drc ? dram controller mode register? for details. ? on a single bit error, the memory controller corrects the error bit and writes back the correct data value to dram, if enabled by software selection. ? does not support ded (double-bit error detect) retries. ? supports maximum of 4 gb dram capacity as shown in ta bl e 1 1 - 2 . ? one memory channel ? support for demand scrub in hardware ? refer to section 16.1.1.45, ?offset 88h: sdrc ? ddr sdram secondary control register? on page 439 for details. ? support for background scrubbing in hardware. ? programmable hardware scrub engine that allows background scrub at a wide range of rates, including, but not limited to: up to 4 gb every hour, day, week, or very fast rates, mainly used for validation purposes. the memory controller supports the following transactions ? simple read transactions. ? supported lengths - 1-7b, 8b, 16b, 24b, 32b, 64b ? read transactions smaller than 32b will result in a full 32b read on the interface ? simple write transactions. ? supported lengths - 8b, 16b, 24b, 32b, 64b ? writes of lengths 8b, 16b and 24b will take the same time on the interface as a 32b write, the actual bytes that are written are specified by the dq masks ? writes of length 40b, 48b, 56b will be treated as a 32b write followed by an 8b, 16b or 24b write ? writes that are smaller than 8b (i.e 1-7b) require a read-modify-write operation and these will be supported upstream in the pipeline in other units. the memory controller will not support read-modify-write operation. ? csr reads and writes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 291 intel ? ep80579 integrated processor ? the memory controller does not support any atomic operations. other units upstream support atomic operations. ? all memory controller operations are aligned on a 64b boundary ? the memory controller interleaves the memory across banks on a 64b boundary ? any transaction that crosses a 64b alignment boundary or is larger than 64b must be split by the upstream agent. ? supports external dimms or so-dimms. 11.3 configurations ta bl e 1 1 - 1 shows the various ddr2 device densities and widths supported by the memory controller. ta bl e 1 1 - 2 shows the various capacity configurations supported in 64b mode. the first column shows the total dram capacity on the channel. the rest of the columns indicate the dram devices features, densities and the number of devices required to achieve the given capacity. a single sided dimm is indicated by no parts populated on side b. double sided dimm has parts populated on both sides. for each configuration, an additional dram part per side is required to support ecc bits. a x8 part provides all the bits required for ecc. note that memory system can be built without ecc enabled. in the 64b configuration, the minimum capacity supported is 256 mb and the maximum capacity supported is 4 gb. table 11-1. supported ddr2 device densities and width density (mb) ddr2x8 256 supported 512 supported 1024 supported 2048 supported 4096 not supported table 11-2. supported dram capacity for 64b mode total dram capacity dram density dram part width total # of parts on side a (w/o ecc) total # of parts on side b (w/o ecc) 256 mb 256 mb x8 8 0 512 mb 256 mb x8 8 8 512 mb x8 8 0 1 gb 512 mb x8 8 8 1 gb x8 8 0 2 gb 1 gb x8 8 8 2 gb x8 8 0 4 gb 2 gb x8 8 8
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 292 order number: 320066-003us ta b l e 1 1 - 3 shows the various configurations supported in the 32b mode.in the 32-bit mode only single rank ddr2 devices are supported. in this mode, the minimum capacity supported is 128 mb and the maximum capacity supported is 1 gb. note: the ep80579 supports only single ranks in 32-bit mode. ta b l e 1 1 - 4 shows the supported dimm raw cards in the registered and unbuffered formats. ta b l e 1 1 - 5 shows the supported ddr2device speed grades for single and dual dimms. dual dimm support uses 2n or 2t command/address timing. table 11-3. supported dram capacity for 32b mode total dram capacity dram density dram part width total # of parts on side a (w/o ecc) total # of parts on side b (w/o ecc) 128 mb 256 mb x8 4 0 256m b 512 mb x8 4 0 512 mb 1 gb x8 4 0 1 gb 2 gb x8 4 0 table 11-4. raw cards supported by the ep80579 raw card number of ddr2 sdrams sdram organization number of ranks a9 x8, planar, single row 1 rdimm f9 1 b18 2 g18 2 d8 1 udimm f9 1 e16 2 g18 2 table 11-5. supported ddr2 data speeds ddr speed 1 dimm 1 rank 1 dimm 2 ranks 2 dimms 1 rank each ddr2-400 r = 1t ub = 1t r = 1t ub = 1t r = 1t ub = 2t ddr2-533 r = 1t ub = 1t r = 1t ub = 1t r = 1t ub = 2t ddr2-667 r = 1t ub = 1t r = 1t ub = 1t r = 1t ub = 2t ddr2-800 r = 1t ub = 2t r = 1t ub = 2t not supported r = registered ub = unbuffered 1t = 1t address/command timing 2t = 2t address/command timing
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 293 intel ? ep80579 integrated processor 11.3.1 rules for populating dimm slots 1. in all configurations, the speed and timing will be the lowest among the 2 dimms, as determined by the spd registers on the dimms 2. dual dimm mode supports a subset of the ddr2 data speeds as shown in ta bl e 1 1 - 5 . 3. ta bl e 1 1 - 6 shows the supported dimm population of the 2 ranks. all of configurations not shown in table 11-6 are not supported.the rank configurations supported are one or two ranks on a single dimm or one rank on each of the 2 dimms. two ranks in each of the 2 dimms (i.e., 4 ranks) is not supported. 4. ta bl e 1 1 - 7 shows the supported rank configurations when using 2 ranks for the single and dual dimm. . table 11-6. supported dimm populations dimm 1 dimm 0 rank 0 rank 1 rank 0 rank 1 1 - single rank empty empty drb0 cs0 odt0 empty 1 - dual rank empty empty drb0 cs0 odt0 drb2 cs1 odt1 2 - single rank drb2 cs1 odt1 empty drb0 cs0 odt0 empty table key: odt0/odt1: odt pins. please refer to section 11.4.2 for more information. cs0/cs1: chip selects drb: dram row boundary register table 11-7. supported rank configurations in single and dual dimm mode single dimm (ddr2) (64 bits - rank 0 & rank 1) (32 bits - rank 0 only) dual dimm (ddr2, 64 bit only) rank 0 rank 1 rank 0, dimm 0 rank 0, dimm 1 128 mb (32 bit only) na na na 256 mb 256 mb 256 mb 256 mb, 512 mb, 1 gb, 2 gb 512 mb 512 mb 512 mb 256 mb, 512 mb, 1 gb, 2 gb 1 gb 1 gb 1 gb 256 mb, 512 mb, 1 gb, 2 gb 2 gb 2 gb 2 gb 256 mb, 512 mb, 1 gb, 2 gb
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 294 order number: 320066-003us 5. there are additional restrictions when 2 ranks are used. both the ranks need to be: ? either registered or unbuffered. no mixing of registered and unbuffered ranks. ? 64 bit mode only. 32-bit mode is not supported in dual rank. 6. for 32-bit mode, only discrete components of single rank are supported. two ranks in 32-bit mode is not supported. ta bl e 1 1 - 3 shows the supported configurations in the 32-bit mode. 11.3.2 dram addressing ta b l e 1 1 - 8 , table 11-9 , ta bl e 1 1 - 1 0 and table 11-11 show the dram device addressing for the various ddr2 device densities supported by the memory controller. note that: ? x4 and x 16 devices are not supported. ? 4gb and higher device density parts are not supported. ? see ta bl e 1 1 - 7 for the supported device densities and widths. table 11-8. 256mb addressing configuration ddr2 32 mb x 8 # of banks 4 bank address ba0, ba1 auto precharge a10 row address a0-a12 column address a0-a9 page size 1kb table 11-9. 512mb addressing configuration ddr2 64 mb x 8 # of banks 4 bank address ba0, ba1 auto precharge a10 row address a0-a13 column address a0-a9 page size 1kb table 11-10. 1gb addressing configuration ddr2 128 mb x 8 # of banks 8 bank address ba0-ba2 auto precharge a10
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 295 intel ? ep80579 integrated processor 11.3.3 memory address translation tables section 11.3.3.1 shows the address bit translation from the system address to the dram row/column/bank address for the different ddr2 configurations supported by the memory controller. 256 mb, 512 mb, 1024 mb and 2048 mb dram device densities are shown but please refer to ta bl e 1 1 - 1 for supported ddr2 device densities and widths. the memory capacity that can be achieved for each device density in the single and dual rank mode is also shown in the address mapping tables. 11.3.3.1 ddr2 address translation tables figure 11-1 shows the translation tables for 64 bit, burst size 4 devices in x8 width. note: only burst 4 is supported for a ddr2 64 data bit interface. figure 11-2 shows the translation tables for 32 bit, burst size 8 devices in x8 width. note: only burst 8 is supported for a ddr2 32 data bit interface. for a list of memory controller supported ddr2 device types and widths see ta bl e 1 1 - 1 . row address a0-a13 column address a0-a9 page size 1kb table 11-11. 2gb addressing configuration ddr2 256 mb x 8 # of banks 8 bank address ba0-ba2 auto precharge a10 row address a0-a14 column address a0-a9 page size 1kb table 11-10. 1gb addressing configuration ddr2 128 mb x 8
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 296 order number: 320066-003us 11.3.4 dram timings the ep80579 is highly configurable in its dram timing configuration, but only a limited subset of the setting combinations possible are verified by intel. the approved and expected settings for the various flavors of supported memory are listed in ta b l e 1 1 - 1 2 . for more information on the drt register see ?offset 78h: drt0 - dram timing register 0? and ?offset 64h: drt1 ? dram timing register 1? . figure 11-1. memory address tables for 64 bit, burst size 4 and x8 ddr2 devices total cap (m b ) single rank device densty (m b) dev ice widt h bus wid th r/c/b addr lines ba2ba1ba0 a14 a13a12a11a10a09a08a07a06a05a04a03a02a01 a00 row 0 7 6 0 0 262524232221201918171615 14 col 0000ap27131211109850 0 row 0 7 6 0 28 26 25 24 23 22 21 20 19 18 17 16 15 14 col 0000 a p27131211109850 0 row 8 7 6 0 28 26 25 24 23 22 21 20 19 18 17 16 15 14 col 0000 a p2713121110 9 29 5 0 0 row 8 7 6 30 28 26 25 24 23 22 21 20 19 18 17 16 15 14 col 0000 a p2713121110 9 29 5 0 0 256 512 1024 64 15x10x3 2048 512 8 1024 8 2048 8 64 14x10x2 64 14x10x3 256 8 64 13x10x2 figure 11-2. memory address tables for 32 bit, burst size 8 and x8 ddr2 devices device densty (m b) dev ice widt h bus wid th r/c/b add r lin es ba2 ba1 ba0 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00 row0760026252423222120191817161514 col 0000ap1351211109800 0 row07602726252423222120191817161514 col 0000ap1351211109800 0 row87602726252423222120191817161514 col 0000ap13512111092800 0 row 8 7 6 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 col 0000ap13512111092800 0 256 8 32 13x10x2 512 8 32 14x10x2 1024 8 32 14x10x3 2048 8 32 15x10x3 table 11-12. supported dram timings memory speed cl (cas latency) trcd (ras-cas delay) trp (ras precharge) ddr2-400 a 33 3 ddr2-400 b 44 4 ddr2-533 4 4 4 ddr2-667 5 5 5 ddr2-800 55 5 66 6 a: 3-3-3 is not supported for systems which require odt b: may be accomplished by programming 3-3-3 parts to 4-4-4
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 297 intel ? ep80579 integrated processor 11.3.4.1 2t timing mode the address and command group (bank address ba[2:0], address ma[14:0], command pins ras_l, cas_l and we_l) of pins to the dram devices can be clocked either by 1t or 2t timing as shown in figure 11-3 . the control group of pins (cke, cs, odt) are not impacted by the 2t timing mode. when in 1t timing mode, a new command can be issued to the dram devices every dram clock cycle. in 2t timing mode, a new command can be issued to the dram devices every other dram clock cycle i.e., the address and command bus needs to be held valid for 2 cycles. 2t timing reduces the efficiency of the command bus by half but it doubles the setup and hold time for the command and address bus. the timing for the dram data bus and all other signals to the dram devices remain the same between 1t and 2t timing modes. on the ep80579, unbuffered dual dimm configurations are supported in 2t timing mode. single dimm configurations are supported in 1t timing mode. please refer to ta bl e 1 1 - 5 for details. the 2t timing mode can be selected by setting the 2t or1t bit in ?offset 64h: drt1 ? dram timing register 1? . note: 1t/2t timing is also referred to as 1n/2n timing. figure 11-3. 2t and 1t timing mode ck address / command control 2 cycle address/command ck address / command control 1 cycle address/ command 2t timing mode 1t timing mode nop nop nop nop
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 298 order number: 320066-003us 11.3.5 dq/dqs mapping the data signal (dq) to data strobe (dqs) relationship is controlled by the setting in the dram row attribute (dra) registers (see section 16.1.1.40, ?offset 70h: dra[0-1] ? dram row [0:1] attribute register? for details). bits 7:6 and 3:2 of these registers respectively define the device width for the odd and even rows, which is also used in the mapping of dqs signals to dq signals. ta b l e 1 1 - 1 3 shows the mapping of dqs to dq in general terms. ta bl e 1 1 - 1 4 gives the exact relationship. 11.3.6 32-bit mode dq[31:0] and the associated dqs[3:0] are connected to the dimms in 32-bit mode. operation in 32-bit mode is invisible to software and on-chip memory controller interfaces. 11.4 ddr2 features the ddr2 generation of technology introduces some new features beyond standard ddr. this section highlights those supported. 11.4.1 interface signalling voltage the memory controller supports 1.8 v signaling for ddr2-400, ddr2-533, ddr2-667 and ddr2-800 dimms. table 11-13. dra mapping for dqs bits definition dqs per dq 00 reserved na 01 x8 ddr 1 dqs strobe per data byte 10 reserved na 11 reserved na table 11-14. dqs to dq mapping for x8 devices x8 devices dq byte dqs bit 00 11 22 33 44 55 66 77 88
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 299 intel ? ep80579 integrated processor 11.4.2 on-dimm die termination (odt) the jedec ddr2 dram specification requires that ddr2 dimm devices provide selectable on-diedimm termination (odt) as an alternative to traditional discrete termination on the motherboard. the on-dimm termination odt feature is enabled via the ddr extended memory register select (emrs) command odtena and supports both 75 and 150 terminations activated dynamically via dedicated on-dimm termination odt interface signals on the dimm. the ep80579 implements two odt pins to control the behavior of the termination on the two ranks of dram devices. the mapping of the cs & odt pins for the various dimm configurations is shown in ta b l e 1 1 - 6 . the behavior of these odt signals can controlled by setting the appropriate bits in the section 16.1.1.49, ?offset b0h: ddr2odtc - ddr2 odt control register? . the ep80579 controls operation of ddr2 devices with or without on-dimmdie termination enabled, but is verified by intel only in on-die (odt) enabled mode of operation. odt can be disabled by setting the appropriate bits in dramodt bit in section 16.1.1.43, ?offset 7ch: drc ? dram controller mode register? . table 11-15 shows the odt related timing parameters. the ep80579 supports operation of ddr2 devices with or without on-dimmdie termination enabled, but is verified by intel only in the on-die (odt) enabled mode of operation. odt can be disabled by setting the dramodt bit in section 16.1.1.43, ?offset 7ch: drc ? dram controller mode register? . table 11-15. odt timing parameters parameter description value tck clock period 5, 3.75, 3, 2.5ns tond odt turn on delay 2 tck tofd odt turn off delay 2.5 tck cl cas latency 3, 4, 5, 6 rl read latency cl wl write latency (rl - 1) cl - 1 bl burst length 4, 8 odt_rd_on assertion of odt pin to inactive slot during reads = rl - tond - 1 = rl - 3 odt_rd_ontime time for which the odt pin is asserted = tond+1+bl/2+0.5-tonf = 2+1+bl/2+0.5-2.5 = bl/2+1 odt_wr_on assertion of odt pin to inactive slot during writes = wl - tond - 1 = wl - 3 odt_wr_ontime time for which the odt pin is asserted = tond+1+bl/2+0.5-tonf = 2+1+bl/2+0.5-2.5 = bl/2+1 ? for wl = 2 (cl = 3), the odt_wr_on = -1. this requires the controller to enable odt 1 tck before the write command is issued. ep80579 memory controller will not support asserting the odt pin before it issues the write command. the result is that for cl=3 , the termination in the inactive slot will be turned on at the same time the dq bus is being driven by the memory controller. ? the odt turn on and off timings will be calculated by the hardware based on the dram configuration parameters: cl and bl.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 300 order number: 320066-003us 11.4.2.1 odt control of reads during a read command in a 2 slot configuration as shown in figure 11-4 , the memory controller will enable odt on the inactive slot. the odt pin will be asserted by the controller such that the termination in the inactive slot will be enabled 1 tck before the active slot starts driving the dq bus. the termination will be turned-off by the controller ? tck after the last dq is driven by the active slot as show in figure 11-4 . there is no assertion of the odt signal to the dram device in a 1 slot configuration. please refer the section 16.1.1.49, ?offset b0h: ddr2odtc - ddr2 odt control register? for more details on the csr that needs to be programmed by bios so that the memory controller drives the proper odt control signals. 11.4.2.2 odt control of writes during a write command in a 2 slot configuration as shown in figure 11-5 , the ep80579 memory controller will enable odt on the inactive slot. the odt pin will asserted by the controller such that the termination in the inactive slot will be enabled 1 tck before the controller starts driving the dq bus (except for configurations where cl = 3). the termination will be turned-off by the controller ? tck after the last dq is driven by the controller to the active slot as shown in figure 11-5 . during a write command in a one slot configuration, the memory controller will enable odt to the active slot such that the termination is enabled 1 tck before the controller starts driving the dq bus (except for configurations where cl = 3, see note below). figure 11-4. odt timing on back-to-back reads to different slots 0 1 2 3 4 5 6 7 8 termination on slot 2 read a slot 1 odt slot 2 tond = 2 tck c l = 4 bl = 4 tonf = 2.5 tck read a slot 2 bl = 4 c l = 4 termination on slot 1 tond = 2 tck tonf = 2.5 tck odt slot 1 dq slot 2 rtt slot 1 rtt
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 301 intel ? ep80579 integrated processor please refer the section 16.1.1.49, ?offset b0h: ddr2odtc - ddr2 odt control register? for more details on the csr that needs to be programmed by bios so that the memory controller drives the proper odt control signals. note: the memory controller will not enable odt before the write command is issued on the dram interface (see ta b l e 1 1 - 1 5 for more details). for configurations with cl=3, wl=2 the controller will assert the odt pin along with the write command. this will result in the termination in the inactive slot to be enabled at the same time the controller starts driving the dq data bus. 11.4.3 on-die termination (odtz) on the ep80579 the ep80579 supports odt (referred to as odtz to differentiate it from the on- dimmdie termination, odt that is implementation on the dram devices) on the dq/ dqs buffers to improve signal integrity on the inbound path (read data from dram). odtz will be enabled on read accesses to the dram devices and can be in one of the 3 states - 60ohms, 120ohms or off. odtz will be automatically disabled when the ep80579 dq/dqs buffers are enabled for a write access to the dram device. there are no timing parameters implemented to control this functionality and the ddrio pads are responsible for ensuring that odtz is in the disabled state when issuing writes to the dram devices. the termination value for odtz can be set by programming the odtzena bit in section 16.1.1.45, ?offset 88h: sdrc ? ddr sdram secondary control register? . figure 11-5. odt timing on back-to-back writes to different slots 0 1 2 3 4 5 6 7 8 termination on slot 2 write a slot 1 odt slot 2 tond = 2 tck wl = 3 bl = 4 tonf = 2.5 tck write a slot 2 bl = 4 wl = 3 termination on slot 1 tond = 2 tck tonf = 2.5 tck odt slot 1 dq slot 2 rtt slot 1 rtt
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 302 order number: 320066-003us 11.4.4 refresh the ep80579 supports generation of the refresh commands (ref) that are necessary for the dram devices to retain its data. when the refresh cycle is launched by memory controller an address counter, internal to the dram device, supplies the bank address during the refresh cycle. no control of the address bus is required for a refresh cycle. when the refresh cycle has completed, all banks of the ddr2 device will be in the precharged (idle) state. a delay between the refresh command and the next activate command or subsequent refresh command must be greater than or equal to the refresh cycle time (trfc). there are 3 mechanisms through which the ep80579 memory controller will generate the refresh commands: 1. programmable counter: the refresh engine can be programmed to generate refresh commands at programmable time intervals. the choice of intervals are meant to cover ddr2 device trefi specifications. please refer to section 16.5.1.3, ?offset 40h: dcalcsr ? ddr calibration control and status register? details on programming the refresh engine. 2. programmable opcode generation: a single refresh command can be generated under software control using the available opcodes in section 16.5.1.3, ?offset 40h: dcalcsr ? ddr calibration control and status register? . 3. self-refresh exit state machine: the self-refresh exit engine will issue one refresh command to each rank after it brings them out of self refresh. note: the ep80579 does not support posted refresh cycles. 11.4.5 self-refresh the ep80579 supports the generation of self-refresh commands that can be used to retain data in the dram devices without any support from the memory controller. the dram device has built-in counters timers to accommodate the self-refresh operation. there are 2 mechanisms to enter and exit the self-refresh mode: 1. self-refresh entry a. s3: the memory controller will issue a self-refresh entry command at the end of the s3 sequence. b. programmable opcode generation: a self-refresh entry command can be generated under software control using the available opcodes section 16.5.1.3, ?offset 40h: dcalcsr ? ddr calibration control and status register? . 2. self-refresh exit a. power up after s3 event: the memory controller implements a self-refresh exit engine which under software control can bring the dram devices out of self- refresh. refer to table 16-226, ?rules about issuing self-refresh and refresh commands using dcalcsr.opcode? on page 604 for details on the rules that software should follow when using this mechanism. b. writing to drc.cke[1:0] register bits: by writing to the drc.cke[1:0] registers, software can assert the cke pins to the dram devices bringing them out of self-refresh.please refer to section 16.5.1.59, ?offset 1f4h: mb_err_data32 - memory test error data 3? for more details. the de-emphasis feature on the command/clock pins should be disabled before entering self-refresh. please see the demca bit in section 16.5.1.63, ?offset 264h: ddriomc1 - ddr io mode control register 1? for more details.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 303 intel ? ep80579 integrated processor 11.4.6 rcomp the ep80579 supports rcomp for the ddr pads. rcomp control is implemented for 2 groups of ddr pads. the rcomp used for the 2 groups can either be static or dynamic based on ddriomc2.legoverride[5:4]. for more details on how to control the rcomp for the 2 groups of ddr pads please see section 16.5.1.64, ?offset 268h: ddriomc2 - ddr io mode control register 2? . the final values that are used for group 1 and group 2 drivers can be viewed using the bits in section 16.5.1.29, ?offset f0h: diomon - ddr i/o monitor register? . ? group1: data, data mask and data strobes: ? ddriomc2.legoverride[4:0] bits can be used in dynamic mode to achieve the target impedance on the group 1 ddr pads. in dynamic rcomp mode, these csr bits control several pull-up devices that are binary sized. the pull-up devices are tuned using an external resistor (rext). in static mode, ddriomc2.legoverride[3:0] determines the rcomp value used by the group 1 ddrio pads. ? group2: command, address and clock: ? in dynamic rcomp mode the digital control for these group of ddr pads is derived by multiplying the group 1 digital control by a factor determined by ddriomc2.legoverride[6:9]. in static rcomp mode, ddriomc2.legoverride[6:9] directly controls the rcomp value used by the group 2 ddrio pads. 11.4.7 ddr2 mr and emr settings table 11-16 shows the supported settings of ddr2 mode register (mr) and extended mode register (emr). note that only the architecturally relevant settings of the mr and emr are listed in this table. these regist ers can be updated using the mrs and emrs commands. please see section 16.5.1.3, ?offset 40h: dcalcsr ? ddr calibration control and status register? and section 16.5.1.4, ?offset 44h: dcaladdr - ddr calibration address register? for more details on generation of mrs and emrs commands. table 11-16. supported ddr2 mr and emr settings mr/emr feature ep80579 support burst type sequential only burst length 4 (64-bit mode) and 8 (32-bit mode) write recovery for auto-precharge supported. settings based on speed bins. please see section 16.0, ?imch registers? for details. cas latency 3, 4, 5 and 6 depending upon speed bin. please see table 11-12 and section 16.0, ?imch registers? for more details. odt (emr) supported. please see section 11.4.2 for more details. ocd calibration (emr) not supported. additive latency (emr) not supported.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 304 order number: 320066-003us 11.4.8 scrubbing support the memory controller will support both demand scrubbing and background scrubbing in hardware. this section provide details of the scrubbing mechanism. 11.4.8.1 demand scrubbing when the controller detects a single bit error on a dram read, the ecc logic fixes the single bit error and returns the corrected data to the requester. the controller also writes the corrected data back into dram using the demand scrub operation. 11.4.8.2 background scrubbing the controller supports a simple state machine that periodically injects read transactions into the stream. the scrub rate meets a general requirement for scrubbing a 4gb memory capacity every 24 hours. it can also be programmed to scrub the entire ddr at faster rates, if that is desired. rates available extend from an entire scrub every few days, to every day, every hour, every minute, and even very fast rates, mainly used for validation purposes. data for a background scrub read operation is discarded if no error is detected on the read. when a single bit error is detected on a background scrub read transaction, the mechanism specified in figure 11.4.8.1 is used to correct the single bit error in dram. the read data is dropped. when a double bit error is detected on a background scrub read transaction, the controller log the error and interrupts the ia-32 core. 11.5 error handling the memory controller accesses may encounter data with ecc violations and/or parity errors. ? for writes with bad parity, as indicated on bits in the command from either aioc memory target (mt) or imch, the memory controller will execute the write, poisoning the data as it writes it to ddr. please see table 11-17 for the granularity of poisoned data. poisoning is accomplished by inverting each bit of ecc calculated for that particular write, based on the bad write data sent to the memory controller from aioc or imch. ? for reads from ddr with single bit parity errors, the memory controller will correct all correctable errors, and return the data, to either requestor, corrected, and without a bad parity indication. status logging, as discussed above, will be done. ? for reads from ddr with multiple bit, uncorrectable ecc violations, the memory controller will return the data to either requestor, however, a bad parity indication will be driven back with the data. please see table 11-17 for the granularity of poisoned data. aioc memory target (mt) or imch should poison the data when seeing the bad parity bit set, along with the read data returned.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 305 intel ? ep80579 integrated processor for compatibility with accepted ia platform algorithms and mechanisms, the memory controller will follow general ia error logging and reporting mechanisms as closely as possible with the following exception: ? the memory controller does not implement uncorrectable retries (ded retries). therefore all registers and bit definitions that support uncorrectable retries are not implemented in the memory controller. table 11-17. poisoning granularity command error source command source memory controller action read from dram dram (ded) imch poison parity bits on 32b granularity and return read data to imch. read from dram dram (ded) aioc mt poison parity bits on 8b granularity and return read data to aioc memory target (mt). write to dram ia or io device including aioc (parity error) imch poison ecc bits on 16b granularity and write to dram. write to dram aioc (parity error) aioc mt poison ecc bits on 8b granularity and write to dram. ? ecc can be enabled by setting the ddim bit in section 16.1.1.43, ?offset 7ch: drc ? dram controller mode register? . ? poisoning of write data to dram can be enabled using the mempen bit in section 16.1.1.44, ?offset 84h: eccdiag ? ecc detection/correction diagnostic register? . ? poisoning of read data from dram to imch or aioc mt can be enabled by using endp bit in section 16.1.1.43, ?offset 7ch: drc ? dram controller mode register? .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 306 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 307 intel ? ep80579 integrated processor 12.0 enhanced direct memory access controller (edma) the imch includes an integrated four-channel enhanced direct memory access (edma) controller to facilitate ?push model? block transfers without ia-32 core intervention for higher overall system performance. this section details the operating modes, setup, interfaces, register set, and high-level implementation of the edma controller. 12.1 overview the edma engine provides a highly efficient means to move data within local system memory or from the local system memory to the i/o subsystem. each edma channel provides low-latency, high-throughput data transfer capability with minimal ia-32 core intervention. for the ia-32 core, it is a ?fire and forget? type of memory transfer, with a doorbell starting mechanism and interrupt capability for signaling completion. each channel optimizes block transfers of data through a linked-list descriptor chaining mechanism that supports scatter/gather operations. each channel is responsible for providing the edma programming interface, ex ecuting the data transfers, and handling any errors encountered during operation. each channel initiates traffic on both the local system memory and outbound traffic arbiter interfaces, and is designed such th at each independent channel is capable of generating at least 1 gb/s of traffic during data hauls. in the absence of competition from other traffic sources, multiple channels could theoretically saturate the local memory interface. see figure 12-1 . each channel is independently enabled by setting the start bit in the control configuration register. the start bit is cleared after power-up or reset and consequently the edma controller is disabled until software explicitly turns each one on.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 308 order number: 320066-003us 12.1.1 features the following features are supported by the edma controller: ? four independent channels (see figure 12-2 ) ? dedicated data transfer queue per channel ? full register set for descriptor and transfer handling per channel ? support for transfer between main memory locations, and from memory to the i/o subsystem ? pci express* support of traffic class to provide external prioritization of traffic ? supports transfers only between two physical addresses ? 32-bit (4 gb) addressing range on the local system memory interface figure 12-1. concept diagram of edma data path b6119-01 cmach0 cmach2 cmach3 cmach1 edma arbiter ep80579 edma engine memory pci express interface port a memory-to-memory edma data path memory-to-i/o edma data path transaction requests pci express port a links
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 309 intel ? ep80579 integrated processor ? 32-bit addressing range on the memory mapped i/o subsystem interface (no nsi access) ? maximum transfer of 16 mb transfers per descriptor ? fully programmable by the ia-32 core ? configuration space mapping for edma engine capability and control ? memory-mapped space for edma channel-specific register sets ? chain mode edma transfer with automatic data chaining for scattering/gathering of data blocks ? edma chaining continued until a ?null? descriptor pointer is encountered ? support for appending a block to the end of current edma chain ? automated descriptor retrieval from local memory during chaining ? single read ? programmable independent alignment between source and destination ? byte aligned transfer on the local system memory interface ? byte aligned transfer on the i/o subsystem interface ? support for non-coherent transfers both to and from system memory on a per descriptor basis ? independent control of coherency for source and destination ? programmable support for interrupt generation on block?by-block basis ? selectable msi or legacy level-sensitive interrupt function ? end of current block transfer ? end of current chain ? for any error causing a transfer to abort ? increment of the source and destination address for standard transfers ? increment of the destination and decrement of the source address to enable byte stream reversal ? constant address mode for the destination address based on the transfer granularity to enable targeting of memory mapped i/o fifo devices ? buffer/memory initialization mode 12.1.2 logical block diagram figure 12-2 shows the conceptual interface of the edma channels to different l interfaces.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 310 order number: 320066-003us 12.2 channel programming interface the edma channel programming interface is accessible from the ia-32 core via a combination of chain descriptors (shown in figure 12-3 ) written to main memory and a memory-mapped internal register set. the edma controller provides four channels, each of which can be independently used to transfer data within the local system memory or from the local system memory to the i/o subsystem. each channel has its own set of 12 registers. refer to ?memory mapped i/o for edma registers? on page 651 for a description of the channel register set. the channel programming interface is accessible from the ia-32 core via a combination of descriptors written to main memory and a memory-mapped internal register set. each channel is programmed independently. each channel supports full chaining capability. the chain descriptors can be cascaded together in system memory to form a linked list. each chain descriptor contains all the information necessary for transferring a block of data, as well as a pointer to the next chain descriptor in the list. the next descriptor pointer of the last chain descriptor in a linked list will be a null pointer (address zero), indicating the end of that chain. figure 12-2. conceptual diagram of four channel edma engine edma channel1 edma channel0 edma arbiter reqs gnts pci express interface memory interface fsb interface cfg/tap interface system arbiter edma channel2 edma channel3
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 311 intel ? ep80579 integrated processor throughout this document, all register references are made using the name of the lower 32-bit register, irrespective of whether the target is a 32-bit or 64-bit register with lower and upper halves. 12.3 chaining operation an edma access transfers a block of data from one address to another. the desired transfer is specified by setting up a linked list of chain descriptors in the local system memory, and initiated by programming the first chain descriptor start address into the next descriptor address registers (ndar/nduar) of the edma channel and setting the start bit of the channel control register (ccr). each block of the transfer is defined by a descriptor in main memory containing the source address, destination address, transfer length and control values. setting the start bit of the channel control register (ccr) causes the channel to fetch the current chain descriptor information and place it into its corresponding register set. once all the register information has been fetched, the actual data transfer starts. note: the start bit will be ignored unless the channel status register (csr) is in an appropriate state. software must ensure that the status bits for end of chain, stopped, aborted, and active are all clear prior to attempting to initiate a new transfer with the start function. 12.3.1 chain descriptor definition all edma transfers are controlled by chain descriptors in the local system memory. a single block transfer will specify only a single chain descriptor. chain descriptors can be linked together to form a linked list, providing a capability for complex edma scatter/ gather operations. figure 12-3 shows the format of a chain descriptor. each chain descriptor consists of eight contiguous dwords (32-bits) in the local system memory, and must be naturally aligned to an eight dword boundary. all eight dwords must be defined and are required for the proper operation of the edma engine.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 312 order number: 320066-003us 12.3.2 dma chain descriptor in memory each chain descriptor is composed of eight dwords. each dword in the chain descriptor in the local memory is analogous to the corresponding edma channel register value. the bit definitions in the chain descriptor in memory are identical to those of the corresponding channel register. refer to the edma channel-specific register definitions in ?memory mapped i/o for edma registers? on page 651 for descriptions of the fields defined by a chain descriptor. after a transfer has been requested, the edma channel reads the specified chain descriptor from local system memory and updates its own corresponding channel registers automatically. 12.3.3 chain descriptor usage a linked list of chain descriptors may be built in the local system memory to transfer data within the local system memory or from local system memory to i/o subsystem memory. an application may build multiple chain descriptors to transfer many blocks with differing source addresses, destination addresses, data transfer counts, alignments, and coherence attributes. the application may connect these chain descriptors using the next descriptor address in a sequence of chain descriptors, creating a linked list of edma transfers, all of which may complete without any processor intervention. figure 12-4 shows a linked list of transfers built in local system memory and illustrates how they are ?chained? together. figure 12-3. chain descriptor in memory lower 32-bit source memory address register b4483-01 upper 32-bit source memory address register lower 32-bit destination memory address register upper 32-bit address of next chain descriptor register lower 32-bit address of next chain descriptor register upper 32-bit address of next chain descriptor register number of bytes to transfer register descriptor control register source upper address (suar) destination address (dar) destination upper address (duar) source address (sar) next descriptor address (ndar) next descriptor upper address (ndaur) transfer count (tcr) descriptor control (dcr) chain descriptor in memory description
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 313 intel ? ep80579 integrated processor it is possible but unexpected that the source and destination address ranges defined by chain descriptors may overlap in physical memory. while there are scenarios where this may produce no errors in the resulting memory image, the software must ensure that no failure results from such usage. hardware checks are not built into the edma mechanism to ensure that source and destination physical address ranges do not overlap. similarly, there are no hardware interlocks to ensure that independent channels are not programmed to modify the same address range simultaneously. if software were to create such a situation, the resultant memory image would be indeterminate, since there are no guarantees as to the relative access ordering among simultaneously active channels. figure 12-4. chaining mechanism source address (sar) source upper address (suar) destination address ( dar) destination upper address (duar) next descriptor address (ndar) next descriptor upper address ( nduar) descriptor control (dcr) next descriptor address register (32 -bit or 64-bit) source address (sar) source upper address (suar) destination address (dar) destination upper address (duar) next descriptor address (ndar) next descriptor u pper a ddress (nduar) descriptor control (dcr) source address (sar) source upper address (suar) destination address (dar) destination upper address (duar) next descriptor up per a ddress (nduar) descriptor control (dcr) first block transfer second block transfer nth block transfer end of chain (null value) linked descriptors in memory next descriptor address (ndar) transfer count (tcr) transfer count (tcr) transfer count (tcr)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 314 order number: 320066-003us 12.3.4 scatter/gather transfer the edma descriptors in memory may be defined such that they cause the channel to perform typical scatter/gather data transfers. to ?gather? data, software may create a linked list of descriptors that will move non-contiguous source blocks of data into a contiguous set of destination blocks. to ?scatter? data, software may create a linked list of descriptors that will move contiguous blocks of source data to non-contiguous destination blocks. it is even possible to program the edma transfer descriptors in such a way that some blocks of source data within a single chain are moved to new memory locations, while other blocks are moved out to the i/o subsystem. there is no hardware restriction limiting the nature of source and destination address ranges, other than that the source and destination types (memory or i/o subsystem) must match the descriptor address mappings. the imch aborts the edma operation and reports a programming error if this requirement is not met. 12.3.5 appending to a descriptor chain after an edma channel has started processing a linked list of descriptors, the application software may need to append a chain descriptor to the end of the current chain without tearing down the transfer in progress. such an operation requires a mechanism to guarantee that a descriptor is never in the process of modification by the ia-32 core while being retrieved by the edma channel (this would result in a hybrid descriptor loaded into the corresponding edma channel register set, and spurious operation). the suspend function of the edma controller is defined to facilitate this type of usage. the preferred mechanism for appending to a linked list currently being processed is to suspend the current transfer, modify the terminal chain descriptor to update its next descriptor address field(s), and then allow the transfer to resume. this is accomplished by first setting the suspend bit in the channel control register (ccr) followed by a read of the channel status register (csr) to verify that the suspend has taken effect.the next descriptor address fields of the terminal chain descriptor in the current linked list are updated with the address of th e first descriptor to be appended. after this update has occurred, software then clears the suspend bit, sets the channel resume bit and allows execution to proceed. note: a single write to the ccr may update both bits simultaneously. this append algorithm covers the following cases: ? the edma channel has completed execution of the terminal descriptor in the original chain, and is idle. the edma channel examines the channel resume bit when the channel control register (ccr) is written. if the bit is set, the edma channel will automatically clear the bit and re-read the last chain descriptor (as indicated by cdar/cduar), which updates ndar with the appended chain descriptor address. a non-null value in ndar will result in a fetch of the target chain descriptor, and resumed execution. (if the resulting ndar/nduar pair remains null, the edma channel will remain idle.) ? the edma channel is executing a descriptor prior to the terminal chain descriptor in the linked list. regardless of whether the channel completes execution of its current descriptor prior to the ccr write to clear suspend and set channel resume, the channel will re-read the current chain descriptor in response to the channel resume bit. the next chain descriptor in the chain will be fetched from the address indicated by ndar/nduar, and the channel will continue execution. the appended chain descriptor (or descriptors) will be executed after the channel reaches the end of the original chain. ? the channel is executing the terminal chain descriptor at the time of the suspend command. the channel will complete the final chain descriptor of the original linked
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 315 intel ? ep80579 integrated processor list and examine the state of the channel resume bit when the suspend bit is cleared. as in the prior case, the channel will re-read the current chain descriptor to update ndar/nduar, load the first appended chain descriptor, and resume execution. the only difference in this case is that the re-read operation on the current chain description was required for proper execution (in the prior case it was wasted effort, but did not result in erroneous behavior). if the channel had completed execution of the terminal chain descriptor and set the ?end of chain? status bit, this bit is automatically cleared when the channel resumes operation. ? if the current transfer had a non-fatal error, it follows one of the above cases. if the error is fatal, the channel will abort, and the software must take proper action and restart the edma transfer. note that the channel will ignore the state of the channel resume bit if the abort status has not been cleared from the csr. this simplifies the case of linked list append, as software need not take extra steps to verify that no errors exist prior to setting the channel resume bit. the normal polling or interrupt mechanism may handle the error without interacting with the append routine. note: software is at liberty to modify the next descriptor address fields of the terminal chain descriptor at any time after setting the suspend bit in the ccr ? there is no requirement that software verify that the channel has gone idle prior to modifying the memory image. also, software does not need to verify that the channel has completed execution of the current chain descriptor and acknowledged suspend edma prior to issuing the final update to csr that sets the channel resume bit. the hardware interlock will cover the case where the end of the chain descriptor is reached during the append sequence, but proper operation is guaranteed regardless of whether the interlock is exercised. a further simplification to the linked list append sequence is possible in the case of chain descriptors located strictly below the 4 gb boundary in memory; that is, in the case where nduar of the terminal descriptor is zero and only ndar contains asserted bits. under these conditions, it is safe to issue the ndar write cycle without first suspending operation, because there is no risk of a hybrid ndar/nduar pair retrieved by the channel. if desired, software could take the simplified approach of issuing the descriptor update followed by a ccr write to set the channel resume bit. in all cases, this will result in successful execution of the appended chain irrespective of current execution status. 12.3.6 splicing a descriptor chain into a linked list software may utilize a slight modification of the algorithm described in ?appending to a descriptor chain? on page 314 to splice a new descriptor or chain of descriptors into the chain already executing. such an operation would be useful to provide service to a higher priority edma transfer without aborting work already in progress. the steps required to splice into a chain are as follows: 1. write to the ccr to set the suspend edma bit. 2. read the cdar/cduar pair to determine which chain descriptor the edma channel is currently executing. 3. read the next descriptor address field of the current chain descriptor, and write the retrieved address into the next descriptor address field of the terminal chain descriptor in the linked list to be spliced-in. 4. write the address of the descriptor (or lead descriptor of the chain) to be spliced-in into the next descriptor address field of the current descriptor (in memory). 5. write to the ccr to clear the suspend bit and set the channel resume bit.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 316 order number: 320066-003us the hardware interlock of the suspend function will guarantee that the channel will not proceed beyond the current chain descriptor until the suspend bit has been cleared in the ccr, and the channel resume function will guarantee that the current chain descriptor will be re-read to retrieve the modified ndar/nduar value pointing to the spliced chain descriptor. the channel will resume execution with the head of the spliced linked list, and will traverse that linked list back to its original list of chain descriptors. note: the channel must refrain from updating cdar/cduar from ndar/nduar in addition to dropping the returned data. were the cha nnel to update its cdar/cduar values, it would ?skip? the entire spliced chain in response to channel resume, because software would have spliced in the new descriptor chain at a position ?behind? the new value for cdar/cduar in the original chain. 12.4 transfer types the edma controller is optimized to perform high throughput data transfers between local memory locations, and from local memory to i/o subsystem memory. supported transfer types are summarized in the following subsections. 12.4.1 local memory to local memory the local memory to local memory transfer will move blocks of data specified by descriptors from one region in main memory to another. the channel control hardware will issue read cycles to the local memory interface using an incrementing or decrementing source address, and place the retrieved data into a channel buffer. it will then issue write cycles back to the memory interface using an incrementing or constant destination address. each edma channel supports pipelining making it possible for a single channel to have multiple read and write cycles active at the same time. all read requests to memory are a full cache-line in length (64 b), so the edma channel must discard data as needed to realign the initial read in a transfer to the alignment specified by the source address. the number of cache-line reads issued by the controller in any given internal arbitration cycle is dependent upon the number of available cache-line spaces in the data queue, and upon the configuration of the inbound/outbound arbiter, but is limited to a maximum of two cache-line requests. all write requests to memory are also a full cache-line in length, although not all bytes must be enabled for every write. the edma channel is responsible for translating the alignment specified by the destination address registers and the destination alignment bit in dcr into a corresponding set of byte enables for the initial write in a transfer. once the initial alignment has been enforced, the rest of the transfer on behalf of any given descriptor is contiguous. 12.4.2 local memory to i/o subsystem memory the local memory to i/o memory transfer will move blocks of data specified by chain descriptors from a source region in main memory to a destination region in the i/o subsystem. the channel control hardware will issue read cycles to the local memory interface using an incrementing or decrementing source address, and place the retrieved data into a channel buffer. it will then issue write cycles to the i/o subsystem using an incrementing or constant destination address. each edma channel supports pipelining for this transfer type as well, thus multiple read and write requests may be outstanding from the same edma channel at any given time during a block transfer. all read and write requests are full cache-line size (64 b), irrespective of alignment and length specified in the descriptors; it is up to the edma channel to discard read data and calculate write byte enables to enforce the descriptor alignment specified.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 317 intel ? ep80579 integrated processor the number of reads issued by each edma channel in any given internal arbitration cycle is dependent upon the number of available cache-line spaces in the data queue, and upon the configuration of the inbound/outbound arbiter, but is limited to a maximum of two cache-line requests. the number of writes issued in any given arbitration cycle is dependent upon the number of cache-lines waiting in the data queue, and upon the ccr configuration, but is limited to a maximum of two cache-line requests. the edma controller never speculatively issues a write in anticipation of data returning from the memory subsystem. 12.4.3 i/o memory to local memory the i/o memory to local memory transfer is not supported. 12.4.4 i/o memory to i/o memory the i/o memory to i/o memory transfer is not supported. 12.5 addressing each edma is capable of 36-bit addressing on both source and destination interfaces. alignment specification is independent for source and destination. transfers may be specified to be aligned to any byte boundary except in destination constant address modes where the granularity is greater than 1-byte. each edma channel uses direct addressing for both the source and destination interfaces. there is no internal support for any virtual address translation. each edma channel will attempt to compensate for misalignment between source and destination. at a minimum, misalignment will result in decreased performance at either end of the transfer, where a second read is required prior to the first write, or vice- versa. 12.5.1 address coherence each edma channel provides support for non-coherent access specification to improve bandwidth and provide more consistent average latency, as well as to free the fsb for simultaneous ia-32 core traffic. the source and destination addresses for each dma channel may be independently specified on a chain descriptor granularity via bit settings in the dcr to be either coherent or non-coherent. for non-coherent accesses, no fsb snoop cycle is issued on behalf of edma memory accesses to snoop processor caches. the software must verify that snoops of ia-32 core caches are not required for proper system operation prior to setting eith er of the non-coherent bits in any given descriptor. non-coherent accesses are used for un-cacheable memory regions, or for cacheable regions where software can guarantee no modified state in any ia-32 core cache by some other means. the non-coherent attribute further implies relaxed posted write ordering as defined by pci/pci-x. a non-coherent write may pass coherent posted writes en route to memory. software should verify that snoops of ia-32 core caches are not required for proper system operation prior to setting either of the non-coherent bits in the dcr field of any given descriptor. software need not take special steps to accommodate the relaxed ordering behavior, because each channel will only generate a single stream of output per descriptor, and no ordering is defined between competing i/o subsystem traffic sources. non-coherent access may be used for uncacheable memory regions, or for cacheable regions where software can guarantee the ia-32 core cache state has not been modified by other means.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 318 order number: 320066-003us an example usage model for non-coherent accesses is management of data block areas reserved for use by an edma -capable peripheral device, such as a network interface controllers (nic). the nic writes data directly into a buffer in memory allocated for the exclusive use of that device. each edma channel would then execute a block transfer from that buffer to an area allocated for ia-32 core use. both integrity verification and security functions executed by the ia-32 core could follow such a model. as long as software ensures that the ia-32 core never traverses the device-allocated memory, the block transfer could be accomplished using non-coherent source address reads followed by coherent destination address writes. note: i/o subsystem destination addresses are always treated as non-coherent or coherent based on the bit setting in the dcr. setting the destination coherency bit will result in the pci-express snoop not required attribute bit being clear, snoop required. example: setting bdf 010 offset 2c dcrx register bit 7 destination non-coherent = 0 => snoop not required attribute bit = 1 destination coherent = 1 => snoop not required attribute bit = 0 12.5.2 addressing modes many different addressing modes are available, including standard byte movement mode, byte reversal mode, constant address mode, and memory and buffer initialization modes. in the examples shown for each of the following modes, a 64-bit interface is used for simplicity. the interface could be the memory interface or an external device on an expansion bus. internally, the edma data path is significantly wider. 12.5.2.1 standard byte movement mode standard byte movement mode is the most common method in which data is transferred within the memory sub-system. in this mode, the source and destination are specified down to the byte address. the source address is incremented as data is read and the destination address is incremented as data is written. transfers can be memory to memory or memory to memory mapped i/o. figure 12-5 illustrates a memory to memory data transfer between unaligned 64-bit, source and destination addresses.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 319 intel ? ep80579 integrated processor 12.5.2.2 decrement/byte reversal mode decrement/byte reversal mode is useful when an entire data stream needs to be reversed at the byte level. this must not be confused with endian swapping, as this implies a specific word size. in this mode, the source and destination are specified down to the byte address. the source data is read in reverse order and written to the destination in increasing order. transfers can be memory to memory or memory to memory mapped i/o. figure 12-6 illustrates a memory to memory data transfer between unaligned 64-bit, source and destination addresses when the source is in decrement mode and the destination is in increment mode. figure 12-5. source and destination in increment mode transfer address b4484-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 8 16 1 9 8 7 6 5 4 3 17 16 15 14 13 12 11 20 19 2 10 18 a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0308h 4001 0310h 4001 0318h lsb msb memory 64-bit source data block transfer 10 programmed values 0000 0088h a000 0201h 4001 0307h 0000 0014h 0000 001fh edmactl suar/sar duar/dar tcr dcr source qword load@a0000200 qword load@a0000208 qword load@a0000210 destination byte store@40010307 qword store@40010308 qword store@40010310 3-byte store@40010318 64-bit destination byte number bus operation
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 320 order number: 320066-003us 12.5.2.3 constant address modes in constant address mode, there is built-in support for ?mailbox? destinations in the memory mapped i/o subsystem. a mailbox is a single or limited set of addresses used to collect information for dispersal later to their actual destination addresses by the receiving device. in constant address mode, one, two, or four bytes will be sent repeatedly until the byte count is satisfied. the source address can be byte aligned; however, unlike other transfer modes, in constant address mode the destination address must be aligned to the granularity size. no errors will be flagged if the destination address is not matched to the granularity, but the required lower address bits will be ignored. additionally, software must ensure that the transfer byte count is an integer multiple of the granularity size. no error will be flagged if the transfer byte count is not an integer multiple and the remaining bytes in the requested granularity will be padded and transferred. figure 12-6. source in decrement and destination in increment mode transfer (byte reversal) address byte number b4485-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 8 16 20 12 13 14 15 16 17 4 5 6 7 8 9 10 1 2 19 11 3 a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0308h 4001 0310h 4001 0318h lsb msb memory 64-bit source data block transfer 10 programmed values 0000 0088h a000 0214h 4001 0307h 0000 0014h 0000 101fh edmactl suar/sar duar/dar tcr dcr source qword load@a0000210 qword load@a0000208 qword load@a0000200 destination byte store@40010307 qword store@40010308 qword store@40010310 3-byte store@40010318 64-bit destination 18 17 bus operation
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 321 intel ? ep80579 integrated processor in this mode, the edma will write to the address that is placed in the dar/duar pair with the transfer size specified in the granularity field. the transfers will continue until the byte count register is satisfied. logicall y, transfers will only be memory to memory mapped i/o. constant address mode can be used with an increasing or decreasing source address to present data to the external device in either order. figure 12-7 through figure 12-9 illustrate data transfers between an unaligned 64-bit, source and a constant destination addresses when the source is in increment mode. figure 12-7. source in increment and destination in 1-byte granularity constant mode transfer address b4486-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 8 16 1 2 a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0300h 4001 0300h 4001 0300h lsb msb memory 64-bit source data block transfer 10 programmed values 0000 0088h a000 0201h 4001 0307h 0000 0014h 0000 403fh edmactl suar/sar duar/dar tcr dcr source qword load@a0000200 qword load@a0000208 qword load@a0000210 destination byte store@40010307 (20 times) 64-bit destination byte number bus operation 20
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 322 order number: 320066-003us figure 12-8. source in increment and destination in 2-byte granularity constant mode transfer address b4487-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 8 16 2 4 a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0300h 4001 0300h 4001 0300h lsb msb memory 64-bit source data block transfer 10 programmed values 0000 0088h a000 0201h 4001 0306h 0000 0014h 0002 403fh edmactl suar/sar duar/dar tcr dcr source qword load@a0000200 qword load@a0000208 qword load@a0000210 destination 2-byte store@40010306 (10 times) 64-bit destination byte number bus operation 20 1 3 19
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 323 intel ? ep80579 integrated processor figure 12-10 , figure 12-11 , and figure 12-12 illustrate data transfers between an unaligned 64-bit, source and a constant destination addresses when the source is in decrement mode. figure 12-9. source in increment and destination in 4-byte granularity constant mode transfer address b4488-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 8 16 4 8 a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0300h 4001 0300h 4001 0300h lsb msb memory 64-bit source data block transfer 10 programmed values 0000 0088h a000 0201h 4001 0304h 0000 0014h 0004 403fh edmactl suar/sar duar/dar tcr dcr source qword load@a0000200 qword load@a0000208 qword load@a0000210 destination dword store@40010304 (5 times) 64-bit destination byte number bus operation 20 3 7 19 2 6 18 1 5 17
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 324 order number: 320066-003us figure 12-10.source in decrement and destination in 1-byte granularity constant mode transfer address b4489-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 8 16 20 19 a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0300h 4001 0300h 4001 0300h lsb msb memory 64-bit source data block transfer 10 programmed values 0000 0088h a000 0214h 4001 0307h 0000 0014h 0000 503fh edmactl suar/sar duar/dar tcr dcr source qword load@a0000200 qword load@a0000208 qword load@a0000210 destination byte store@40010307 (20 times) 64-bit destination byte number bus operation 1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 325 intel ? ep80579 integrated processor figure 12-11.source in decrement and destination in 2-byte granularity constant mode transfer byte number 10 edmactl suar/sar duar/dar tcr dcr programmed values 0000 0088h a000 0214h 4001 0306h 0000 0014h 0002 503fh address a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0300h 4001 0300h 64-bit destination lsb memory 19 17 12 11 10 9 8 7 6 5 4 3 2 1 msb 64-bit source data block transfer 20 19 18 17 16 15 14 13 4001 0300h 1 ... 20 18 2 bus operation qword load@ a0000210 qword load@ a0000208 qword load@ a0000200 2-byte store@ 40010306 source destination (10 times)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 326 order number: 320066-003us 12.5.2.4 buffer and memory initialization modes the edma can be used to write a constant value to local memory or to memory mapped i/o. as with normal transfers, descriptors are used to specify the memory blocks to which the data contained in the source address register is written. when buffer or memory initialization modes are selected, the data in the sar is sent to the destination address. no data is fetched. data is transferred in 32-bit replicated chunks to the destination. the transfers will continue until the byte count register is satisfied. 12.5.2.4.1 memory initialization mode memory initialization mode transfers can be to memory or to memory mapped i/o. in this mode, the destination can be specified down to the byte address. figure 12-13 illustrates memory initialization to an arbitrary destination address. figure 12-12.source in decrement and destination in 4-byte granularity constant mode transfer byte number 10 edmactl suar/sar duar/dar tcr dcr programmed values 0000 0088h a000 0214h 4001 0304h 0000 0014h 0004 503fh address a000 0200h a000 0208h a000 0210h 4001 0300h 4001 0300h 4001 0300h 64-bit destination lsb memory 17 13 12 11 10 9 8 7 6 5 4 3 2 1 msb 64-bit source data block transfer 20 19 18 17 16 15 14 13 4001 0300h 1 18 14 2 19 15 3 20 16 4 bus operation qword load@ a0000210 qword load@ a0000208 qword load@ a0000200 dword store@ 40010304 source destination (5 times)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 327 intel ? ep80579 integrated processor 12.5.2.4.2 buffer initialization mode buffer initialization mode transfers will logically only be to memory mapped i/o and will utilize the constant destination mode and granularity fields of the dcr. the address granularity is dictated by the granularity field in the dcr. no errors will be flagged if the destination address is not matched to the granularity, but the required lower address bits will be ignored. figure 12-14 though figure 12-16 illustrate buffer initialization mode to an arbitrary destination address. figure 12-13.source in memory initialization and destination in increment mode transfer value xx bus operation byte store@ 40010307 qword store@ 40010308 qword store@ 40010310 destination 4001 0300h 4001 0308h 4001 0310h 64-bit destination lsb memory a5 a5 81 bc e6 a5 81 bc e6 81 bc e6 msb a5 81 bc e6 a5 81 bc e6 4001 0318h 3-byte store@ 40010318 edmactl suar/sar duar/dar tcr dcr programmed values 0000 0088h a581 bce6h 4001 0307h 0000 0014h 0000 201fh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 328 order number: 320066-003us figure 12-14.source in buffer initialization and destination in 1-byte granularity constant mode transfer figure 12-15.source in buffer initialization and destination in 2-byte granularity constant mode transfer byte number 10 edmactl suar/sar duar/dar tcr dcr programmed values 0000 0088h a581 bce6h 4001 0307h 0000 0014h 0000 503fh address 4001 0300h 4001 0300h 4001 0300h 64-bit destination lsb memory a5 a5 msb 4001 0300h a5 ... bus operation byte store@ 40010307 destination (20 times) byte number 10 edmactl suar/sar duar/dar tcr dcr programmed values 0000 0088h a581 bce6h 4001 0306h 0000 0014h 0002 503fh address 4001 0300h 4001 0300h 4001 0300h 64-bit destination lsb memory a5 a5 msb 4001 0300h a5 ... 81 81 81 bus operation 2-byte store@ 40010306 destination (10 times)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 329 intel ? ep80579 integrated processor 12.5.3 pci express traffic class to provide traffic shaping and quality of service within the system fabric, the edma contains the traffic class field within the dcr. traffic class is provided to the external switches, bridges, and other fabric devices to allow one transaction to pass another based on a software generated priority map. the three bit field in the dcr is directly copied to the transaction traffic class field in the pci-express header as write transactions are generated to pci-express. this field is ignored for all other destinations. 12.6 channel data queuing each channel contains a data buffer that is four cache-lines in size (256 bytes). the data buffer holds data temporarily to facilitate pipelining and hide latency, improving the throughput of data transfers between the source and destination. 12.7 error conditions any of several possible error conditions may arise during a transfer depending on which interfaces the transfer utilizes. the interfaces covered are the edma controller interface, the memory interface, and the i/o subsystem destination port interface. all error conditions are reported by setting the corresponding error bits in the channel status register (csr). the subsections below describe all possible errors at each interface that the edma controller must detect and report. for those errors resulting in a channel abort, the response to the error is highly configurable. the controller may be configured to figure 12-16.source in buffer initialization and destination in 4-byte granularity constant mode transfer byte number 10 edmactl suar/sar duar/dar tcr dcr programmed values 0000 0088h a581 bce6h 4001 0304h 0000 0014h 0004 503fh address 4001 0300h 4001 0300h 4001 0300h 64-bit destination lsb memory a5 a5 msb 4001 0300h a5 ... 81 81 81 bc bc bc e6 e6 e6 bus operation dword store@ 40010304 destination (5 times)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 330 order number: 320066-003us generate a ia-32 core interrupt upon detection of an error. beyond this mechanism, errors detected and logged in the csr may be escalated as described in the chapter on rasum and exception handling. refer to the edma access disposition tables in chapter 10.0, ?system address map,? for an overview of defined ranges in the memory map and associated edma access treatment. 12.7.1 controller interface error the following errors may be reported for any edma initiated access, regardless of target interface: ? illegal ndar address ? the descriptor pointer in ndar is not naturally eight dword aligned ? the value in ndar does not point to a valid memory location ? illegal source address ? address does not comply with the source type bit in the dcr ? address out of range ? illegal destination address ? address does not comply with the destination type bit in the dcr ? address out of range ? accesses to any iich address region via the nsi ? data parity error (corrupt data) returned by memory read retrieving descriptor information all controller interface errors are fatal to the transfer in process and will result in channel abort. note: this includes data parity errors, since an error in reading a descriptor implies a corrupt descriptor in main memory, and in this case, it is impossible for the channel to determine precisely what part of the descrip tor is damaged. the automatic abort upon detection of a corrupt descriptor is necessary to prevent any further data corruption as a result of its execution. 12.7.2 memory interface error the following errors may be reported for a edma initiated access (read or write) on the local memory interface: ? addressing error (source or destination) ? physical edma address above remaplimit (see section 10.6.1 ) ? physical address not allocated to memory (including pam destination mapping) ? physical address specified an illegal memory destination (e.g., protected smm range) ? data parity error in reading data from the edma data queue ? data parity error (poisoned data) retu rned by memory read for payload data there is no time-out mechanism associated with transfers. the edma channel assumes that all reads to memory will eventually return, although they may return corrupt data, and will wait indefinitely for an outstanding read.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 331 intel ? ep80579 integrated processor addressing errors are fatal and will result in a edma channel abort, logged in csr bit 4. the channel response to data errors is configurable; the channel may be programmed to abort, or to propagate the bad data to its destination. 12.7.3 i/o interface error the following errors may be reported for a edma initiated access (write) on an i/o interface: ? address crossed into a memory destination range (checked on each write access) ? address crossed to a new destination port during a transfer (checked at 4 kb boundaries) the latter error will result if poorly formed destination descriptor information specifies a length plus address combination that crosses the addressing boundary between independent outbound ports on the i/o subsystem. any transfer with a destination range crossing an aligned 4 kb boundary in address space may encounter this error. addressing errors are fatal and will result in a channel abort. channel response to data errors is configurable; each channel may be programmed to abort, or to propagate the corrupt data to its destination. 12.8 channel arbitration arbitration among the four independent channels occurs in two stages. each channel has an independent bus request/grant pair to the arbiter internal to the controller. the controller in turn has a single request/grant pair to the main arbiter. the arbiter within the controller handles the fairness among channels, while the inbound/outbound arbiter handles fairness between the edma channels and other competing traffic sources. the internal arbiter uses a strict round-robin policy, with the added modification of an optional ?high priority? designation for one channel at any given time. thus a set of competing channels will achieve balanced bandwidth performance during normal operation. the inbound/outbound arbiter provides a programmable single or double ?grant duration? for the edma controller. thus the channel that ?wins? internal arbitration may be allowed to issue one or two access requests back-to-back in a single arbitration cycle. the second request is accepted if the inbound/outbound arbiter is programmed to a grant count of 2 the requesting channel has two consecutive requests of the same type targeting the same destination ready to send, and there are sufficient command and data resources available for the second request. 12.8.1 normal arbitration scheme a fully connected round-robin arbiter provid es a distinctive balanced service among competing requestors. each of the actively competing channels will receive an equal fraction of the bandwidth service provided by the inbound/outbound arbiter on behalf of each edma channel. in the absence of any competition from the ia-32 core, pci express ports, or other i/o, each edma channel will be allowed to saturate the memory interface. for example, given a memory in terface ?saturation point? of 4 gb/s, the round-robin scheme would be equally distributed between the competing edma channels.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 332 order number: 320066-003us 12.8.2 prioritized arbitration scheme the high priority option in the arbitration scheme provides for a single ?high priority? channel to receive favorable latency and bandwidth service in the face of multiple competing ?normal priority? channels. this is accomplished by designating the high priority channel using a priority enable bit and a two-bit field (to select one of four channels) in the edma control register. the internal edma controller arbiter modifies its arbitration algorithm to provide a grant to the priority channel between the grants for each of the other channels, which retain their round-robin prioritization relative to each other. for example, given a hypothetical memory interface bandwidth of 4 gb/s, the priority-modified scheme would result in 2 gb/s (half the available bandwidth) for the designated priority channel, and the remaining 2 gb/s split equally among the other competing channels. the limitation that a single channel at a time be designated as the priority channel is an acknowledgement that quality of service differences, given multiple ?priority? channels, would be slight in this implementation with two-level arbitration and only four competing channels. it is anticipated that software will be able to determine when an application is particularly sensitive to service level, has been allocated a channel, and will manage the assignment of priority accordingly. if more than one such ?sensitive? application is in flight at the same time, it is perceived to be more efficacious to allow fair competition between those sources, and let the kernel or device driver software attempt to manage competition for resources at the system level to prevent service level problems. each edma channel supports dynamic modification to the priority channel settings (while one or more channels are active). a write to the control register that changes the priority channel configuration takes affect at the next arbitration decision point after the write has completed. there is no direct interlock between the arbiter configuration and any of the active channels. such an event is effectively an environment change, orthogonal to work in progress on any given channel. 12.9 configuration the edma controller uses memory-mapped configuration registers for the majority of its per channel register sets. the controller is software compatible with standard pci device configuration and implements a standard pci header in its configuration- mapped register set as shown in figure 12-1 . the memory-mapped register space associated with the controller is identified by a 32-bit memory base address register (bar). table 12-1 provides an overview of the memory-mapped register set for a representative channel of the controller. table 12-1. channel 0 memory-mapped register set memory mapped i/o for edma channel 0 memor y offset access size default sticky channel control register (ccr0) 00-3h rw 32 bits 0000_0000h no channel status register (csr0) 04-07h rwc, ro 32 bits 0000_0000h no current descriptor addr reg (cdar0) 08-0bh ro 32 bits 0000_0000h no current descriptor upper addr reg (cduar0) 0c-0fh ro 32 bits 0000_0000h no source address register (sar0) 10-13h ro 32 bits 0000_0000h no source upper address register (suar0) 14-17h ro 32 bits 0000_0000h no destination address register (dar0) 18-1bh ro 32 bits 0000_0000h no destination upper address register (duar0) 1c-1fh ro 32 bits 0000_0000h no
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 333 intel ? ep80579 integrated processor all internal registers are accessible through host-initiated configuration space accesses or smbus interface accesses. internal registers are not accessible from the i/o subsystem interfaces. 12.9.1 power up/default status upon power-up or hardware reset, the channe l registers are initialized to their default values. all reserved and unimplemented registers and bits in the device return zero on reads and are unaffected by writes. 12.9.2 channel-specific register definitions each channel has twelve 32-bit memory-mapped registers for its independent operation. eight of these registers (refer to the descriptions below) are loaded automatically from their corresponding fields in the chain descriptor when a new descriptor is fetched from local memory during normal operation. the format of the corresponding descriptor fields in memory is identical to the format defined for the channel-specific registers. refer to ?memory mapped i/o for edma registers? on page 651 for bit definitions. read/write access is available only to the following: ? channel control register (ccr) ? channel status register (csr) ? next descriptor address register (ndar) ? next descriptor upper address register (nduar) the remaining registers are read-only and are automatically loaded with new values defined by the chain descriptor whenever the channel reads a chain descriptor from local system memory. note: automatic loading of the channel-specific registers occurs after the memory read completion returns the descriptor data (32 b), and verification has taken place. verification includes checking parity on the data returned and checking that the channel is properly configured to receive new descriptor data. (if a suspend is in progress, the descriptor data will be dropped in honor of the suspend.) 12.9.2.1 channel control register ? ccr the channel control register (ccr) specifies the overall operating environment for the channel. this is a read/write register, and is cleared to zero on power-on or system reset (contains no sticky bits). application software initializes this register only after initializing the chain descriptors in system memory and updating the next address registers with the location of the first chain descriptor in memory. the ccr may be written when the channel is active to modify channel operation (stop, suspend, etc.) while the channel is active. next descriptor address register (ndar0) 20-23h rwl 32 bits 0000_0000h no next descriptor upper address register (nduar0) 24-27h rwl 32 bits 0000_0000h no transfer count register (tcr0) 28-2bh ro 32 bits 0000_0000h no descriptor control register (dcr0) 2c-2fh ro 32 bits 0000_0000h no table 12-1. channel 0 memory-mapped register set
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 334 order number: 320066-003us the following bits are defined in the ccr: ? start: initiate a new transfer (requires that the csr be appropriately cleared) ? stop: abort the current transfer (immediately) ? suspend: suspend the current transfer (upon completion of the current descriptor) ? channel resume: resume a suspended transfer (retrieve the descriptor indicated by ndar/nduar from local memory, and proceed with execution per the value returned). requires that the stopped and abort status bits in the csr be clear to take effect and will automatically clear end of chain and end of transfer flags. refer to ?offset 00h: ccr0 - channel 0 channel control register? on page 653 for the format of the ccr. 12.9.2.2 channel status register ? csr channel status register (csr) contains flags to indicate the channel status. the register is read by application software to get the current channel status and to determine the source of interrupts. csr is cleared to zero on power-on or system reset. this is a read/write register. the following bits are defined in csr: ? channel active: transfer in progress ? aborted: transfer encountered an error ? stopped: transfer stopped via software request (stop bit detected) ? suspended: transfer suspended via software request (suspend bit detected) ? end of transfer: channel has completed execution of (at least one) descriptor ? end of chain: channel has completed execution of the terminal descriptor (null ndar/nduar) refer to ?offset 04h: csr0 - channel 0 channel status register? on page 656 for the format of csr. 12.9.2.3 current descriptor address register ? cdar the current descriptor address register (cdar) contains the lower 32-bits of the address for the current chain descriptor in local system memory. the cdar is cleared to zero on power-on or system reset, and is loaded automatically with the value from the next descriptor address register (ndar) when a new block transfer is initiated. this register is read-only, and may be polled by software to monitor the progress of the channel as it traverses the descriptor chain. 1 12.9.2.4 current descriptor upper address register ? cduar the upper address will not be used in the ep80579, which is limited to 32-bit addressing. the current descriptor upper address register (cduar) contains the upper 32-bits of the address of the current chain descriptor in local system memory. the cduar is cleared to zero on power-on or system reset and is loaded automatically with the value from the next descriptor upper address register (nduar) when a new block transfer is initiated. this register is read-only. 1 1. note that the imch does not provide an interlock to guar antee that consecutive reads to the cdar/cduar pair return portions of the same descriptor in the event of a collision be tween the read accesses and a descriptor load operation. if software requires knowledge of the current descriptor, the ?suspend? function must be invoked prior to polling these registers.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 335 intel ? ep80579 integrated processor 12.9.2.5 source address register ? sar the source address register (sar) contains the lower 32-bits of the source address for the current transfer. the sar is cleared to zero on power-on or system reset and is loaded automatically with the source address field of the chain descriptor (first dword) when a new chain descriptor is read from memory. the address can be aligned to any byte boundary. the system destination for reads to this address range must match the source type setting of the dcr or the transfer will abort. 12.9.2.6 source upper address register ? suar the upper address will not be used in the ep80579, which is limited to 32-bit addressing. the source upper address register (suar) contains the upper 32-bits of the source address for the current transfer. the suar is cleared to zero on power-on or system reset and is loaded automatically with the source upper address field of the chain descriptor (second dword) when a new chain descriptor is read from memory. 12.9.2.7 destination address register ? dar the destination address register (dar) contains the lower 32-bits of the destination address for the current transfer. the dar is cleared to zero on power-on or system reset and is loaded automatically with the destination address field of the chain descriptor (third dword) when a new chain descriptor is read from memory. the address can be aligned to any byte boundary. the system destination for writes to this address range must match the destination type setting of the dcr or the transfer will abort. 12.9.2.8 destination upper address register ? duar the upper address will not be used in the ep80579, which is limited to 32-bit addressing. the destination upper address register (duar) contains the upper 32-bits of the destination address for the current transfer. the duar is cleared to zero on power-on or system reset and is loaded automatically with the destination upper address field of the chain descriptor (fourth dword) when a new chain descriptor is read from memory. 12.9.2.9 next descriptor address register ? ndar the next descriptor address register (ndar) contains the lower 32-bit address of the next descriptor chain in the local system memory. the ndar is cleared to zero on power-on or system reset and is loaded automatically with the next descriptor address field of the chain descriptor (fifth dword) when a new chain descriptor is read from memory. this address must be aligned to an 8-dword address boundary. a value of zero implies the end of chain if the value of next descriptor upper address (loaded into the nduar) is also zero. application software writes this register with the address of the first chain descriptor in memory prior to initiating a transfer. note: the application software must make sure that the start bit in the ccr and the channel active bit in the csr are clear prior to writing to the ndar. the imch protects this register from being written when these bits are not clear. if the ndar and nduar are zero when the start bit is set, no transfer will be initiated.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 336 order number: 320066-003us 12.9.2.10 next descriptor upper address register ? nduar the upper address will not be used in the ep80579, which is limited to 32-bit addressing. the next descriptor upper address register (nduar) contains the upper 32-bit address of the next descriptor chain in the local system memory. all address bits above bit 35 must be zero or the transfer will abort and an error will be reported. a value of zero implies the end of chain if the value of next descriptor address (loaded into the ndar) is also zero. nduar is cleared to zero on power-on or system reset and is loaded automatically with the next descriptor upper address field of the chain descriptor (sixth dword) when a new chain descriptor is read from memory. application software (likely the device driver) writes this register with the address of the first chain descriptor in the memory prior to initiating a transfer. note: the application software must make sure that the start bit in the ccr and the channel active bit in the csr are clear prior to writing to the nduar. the imch protects this register from being written when these bits are not clear. if the ndar and nduar are zero when the start bit is set, no transfer will be initiated. 12.9.2.11 transfer count register ? tcr the transfer count register (tcr) contains the length of the current transfer in bytes. the tcr is cleared to zero on power-on or system reset and is loaded automatically with the transfer count field of the chain descriptor (seventh dword) when a new chain descriptor is read from memory. the tcr allows for a maximum transfer of 16 mb, commensurate with current operating system capabilities. a value of zero is valid and results in no data being transferred and no cycles generated on the source or destination buses. it also results in completion bits being set after successful completion ?same as if it were a no zero length transfer?. 12.9.2.12 descriptor control register ? dcr the descriptor control register (dcr) contains control values for the transfer on a per descriptor basis. the dcr is cleared to zero on power-on or system reset and is loaded automatically with the descriptor control field of the chain descriptor (eighth dword) when a new chain descriptor is read from memory. the values in the dcr may vary for different descriptors within a single chain. note: the descriptor control register value stipulates coherence attributes for both the source and destination addresses defined by this chain descriptor. independent bits are also defined to specify whether the source and destination address ranges are to be treated as ?coherent? or ?non-coherent? by the imch. when the dcr value stipulates that one or both of the source and destination are to be treated as ?non-coherent? space, the imch will rely on software to maintain system memory coherency and will not issue fsb cycles during the block transfer to snoop processor caches on behalf of the corresponding address range(s). the following bits are defined in the ccr: ? destination address mode: two bits specify destination address as increment or constant ? granularity of the transfer in destination constant address mode: two bits (1b, 2b, or 4b) ? pci-express destination traffic class: three bits define this traffic class ? source address mode: two bits specify source address as increment, decrement, or buffer/memory initialization ? buffer/memory initialization mode: specifies a write to fill an area of memory
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 337 intel ? ep80579 integrated processor ? destination coherency: specifies whether destination addresses should be snooped on the fsb ? source coherency: specifies whether source addresses should be snooped on the fsb ? destination type: specifies whether the destination is local memory or the i/o subsystem ? source type: specifies whether the source is local memory or the i/o subsystem (defined only for symmetry, i/o subsystem source addresses are not supported) ? abort interrupt enable: specifies whether to generate an interrupt on abort ? stop interrupt enable: specifies whether to generate an interrupt on stop ? suspend interrupt enable: specifies whether to generate an interrupt on suspend ? end of transfer interrupt enable: specifies whether to generate an interrupt on eot ? end of chain interrupt enable: specifies whether to generate an interrupt on eoc refer to chapter , ?offset 2ch: dcr0 - channel 0 descriptor control register,? for the format of the dcr. 12.10 interrupts each edma channel can be configured to generate interrupts to the processor interface. the interrupt enable bits for end of transfer and end of chain in the descriptor control register (dcr) determine if the channel generates an interrupt upon successful error- free completion of a transfer. the abort interrupt enable bit in the dcr determines if the channel generates an interrupt upon encountering an error. refer to ?error conditions? on page 329 for details on errors on both the source and destination interface. table 12-2 summarizes the status flags, and the conditions under which interrupts will be generated. each chain descriptor can independently set or clear the various interrupt enable bits in the descriptor control register. this level of control for interrupt generation permits flexibility in synchronization between application software and transfers in progress. if interrupts are not enabled, synchronization can be achieved by polling the status bits in the channel status register (csr). note: ?-? in the table below equates to a non valid combination
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 338 order number: 320066-003us 12.10.1 interrupt routing mechanisms two different mechanisms are available to route interrupts generated by channels to the ia-32 core. note that the interrupt mechanism itself is not channel-specific; all channels generating interrupts share the same interrupt vector and handler. this is in line with the expectation that a single device driver controls each edma channel at large, rather than independent drivers per channel. the first interrupt mechanism uses the integrated ioxapic and 8259 emulation hardware. all interrupts from the channels are logically or?ed and routed to the interface controller for propagation via the in-band assert_intx and deassert_intx special cycles, emulating a level-sensitive interrupt output. the imch tracks these special cycles, and forwards the signaled interrupt to the ia-32 core. if the apic enable bit is set, an interrupt will result in an apic message. if the apic enable bit is clear (unanticipated but possible), an interrupt will result in a legacy mode 8259-style level sensitive interrupt directly to the ia-32 core socket. the second interrupt mechanism uses message signaled interrupt (msi) generation functionality integrated into the edma. internal interrupt messaging utilizes the pci message capability structure and does not support external interrupt input routing. table 12-2. interrupt summary interrupt conditions channel status register (csr) flags dcr bit settings (intr enable bits) channel active stopped suspended end of transfer end of chain channel aborted (error) stop intr enable suspend intr enable eot intr enable eoc intr enable abort intr enable stopped 010 2 ---1 4 ---- suspended 00 2 11 3 ---1--- end of transfer 1- -1-- --1-- end of chain 0- -11- ---1- channel abort 1 0- -001--- -1 notes: 1. the imch ensures that any aborted transfer will be reported via the channel abort status bit and that this bit will never be accompanied by an end of tran sfer or end of chain indication. this ensures that software never mistakes an aborted transfer for a successfully completed transfer ? even if the error is not detected until the final write to the final de stination address of the terminal chain descriptor. 2. the stop and suspend functions are mutually exclusive, and only one of the two status bits will ever be asserted by the imch. in the event that software asserts both controls in the ccr, the stop function will take precedence. 3. the edma suspend function causes the channel to suspend operation at the completion of the current descriptor. the eot status bit will always accompany the suspended status bit. note that even if interrupts are enabled for both eot and suspend, only a single interrupt event will result. 4. the stop function causes the channel to abort the transfer in progress immediately. it is recommended that software read back the channel status register to verify that a stop command has taken effect, since this will be much faster than setting the interrupt enable for stop and waiting for the interrupt to occur.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 339 intel ? ep80579 integrated processor (that is, the limited msi functionality described here is dedicated to the edma channel.) this second mechanism is preferred for interrupt signaling, but is only available in platforms running an msi-capable operating system. selection between these two mechanisms is automatic in the imch. if msi messaging is enabled, as indicated by the enable bit in the msi control register, then the msi interrupt mechanism is used. if msi message generation is disabled, any initiated interrupt will use the dedicated pin legacy mechanism. for both interrupt mechanisms, the interrupt service routine (isr) must service all interrupts for all channels. the memory-mapped edma controller global status register must be statused before returning from the isr to ensure no additional interrupts have occurred. failure to address interrupts in all channels will result in potential system starvation. 12.10.2 message signaled interrupt (msi) the edma controller is capable of generating upstream interrupt messages (msi) directly to the ia-32 core. an msi is signaled via a memory write to address 0feex_xxxxh. three 32-bit registers are required in the controller to support this mechanism. the default values of these registers are compatible with the default value of the ioxapic specification. the three registers are the msi control register (msicr), msi address register (msiar), and msi data register (msidr). software must program these registers to appropriate values prior to enabling internal msi functionality. note: it is unsafe to enable the integrated msi apic function of the controller in environments under control of a non msi-capable operating system. the msi mechanism supports differentiation between interrupts generated during normal operation (eot, eoc, stop, and suspend) and interrupts due to errors (abort). this extra level of granularity is unavailable via the legacy interrupt mechanism. to facilitate use of a single device driver for the entire edma function, a single msi register set services all channels. the support for two different messages on behalf of the controller is included in the msi register set. refer to ?edma registers: bus 0, device 1, function 0? on page 501 for the format of these registers. note: the integrated apic functionality will not support level-sensitive interrupt emulation requiring the use of broadcast eoi cycles from the fsb. no path is provided to handle such traffic from ia-32 core to edma control engine. thus the only supported msi type is the edge-triggered variety. the following subsections describe the register set for msi support. 12.10.2.1 msi control register ? msicr the msi control register (msicr) contains control information for msi interrupt capability. the multiple-message enable field and msi enable are contained in this register. 12.10.2.2 msi address register ? msiar the msi address register (msiar) contains address information specifying the message destination address for msi interrupts.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 340 order number: 320066-003us 12.10.2.3 msi data register ? msidr the msi data register (msidr) contains routing and priority data for generation of msi interrupts. 12.10.3 interrupt ordering to support msi signaling as transfers complete, the imch must take special steps in hardware to ensure that ia-32 core accesses to memory in response to msi do not experience producer/consumer ordering failures. specifically, the chip must internally guarantee functionality equivalent to a logical ?fence? operation between the msi and subsequent ia-32 core traffic from the fsb. 12.10.3.1 interrupt ordering for memory destination the failure to be prevented for interrupts signaled at the end of transfers to memory destinations is as follows: ? each edma channel is programmed to move a single cache-line of data and issue an msi upon completion. this is a special case, for illustrative purposes; a similar scenario arises for the last few writes of a multi-line transfer. ? as soon as the write data is posted into the inbound/outbound arbiter headed for the memory interface, the msi is issued directly to the fsb. note that the transfer to memory may be issued without an accompanying fsb snoop cycle (non- coherent), thus the data and interrupt message are logically traversing independent traffic paths. ? in response to the msi, the ia-32 core i ssues a memory read to retrieve the data from memory. in the absence of an internal interlock, this read may proceed to the memory controller before the posted write data is accepted into the memory controller from the inbound/outbound arbiter. this is where the error occurs, because the memory controller will not have any information regarding the relative issue order of the write and the read ? if the read gets there first, it will retrieve stale data. to prevent such a failure, the inbound/outbound arbiter includes specialized hardware to guarantee that all posted write data received ahead of an msi are forwarded out of the arbiter before the msi message will be forwarded to the fsb. a similar interlock in the inbound/outbound arbiter prevents failures in the non- interrupt case. when software is polling the channel status register (csr) to detect transfer completion, specialized hardware gu arantees that the read completion stalls until all prior posted write data is forwarded out of the arbiter. 12.10.3.2 interrupt ordering for outbound destination the failure to be prevented for interrupts signaled at the end of transfers to outbound port destinations is as follows: ? each edma channel is programmed for a single block transfer to an i/o device, with interrupt notification enabled at the completion of that transfer. for this example, msi generation is disabled. ? when the final write of the transfer is posted into the inbound/outbound arbiter, a level-sensitive interrupt is signaled directly to the interrupt output pin, bypassing all internal queue structures. ? if the integrated ioxapic is enabled, the response to the interrupt pin will be an apic message received. if the apic is disabled, a sideband interrupt is signaled directly to the ia-32 core via a level sensitive output.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 341 intel ? ep80579 integrated processor ? for either case, the likely software response to the interrupt will be a posted write ?door-bell? access to a memory mapped control register in the edma destination device to communicate completion of the transfer. (semantic: edma transfer completed without errors, you have all the data, go.) ? in the absence of internal interlocks as described above, multiple failures are possible. the apic message could bypass edma data pending within the inbound/ outbound arbiter, and the ia-32 core doorbell write could do the same. this would result in stale data ?executed? in response to the doorbell. the internal imch hardware interlock prevents apic messages from being forwarded to the fsb while posted data remains pending in the inbound/outbound arbiter. this prevents most of the problematic behavior in this case. if the apic is disabled, the ia- 32 core must retrieve the interrupt vector from the 8259 emulator, and the read completion interlock will then guarantee that all posted write data has cleared the arbiter. another potential issue is relaxed write ordering within a system agent en route to the edma destination device. if the hardware were to issue edma outbound posted writes and ia-32 core posted writes with differing stream id codes, an intermediary component may allow the ia-32 core doorbell access to move around posted edma data. this would again result in stale data ?executed? by the destination device. the imch could solve this problem by issuing an explicit fence between the final edma write and the interrupt, preventing subsequent ia-32 core accesses from reordering en route to the destination. a simpler (but more limited) solution is to utilize the same stream id for all outbound traffic regardless of source. this makes transactions initiated by each edma channel indistinguishable from those initiated by any of the ia- 32 core threads. with no stream id information to determine reordering legality, an intermediary device must necessarily enforce strong ordering for all accesses outbound. the single initiator id in concert with the internal interlock for apic messages and read completions is sufficient to guarantee proper behavior. the implementation guarantees that any flag write or data read to the destination port will necessarily push the edma transfer data ahead of it, ensuring correct producer/consumer operation. 12.11 initiating an edma transfer the following subsections detail the steps the software must take in programming a channel to initiate a transfer (or chain of transfers). the steps covered include channel initialization, transfer start, and suspend or stop. each channel is designed to have independent control of interrupt enabling and generation, and independent transfer attribute controls; this provides the greatest flexibility to the application program. 12.11.1 setup and initiation initializing a channel begins with constructing one or more chain descriptors in local system memory. each chain descriptor takes the form described in section 12.3.1, ?chain descriptor definition? on page 311 . once the descriptors are defined, the following steps are required to initiate a transfer: 1. ensure the edma channel is enabled and in normal mode by setting the edma enable and mode bits of the edma control register. 2. the channel must be inactive/idle prior to starting a transfer. this may be verified by reading the channel active bit in the channel status register (csr), which is clear when the channel is inactive/idle. 3. update the next descriptor address register (ndar/nduar) with the address of the first chain descriptor in local system memory.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 342 order number: 320066-003us 4. clear the channel status register (csr) of any asserted error or status bits. each edma channel will not initiate a new transfer when an error condition remains in the csr. 5. clear the suspend bit and set the start bit in the channel control register (ccr). since this is the start of a new transfer and not the resumption of a previous transfer, the channel resume bit in the ccr must be clear. (resume overrides start.) 6. the channel starts the transfer by fetching the chain descriptor at the address contained in the next descriptor address register (ndar/nduar). the channel moves the ndar/nduar values into the cdar/cduar, and loads the chain descriptor values into their corresponding internal registers. if the load completes without any error, the actual data transfer begins. the current descriptor address register (cdar/cduar) now contains the address of the chain descriptor just fetched and the next descriptor address register (ndar/nduar) now contains the descriptor address of the next descriptor in the chain, if any. 7. when the current edma transfer has completed without any errors, the channel fetches the next chain descriptor from the address contained in the next descriptor address register (ndar/nduar) automatically without any software intervention, and proceeds with the next block transfer (provided the value in the ndar/nduar pair is non-zero). the last descriptor in the chain list has a null value in the next descriptor address field, specifying the end of the chain. the null value in the next descriptor address register (ndar/nduar) notifies the channel not to read additional chain descriptors from local system memory, and the channel goes idle. 12.11.2 suspend function software may temporarily suspend execution of a descriptor chain by setting the suspend bit in the channel control register (ccr). the target channel will complete execution of the current descriptor and suspend operation without losing current status. software may later cause the channel to resume execution of the descriptor chain by writing to the ccr to clear the suspend bit and set the resume bit. in response, the channel will initiate a descriptor fetch from the ndar/nduar, and resume the suspended operation. software does not need to re-program the channel configuration after a suspend sequence. 12.11.3 stop function software may intentionally abort a transfer by setting the stop bit in the channel control register (csr). once aborted, the transfer cannot be resumed. in response to the stop bit, the target channel will immediately cease fetching source data, drain any buffered destination data, and go idle. usage of this mechanism will result in assertion of the stopped status bit in the csr, and will generate an interrupt if so enabled. (note that the stop function is sufficiently fast in the imch that reading back the channel status register is preferred over utilizing the interrupt on stop function.) usage of the stop mechanism will not result in assertion of the abort status bit, nor will it generate an ?interrupt on abort? indication if so enabled. the channel differentiates an abort on error from an abort on software command, and will ensure that all error status bits remain clear. if the msi mechanism is in use for interrupt generation, and independent messages are defined for abort on error and normal run-time interrupts, the latter message type will be utilized on behalf of the stop function.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 343 intel ? ep80579 integrated processor 12.11.4 edma process flow figure 12-17 provides a high-level flow chart of the edma initialization sequence. figure 12-18 provides a similar view of the edma completion sequence. figure 12-17.initiation flow chart initiate edma transfer b4492-01 program edma appending to existing chain is channel active set? return no yes yes set suspend edma bit update terminal descriptor in memory set channel resume bit, clear suspend bit wait time out? no no error return yes program edma clear channel status register 1. set next descriptor address register (64b) 2. set channel control register (start edma bit and other control bits) return
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 344 order number: 320066-003us figure 12-18.completion flow chart transfer over interrupt received b4493-01 release current descriptor interrupt expected? end of chain? return yes no no initiate edma transfer yes polled transfer over is channel status good? clear completion status and interrupt / eoi error return no yes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 345 intel ? ep80579 integrated processor 13.0 platform configuration 13.1 rasum features - smbus access configuration registers are accessible from either the ia-32 core or from the smbus. the ia-32 core will be able to access all configuration registers through host configuration cycles. access via smbus is read/write to the imch configuration registers. the smbus cannot use the imch's sm-port target interface to access any register in the iich or outside of cmi. each device must have its own smbus target port. cmi does not shadow the rasum registers for the smbus. to clear these registers, a write access will need to be performed. the imch smbus has full read/write access to the imch pci legacy registers. the imch global rasum register set and those registers applicable to logical bus#0 and memory are implemented in function 1 of device 0. rasum registers specific to other internal devices appear in the register map for the associated device. the imch error control registers are in function 1, and are read/write accessible by the processor and through the smbus. the imch error logging registers are also available to the processor and smb master in function 1. the imch rasum control register and the ?cmd? registers (serrcmd, smicmd, etc.) which control generation of serr#, smi#, and sci# are read/write accessible by the processor and through the smbus. fsb-initiated accesses to configuration space registers are serviced through configuration ring. it is perfectly legal for an smbus access to be requested while an fsb-initiated access is already in progress. in other words, smbus configuration accesses and processor configuration cycles may occur at the same time. the imch supports ?wait your turn? arbitration to resolve all collisions and overlaps, such that the access that reaches the configuration ring arbiter first is serviced first while the conflicting access is held off. an absolute tie at the arbiter is resolved in favor of the fsb. 13.2 platform configuration structure conceptual overview the imch and iich are physically connected by an internal interface called nsi (north south interface). from a configuration standpoint, nsi is logically pci bus #0. as a result, all devices internal to the imch and iich, except host switch devices appear to be on pci bus #0. the system's primary pci expansion bus is physically attached to the iich and, from a configuration perspective, appears to be a hierarchical pci bus behind a pci-to-pci bridge and therefore has a programmable bus number. the pci express ports appear to system software to be real pci buses behind pci-to-pci bridges that reside as devices on pci bus #0. cmi decodes multiple pci device numbers. the configuration registers for the devices are mapped as devices residing on pci bus #0 except for host switch devices. each device number may contain multiple functions. see table 13-1, ?pci devices and functions on bus 0? for device and function assignments.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 346 order number: 320066-003us 13.2.1 imch pci devices the pci predefined header has five fields that deal with device identification. all devices are required to implement these fields. generic configuration software is able to easily determine the device available for use. these registers are read only. the five fields are vendor id, device id, revision id, header type, and class code: ? the 16-bit vendor id is assigned by pci sig and has a value of 8086h for intel. ? the 16-bit device id is assigned by the vendor. ? the 8-bit revision id is chosen by the vendor to indicate the different steppings of a device. the value 00h designates an a0 stepping. the value 01h designates an b0 stepping. ? the header type specifies the structure of the second half of the header, and also whether or not the device has multiple functions. the value 80h indicates a multi- function device. ? the class-code field identifies the generic function of the device. the class-code is further broken into three sub-fields, base class, sub-class, and programming interface. cmi proper has a base class code of 06h indicating a bridge device. the sub-class value of 00h indicates a host bridge. a disabled or non-existent imch device?s configuration register space is hidden, returning all 1?s for reads and dropping writes just as if the cycle terminated with a master abort on pci. if one or more iich devices or some of their functions are not supported on the platform, each can be disabled individually. when a device or function is disabled, it does not appear at all to the software: no responses to any register reads and no responses to any register writes. this is intended to prevent software from thinking that a device or function is present (and reporting it to the end-user). when a pci express interface is unpopulated or fails to train, the associated configuration register space is hidden, returning all ones for all registers just as if the cycle terminated with a master abort on pci. also, if pci express port pea0 is configured for x8 operation rather than x4, the corresponding pci express port pea1 configuration space will be hidden. table 13-1. pci devices and functions on bus 0 device function function description 00imch 0 1 imch, error status 10imch edma engine 2 0 imch pci express port a0 x8 or x4 unit 8 0 imch test and device 0 overflow 31 0 iich lpc interface 31 2 iich sata controller 31 3 iich smbus controller 31 5 reserved 31 6 reserved 29 0 iich usb controller #1 29 7 iich usb 2.0 controller
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 347 intel ? ep80579 integrated processor 13.2.2 iich pci devices logically, the iich appears as multiple pci devices within a single physical component also residing on pci bus #0. one of the iich devices is a pci-to-pci bridge. logically, the primary side of the bridge resides on pci #0 while the secondary is a standard pci expansion bus. note: the internal devices in the imch and iich (except host switch devices) logically constitute as pci bus #0 to configuration software (see figure 13-1 ).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 348 order number: 320066-003us figure 13-1. bus 0 device map cpu pci config window in i/o space nsi interface imch pci express bridge bus #0, dev #2 pci express bridge bus #0, dev #3 nsi, ddr2, fsb bus #0, dev #0 nsi interface sata bus 0, device 31 function 2 iich nsi (logical pci bus #0) 8/4bit pci express pci-to-pci bridge 4bit pci express usb classic host bus 0, device 29 function 0 usb2 host bus 0, device 29 function 7 smbus controller bus 0, device 31 function 3 lpc bridge bus 0, device 31 function 0 pci express enchanced config window in mem space edma registers bus #0, dev #1 bus m
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 349 intel ? ep80579 integrated processor 13.3 routing configuration accesses the imch supports up to two x4 pci express interfaces: ?pea0 ?pea1 these two interfaces can be combined to form a x8 interface, pea. the imch is responsible for routing pci configuration cycles to the proper interface. pci configuration cycles to iich internal devices and downstream devices are routed to the iich via the internal nsi bus. pci configuration cycles to the imch pci express interfaces are routed to pea(0:1). routing of configuration accesses to pea(0:1) is controlled via the standard pci-to-pci bridge mechanism using information contained within the primary bus number, th e secondary bus number, and the subordinate bus number registers of the corresponding pci-to-pci bridge device. a detailed description of the mechanism for translating ia-32 core i/o bus cycles to configuration cycles on one of the buses is described below. note: the imch supports a variety of connectivity options. when any of the imch?s interfaces are disabled, the associated interface?s device registers are hidden. all configuration cycles (reads and writes) to disabled devices on bus #0 are forwarded to the nsi where they will master abort. 13.3.1 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the ia-32 core. configuration space is supported by a mapping mechanism implemented within the imch. the pci specification defines two mechanisms to access configuration space, mechanism #1 and mechanism #2. cmi supports mechanism #1. the configuration access mechanism makes use of the config_address register and config_data register. to reference a configuration register a dword (32-bit) i/o write cycle is used to place a value into config_address that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. config_address[31] must be a ?1? to enable a configuration cycle. config_data then becomes a window into the four bytes of configuration space specified by the contents of config_address. any read or write to config_data will result in the imch translating the config_address into the appropriate configuration cycle. the imch is responsible for translating and routing the ia-32 core i/o accesses to the config_address and config_data registers to internal imch configuration registers, for nsi, and pci express ports pea(0:1). note: it is only possible to generate 1-4 byte configuration accesses via this mechanism, which is in line with imch capabilities. the imch only supports accesses up to 1 dword (32 bits) in size into the configuration register space (internal or external).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 350 order number: 320066-003us 13.3.2 pci bus #0 configura t ion mechanism the imch decodes the bus number (bits 23:16) and the device number fields of the config_address register. if the bus number field of config_address is 0, the configuration cycle is targeting a pci bus #0 device. the host-nsi bridge entity within the imch is hardwired as device #0 on pci bus #0. the edma controller within the imch is hardwired as device #1 on pci bus #0. the host-pea0 bridge entity within the imch is hardwired as device #2 on pci bus #0. the host-pea1 bridge entity within the imch is hardwired as device #3 on pci bus #0. the pci-to-pci bridge entity within the imch is hardwired as device #4 on pci bus #0 configuration cycles to any of the imch?s enabled internal devices are confined to the imch and not sent over nsi. accesses to disabled imch internal devices, or devices #10 to #31 is forwarded over nsi as type 0 configuration cycles. a[1:0] of the nsi request packet for the type 0 configuration cycle is ?00?. bits 31:2 of the config_address register is translated to the a[31:2] field of the nsi request packet of the configuration cycle as shown in figure 13-2 . the iich decodes the type 0 access and generates a configuration access to the selected internal device. 13.3.3 primary pci and downstre am configuration mechanism if the bus number in the config_address is non-zero, and does not lie between the secondary bus number register and the subordinate bus number register for one of the pci express ports, the imch will generate a type 1 nsi configuration cycle. a[1:0] of the nsi request packet for the type 1 configuration cycle is ?01?. bits 31:2 of the config_address register is translated to the a[31:2] field of the nsi request packet of the configuration cycle as shown in figure 13-3 . this nsi configuration cycle is sent over nsi. if the cycle is forwarded to the iich via nsi, the iich compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its p2p bridges to determine if the configuration cycle is meant for the primary pci or one of the iich?s pci express ports. figure 13-2. nsi type 0 configuration address translation config_address 31 24 23 16 15 11 10 8 7 2 1 0 1 reserved 0 device number function register number x x nsi type 0 configuration address extension 31 28 27 24 23 16 15 11 10 8 7 2 1 0 reserved device number function register number 0 0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 351 intel ? ep80579 integrated processor 13.3.4 imch pci express bus configuration mechanism from the configuration perspective, the pci express ports are seen as pci bus interfaces residing on a secondary bus side of the ?virtual? pci-to-pci bridges referred to as the imch host-pci express bridge. on the primary bus side, the ?virtual? pci-to- pci bridge is attached to pci bus #0. therefore the primary bus number register is hardwired to ?0?. the ?virtual? pci-pci bridge entity converts type #1 pci bus configuration cycles on pci bus #0 into type 0 or type 1 configuration cycles on the pci express interfaces. type 1 configuration cycles on pci bus #0 that have a bus number that matches the secondary bus number of one of the imch?s ?virtual? p2p bridges are translated into type 0 configuration cycles on the appropriate pci express interface. the address bits are mapped as described in figure 13-3 . if the bus number is non-zero, greater than the value programmed into the secondary bus number register, and less than or equal to the value programmed into the corresponding subordinate bus number register the configuration cycle is targeting a pci bus downstream of the targeted pci express interface. the imch will generate a type 1 configuration cycle on the appropriate pci express interface. the address bits are mapped as described in figure 13-4 . to prepare for mapping of the configuration cycles on pci express the initialization software will go through the following sequence: scan all devices residing on the pci bus #0 using type 0 configuration accesses. for every device residing at bus #0 which implements pci-to-pci bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. this process will include the configuration of the ?virtual? pci-to-pci bridges within the imch used to map the pci express device?s address spaces in a software specific manner. figure 13-3. nsi type 1 configuration address translation config_address 31 24 23 16 15 11 10 8 7 2 1 0 1 reserved bus number device number function register number x x nsi type 1 configuration address extension 31 28 27 24 23 16 15 11 10 8 7 2 1 0 reserved bus number device number function register number 0 1 figure 13-4. mechanism #1 type 1 configuration address to pci address mapping 1 reserved bus number device number function number 3130 24 10 11 15 16 23 8 7 reg. index x x 20 1 config_address 1 0 bus number device number function number 3130 24 10 11 15 16 23 8 7 reg. index 0 1 20 1 pci address ad(31:0)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 352 order number: 320066-003us 13.3.5 imch configuration cycle flow chart figure 13-5. imch configuration flow chart dw i/o write to config_addr ss with bit 31=1 i/o read/write to config_data bus#=0 device#=0 bus#= secondary bus in imch dev#2 bus#= secondary bus in imch dev#3 yes yes imch generates type 0 access to pea0 no no no no yes imch generates type 0 access to pea1 yes yes no yes no imch claims if function=0 and device 1 is enabled imch claims if function=0 and device 2 is enabled imch claims if function=0 and device 3 is enabled imch generates nsi type 0 configuration cycle no access through memory aperture bus# >sec bus bus# <=sub bus in imch dev#2 yes imch generates type 1 access to pea0 no yes imch generates type 1 access to pea1 bus# >sec bus bus# <=sub bus in imch dev#3 imch generates nsi type 1 configuration cycle no device#=1 device#=2 device#=3 device#=4 imch claims if function=0, or 1 and that function is enabled bus#= secondary bus in imch dev#4 no imch generates type 0 access to pci-to-pci bridge yes note: this path will never be taken since no bridge will ever be beneath the pci-to-pci bridge. imch claims if function=0 and device 4 is enabled yes no bus# >sec bus bus# <=sub bus in imch dev#4 no imch generates type 1 access to pci-to-pci bridge yes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 353 intel ? ep80579 integrated processor 13.4 imch register introduction the imch contains two sets of software accessible registers, accessed via the ia-32 core i/o address space: control registers i/o mapped into the ia-32 core i/o space, which control access to pci configuration space, and internal configuration registers residing within the imch, which are partitioned into multiple logical device register sets (?logical? since they reside within a single physical device). the imch internal registers (i/o mapped and configuration registers) are accessible by the ia-32 core. the registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of config_address, which can only be accessed as a dword. all multi-byte numeric fields use ?little-endian? ordering (i.e., lower addresses contain the least significant parts of the field). note: irrespective of the access mechanism used (i/o register mechanism, or memory- mapped mechanism), the imch only supports 1-4 byte accesses into configuration space. software must (if necessary) take steps to prevent use of opcodes that would treat configuration space destinations as objects greater than a single dword (32 bits) in size. such attempted usage will result in spurious behavior up to and including hanging the platform. some of the imch registers described in this section contain reserved bits which are labeled ?reserved?. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, write operation for the configuration address register. in addition to reserved bits within a register, the imch contains address locations in the configuration space of the host-nsi bridge entity that are marked either ?reserved? or ?intel reserved?. the imch responds to accesses to ?reserved? address locations by completing the host cycle. when a ?reserved? register location is read, a zero value is returned. (?reserved? registers can be 8-, 16-, or 32-bit in size). write operations to ?reserved? registers have no effect on the imch. registers that are marked as ?intel reserved? must not be modified by system software. writes to ?intel reserved? registers may cause system failure. reads to ?intel reserved? registers may return a non-zero value. upon a reset, cmi sets its entire internal configuration registers to predetermined default states. at reset, some register values are determined by external strapping options. a register?s default value represents the minimum functionality feature set required to successfully bring up the system. it is the responsibility of the system initialization software (usually the bios) to properly determine the dram configurations, operating parameters and optional system features that are applicable, and to program cmi registers accordingly. 13.5 imch sticky registers certain registers in the imch are sticky through a hard-reset. they will only be reset on a power-good reset. in general, these registers are the error logging registers and a few special cases. the error command registers are not sticky, so that on reset bogus errors are not reported and that errors are not reported through a mechanism that hasn?t been set up in code yet. only those registers that are explicitly marked as ?sticky: yes? are sticky. those not marked or those marked as no are not sticky. the following registers are sticky:
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 354 order number: 320066-003us ? device 0, function 0: critical dram control registers, a portion of drc, drt clock gearing and clock disable registers ? device 0, function 0: eco sticky register ? device 0, function 0, bar 14: bios notepad sticky register ? device 0, function 1: error information registers (not the command registers) ? device 2, function 0: error information registers (not the command registers) ? device 3, function 0: error information registers (not the command registers) ? device 8, function 0: pilot control registers ? device 8 function 0: power on configuration bits 13.6 imch i/o mapped registers the imch contains two registers that reside in the ia-32 core i/o address space ? the configuration address (config_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window. 13.6.0.1 offset 0cf8h: config_address - configuration address register config_address is a 32-bit register that can be accessed only as a dword. a byte or word reference will ?pass through? the configuration address register and nsi onto the iich as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. table 13-2. summary of imch pci configuration registers mapped in i/o space offset start offset end register id - description default value 0cf8h 0cf8h ?offset 0cf8h: config_address: configuration address register? on page 354 00000000h 0cfch 0cfch ?offset 0cfch: config_data: configuration data register? on page 355 00000000h table 13-3. offset 0cf8h: config_address: configuration address register (sheet 1 of 2) description: view: ia f base address: 0000h (io) offset start: offset end: 0cf8h 0cf8h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 cfge configuration enable. 0 = accesses to pci configuration space are disabled. 1 = accesses to pci configuration space are enabled. 0h rw 30 :24 reserved reserved. these bits are read only and have a value of 0. 0h ro 23 :16 bus_number contains the bus number being targeted by the configuration cycle. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 355 intel ? ep80579 integrated processor 13.6.0.2 offset 0cfch: config_data - configuration data register config_data is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by config_data is determined by the contents of config_address. 13.7 imch memory mapped registers certain dram compensation control, edma control/status registers, nsi control/status and pci express will reside in memory mapped space instead of configuration space. these memory mapped address regions are setup through base address registers and capability pointers, which will reside in configuration address space. these registers are documented in the configuration register chapter. these base address registers follow the standard definition as found in the pci express specification . these memory mapped register regions must not be marked as wc (write-combining), as all accesses to the registers within these regions are limited to dword access, and write-combining is not allowed. further, these registers must not be accessed utilizing ia-32 core operations with a data operand size greater than 32-bits, as such access is strictly unsupported by the imch. 15 :11 device_number selects one of the 32 possible devices per bus. 0h rw 10 :08 function_numb er selects one of eight possible functions within a device. 0h rw 07 :02 register_numb er this field selects one register within the particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to a[07:02] during nsi or pci express configuration cycles. 0h rw 01 :00 reserved reserved 0h table 13-3. offset 0cf8h: config_address: configuration address register (sheet 2 of 2) description: view: ia f base address: 0000h (io) offset start: offset end: 0cf8h 0cf8h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 13-4. offset 0cfch: config_d ata: configuration data register description: view: ia f base address: 0000h (io) offset start: offset end: 0cfch 0cfch size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 cdw configuration data window. if bit 31 of config_address is one any i/o access to the config_data register is mapped to configuration space using the contents of config_address. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 356 order number: 320066-003us 13.8 pci express enhanced configuration mechanisms pci express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by pci 2.2 configuration space. pci express configuration space is divided into a pci 2.2 compatible region, which consists of the first 256 b of a logical device?s configuration space and an extended pci express region which consists of the remaining configuration space. the pci 2.2 compatible region can be accessed using either the mechanisms defined in the pci 2.2 or using the enhanced pci express configuration access mechanism. all changes made using either access mechanism are equivalent; however, software is not allowed to interleave pci express and pci access mechanisms to access the configuration registers of devices. the extended pci express region can only be accessed using the enhanced pci express configuration access mechanism. 13.8.1 pci express configuration transaction header the pci express configuration transaction header includes an additional four bits for the register number field (extendedregisteraddress[3:0]) to provide additional configuration space. the pci 2.2 compatible configuration access mechanism uses the same request format as the enhanced pci express mechanism. for pci compatible configuration requests, the extended register address field must be all zeros. to maintain compatibility with pci configuration addressing mechanisms, system software must access the enhanced configuration space using dword operations (dword-aligned) only . 13.8.2 enhanced configuratio n hardware implications the imch must translate the memory-mapped extended enhanced pci express configuration access cycles from the host processor to pci express configuration cycles. devices are required to respond to an additional four bits for decoding configuration register access. devices must decode the extendedregisteraddress[3:0] field of the configuration request header. this field is used in conjunction with the register number to specify the dword address of the register being accessed. a pci express device must be able to operate with basic required functionality in a legacy environment without requiring access to any extended pci express configuration. figure 13-6. pci express configuration transaction header b4494-01 +0 fmt x 0 type 765 210 43 765 210 43 tc 0 0 0 765 210 43 reserved 65 210 43 length 0 0 0 0 0 0 0 0 0 0 1 7 1st dw be +1 +2 +3 reserved ext. reg. address bus number device number function number requester id tag register number r r t d e p attr 0 0 r last dw be 0 0 0 0 r
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 357 intel ? ep80579 integrated processor 13.8.3 enhanced configuration memory address map the enhanced configuration memory address map is positioned into cmi memory space by use of the pci express enhanced configuration base register known as hecbase. this register contains the address that corresponds to bits 31 to 28 of the base address for pci express enhanced configuration space below 4 gb. configuration software will read this register to determine where the 256 mbyte range of memory addresses resides for enhanced configuration. this register defaults to a value of e, which corresponds to e000 0000 for the imch. it is not intended that this value is ever changed by bios. 13.8.4 enhanced configuration fsb address format ta bl e 1 3 - 5 presents the enhanced configuration address format for the front side bus. note that bits 31:28 of ta b l e 1 3 - 5 correspond to the default value of hecbase. figure 13-7. enhanced configuration memory address map b4495-01 bus 255 0xffffffff bus 1 bus 0 0x1fffff 0xfffff 0 0xfffff 0x7fff 0x1fff device 0 function 0 device 0 function 0 device 0 function 1 0xfffff device 0 function 0 located by pci express base address (hecbase) table 13-5. enhanced configuration fsb address format bits description 35:32 0h 31:28 eh 27:20 bus number 19:15 device number 14:12 function number 11:00 register offset
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 358 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 359 intel ? ep80579 integrated processor 14.0 ras features and exception handling cmi is designed to bring enterprise level reliability, availability, serviceability, usability, and manageability (rasum) to the embedded platform. 14.1 ras features 14.1.1 data protection due to the nature of having various data protection schemes on the different interfaces (ecc, parity, and crc) it is necessary to be able to convert between them when transferring data internally. to accomplish this, protection of internal data is done with parity. 14.1.1.1 dram ecc the dram interface uses a standard sec/ded ecc across a 64-bit data quantity. 14.1.1.2 pci express interface these high-speed serial interfaces have tr aditional crc protection. the data packets utilize a 32-bit crc protection scheme, specifically the same crc-32 used by ethernet - 0x04c11db7. the smaller and less error-prone link packets utilize a 16-bit crc scheme. since packets utilize 8b/10b encoding and not all encodings are used, this provides further data protecti on because illegal codes can be detected. also, if errors are detected on the reception of data packets due to various transients, these data packets can be retransmitted. hardware logic supports this link-level retry without software intervention. 14.1.1.3 data error propagation between interfaces/units due to the nature of having various data protection schemes; ecc, parity, and crc - it is necessary to be able to convert between the separate schemes. beyond this requirement, it is necessary to indicate whether or not incoming data is corrupted. also, it is useful to know when internal data has been corrupted during transit. to accomplish this, the imch uses parity to protect internal data. this requires units to add two parity bits for each 64 bits of data path width. data received by a unit from outside the chip creates two parity bits to travel with the data, one provides parity on the upper 32 bits, and the other provides parity on the lower 32 bits. if either of the 32-bit halves is required to be poisoned, both halves are poisoned. this provides the user of the data a mechanism to recognize when a bit was flipped in transit by detecting when only one of the parity bits is bad. the user will flag this error condition as well as mark both halves bad. this covers both cases of the data starting out as either good or bad. if it started out as good, but a bit was flipped, it is indeed corrupted and must be marked as such. in the case where it started out as bad, and a bit was flipped, it is still corrupted, although probably a different data value than its starting value. this scheme works when all quantities being passed are 64 bits or greater. if a data path must be padded, it must be padded with zeroes. even parity will be used for
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 360 order number: 320066-003us this scheme; meaning that the total number of asserted bits including the parity bits is an even number of bits. this parity protection scheme applies to different interfaces on the chip hence the name: ?chip two bit parity? or ctb parity. note: due to edma byte realignment and parity manipulation, a single ctb parity bit error observed by the edma unit may poison either 2 or 4 dwords depending on the resultant alignment. refer to the edma chapter for more details. 14.1.2 dram data integrity 14.1.2.1 periodic memory scrubbing when enabled a special dram memory scrubbing unit will walk through all dram, on a periodic basis, doing reads. correctable e rrors found by the read are corrected and then the good data written back to dram. a write is only performed when a single bit error has been detected and is correctable, except when an incoming write to the same memory address is detected. in this case the scrub write is dropped and the scrub counter is advanced since this location is already being written. these transactions are treated as non-coherent, since these addresses are not placed on the fsb. the scrub unit starts at an address than can be programmed and counts to 0. the scrub rate is also programmable so using this method, a 4 gb system can be completely scrubbed in less than a day. the cumulative effect of these scrub writes do not cause any noticeable degradation to memory bandwidth, although they will cause a greater latency for that one very infrequent read that is delayed due to the scrub write cycle. 14.1.2.2 dram hardware initialization hardware will be used to initialize main memory under the direction of bios. once bios has programmed the imch with the dimm profile, and has configured and calibrated the imch and populated dimms, it can utilize the mbist csrs to initialize and/or test populated memory. the initialization of mbistcsr will traverse the target range of memory addresses as rapidly as possible, providing an order of magnitude performance improvement over ia-32 core-generated initialization or test. the mbist engine can be configured to choose values other than zero. the eight fixed hex data values selectable are alternating pairs of 0/f, a/5, 3/c, or 6/9. alternate modes are provided in which lfsr random data may be used, or software explicitly specifies the full pattern of bits to be written in a collection of mbist data registers with or without a shift after every write. in all cases of pattern based initialization and test, the mbist function does not calculat e ecc on the fixed pattern or programmed value to be written across the target address range. rather, the fixed pattern is extended to cover the data devices as well as the ecc devices in the target dimm, and a strict bit-wise comparison is utilized to determine whether read-back verification passes or fails. once all desired testing has been completed, whql requirements dictate that memory be completely initialized to ?0? prior to transferring control to the operating system. to accomplish this, bios must clear all the mbistdata registers and utilize the explicit pattern mode of mbist. it is possible to initialize memory a rank at a time, or en- masse, at the discretion of bios. 14.1.2.3 uncorrectable retries the memory controller will not support uncorrectable retries.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 361 intel ? ep80579 integrated processor 14.1.2.4 dram refresh as with any dram device, the storage element is inherently leaky, and must be recharged periodically to avoid loss of data integrity. circuitry in the memory subsystem will ensure that refresh cycles occur in a periodic fashion across all active dimms to meet the specific dram requirements. 14.1.2.5 ddr i/o hardware assisted calibration to determine read capture timing, hardware assisted calibration logic writes a pattern into memory and then reads the data back with different hardware settings until the optimum timing is found. such calibration is described in the initialization walk-through provided in the clocking and reset chapter of this document. hardware provides the capability to tune receive-enable timing, dqs centering within the received data eye (both vertical and horizontal), output drive strength, and receive termination. 14.1.3 pci express data integrity the pci express interfaces will incorporate se veral features to make this interface as robust as possible without software intervention. 14.1.3.1 pci express training to establish a connection between pci express endpoints, they both participate in a sequence of steps known as training. this sequence will establish the operational width of the link as well as adjust skews of the various lanes within a link so that the data sample points can correctly take a data sample off of the link. the x4 link pairs capable of collapsing to x8 will first attempt to train independently, and will collapse to a single link at the x8 width upon detection of a single device returning link id information upstream. once the number of links has been established, they will negotiate to train at the highest common width, and will step down in its supported link widths in order to succeed in training. the ultimate result may be that the link has trained as a x1 link. although the bandwidth of this link size is substantially lower than a x8 link or even a x4 link, it will allow communication between the two devices. software will then be able to interrogate the device at the other end of the link to determine why it failed to train at a higher width, something that would not be possible without support for the x1 link width. it should be noted that width negotiation is only done during training or retraining, but not recovery. 14.1.3.2 pci express retry the pci express interface incorporates a li nk level retry mechanism. the hardware detects when a transmission packet is corrupted and a retry of that particular packet and all following packets will be performed. although this will cause a temporary interruption in the delivery of packets, it does so in order to maintain the link integrity. 14.1.3.3 pci express recovery when numerous errors occur, the hardware may determine that the quality of the connection is in question, and the end points can enter a quick training sequence known as recovery. the width of the connection will not be renegotiated, but the adjustment of skew between lanes of the link may occur. this occurs without any software intervention, but the software may be notified. 14.1.3.4 pci express retrain if the hardware is unable to perform a successful recovery then the link will automatically revert to the polling state, and initiate a full retraining sequence. this is a drastic event with an implicit reset to the downstream device and all subordinate
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 362 order number: 320066-003us devices, and is logged by the imch as a ?link down? error. if escalation of this event is enabled, software is notified of the link dl_down condition. once software has to be involved, then data will likely be lost, and processes need to be restarted, but this is still preferred to having to shut the system down, or go offline for an extended period of time. 14.1.4 test/support major buses 14.1.4.1 iich xor the iich supports xor chain test mode. this non-functional test mode is a dedicated test mode when the chip is not operating in its normal manner. 14.1.4.2 smb (imch) full access to internal configuration registers via the system management bus is supported. this will allow a server management card to control system configuration and to read various error/status information. accesses to devices marked as not present will still be possible through smb. 14.1.4.3 smb (iich) the iich smb is smbus 2.0 compliant and it is compatible with most 2-wire components that are also i2c compatible. the host interface allows ia-32 core to communicate via smbus, the slave interface allows external microcontroller to access system resource in iich. this iich smb does not support access to internal configuration registers. 14.1.4.4 i 2 c access to the external dimms will be through the iich, via i 2 c. this will be used to determine the nature of the dimms present in order to configure the memory subsystem correctly. 14.2 exception handling there are a variety of exception conditions. some are internally detected; some are detected on input pins; some are passed on behalf of other devices. all recognized exceptions eventually cause the imch to do one of the following: send a serr message, send a sci message to the iich, send a smi message to the iich, assert mcerr# on the front side bus, or do nothing. there is no determination of which errors go to which of the three error message schemes; it merely provides the capability for all combinations. it is the responsibility of the bios to determine the ultimate error reporting scheme. there will be an attempt to classify errors to whether they are fatal or non-fatal to more closely match the enterprise error presentation. 14.2.1 ferr/nerr global register scheme the global ferr register consists of three fields. the first or fatal field has 14b indicates the first signaled fatal global error from 14 different units. the second or non- fatal field indicates the first non-fatal global error that occurs from the same 14 different units. a non-fatal error may be ei ther correctable or uncorrectable, but not figure 14-1. global ferr/nerr register representation fatal (14b) non-fatal (14b) reserved (4b)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 363 intel ? ep80579 integrated processor fatal. these two fields usually have at most one bit asserted in each field. in the event of simultaneous errors occurring in the same core clock, more than one bit in a field may be set. the third 4-bit field is reserved for future enhancements. the global nerr register consists of these same three fields with slightly different functionality. instead of just the first fatal or non-fatal global errors recorded, this register indicates the second, third, fourth, etc. global errors that are reported by the imch. these two registers do not indicate what the error was, they just indicate the severity of the error and what unit has more specific error information. 14.2.1.1 ferr/nerr unit registers each major unit will have a minimum of a pair of registers, known as the first error (ferr) and next error (nerr). each unit has different and specific error bit definitions, and provides the specific type of error; information that is not found in the global registers. it is important to note that the unit ferr/nerr registers are simpler than the global for purposes of reuse and ease of implementation. while the global ferr register has a fatal and a non-fatal field, which lock down separately, the unit ferr register only has one field. the unit is however still required to send out separate fatal and non-fatal indications to the global ferr register if they detect both classifications of errors. some units will support only one type. a unit that doesn?t detect errors would not support either type. 14.2.1.2 clearing ferr/nerr registers the following write-up is the recommended guideline to minimize the loss of errors information. for a given ferr/nerr register pair, the ferr is read and then cleared first, and followed by the nerr. this sequence is true for either the global ferr/nerr register pair or any given unit. any errors occurring after the ferr is cleared will then cause the ferr to have a non-zero value. after the global ferr/nerr register pair is cleared, the unit ferr/nerr register pairs are interrogated, but only those indicated by the global ferr/nerr registers. once the unit pair has been cleared, the unit ferr can be read again to ensure that no errors occurred during this local unit sequence. after the first unit ferr/nerr register pair has been serviced, this same sequence is performed for all other unit ferr/nerr register pairs that indicated errors in the global ferr/nerr registers. once all unit error registers have been serviced, the final st ep is to read the global ferr register to determine if all system errors have been serviced. it is possible that errors could have occurred for a particular unit after that unit was serviced during the error routine, or that a unit had errors after the reading of the global ferr/nerr registers. when clearing errors, software must clear all the ferr/nerr bits in the local interface registers before clearing the global ferr/nerr registers. if the local registers are not cleared first, then the global ferr/nerr registers will latch the same error again as soon as they are cleared. this implementation allows software to clear the local ferr/ nerr registers, and then go clear the global ferr/nerr. s/w then reads back the global ferr/nerr and if it is non-zero, then a new error has occurred. if the global ferr/nerr has no bits set, then there are no more system errors.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 364 order number: 320066-003us 14.2.1.3 ferr/nerr unit specific each unit has different and specific error bit definitions. 14.2.1.4 serr/smi/sci enabling registers each error reported has a full matrix of direction as to what error message it generates. for each unit ferr/nerr pair there are three more registers that enable each error for one of the three specific error messages. the logic does not appear to preclude the generation of all three messages for a single error, but this would not be a recommended configuration, and this needs to be looked into further. serr stands for system error and is for reporting address and data parity errors, or any other catastrophic system error. sci stands for system control interrupt and is a shareable interrupt used to notify the os of acpi events. smi stands for system management interrupt and is an os-transparent interrupt generated by events on legacy systems. figure 14-2. ferr/nerr service routine read global ferr & snapshot error irpt/msg clear global ferr always always read global nerr & snapshot always read local ferr always clear local ferr elseif error type has support registers clear global nerr always read local nerr clear local nerr always read support registers always else read support registers else if error type has support registers read global ferr always if no local errors indicated note: the local reads must be performed for the next unit, if any, indicated in the ferr/nerr snapshot taken exit if no errors service routine [unit] service routine [global] else
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 365 intel ? ep80579 integrated processor 14.2.1.5 mcerr enabling registers an additional entry to the matrix of error signaling paths is the mcerr (machine check error) enabling register. in addition to the serr, smi, and sci enabling registers, the mcerr enabling register allows the occurrence of an error to result in the mcerr# signal to be asserted on the front side bus. machine check error is asserted to indicate an unrecoverable error, which is not a bus protocol violation. 14.2.1.6 error escalation register since all error bits in the error registers are fully configurable, meaning that a given error can be configured to go to any of the four messaging methods, no global error escalation mechanism is required. although, the errors occurrence is accumulated in the global ferr/nerr registers, all error messaging is initiated from the units themselves, and not from a central location. 14.2.1.7 error masking a new feature being added for cmi is the concept of an error masking register. each unit has a mask register, which blocks the recognition/logging/reporting of each specific error type. since the error will not be recognized when the corresponding mask bit is set, no error messages can be generated. this feature allows intelligent software to ignore specific error types during critical areas of code, where it does not want to be informed of errors that it will create, without ignoring other error types that it doesn?t expect to happen. these mask bits will default to unmasked, and must be set by software or bios to take effect. 14.2.1.7.1 locking dram address and syndrome on errors the first pair of error logging registers for ce (correctable errors) dram_secf_add and dram_secf_syndrome are locked when bit 0 of the dram_ferr is set. the second pair of error logging registers for ce (correctable errors) dram_secn_add and dram_secn_syndrome are locked when bit 0 of the dram_nerr is set. these pairs of two registers will retain their value even if new ce?s are found. this allows the first (and possibly next) error to be captured and held instead of retaining the last. corrected data errors as a result of either demand reads or scrubber-initiated traffic will be reflected in these error registers. the logging register for ue (uncorrectable errors), dram_ded_add is locked when bit 1 of the dram_ferr or dram_nerr is set. this register holds the address of uncorrectable errors on data reads not initiated by the scrubber for either periodic or demand scrubbing. the logging register for scrub detected errors, dram_scrub_add should be locked when bit 2 of the dram_ferr or dram_nerr is set. this register holds the address for scrubber-initiated transactions for either demand or periodic memory scrubbing. when the ferr/nerr registers are cleared the logging registers are free to update their contents until such time that either of these ferr/nerr registers again lock.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 366 order number: 320066-003us 14.2.1.8 pci express errors and errors on behalf of pci express imch-specific error detection, masking, and escalation mechanisms operate on a parallel path to their standardized counterparts included in the pci express* interface specification, rev 1.0a . pci express errors are classified as either correctable or uncorrectable. uncorrectable errors are further broken down as fatal or non-fatal. pci express specified correctable errors ar e logged in the correctable error status register (device 2-3, function 0, offset 110 - 113h), unless they are masked by a corresponding bit in the correctable error detect mask register (device 2-3, function 0, offset 150-153h). pci express specified uncorrectable errors are logged in the uncorrectable error status register (device 2-3, function 0, offset 104-107h), unless they are masked by a corresponding bit in the uncorrectable error detect mask register (device 2-3, function 0, offset 14c-14fh). the uncorrectable error severity register (device 2-3, function 0, offset 10c - 10fh) determines if bits in the uncorrectable status register are treated as uncorrectable fatal or uncorrectable non-fatal errors. the device status register (6eh) bits are set when the corresponding category of bit is set in the uncorrectable and correctable status registers. reporting of non-masked error bits to the root complex hierarchy of pci express error registers is controlled on three different levels. individual errors are masked for reporting by the uncorrectable error mask (device 2-3, function 0, offset 108-10bh) and the correctable error mask (device 2-3, function 0, offset 114-117h) registers. individual error category (fatal, non-fatal, correctable, or unsupported) reporting is enabled in the device control register (device 2-3, function 0, offset 6ch) bits 3:0. finally, uncorrectable error reporting (fatal or non-fatal) reporting may also be enabled by setting the serr enable bit in the pci command register (device 2-3, function 0, offset 04-05h). there is an error pointer, in the advanced error capability and control register (device 2-3, function 0, offset 118-11bh) which will log the first uncorrectable error that is enabled for reporting. also some uncorrectable errors, when they are the first uncorrectable error, will log their corresponding header log in the header log registers (device 2-3, function 0, offset 11c-12bh). an error pointer for unmasked correctable errors has been added in the error do command register (device 2-3, function 0, offset 148-14bh). these internally detected errors when they are reported are referred to as virtual error messages. these are different from errors which are detected by the downstream device which then sends an error message to the root complex, which are referred to as externally detected or ?received? error messages. the received system error bit in the secondary status register (device 2-3, function 0, offset 1e-1f) is set when either fatal or non-fatal messages are received at the root complex. at this point in the pci express error hierarchy, these virtual error messages are logically ored with the received error message s, and will just be referred to as fatal, non-fatal, or correctable error messages, no reference to either virtual or received. when enabled by the enable system error bit in the pci command register, any fatal or non-fatal messages will set the signaled system error bit in the pci status register (device 2-3, function 0, offset 06-07h). the root port error message status register (device 2-3, function 0, offset 130-133h) will indicate first and multiple errors of each error message category, and the corresponding error source ids of the first correctable and uncorrectable error messages will be th e logged in the error source id register (134h). these errors that have been reported to th e root complex can now be reported to the system, via the category enables in the root port error command register (device 2-3, function 0, offset 12c-12fh) for interrupts. these interrupts can be in the form of
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 367 intel ? ep80579 integrated processor legacy type interrupts if so enabled in the pci command register and msi is not enabled, or message signaled interrupts if so enabled in the msi capabilities register (device 2-3, function 0, offset 5a-5bh). the root port control register (device 2-3, function 0, offset 80-83h) enables errors to be reported to the system via other imch specific methods, again on a category basis. the error do command register, selects between the four methods of system signaling, serr, sci, smi, and mcerr. the error model outside of pci express includes a local ferr/nerr pair of registers in each unit and a global ferr/nerr pair of registers that indicates which unit had problems. the local ferr/nerr register pair (device 2-3, function 0, offset 160-163h & 164-167h) includes pci express defined errors and additional detected errors within the pci express unit. this register pair has three sets of error bits for the three categories of errors: the first set for received messages, the second set for internally detected errors (virtual messages need not have been generated), and unit specific errors outside of the pci express spec, and the third set for device errors. this error scheme sets ferr/nerr error bits regardless whether or not they were reported via interrupt or other signaling method. the signaling due to unit specific errors has its logic dependent on the pci express unit error register (device 2-3, function 0, offset 140-143h). the errors flagged in this register must be cleared before exiting the error service routine. the signaling due to received messages has its logic dependent on the root error message status register (device 2-3, function 0, offset 130-133h). the root error status register must be cleared before exiting the error service routine. the signaling due to internally detected pci express errors has its logic dependent on the device status register (device 2-3, function 0, offset 6e-6fh). the device status register must be cleared before exiting the error service routine. software must clear the global ferr first, and then the global nerr. software then clears the local ferr register and the local nerr register of each unit in that order. after clearing ferr and then clearing nerr, the local ferr must be read to make sure that remains ?0? indicating no more errors have occurred during the clearing of these registers. after all units? ferr & nerr registers have been cleared, the global ferr is again read to ensure that no additional errors occurred during the clearing sequence. since the pci express units have more hierarchy than other units, more registers must be cleared other than just the local ferr and nerr registers. after clearing the local ferr & nerr, one must also clear the root error status, unit error status, device status, uncorrectable error status, and correctable error status registers. one only needs to clear the pci status and secondary status registers if these are being utilized in a given particular error model. no logic depends on the state of any of these status bits. if not utilized, they can be ignored. if a pci express error handler is used, with no knowledge of the ferr/nerr registers, then clear the pci express specific registers: device status, uncorrectable error status, correctable error status, and root error status. the imch specific unit errors would not be enabled for reporting errors. figure 14-3 helps to illustrate the relationship of the error registers from the pci express* specification. 14.2.1.9 configurable error containment at the legacy interface depending on the i/o devices in use, data errors could have catastrophic effects when allowed to propagate. the legacy interface has the configurability of allowing the poisoning and propagation of data errors or to stop the data from transferring at all and escalate the data errors to the system. this is extreme behavior, which can be enabled or disabled, in order to prevent data corruption on a critical device, and is referred to as ?stop and scream?. refer to the error injection section for more details.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 368 order number: 320066-003us 14.3 error conditions signaled the iich-notification action taken by the imch upon detection of an error is controlled through three registers. the serrcmd register enables the generation of the serr message, the scicmd register enables the generation of the sci message, and the smicmd register enables the generation of smi messages. special cycle types of do_serr, do_sci, or do_smi may be transmitted to the iich. the iich receives the exception notification from the imch and may be configured to notify the processor of the condition. once the processor has been interrupted, it polls the system to determine the cause of the exception. if the imch initiated the exception condition by sending a message over nsi, then the processor is so informed by the iich. at this point, the processor may read the imch?s error status registers to determine the exact cause of the condition. the processor explicitly clears the status bit that points to the exception condition. the imch in addition to signaling errors to the iich for further handling, has added the capability of signaling the processor directly by use of the front side bus error signal mcerr#. the processor, upon observing this signal active, enters into special error handling code known as machine check code. figure 14-3. pci express error handling uncorrectable error mask exp_uncerrmsk correctable error status exp_corerrsts correctable error mask exp_corerrmsk uncorrectable severity exp_uncerrsev enable syserr mask on a per bit basis nf fatal message uncorrectable errors correctable errors correctable message non-fatal message v i r t u a l f a t a l m e s s a g e c f device status exp_ devsts device control exp_ devctl pcicmd[8] mask on a per bit basis virtual correctable message virtual non-fatal message adv. error capability & control exp_aercacr header log register exp_hdrlog[3:0] uncorrectable error status exp_uncerrsts uncorrectable error detect mask exp_uncerrdmsk correctable error detect mask exp_corerrdmsk uncorrectable severity exp_uncerrsev all uncs f nf c c nf f root error status exp_rperrmsts error source id exp_errsid report select exp_errdocmd mcerr sci smi msi intx 1 st error indicators 1 st error source ids imch specific registers in dark grey serr correctable error ptr exp_errdocmd nfm fm ur bctrl[1] serre virtual & recieved message logic sec_sts[14] rse all uncs unsupport request ur [3] pcists[14] sse fnf c uncs w/o ur msicapa [0] msi enable root error cmd exp_rperrcmd irpt enable per type root control exp_rpctl report enable root error cmd exp_rperrcmd irpt enable per type
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 369 intel ? ep80579 integrated processor for each type of error detected in a given unit, there is a bit that corresponds to that error in the unit_ferr, unit_nerr, serrcmd_unit, smicmd_unit, scicmd_unit, and mcerrcmd_unit registers. (note that one and only one xcmd bit can be enabled per error type.) the first occurrence of an error type will be indicated by the bit assertion in the unit_ferr. if that error occurs again than the corresponding bit will be set in the unit_nerr register. when a bit is asserted in either the unit_ferr or unit_nerr, and if the corresponding enable bit is set in one of the named cmd registers, then an error signal will be asserted, corresponding to the name of the cmd register: do_serr, do_sci, do_smi, or do_mcerr. the assertion of the do_serr signal also requires that the serr enable in the pcicmd register is set. the assertion of the do_serr signal also causes the appropriate serr signaled status bit to be set in the pcists register. table 14-1. pseudocode for edma errors (sheet 1 of 2) condition source action status the descriptor pointer in next descriptor address register is of incorrect type or range for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[7]=0 and serrcmd_edma[7]=1 and r_edge{edma_ferr[31] or edma_nerr[31]}); do_smi if edma_emask[7]=0 and smicmd_edma[7]=1 and r_edge{edma_ferr[31] or edma_nerr[31]}; do_sci if edma_emask[7]=0 and scicmd_edma[7]=1 and r_edge{edma_ferr[31] or edma_nerr[31]}; do_mcerr if edma_emask[7]=0 and mc errcmd_edma[7]=1 and r_edge{edma_ferr[31] or edma_nerr[31]}; edma_ferr[31] the descriptor pointer in next descriptor address register is not aligned to eight double-word boundary for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[6]=0 and serrcmd_edma[6]=1 and r_edge{edma_ferr[30] or edma_nerr[30]}); do_smi if edma_emask[6]=0 and smicmd_edma[6]=1 and r_edge{edma_ferr[30] or edma_nerr[30]}; do_sci if edma_emask[6]=0 and scicmd_edma[6]=1 and r_edge{edma_ferr[30] or edma_nerr[30]}; do_mcerr if edma_emask[6]=0 and mc errcmd_edma[6]=1 and r_edge{edma_ferr[30] or edma_nerr[30]}; edma_ferr[30] the source address does not comply with the source type or range for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[5]=0 and serrcmd_edma[5]=1 and r_edge{edma_ferr[29] or edma_nerr[29]}); do_smi if edma_emask[5]=0 and smicmd_edma[5]=1 and r_edge{edma_ferr[29] or edma_nerr[29]}; do_sci if edma_emask[5]=0 and scicmd_edma[5]=1 and r_edge{edma_ferr[29] or edma_nerr[29]}; do_mcerr if edma_emask[5]=0 and mc errcmd_edma[5]=1 and r_edge{edma_ferr[29] or edma_nerr[29]}; edma_nerr[29] the source address is not aligned as specified by the source address bit for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[4]=0 and serrcmd_edma[4]=1 and r_edge{edma_ferr[28] or edma_nerr[28]}); do_smi if edma_emask[4]=0 and smicmd_edma[4]=1 and r_edge{edma_ferr[28] or edma_nerr[28]}; do_sci if edma_emask[4]=0 and scicmd_edma[4]=1 and r_edge{edma_ferr[28] or edma_nerr[28]}; do_mcerr if edma_emask[4]=0 and mc errcmd_edma[4]=1 and r_edge{edma_ferr[28] or edma_nerr[28]}; edma_ferr[28] the destination address does not comply with the destination type or range for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[3]=0 and serrcmd_edma[3]=1 and r_edge{edma_ferr[27] or edma_nerr[27]}); do_smi if edma_emask[3]=0 and smicmd_edma[3]=1 and r_edge{edma_ferr[27] or edma_nerr[27]}; do_sci if edma_emask[3]=0 and scicmd_edma[3]=1 and r_edge{edma_ferr[27] or edma_nerr[27]}; do_mcerr if edma_emask[3]=0 and mc errcmd_edma[3]=1 and r_edge{edma_ferr[27] or edma_nerr[27]}; edma_ferr[27]
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 370 order number: 320066-003us the destination address is not aligned as specified by the destination address bit for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[2]=0 and serrcmd_edma[2]=1 and r_edge{edma_ferr[26] or edma_nerr[26]}); do_smi if edma_emask[2]=0 and smicmd_edma[2]=1 and r_edge{edma_ferr[26] or edma_nerr[26]}; do_sci if edma_emask[2]=0 and scicmd_edma[2]=1 and r_edge{edma_ferr[26] or edma_nerr[26]}; do_mcerr if edma_emask[2]=0 and mc errcmd_edma[2]=1 and r_edge{edma_ferr[26] or edma_nerr[26]}; edma_ferr[26] data parity error in reading source data from system memory for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[1]=0 and serrcmd_edma[1]=1 and r_edge{edma_ferr[25] or edma_nerr[25]}); do_smi if edma_emask[1]=0 and smicmd_edma[1]=1 and r_edge{edma_ferr[25] or edma_nerr[25]}; do_sci if edma_emask[1]=0 and scicmd_edma[1]=1 and r_edge{edma_ferr[25] or edma_nerr[25]}; do_mcerr if edma_emask1]=0 and mc errcmd_edma1]=1 and r_edge{edma_ferr[25] or edma_nerr[25]}; edma_ferr[25] received configuration write command when edma is in normal mode for edma channel 3. internal do_serr and set pcists10[sse] if (pcicmd10[serre]=1 and edma_emask[0]=0 and serrcmd_edma[0]=1 and r_edge{edma_ferr[24] or edma_nerr[24]}); do_smi if edma_emask[0]=0 and smicmd_edma[0]=1 and r_edge{edma_ferr[24] or edma_nerr[24]}; do_sci if edma_emask[0]=0 and scicmd_edma[0]=1 and r_edge{edma_ferr[24] or edma_nerr[24]}; do_mcerr if edma_emask[0]=0 and mc errcmd_edma[0]=1 and r_edge{edma_ferr[24] or edma_nerr[24]}; edma_ferr[24] edma channel 2 errors internal same bit functionality as bits 31:24 except these are for edma channel 2. (use bits 23:16) edma channel 1 errors internal same bit functionality as bits 31:24 except these are for edma channel 1. (use bits 15:8) edma channel 0 errors internal same bit functionality as bits 31:24 except these are for edma channel 0. (use bits 7:0) table 14-1. pseudocode for edma errors (sheet 2 of 2) condition source action status
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 371 intel ? ep80579 integrated processor 15.0 platform management (imch) this chapter provides an overview of the system management support provided by the imch. there are two primary management support features in the imch: ? integrated system management bus (smbus) interface ? architectural support for platform power management note: material in this chapter is specific to the imch and does not apply to the iich. 15.1 integrated smbus interface the imch provides a fully functional system management bus (smbus) target interface, which provides direct access to all internal imch configuration register space. smbus access is available to all internal configuration registers, regardless of whether or not the register in question is normally accessed via the memory-mapped mechanism or the standard configuration mechanism. this provides for highly flexible platform management architectures, part icularly given a baseboard management controller (bmc) with an integrated network interface controller (nic) function. 15.2 smbus target architecture the smbus target integrated into the imch is compatible with the system management bus (smbus) specification, version 2 . a brief overview of the smbus architecture is provided below for reference. 15.2.1 high level operation the smbus interface consists of two interface pins: a clock and serial data. multiple initiator and target devices may be electrically present on the same pair of signals. each target recognizes a start signaling semantic and recognizes its own seven-bit address to identify pertinent bus traffic. the imch address is hard-coded to 011_0000. the protocol allows for traffic to stop in ?midsentence,? requiring all targets to tolerate and properly ?clean up? in the event of an access sequence that is abandoned by the initiator prior to normal completion. the imch is compliant with this requirement. the protocol comprehends ?wait states? on read and write operations, which the imch takes advantage of to keep the bus busy during internal configuration space accesses. 15.2.1.1 smbus register summary ta bl e 1 5 - 1 provides a quick-reference summary of the smbus target register space. these registers are part of the target itself and therefore not accessible by any other means other than the direct smbus connection.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 372 order number: 320066-003us ta b l e 1 5 - 1 and table 15-2 indicate the sequence of data as it is presented on the smbus following the byte address of the imch itself. this is not necessarily to indicate any specific register stack or array implemented in the imch. the registers can take on different meanings depending on whether it is a configuration or memory-mapped access type. the command indicates how to interpret the registers. refer to the system management bus (smbus) specification, version 2 for interface protocol details. table 15-1. smbus register summary symbol full name/function cmd command bytcnt byte count addr3 bus number (only lower five bits are utilized) addr2 device/function number addr1 extended reg number (bits 03:00 - 4 k page extension) addr0 register number (offset into function space) data3 data, fourth byte (31:24) data2 data, third byte (23:16) data1 data, second byte (15:08) data0 data, first byte (07:00) sts status, only for reads table 15-2. smbus memory-mapped register summary symbol full name/function cmd command bytcnt byte count addr3 destination memory (bar selection) addr2 address offset 23:16 (filler-used to zero out register) addr1 address offset 15:08 (15:12 not used) addr0 address offset 07:00 (11:00 used for 4 k page) data3 data, fourth byte (31:24) data2 data, third byte (23:16) data1 data, second byte (15:08) data0 data, first byte (07:00) sts status, only for reads table 15-3. addr3 memory assignments addr3 destination memory assignments 00_000000 nsi 00_000001 edma 00_001000 ddr2 all others reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 373 intel ? ep80579 integrated processor 15.2.1.2 internal register access mechanism all smbus accesses to the internal register space are initiated via a write to the cmd register. any register writes received by the imch while a command is already in progress receive a nak to prevent spurious operation. the master is no longer expected to poll the cmd register to prevent clobbering a command in progress prior to issuing further writes. the smbus access is delayed by stretching the clock until such time that the data is delivered. note that per the system management bus (smbus) specification, version 2 , this interval can not be longer than 25 ms. to set up an internal access, the four addr bytes are programmed, followed by a command indicator to execute a read or write. depending on the type of access, these four bytes indicate either the bus number, device, function, extended register offset, and register offset; or the memory-mapped region selected and the address within the region. the configuration type access utilizes the traditional bus number, device, function, and register offset; but also uses an extended register offset, which expands the addressable register space from 256b to 4 kb. the memory-mapped type access redefines these bytes to be a memory-mapped region selection byte and the memory address within the region. table 15-2 and ta b l e 1 5 - 3 show this information. fsb-initiated accesses to registers are serviced through the configuration ring. for these registers, it is perfectly legal for an smbus access to be requested while an fsb- initiated access is already in progress. the imch supports ?wait your turn? arbitration to resolve all collisions and overlaps, such that the access that reaches the configuration ring arbiter first is serviced first while the conflicting access is held off. an absolute tie at the arbiter is resolved in favor of the fsb. note that smbus accesses must be allowed to proceed even if the internal transaction handling hardware and one or more of the other external interfaces are hung or otherwise unresponsive. 15.2.1.3 smbus register definitions 15.2.1.3.1 cmd ? command register when written, this command register indicates the type and size of transfer. all configuration accesses from the smbus port are initiated by writing to this register. while a command is in progress, all future wr ites or reads are nack?ed by the imch to avoid overwriting registers while in use. the two command size fields allow for more flexibility on how the data payload is transferred, both internally and externally. the begin and end bits support the breaking of th e transaction up into smaller transfers, by defining the start and finish of an overall transfer. table 15-4. command (cmd) register (sheet 1 of 2) bit description 07 begin transaction indicator 0 = current transaction is not the first of a read or write sequence. 1 = current transaction is the first of a read or write sequence. on a single transaction sequence this bit is set along with the end transaction indicator. 06 end transition indicator 0 = current transaction is not the last of a read or write sequence. 1 = current transaction is the last of a read or write sequence. on a single transaction sequence this bit is set along with the begin transaction indicator. 05 address mode: indicates whether memory or configuration space is being accessed in this smbus sequence. 0 = memory mapped mode 1 = configuration register mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 374 order number: 320066-003us 15.2.1.3.2 bytcnt ? byte count register the byte count register indicates the number of bytes following the byte count register when performing a write or when setting up for a read. the byte count is also used when returning data to indicate the following number of bytes (including the status byte), which are returned prior to the data. note that the byte count is only transmitted for block type accesses on smbus. smbus word or byte accesses do not use the byte count. 15.2.1.3.3 addr3 ? address byte 3 register this register must be programmed with the bus number of the desired configuration register in the lower five bits for a configuration access. for a memory-mapped access this field selects which memory-map region is being accessed. there is no status bit to poll to see if a transfer is currently in progress, because by definition, if the transfer completed, the task is done. the clock stretch is used to guarantee the transfer is truly complete. the ep80579 does not support access to other logical bus numbers via the smbus port. all registers ?attached? to the configuration mechanism that the smbus has access to, reside on logical bus#0. 04 reserved - set to 0. 03: 02 internal command size: all accesses are naturally aligned to the access width. this field specifies the internal command to be issued by the smbus slave logic to the imch core. 00 = read dword 01 = write byte 10 = write word 11 = write dword 01: 00 smbus command size: this field specifies the smbus command to be issued on the smbus. this field is used as an indication of the length of the transfer so that the slave knows when to expect the pec packet (if enabled). 00 = byte 01 = word 10 = dword 11 = reserved table 15-4. command (cmd) register (sheet 2 of 2) bit description table 15-5. byte count register position description 07:00 byte count: number of bytes following the byte count for a transaction. table 15-6. address byte 3 register position configuration register mode de scription memory mapped mode description 07:05 ignored. memory map region to access. 00h = nsi 01h = edma 08h = ddr2 others = reserved 04:00 bus number: must be zero: the smbus port can only access devices on the imch and all devices are bus zero.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 375 intel ? ep80579 integrated processor 15.2.1.3.4 addr2 ? address byte 2 register this register must be programmed with the device number and function number of the desired configuration register if for a configuration type access, otherwise it must be set to zero. 15.2.1.3.5 addr1 ? address byte 1 register this register must be programmed with the upper address bits for the register with the 4k region. whether it is a configuration or memory-map type of access, only the lower bits are utilized, the upper four bits are ignored. 15.2.1.3.6 addr0 ? address byte 0 register this register indicates the lower eight address bits for the register within the 4 k region, regardless of whether it is a configuration or memory-map type of access. 15.2.1.3.7 data ? data register this field is used to receive the read data or to provide the write data associated with the desired register. at the completion of a read command, this field contains the data retrieved from the selected register. all reads return an entire aligned dword (32 bits) of data. the appropriate number of byte(s) of this 32-bit logical register must be written with the desired write data prior to issuing a write command. for a byte write only, bits 7:0 are used, for a word write, only bits 15:0 are used, and for a dword write, all 32 bits are used. table 15-7. addr2 ? address byte 2 register position configuration register mode description memory mapped mode description 07:03 device number. can only be devices on the imch. zeros used for padding. 02:00 function number. table 15-8. addr1 ? address byte 1 register position description 07:04 ignored. 03:00 extended register number. upper address bi ts for the 4 k region of register offset. table 15-9. addr0 ? address byte 0 register position description 07:00 register offset.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 376 order number: 320066-003us 15.2.1.3.8 sts ? status register for a read cycle, the data is preceded by a byte of status. ta b l e 1 5 - 1 1 shows how these bits are defined. 15.2.1.4 unsupported access addresses it is possible for an smbus master to program an unsupported bit combination into the addr registers. the imch does not support such usage, and may not gracefully terminate such accesses. 15.2.1.5 smbus transaction pictograms since the new smbus target interface is of enterprise origin, it is more complex than the original smbus target interface of desktop origin. the following drawings are included to demonstrate the different types of transactions, especially how they can be broken up into multiple smaller transfers. table 15-10. offset 04-07: data - data register bits type reset description 31:24 rw 00h byte 3 (data3): data bits [31:24] 23:16 rw 00h byte 2 (data2): data bits [23:16] 15:08 rw 00h byte 1 (data1): data bits [15:8] 07:00 rw 00h byte 0 (data0): data bits [7:0] table 15-11. status register position description 07 internal timeout 0 = smbus request is completed within 2 ms internally 1 = smbus request is not completed in 2 ms internally 06 ignored 05 internal master abort 0 = no internal master abort detected 1 = detected an internal master abort 04 internal target abort 0 = no internal target abort detected 1 = detected an internal target abort 03:01 ignored 00 successful 0 = the last smbus transaction was not completed successfully 1 = the last smbus transaction was completed successfully
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 377 intel ? ep80579 integrated processor figure 15-1. dword configuration read protocol figure 15-2. dword configuration write protocol figure 15-3. dword memory read protocol figure 15-4. dword memory write protocol b4518-01 dword configuration read protocol (smbus block write/block read, pec disabled) 0110_000 w a cmd =11000010 a byte count = 4 a bus number a device/ function a a a s reg number [7:0] reg number [15:0] p s 0110_000 w a cmd =11000010 a s s 0110_000 r a byte count = 5 a status a data[31:24] a data[23:16] a a s data[15:8] sr n data[7:0] p clock stretch b4531-01 dword configuration write protocol (smbus block write, pec disabled) 0110_000 w a cmd = 11001110 a byte count = 8 a bus number a device/ function a a s reg number [15:8] s a data[23:16] a data[16:8] a data[7:0] clock stretch a a reg number [7:0] data[31:24] p b4532-01 0110_000 w a cmd =11100010 a byte count = 4 a destination memory a add offset [23:16] a a a s add offset [15:8] p s 0110_000 w a cmd =11100010 a s s 0110_000 r a byte count = 5 a status a data[31:24] a data[23:16] a a s data[15:8] s r n data[7:0] p dword memory read protocol (smbus block write/block read, pec disabled) clock stretch add offset [7:0] b4533-01 dword memory write protocol (smbus block write, pec disabled) 0110_000 w a cmd = 11101110 a byte count = 8 a destination memory a add offset [23:16] a a add offset [15:8] s a data[23:16] a data[16:8] a data[7:0] clock stretch a a add offset [7:0] data[31:24] p
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 378 order number: 320066-003us figure 15-5. dword configuration read protocol figure 15-6. dword configuration write protocol b4534-01 dword configuration read protocol (smbus word write/word read, pec disabled) 0110_000 w a cmd = 10000001 a bus number a device/function a p 0110_000 w a cmd = 01000001 a register num [15:8] a register num [7:0] a p clock stretch 0110_000 w a cmd = 10000001 a 0110_000 r a status a data[31:24] n p 0110_000 w a cmd = 00000001 a 0110_000 r a data[23:16] a data[15:8] n p 0110_000 w a cmd = 01000000 a 0110_000 r a data[7:0] n p sr s s s s sr s sr b4535-01 dword configuration write protocol (smbus word write, pec disabled) 0110_000 w a cmd = 10001101 a bus number a device/function a s p 0110_000 w a cmd = 00001101 a register num [15:8] a register num [7:0] a s p 0110_000 w a cmd 00001101 a data[31:24] a data[23:16] a s p 0110_000 w a cmd = 01001101 a data[15:8] a data[7:0] a s p clock stretch 0110_000 w a cmd = 10101101 a destination memory a add offset [23:16] a s p 0110_000 w a cmd = 00101101 a add offset [15:8] a add offset [7:0] a s p 0110_000 w a cmd 00101101 a data[31:24] a data[23:16] a s p 0110_000 w a cmd = 01101101 a data[15:8] a data[7:0] a s p clock stretch
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 379 intel ? ep80579 integrated processor figure 15-7. dword memory read protocol figure 15-8. dword configuration write protocol b4536-01 dword memory read protocol (smbus word write/word read, pec disabled) 0110_000 w a cmd = 10100001 a destination memory a add offset [23:16 a s p 0110_000 w a cmd = 01100001 a add offset [15:8] a add offset [7:0] a s p clock stretch 0110_000 w a cmd = 10100001 a s 0110_000 r a status a data[31:24] n sr p 0110_000 w a cmd = 00100001 a s 0110_000 r a data[23:16] a data[15:8] n sr p 0110_000 w a cmd = 01100000 a s 0110_000 r a data[7:0] n sr p b4544-01 dword configuration write protocol (smbus byte write, pec disabled) 0110_000 w a cmd = 10001000 a bus number a s p 0110_000 w a cmd = 00001000 a device/function a s p a p clock stretch 0110_000 w a cmd = 00001000 a register num [15:8] a s p 0110_000 w a cmd = 00001000 a register num [7:0] a s p 0110_000 w a cmd = 00001000 a data[w:x] a s p 0110_000 w a cmd = 01001000 a data[y:z] s
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 380 order number: 320066-003us 15.2.2 suggested smbus usage models 15.2.2.1 remote error handling the ep80579 supports error escalation via both smi and mcerr fsb signaling, thus error handling may be implemented in system management mode (smm) software, machine check architecture (mca) software, or a combination of the two. such software could direct a bmc with an integrated nic to ?call home? when errors are reported by the imch. the bmc could then interrogate internal imch error logging registers under remote control across the network interface, providing full identification and isolation of reported errors as described elsewhere in this document. the possibility also exists for remotely managed reconfiguration via the smbus target port, as well as remotely managed system reboot via the bmc (if necessary). 15.2.2.2 remote platform monitoring the smbus target also provides a sophisticated bmc with the capability to monitor the health of an ep80579-based platform, such that statistics on correctable error location and frequency may be tracked remotely in an effort to anticipate and prevent more serious failures. the imch includes significant rasum functionality on both its memory subsystem and its pci express interfaces. some types of errors are expected at a modest frequency within a platform of this complexity, and the imch provides internal hardware to track the frequency of such errors. these include correctable ecc errors on the memory interface, as well as transient communication errors on the high-speed serial pci express interfaces ? refer to chapter 14.0, ?ras features and exception handling? for further details. the bmc could be remotely directed to periodically poll the internal error logging registers of the imch, permitting a remote management software package to maintain a running profile of error types and frequencies experienced by an ep80579-based platform. changes in error frequency or type could be flagged by the remote monitoring software to prompt follow-up preventative maintenance on the platform. 15.3 platform power management support the imch is compatible with the pci bus power management interface specification , revision 1.1 (referred to here as pci-to-pmi). th e imch is also compatible with the advanced configuration and power interface specification, rev. 2.0 (acpi) . the ep80579 is designed to operate seamlessly with operating systems employing these specifications. the anticipated implementation for platform power management control is an add-on component connected to the iich component of the core logic via its lpc and/or smbus interfaces. 15.3.1 supported system power states the imch and the system power states are analogous, thus no ?device? power states are defined for the imch. as a result, the imch power state may be directly inferred from the system power state. like all systems, ep80579-based platforms must support the s0 (fully active) state at a minimum. the imch also supports s1 (idle), s3 cold (suspend to ram), s4 (suspend to disk), and s5 (soft off). s2 (power-on suspend) and s3 hot are not supported.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 381 intel ? ep80579 integrated processor s3 support requires specialized internal hardware. a request to enter the s3 power state is communicated to the imch by the iich. in response, the imch flushes all data from the internal coherent write buffer, sequences all active dimm rows into their ?self- refresh? state, and then returns an ack_sx special cycle to the iich. upon completion of this sequence, the imch tolerates the removal of all clock references and power sources, save the ddr2 interface power. ddr2 interface power must be supplied so that the imch may hold the dimms in self-refresh. a full system initialization and configuration sequence is required upon system exit from the s3 state, as all (non- aux) internal configuration information has been throughout the platform, but exit latency is much lower than it would be from s5, as the memory image has been maintained. note: the go_s3 message indicates that the iich is getting ready to put the system into s3, s4 or s5 state. the extra internal logic support for s3 and s4 is not required for the s5 (soft off) system power state because all data in the memory array is lost regardless, and the coherent write buffer is architecturally part of the data stored in main memory. 15.3.1.1 supported cpu power states ep80579-based platforms support the c0, c1, c2 and c3 states as defined by the advanced configuration and power interface specification (acpi) . this implies that the core logic anchored by the imch properly understands and handles messaging between the imch and the fsb to facilitate transitions into and out of these states. 15.3.1.2 supported device power states the imch supports all pci-to-pmi and pci express messaging required to place any subordinate device on any of its pci express ports into any of the defined device low power states. peripherals attached to the pci segments provided via a pxh component may be placed in any of their supported low power states via messaging directed from the imch through the intervening pci express hierarchy. directly attached native pci express devices are not limited in their available low power states, although not all available states support the downstream device ?wake-up? semantic. further details about pci express power management support and accompanying pci express and subordinate device power management support are provided in section 15.3.3, ?pci express interface power management? on page 382 . 15.3.1.3 supported bus power states no low power bus states are supported by the ep80579 on its internal nsi interface between the imch and the iich. also, imch does not support placement of the iich only into any low-power state below d0, other than as a side-effect of placing the entire system into one of the s3 cold, s4, or s5 states. significant low power mode support is provided for the several imch pci express ports, as detailed in section 15.3.3, ?pci express interface power management? on page 382 . 15.3.2 ddr2 interface power management ddr2 self-refresh is supported as an integral piece of the s3 support.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 382 order number: 320066-003us 15.3.3 pci express interface power management in pci express, the traditional bus (b*) power states assigned to system buses are replaced by link (l*) power states, which are largely managed by hardware without software intervention. entry into and out of these states may be initiated by two distinct mechanisms: ? traditional pci-pmi type software managed state changes ? non-traditional pci express autonomous hardware state changes the latter transition type is designated ?active state power management,? (aspm) and included with the pci express interface specification, rev. 1.0a . 15.3.3.1 pci express link power state definitions support for all of the following pci express link power states is required for pci express specification compatibility: note: the imch does not support all pci express link power states. ? l0 ? active state with all operations enabled (default state after platform initialization). ? l0s ?low latency, energy saving standby state, disabling exchange of both transaction layer packets and device link layer messages. this state is used exclusively by the aspm pci express function, with entry and exit managed autonomously by pci express interface hardware. ? l1 ? (only supported in software managed state changes) moderate to high latency, very low power, standby state, disabling exchange of both transaction layer packets and device link layer messages. entered when the downstream device is programmed to a device power state below the d0 active state, or optionally under hardware control during aspm. the clock remains active in l1, and exit from this state may be initiated by either the upstream or the downstream device. ? l2/l3 ready ? staging point for removal of main power and clocking. new intermediate state not directly related to pci pm d-state transitions, nor to aspm. hand-shaking lands the link in this state in anticipation of power removal, at which point the link moves to either l2 or l3 depending upon the presence of vaux. ? l2 ? high latency, very low deep sleep state, disabling exchange of transaction layer packets and device link layer messages. l2 is characterized by removal of clocking and main power, but presence of vaux power. exit is initiated by restoring clocking and power, and full initialization. ? l3 ? high latency, link off state with power, vaux, and clock reference removed. exit is initiated by restoring clocking and power, and full initialization. the imch is fully compliant with the pci express specification , but does not support the optional l1 state via the aspm mechanism. refer to the pci express* interface specification, rev. 1.0a for further detail on the link states and specific information on entry and exit mechanisms. 15.3.3.2 software controlled pci express link states software managed device power state changes do not explicitly control the power l- state of pci express links. instead the l-state is inferred by hardware from the pci-pmi power state of the devices attached to that link. when pm software transitions a pci express device to a low power state, that device automatically negotiates with hardware to bring its upstream link into the appropriate link power state. no link is allowed to be in a link power state ?below? that which is dictated by its attached components.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 383 intel ? ep80579 integrated processor table 15-12 defines the legal relationships between link and attached device power states. several new semantics are introduced with pci express to support pci-pmi compatible software managed device and link power state transitions. the majority of the new functionality is to accommodate an esse ntially edge-triggered, in-band message scheme supporting multi chassis cabled system topologies, which must replace the function of traditional level-sensitive board traces for pm event and wake signaling. further details about pme signaling appears in section 15.3.5, ?pme support? on page 385 . the imch supports messaging to facilitate transition of attached pci express devices to power states d0, d1, d2, and d3 (both d3 hot and d3 cold ). all attached devices are required by the pci express specification to support the d0 and both d3 states, while d1 and d2 support are optional. software should confirm device support of the optional d1 and d2 states prior to attempting thei r use on any attached pci express device. in the d1, d2, and d3 hot states, the attached device is required to suppress initiation of any link traffic other than pme initiation (if enabled) as a master, and must only accept configuration transactions as a target. functional context is maintained in the d1 and d2 states, such that full initialization of the attached device is not required upon the wake-up transition back to the d0 state. in both d3 states, functional context is not maintained, and full initialization is required after a transition back to d0. placing an attached device into a low power state results in automatic transition of the associated pci express port to its l1, l2 or l3 link state (depending upon the device power state). to save additional power in the l2 state, the platform power manager must remove the reference clock from the link. the imch does not provide the necessary internal clock generation and distribution control to allow clock removal from one pci express port interface without impacting the operation of its peer ports on the imch. cmi does not provide support on its pci express link interfaces for the in-band ?tone? required to wake from such a state. 15.3.3.3 hardware controlled pci express link states active-state power management (aspm) support is a required component of pci express specification compliance and is intended to provide granularity and flexibility for pci express components to dynamically manage their own power consumption without software supervision and support. all native pci express components, regardless of device class, must support active transitions to and from the l0s low power link state as a minimum and may optionally support active transitions to and from the l1 low power link state. the imch does not support aspm entry into the l1 state under hardware control. cmi negatively acknowledges (nak) aspm requ ests for l1 state transitions. imch configuration registers reflect this level of support for aspm. table 15-12. relationship between link and device pm states downstream component d-state permissible upstream component d-state permissible interconnect l-state d0 d0 l0, l0s, l1 ? d1 d0, d1 l1 d2 d0, d1, d2 l1 d3 hot d0, d1, d2, d3 hot l1, l2/l3 ready d3 cold d0, d1, d2, d3 hot , d3 cold l2, l3 ? entry into l0s or l1 while attached devices remain in d0 only occurs as a part of aspm. per the pci express spec, l0s support is mandatory, while l1 is optional. l1 is not supported by aspm .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 384 order number: 320066-003us all aspm functionality is disabled by default upon system power-up. it is the responsibility of software to verify a viable platform clocking configuration prior to enabling aspm functionality within the imch or in any attached pci express devices. in topologies where independent clock references are used at any point within the pci express subsystem hierarchy, the ?fast training? sequence associated with aspm is not guaranteed to successfully revive the associated link, and aspm must remain disabled in the devices at both ends of that link. 15.3.3.4 system clocking solution dependencies the topology of the platform clocking solution dictates the viability of aspm on each of the pci express links. this is because the nature of the clocks directly impacts the amount of time required to re-acquire bit and symbol lock in the receiver after an arbitrarily long non-communicative period. when both ends of a link share a clock source, they ?wander? together over the period they are out of communication with each other, and accordingly require a relative ly brief period of training to re-acquire lock. when the two ends of a link utilize completely independent clock references, they may become arbitrarily out of phase with each other while they are in low power states, and therefore require a significantly longer amount of time to re-acquire lock upon waking. for this reason, the pci express interface specification provides for software discovery and communication of the actual clocking topology within the system prior to enabling the aspm feature on any link within the system. there are two primary components to the clocking discovery mechanism. first, all downstream ports, such as those on the imch root device, must report whether they use the same clock source as that provided to the slot (or down-device) connected to that port in the platform. this information is recorded in the slot clock configuration bit of the link status register for each port and system bios is required to initialize these bits accordingly. second, all add-in devices must report whether they utilize the clock reference provided on the add-in slot via the same bit in the same register of their capability structure. system software may examine the settings of the slot clock configuration bits of both the upstream and downstream devices for each port in the system, and determine whether a common clock reference is in use. this information is then communicated to both the upstream and the downstream devices via programming of the common clock configuration bit of the link status register. the setting of this bit determines the reported exit latency requirements for the l1 state. system software may then compare the exit latency requirements with the tolerated exit latencies of the attached device and determine whether or not to enable aspm for each link the system. all aspm functionality defaults to disabled at power-on and remain so unless system software determines it may be enabled. the ?n_fts? parameters exchanged during initial training corresponds to the ?long? exit latencies associated with independent clocks. if software later sets the common clock configuration bits, it is also necessary to force link retraining in order to update the exchanged n_fts information. 15.3.3.5 device and link pm initialization all pci express devices power-on into the d0 uninitialized state and remain in that non- communicative state until they have been configured and at least one of the memory space enable, i/o space enable, or bus master enable bits has been set by system software, at which point the device automatically transitions to the d0 active state indicative of normal operation.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 385 intel ? ep80579 integrated processor 15.3.4 device and slot power limits all add-in devices must power-on to a state in which they limit their total power dissipation to a default maximum according to their form-factor (10 w for add-in edge- connected cards). when bios updates the slot power limit register of the root ports within the imch, the imch automatically transmits a set_slot_power_limit message with corresponding information to the attached device.the platform bios is responsible for properly configuring the slot power limit registers in the imch. failure to do so may result in attached endpoints remaining completely disabled in order to comply with the default power limitations associated with their form-factors. 15.3.5 pme support all information in this section refers to the imch pme support. see chapter 27.0, ?power management? for pme support in iich. in cmi systems, only the system power manager or a device within the pci express hierarchy may initiate a power state change. thus the only power management event (pme) signaling support required in the imch is that associated with pci express. note that a device bridging to another technology, such as a pxh bridging to pci-x, may convert traditional pme signaling into pci express in-band pme messaging and thereby meet this requirement of the imch. pme signaling in pci express is crafted to accomplish two distinct functions. first, it provides a signaling mechanism for devices requiring service to propagate a wake-up request to the power management controller. second, it provides a messaging mechanism for devices requesting a power state change to pass their unique location within the pci express hierarchy to the power management controller. the combination of these two functions provides great flexibility and controllability for the power manager. 15.3.5.1 pme wake signaling wake signaling is only required to provide for device-initiated transition out of low power states where clock and/or power have been removed from the sleeping device. the pme mechanism does not require a wake-up function for attached devices still powered and receiving an interface reference clock, as devices in this state may simply initiate pme messaging directly. wake is only required if the device wishing to initiate a pme message cannot do so without first requesting a change to the system clocking and power profile from the power management controller. the wake signaling aspect of the system power management solution may vary in elegance and granularity. depending upon the support level provided by the power management controller, a wake-up request from any given device may cause power and clocking to be restored to the entire system, to just the affected branch of the pci express hierarchy, or only to the requesting device. while the pci express interface specification provides for two distinct wake signaling mechanisms, cmi supports only the legacy mechanism described below. 15.3.5.1.1 legacy wake mechanism the legacy wake signaling mechanism is analogous to that used in historical pci-based system designs. in this case, the platform architect is responsible for crafting paths routing collected wake signals between wa ke-capable devices and the management controller without participation from the imch and iich equivalent devices. the collection of wake logic must run on auxiliary power, and must comprehend the potential for devices both with and without supplied auxiliary power co-existing on the same branch of the pci express hierarchy. refer to the pci express interface specification for further details on legacy wake signaling.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 386 order number: 320066-003us while familiar and well understood, this mechanism does not provide for device- initiated wake-up in the fully a/c coupled implementation of a multi-chassis pci express-based system solution. the limitation imposed upon cmi-based system is that remote-chassis devices must not be placed in a low-power state with the pci express link clocking and/or power disabled if legacy style wake signaling is desired for any peripheral in that remote chassis. it is still possible for software to place peripheral devices in low power sleep states and to manage the device state of the pci express device attached to the inter-chassis cable. devices in the remote chassis may still initiate power state changes via pme messaging provided the inter-chassis link has not been placed into an uncommunicative state. an alternative for the platform architect would be to place a compatible switch device between the imch and the remote chassis that supports the in-band wake mechanism described below and rely on the switch to forward wake events to the management controller. the platform architect should ensure that the power management controller can adequately isolate the source of a pme wake request as required to take appropriate power management wake-up action. 15.3.5.2 pme messaging once the link requesting a power state change has a communicative upstream link, it sends the pm_pme packet upstream toward the root device (imch), which in turn is responsible for notifying the management controller. this constitutes an in-band ?virtual wire? signaling mechanism to replace the historical solution that involved multiple independent board traces routin g pme requests to the power manager. because the pm_pme propagates ?in-band? on the pci express interface without any side-band signaling support, pme functionality is made available to multi-chassis system solutions. the imch collects and ?or? pme requests from all logical pci express ports and propagates it to iich over the nsi link as an assert_pmegpe message. the iich then generates a specified interrupt to wake the power manager and invokes power management software. the interrupt service routine may then interrogate the various pm status registers to determine the source(s) of pme. the imch would send a deassert_pmegpe message over nsi link after the power state change request has been serviced. 15.3.6 bios support for pci express pm messaging the pci express specification stipulates hierarchical messaging semantics enforced by the root device (imch) to guarantee proper entry into and exit from unpowered device states. cmi acpi bios must make special allowances for support of these semantics. there are two sets of messages that must be software-assisted in cmi based platforms to support power-off device states within the pci express hierarchy. 15.3.6.1 pci express pme_turn_off semantic prior to removing power from any attach ed pci express links anywhere in the hierarchy, the root device must broadcast a pci express ?pme_turn_off? message to all downstream devices on the affected pci express port. the receiving devices propagate this message to all subordinate pci express ports (if any), collect ?pme_to_ack? acknowledgement packets, and finally return a ?pme_to_ack? transaction layer packet back to the root device. once all active ports have acknowledged, the power management device may be notified that it is cleared to modify the collective power state of the pci express hierarchy. these message packets have posted semantics on the interface, thus the turn-off ?pushes? all prior packets to
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 387 intel ? ep80579 integrated processor their endpoints, and the acknowledge ?pushes? any pending inbound traffic all the way to the root. this prevents ?trapping? transactions or pme messages somewhere in the hierarchy at the time power is dropped, ultimately causing them to be lost. in a pure pci express design, the pme_turn_off packet would originate directly at the power manager, or perhaps at the iich providing connection between the power manager and the remainder of the core logic. neither the power manager nor the iich is aware of the pci express messaging mechanism, thus the imch provides device- specific control and status bits for use by its acpi bios. the sequence of events to place a pci express device in an unpowered state is as follows: 1. pci-pm or acpi-compliant o/s software is called to place the system into a low- power sleep state (s3, s4 or s5), prepares for suspension, and calls acpi bios to carry out the platform power transition. 2. the bios then communicates to the root complex that all pci express devices must prepare for power-off. this is accomplished through the device-specific configuration space of the internal virtual pci-to-pci bridges with subordinate pci express hierarchies. the bios must configure each active root port to power-down. when the configuration write is received to set the ?pm turn off? bit, the associated root port transmits a pm_turn_off message downstream. at this point, any traffic in-flight continues to be handled normally by the imch ? routed outbound, and completed inbound. 3. the target pci express device ceases generation of new transactions inbound, waits for all pending transactions to complete and prepares to lose power and clocking. if the target device has a subordinate hierarchy of its own, it propagates the pm_turn_off message downstream and waits for acknowledges from all subordinate ports. once ready to be brought off-line, the target device issues a pm_to_ack tlp cycle in acknowledgement back to the root. note that the link is still communicative at this point, with both power and clock available. 4. after issuing the pm_to_ack cycle, the downstream device then issues a pm_enter_l23 dllp continuously upstream until it receives an acknowledge. in response to the pm_to_ack, the root port will commence the pci express handshake sequence necessary to sets its ?turn off ack? status bit. in response to the pm_enter_l23 dllp, the root transitions its downstream link to the electrical idle state. (this protocol sequence directly mirrors the l1 entry sequence.) 5. acpi bios, which has been waiting for all of the ?turn off ack? status bits to assert, now clears all the command and status bits associated with the pme_turn_off. the routine then informs the power manager to go ahead with the change to the system power state. note that software is required (by the pci express specification) to implement a ?dead-man? timer such that a failure to receive a full complement of ?turn off ack? status bits does not result in an indefinite hang. this timeout is nominally 1 second, after which the power state change proceeds regardless. 6. the power manager drops power and clocking to the target device(s), and all associated links automatically transition to either the l2 or l3 uncommunicative power states. the links enter l2 if vaux is supplied by the platform, otherwise they enter l3. (note that the imch does not support vaux, so all downstream lanes will necessarily go to the l3 state.) the platform remains in the low-power state until a wake event is signaled. in a fully pci express aware core logic implementation, the acpi bios would not need to act as the interlock between the imch and the power manager, as all that functionality would be handled in hardware via direct messaging.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 388 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 389 intel ? ep80579 integrated processor 16.0 imch registers 16.1 imch registers: bus 0, device 0, function 0 the integrated memory controller hub (imch) registers are in bus 0, device 0, function 0. ta b l e 1 6 - 1 provides the register address map for this device and function. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. table 16-1. bus 0, device 0, function 0: summary of imch pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid ? vendor identification register? on page 391 8086h 02h 03h ?offset 02h: did ? device identification register? on page 391 5020h 04h 05h ?offset 04h: pcicmd: pci command register? on page 392 0006h 06h 07h ?offset 06h: pcists: pci status register? on page 393 0010h 08h 08h ?offset 8h: rid - revision identification register? on page 394 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 394 00h 0bh 0bh ?offset 0bh: bcc ? base class code register? on page 394 06h 0eh 0eh ?offset 0eh: hdr - header type register? on page 395 80h 14h 17h ?offset 14h: smrbase - system memory rcomp base address register? on page 396 00000000h 2ch 2dh ?offset 2ch: svid - subsystem vendor identification register? on page 396 0000h 2eh 2fh ?offset 2eh: sid - subsystem identification register? on page 397 0000h 4ch 4fh ?offset 4ch: nsibar - root complex block address register? on page 397 00000000h 50h 50h ?offset 50h: cfg0- imch configuration 0 register? on page 398 0ch 51h 51h ?offset 51h: imch_cfg1 ? imch configuration 1 register? on page 399 00000h 53h 53h ?offset 53h: cfgns1 - configuration 1 (non-sticky) register? on page 399 00h 58h 58h ?offset 58h: fdhc - fixed dram hole control register? on page 400 00h 59h 59h ?offset 59h: pam0 - programmable attribute map 0 register? on page 401 00h 5ah 5ah ?offset 5ah: pam1: programmable attribute map 1 register? on page 402 00h 5bh 5bh ?offset 5bh: pam2 - programmable attribute map 2 register? on page 403 00h 5ch 5ch ?offset 5ch: pam3 - programmable attribute map 3 register? on page 404 00h 5dh 5dh ?offset 5dh: pam4 - programmable attribute map 4 register? on page 405 00h 5eh 5eh ?offset 5eh: pam5 - programmable attribute map 5 register? on page 406 00h 5fh 5fh ?offset 5fh: pam6 - programmable attribute map 6 register? on page 407 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 390 order number: 320066-003us 9ch 9ch ?offset 9ch: devpres - device present register? on page 408 33h 9dh 9dh ?offset 9dh: exsmrc - extended system management ram control register? on page 409 00h 9eh 9eh ?offset 9eh: smram - system management ram control register? on page 411 02h 9fh 9fh ?offset 9fh: exsmramc - expansion system management ram control register? on page 413 07h b8h bbh ?offset b8h: imch_mencbase: ia/asu shared non-coherent (aioc-direct) memory base address register? on page 413 000fffffh bch bfh ?offset bch: imch_menclimit - ia/asu shared non-coherent (aioc-direct) memory limit address register? on page 414 00000000h c4h c5h ?offset c4h: tolm - top of low memory register? on page 415 0800h c6h c7h ?offset c6h: remapbase - remap base address register? on page 416 03ffh c8h c9h ?offset c8h: remaplimit ? remap limit address register? on page 416 0000h cah cbh ?offset cah: remapoffset - remap offset register? on page 417 0000h cch cdh ?offset cch: tom - top of memory register? on page 417 0000h ceh cfh ?offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register? on page 418 e000h d8h d8h ?offset d8h: cachectl0 - write cache control 0 register? on page 418 00h deh dfh ?offset deh: skpd - scratchpad data register? on page 419 0000h f6h f6h ?offset f6h: imch_tst2 - imch test byte 2 register? on page 419 00h 60h at 1h 60h at 1h ?offset 60h: drb[0-3] - dram row [3:0] boundary register? on page 421 ffh 70h at 4h 73h at 4h ?offset 70h: dra[0-1] - dram row [0:1] attribute register? on page 422 00000515h 78h 7bh ?offset 78h: drt0 - dram timing register 0? on page 424 242ad280h 64h 67h ?offset 64h: drt1 - dram timing register 1? on page 431 12110000h 7ch 7fh ?offset 7ch: drc - dram controller mode register? on page 435 00000002h 84h 87h ?offset 84h: eccdiag - ecc detection/correction diagnostic register? on page 437 00000000h 88h 8bh ?offset 88h: sdrc - ddr sdram secondary control register? on page 439 00000002h 8ch 8ch ?offset 8ch: ckdis - ck/ck# clock disable register? on page 441 00h 8dh 8dh ?offset 8dh: ckedis - cke clock enable register? on page 442 00h 90h 93h ?offset 90h: sparectl - spare control register? on page 443 00000000h b0h b3h ?offset b0h: ddr2odtc - ddr2 odt control register? on page 444 00000000h table 16-1. bus 0, device 0, function 0: summary of imch pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 391 intel ? ep80579 integrated processor 16.1.1 register details 16.1.1.1 offset 00h: vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. 16.1.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. table 16-2. offset 00h: vid ? vendor identification register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel 8086h. 8086h ro table 16-3. offset 02h: did ? device identification register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 02h 03h size: 16 bit default: 5020h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the imch host-nsi bridge function 0. 5020h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 392 order number: 320066-003us 16.1.1.3 offset 04h: pcicmd: pci command register since imch device 0 does not physically resi de on a pci bus, many of the bits are not supported. table 16-4. offset 04h: pcicmd: pci command register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 04h 05h size: 16 bit default: 0006h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 fb2b fast back-to-back enable: this bit is hardwired to 0. 0b ro 08 serre serr enable: this bit is a global enable bit for device 0 serr messaging. the imch does not have a serr signal. the imch communicates the serr condition by sending a serr message over nsi to the iich. 0 = disable. the serr message is not generated by the imch for device 0. 1 = enable. the imch enables generation of serr messages over nsi for specific device 0, function 0 error conditions that are enabled via the pcicmd register. the error status is reported in the pcists registers. the only error event enabled through device 0, function 0 is detected parity error which is essentially a nsi poisoned tlp, and is enabled by the parity error enable bit (perre). note: this bit only controls serr messaging for device 0, function 0. device 0, function 1, and devices 1-7 have their own serr bits to control error reporting for error conditions occurring on their respective devices. the control bits are used in a logical or manner to enable the serr nsi message mechanism. 0b rw 07 reserved reserved 0b 06 perre parity error enable: 0 = disable. the imch does not take any action when it detects data corruption on nsi. 1 = enable. the imch generates an serr message over the nsi to the iich when a poisoned tlp is detected by the imch on nsi (dpe set in pcists) and serre is set to 1. 0b rw 05 : 03 reserved reserved 0h 02 bme bus master enable: the imch is always enabled as a master on nsi. this bit is hardwired to 1. writes to this bit position have no effect. 1b ro 01 mae memory access enable: this bit is hardwired to 1. 1b ro 00 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 393 intel ? ep80579 integrated processor 16.1.1.4 offset 06h: pcists: pci status register pcists is a 16-bit status register that reports the occurrence of error events on device 0?s pci interface. since imch device 0 does not physically reside on a pci bus many of the bits are not supported. table 16-5. offset 06h: pcists: pci status register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: this bit is set to 1 whenever it receives a poisoned tlp regardless of the state of the parity error response bit. software may clear this by writing a 1 to this bit. 0b rwc 14 sse signaled system error: 0 = software clears this bit by writing a 1 to the bit location. 1 = imch device 0, function 0 generates a serr message over nsi for any enabled device 0, function 0 error condition. device 0 error co nditions are enabled in the pcicmd register. device 0 error flags are read/reset from the pcists register. the only error that can be enabled to signal system error through device 0, function 0 is the detected parity error which is essentially a nsi poisoned tlp. software may clear this by writing a 1 to this bit. 0b rwc 13 rmas received master abort status: this bit is set if the imch generates a nsi request that receives a completion with unsupported request completion status. software may clear this by writing a 1 to this bit. 0b rwc 12 rtas received target abort status: set to 1 by hardware if the imch generated a request that received a completion with completer abort status. software clears this bit by writing a 1 to this bit location. 0b rwc 11 stas signaled target abort status: the imch does not generate a completer abort on the nsi completion packet. this bit is hardwired to w10. writes to this bit position have no effect. 0b ro 10 : 09 reserved reserved 00b 08 dpd master data parity error detected: this bit is hardwired to 0. 0b rwc 07 fb2b fast back-to-back: reserved. 0b 06 : 05 reserved reserved 00b 04 clist capability list: this bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offset 34h. 1b ro 03 : 00 reserved reserved 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 394 order number: 320066-003us 16.1.1.5 offset 08h: rid - revision identification register this register contains the revision number of the imch device 0. these bits are read- only and writes to this register have no effect. 16.1.1.6 offset 0ah: subc - sub-class code register 16.1.1.7 offset 0bh: bcc ? base class code register table 16-6. offset 8h: rid - revision identification register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the imch device 0. variable ro table 16-7. offset 0ah: subc - sub-class code register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 0ah 0ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 subc sub-class code: this value indicates the sub class code into which the imch device 0 falls. 00h = host bridge 00h ro table 16-8. offset 0bh: bcc ? base class code register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 0bh 0bh size: 8 bit default: 06h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 basec base class code: this value indicates the base class code for the imch device 0. 06h = bridge device 06h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 395 intel ? ep80579 integrated processor 16.1.1.8 offset 0eh: hdr - header type register 16.1.1.9 offset 14h: smrbase - system memory rcomp base address register the smrbase is a standard pci base address register that is used to set the base of the memory mapped registers used to control the system memory i/o buffer rcomp. in addition to calibration, the dcal engine which resides within this memory mapped region also performs ras functions. in addition, there are some bios scratch registers within this region. the actual behavior of this register depends on the smrcomp mmr enable bit in the imch tst2 register (device 0, function 0, offset f6, bit 6). when imch tst2[6] is set, this register behaves like a standard pci bar requesting 4 kbyte of address space. when imch tst2[6] is clear, this register is hardwired to all zeros, effectively disabling the bar and the corresponding sm mmr region. because of the more extensive functionality supported by dcal, it is expected that once this address space has been enabled by system bios, it remains enabled to support various ras features. note: all accesses to these memory mapped registers must be made as a single dword (4 bytes) or less. access must be aligned on a natural boundary. table 16-9. offset 0eh: hdr - header type register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 0eh 0eh size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr note: pci header: the header type of the imch device 0. 80h = multi-function device with standard header layout. this register should return a 00h indicating a single function device, when both functions 1 and 2 are disabled. 80h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 396 order number: 320066-003us 16.1.1.10 offset 2ch: svid - subsystem vendor identification register this value is used to identify the vendor of the subsystem. table 16-10. offset 14h: smrbase - system memory rcomp base address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 14h 17h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 upbits upper programmable base address: these bits are part of the sm mmr region, normally set by configuration software to locate the base address of the region. the actual behavior of this field depends on the sm mmr enable bit in the imch tst2 register (bit 6) as defined above. when imch tst2[6] = 1 these bits are read/write. when imch tst2[6] = 0 these bits are read-only as zeros. 00000h rw or ro 11 : 04 lowbits lower bits: these bits are hardwired to 0. this forces the size of the memory region to be 4 kbyte. 00h ro 03 pf prefetchable: this bit is hardwired to 0 to indicate that the system memory mmr region is non-prefetchable. 0b ro 02 : 01 type addressing type: these bits determine addressing type and they are hardwired to 00 to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space in order to comply with the pci specification for base address registers. 00b ro 00 mspace memory space indicator: hardwired to 0 to identify the mmr range as a memory range as per the specification for pci base address registers. 0b ro table 16-11. offset 2ch: svid - subsystem vendor identification register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subvid subsystem vendor id: this field must be programmed during boot-up to indicate the vendor of the system board. 0000h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 397 intel ? ep80579 integrated processor 16.1.1.11 offset 2eh: sid - subsystem identification register this value is used to identify a particular subsystem. 16.1.1.12 offset 4ch: nsibar - root complex block address register this is the base address for the root complex memory-mapped configuration space. this window of addresses contains the root complex register block for the nsi hierarchy associated with the imch. there is no physical memory within this 4 kbyte window that can be addressed. the 4 kbyte reserved by this register does not alias to any pci 2.3 compliant memory mapped space. all accesses to these memory mapped registers must be made as a single dword (4 bytes) or less. access must be aligned on a natural boundary. table 16-12. offset 2eh: sid - subsystem identification register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subid subsystem id: this field must be programmed during bios initialization. after it has been written once it becomes read-only. when any byte or combination of bytes of this register is written, the register value locks and cannot be further updated. 0000h rwo table 16-14. offset 4ch: nsibar - root complex block address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 4ch 4fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 nsi_ba nsi base address: the bios programs this register resulting in a base address for a 4 kbyte block of contiguous memory address space. this register ensures that a naturally aligned 4 kbyte space is allocated within total addressable memory space of 4 gbyte. system software uses this base address to program the nsi register set. when imch tst2[5] = 1, the nsi memory mapped register space is visible and memory mapped accesses are claimed and decoded appropriately. when imch tst2[5] = 0, the nsi memory mapped register space is disabled and does not claim any memory. (the nsibar register is still read/write accessible.) 00000h rw or ro 11 : 00 reserved hardwired to 0 000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 398 order number: 320066-003us 16.1.1.13 offset 50h: cfg0 - imch configuration 0 register mchcfg consists of imch cfg1 in the upper 8 bits and imch cfg0 in the lower 8 bits. table 16-15. offset 50h: cfg0- imch configuration 0 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 50h 50h size: 8 bit default: 0ch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 0h 02 ioqd in-order queue depth: this bit reflects the value sampled on ha[7]# on the de-assertion of the cpurst#. it indicates the depth of the cpu bus in-order queue. 0 = ha[7]# has been sampled asserted (e.g., logic one, or electrical low). the depth of the ioq is set to one (e.g., no pipelining on the processor bus). ha[7]# may be driven low during cpurst# by an external source. 1 = ha[7]# was sampled as deasserted (e.g. logic zero or electrical high). the depth of the processor bus in- order queue is configured to the maximum (e.g., 12). 1b ro 01 drfd deferred resource fairness disable: 0 = clearing the bit allows the fairness logic to start working again. 1 = setting this bit clears the fairness logic for deferred resources and hold it in reset. note: this bit should only be changed in the event that there is some issue with the fairness logic. 0b rw 00 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 399 intel ? ep80579 integrated processor 16.1.1.14 offset 51h: imch _ cfg1 ? imch configuration 1 register 16.1.1.15 offset 53h: cfgns1 - configuration 1 register this register contains imch control bits that are not sticky. table 16-16. offset 51h: imch_cfg1 ? imch configuration 1 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 51h 51h size: 8 bit default: 00000h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 05 nsg number of stop grant cycles: number of stop grant transactions expected on the fsb bus before a req_c2 packet is sent to the iich. this field is programmed by the bios after it has enumerated the processors and before it has enabled stop clock generation in the iich. once this field has been set, it must not be modified. note that each enabled thread within each cpu generates stop grant acknowledge transactions. note: this register is read/write and not write-once as in some implementations. encoding description 0 0 0 nsi stop grant generated after 1 fsb stop grant 0 0 1 nsi stop grant generated after 2 fsb stop grant 0 1 0 nsi stop grant generated after 3 fsb stop grant 0 1 1 nsi stop grant generated after 4 fsb stop grant 1 0 0 nsi stop grant generated after 5 fsb stop grant 1 0 1 nsi stop grant generated after 6 fsb stop grant 1 1 0 nsi stop grant generated after 7 fsb stop grant 1 1 1 nsi stop grant generated after 8 fsb stop grant 000b rw 04 : 00 reserved reserved 00000b table 16-17. offset 53h: cfgns1 - configuration 1 (non-sticky) register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 53h 53h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 000b 01 thwo throttled-write occurred: 0 = writing a zero clears this bit. 1 = this bit is set by hardware when a write is throttled. this happens when the maximum allowed number of writes has been reached during a time-slice and there is at least one more write to be completed. 0b rw0c
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 400 order number: 320066-003us 16.1.1.16 offset 58h: fdhc - fixed dram hole control register this 8-bit register controls a fixed dram hole from 15?16 mbytes. 00 thro throttled-read occurred: 0 = writing a zero clears this bit. 1 = this bit is set by hardware when a read is throttled. this happens when the maximum allowed number of reads has been reached during a time-slice and there is at least one more read to be done. 0b rw0c table 16-17. offset 53h: cfgns1 - configuration 1 (non-sticky) register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 53h 53h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-18. offset 58h: fdhc - fixed dram hole control register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 58h 58h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 hen hole enable: this field enables a memory hole in dram space. the dram that lies ?behind? this space is not remapped. 0 = no memory hole 1 = memory hole from 15?16 mbytes. accesses in this range are sent to nsi. 0b rw 06 : 00 reserved reserved 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 401 intel ? ep80579 integrated processor 16.1.1.17 offset 59h: pam0 - programmable attribute map 0 register this register controls the read, write, and shadowing attributes of the bios area from 0f0000h-0fffffh. see section 19.0.3, ?pam memory spaces? for more information on pam memory spaces. table 16-19. offset 59h: pam0 - programmable attribute map 0 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 59h 59h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register: this field controls the steering of read and write cycles that address the bios area from 0f0000 to 0fffff. encoding description: 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write-only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw 03 : 00 reserved reserved 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 402 order number: 320066-003us 16.1.1.18 offset 5ah: pam1 - programmable attribute map 1 register this register controls the read, write, and shadowing attributes of the bios areas from 0c0000h-0c7fffh. table 16-20. offset 5ah: pam1: programmable attribute map 1 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 5ah 5ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register 0c4000-0c7fff: this field controls the steering of read and write cycles that address the bios area from 0c4000 to 0c7fff encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write-only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw 03 : 02 reserved reserved 00b 01 : 00 loenable attribute register 0c0000-0c3fff: this field controls the steering of read and write cycles that address the bios area from 0c0000 to 0c3fff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write-only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 403 intel ? ep80579 integrated processor 16.1.1.19 offset 5bh: pam2 - programmable attribute map 2 register this register controls the read, write, and shadowing attributes of the bios areas from 0c8000h-0cffffh. table 16-21. offset 5bh: pam2 - programmable attribute map 2 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 5bh 5bh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register 0cc000-0cffff: encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write-only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw 03 : 02 reserved reserved 00b 01 : 00 loenable attribute register 0c8000-0cbfff: this field controls the steering of read and write cycles that address the bios area from 0c8000 to 0cbfff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. a writes are forwarded to nsi. 1 0 write-only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 404 order number: 320066-003us 16.1.1.20 offset 5ch: pam3 - programmable attribute map 3 register this register controls the read, write, and shadowing attributes of the bios areas from 0d0000h-0d7fffh. table 16-22. offset 5ch: pam3 - programmable attribute map 3 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 5ch 5ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register 0d4000-0d7fff: this field controls the steering of read and write cycles that address the bios area from 0d4000 to 0d7fff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw 03 : 02 reserved reserved 00b 01 : 00 loenable attribute register 0d0000-0d3fff: this field controls the steering of read and write cycles that address the bios area from 0d0000 to 0d3fff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 405 intel ? ep80579 integrated processor 16.1.1.21 offset 5dh: pam4 - programmable attribute map 4 register this register controls the read, write, and shadowing attributes of the bios areas from 0d8000h-0dffffh. table 16-23. offset 5dh: pam4 - programmable attribute map 4 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 5dh 5dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register 0dc000-0dffff: this field controls the steering of read and write cycles that address the bios area from 0dc000 to 0dffff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw 03 : 02 reserved reserved 00b 01 : 00 loenable attribute register 0d8000-0dbfff: this field controls the steering of read and write cycles that address the bios area from 0d8000 to 0dbfff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 406 order number: 320066-003us 16.1.1.22 offset 5eh: pam5 - programmable attribute map 5 register this register controls the read, write, and shadowing attributes of the bios areas from 0e0000h-0e7fffh. table 16-24. offset 5eh: pam5 - prog rammable attribute map 5 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 5eh 5eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register 0e4000-0e7fff: this field controls the steering of read and write cycles that address the bios area from 0e4000 to 0e7fff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw 03 : 02 reserved reserved 00b 01 : 00 loenable attribute register 0e0000-0e3fff: this field controls the steering of read and write cycles that address the bios area from 0e0000 to 0e3fff. encoding description 0 0 dram disabled - all accesses are directed to nsi. 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi. 1 0 write only - all writes are sent to dram. reads are serviced by nsi. 1 1 normal dram operation - all reads and writes are serviced by dram. 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 407 intel ? ep80579 integrated processor 16.1.1.23 offset 5fh: pam6 - programmable attribute map 6 register this register controls the read, write, and shadowing attributes of the bios areas from 0e8000h-0effffh. 16.1.1.24 offset 9ch: devpres - device present register the device present bits can be used to enable/disable devices within the imch and make their pci configuration space respectively visible/invisible to software. the device present bits convey when cleared that the corresponding device is never available. when a bit is 0, the configuration space associated with that device is hidden, returning all 1?s for all configuration register reads just as if the cycle terminated with a master abort on pci. for the two pcie* devices listed the i/o buffers and compensation associated with those devices are disabled and tri-stated. when a bit is 1, the configuration space associated with that device is accessible. for the two pcie* devices the i/o buffers and compensation are enabled. note: bios should write this register as part of its power on configuration sequence. bits within this register are broken into two categories ?rwo or ro? and ?rw? and are functionally defined below. table 16-25. offset 5fh: pam6 - programmable attribute map 6 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 5fh 5fh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00b 05 : 04 hienable attribute register 0ec000-0effff: this field controls the steering of read and write cycles that address the bios area from 0ec000 to 0effff. encoding description 0 0 dram disabled - all accesses are directed to nsi 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi 1 0 write only - all writes are sent to dram. reads are serviced by nsi 1 1 normal dram operation - all reads and writes are serviced by dram 00b rw 03 : 02 reserved reserved 00b 01 : 00 loenable attribute register 0e8000-0ebfff: this field controls the steering of read and write cycles that address the bios area from 0e8000 to 0ebfff. encoding description 0 0 dram disabled - all accesses are directed to nsi 0 1 read-only - all reads are serviced by dram. all writes are forwarded to nsi 1 0 write only - all writes are sent to dram. reads are serviced by nsi 1 1 normal dram operation - all reads and writes are serviced by dram 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 408 order number: 320066-003us ?rwo or ro? bits: all of the ?rwo or ro? bits in this register are gated with a sku value. the sku value has priority over values written by software. this means that if the sku value of this bit is set to a 0, neither a configuration write or a reset sets this bit. if a sku value is not present then the register will have ro access. when a sku value is not present, the device is invisible to software. writes to this register when the sku value is not present, will have no effect, always returning ?0? when read. if a sku value is present the register will have rwo access. note: bios must write a bit to a 0 to disable a device, or a 1 to enable a device. this register can only be written once. after the first write, the register is locked. note: rwo devices that are disabled via software can only be re-enabled via a reset. this register should only be written to at boot time when there is no traffic to or from the pea. once software or bios has written these rwo register bits for the first time after power-up, the register value locks, and cannot be further updated. in other words, once software has disabled rwo devices, they can only be re-enabled via a reset. for rwo access bits the imch does not support turning off a device, and then turning it back on. (the reverse is also true: once software has enabled rwo devices, they can only be re-disabled via a reset.) rw bits: two devices have rw bit access. these devices need to be enabled/disabled for power management during normal operation table 16-26. offset 9ch: devpres - device present register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9ch 9ch size: 8 bit default: 33h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 0b 05 reserved reserved 1b rw 04 device_4_prese nt 0 = pci-to-pci bridge is disabled. 1 = pci-to-pci bridge is enabled. 1b rw 03 device_3_prese nt 0 = pci express* port a1 (x4) is disabled. in this state, port a (device 2) can operate with a maximum x8 link width. 1 = pci express port a1 is enabled. in this state, port a can operate with a maximum x4 link width.when the sku value is cleared, this field is read/write. when the sku value is set, this field becomes a read-only ?0? 0b rwo or ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 409 intel ? ep80579 integrated processor 16.1.1.25 offset 9dh: exsmrc - extended system management ram control register the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mbyte. 02 device_2_prese nt 0 = pci express port a is disabled. 1 = pci express port a is enabled.when the sku value is cleared, this field is read/write. when the sku value is set, this field becomes a read-only ?0? 0b rwo or ro 01 device_1_prese nt 0 = edma controller is disabled. 1 = edma controller is enabled. 1b rwo 00 reserved reserved 1b table 16-26. offset 9ch: devpres - device present register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9ch 9ch size: 8 bit default: 33h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-27. offset 9dh: exsmrc - extended system management ram control register (sheet 1 of 3) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9dh 9dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 h_smrame enable high smram: controls the smm memory space location (above 1 mbyte or below 1 mbyte) 0 = high smram memory space is disabled. 1 = and g_smrame is 1, the high smram memory space is enabled. smram accesses within the range 0feda_0000h to 0fedb_ffffh are remapped to dram addresses within the range 000a0000h to 000bffffh. once d_lck (see ta b l e 3 5 ) has been set, this bit becomes read-only. 0b rwl
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 410 order number: 320066-003us 06 mdap mda present: this bit works with the vga enable bits in the bctrl registers of devices 2?3 to control the routing of cpu initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set if none of the vga enable bits are set. if none of the vga enable bits are set, then accesses to io address range x3bch-x3bfh are forwarded to nsi. if the vga enable bit is not set then accesses to io address range x3bch-x3bfh are treated just like any other io accesses. for example, the cycles are forwarded to pea[0:1] if the address is within the corresponding iobase and iolimit and isa enable bit is not set, otherwise they are forwarded to nsi. note: since the logic performs the address decoding on a dw boundary, the dw that includes the address 3bf also includes addresses 3bc, 3bd, and 3be, and accesses to any of these byte addresses are handled as mda references. mda resources are defined as the following: memory: 0b0000h - 0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) note: the vga region includes i/o space ranges 3b0- 3bbh, and 3c0-3dfh, so there is an overlap between these two i/o regions. any i/o reference that includes the i/o locations listed above, or their aliases, are forwarded to nsi even if the reference includes i/o locations not listed above. the following table shows the behavior for all combinations of mda and vga: vga mda behavior 0 0 all references to mda and vga go to nsi 0 1 illegal combination (do not use) 1 0 all references to vga go to device with vga enable set. mda- only references (i/o address 3bf and aliases) go to nsi. 1 1 vga-only references go to the pci express port which has its vga enable bit set. mda references go to the nsi. 0b rw 05 apicdis apic memory range disable: 0 = the imch send cycles between 0_fec0_0000 and 0_fec7_ffff to nsi, accesses between 0_fec8_0000 and 0_fec8_0fff are sent to pea0, between 0_fec8_1000 and 0_fec8_1fff are sent to pea1b. 1 = the imch forwards all accesses to the ioapic regions to nsi. 0b rw 04 reserved reserved 0b 03 g_smrame global smram enable: 0 = the compatible smram functions are disabled. 1 = the compatible smram functions are enabled, providing 128 kbyte of dram accessible at the a0000h address while in smm (ads# with smm decode). to enable extended smram function this bit has be set to 1. refer to section 16.1.1.26, ?offset 9eh: smram - system management ram control register? for more details. once d_lck (see table 16-28) is set, this bit becomes read-only. 0b rwl table 16-27. offset 9dh: exsmrc - extended system management ram control register (sheet 2 of 3) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9dh 9dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 411 intel ? ep80579 integrated processor 16.1.1.26 offset 9eh: smram - system management ram control register the smramc register controls how accesses to compatible and extended smram spaces are treated. the open, close, and lock bits function only when g_smrame bit is set to a 1. also, the open bit must be reset before the lock bit is set. 02 : 01 tseg_sz tseg size: selects the size of the tseg memory block if enabled. memory from the top of dram space (tolm - tseg_sz) to tolm is partitioned away so that it may only be accessed by the processor interface and only then when the smm bit is set in the request packet. non-smm accesses to this memory region are specially terminated when the tseg memory block is enabled. note that once d_lck (see table 16-28 ) is set, these bits become read- only. 0 0 (tolm ? 128 k) to tolm 0 1 (tolm ? 256 k) to tolm 1 0 (tolm ? 512 k) to tolm 1 1 (tolm ? 1 m) to tolm 00b rwl 00 t_en tseg enable: enabling of smram memory for extended smram space only. 0 = smram memory for extended smram space disabled. 1 = and g_smrame =1 and t_en = 1, the tseg is enabled to appear in the appropriate physical address space. once d_lck (see ta b l e 1 6 - 2 8 ) is set, this bit becomes read-only. 0b rwl table 16-27. offset 9dh: exsmrc - extended system management ram control register (sheet 3 of 3) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9dh 9dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-28. offset 9eh: smram - system management ram control register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9eh 9eh size: 8 bit default: 02h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved 0b 06 d_open smm space open: 0 = the smm space dram is not visible 1 = and d_lck=0, the smm space dram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software must ensure that d_open=1 and d_cls=1 are not set at the same time. this bit becomes ro when d_lck is set to 1. 0b rwl
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 412 order number: 320066-003us 05 d_cls smm space closed: 0 = smm space dram is accessible to data references 1 = smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space dram. this allows smm software to reference through smm space to update the display even when smm is mapped over the vga range. software must ensure that d_open=1 and d_cls=1 are not set at the same time. note: the d_cls bit only applies to compatible smm space. 0b rw 04 d_lck smm space locked: 0 = smm space unlocked 1 = and then d_open is reset to 0 and d_lck, d_open, h_smrame, tseg_sz and t_en become read-only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to lock smm space in the future so that no application software (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. 0b rws 03 reserved reserved. 0b 02 : 00 c_base_seg compatible smm space base segment: this field indicates the location of smm space. smm dram is not remapped. it is simply made visible if the conditions are right to access smm space, otherwise the access is treated as a vga access. since the imch supports only the smm space between a0000 and bffff, this field is hardwired to 010. 010b ro table 16-28. offset 9eh: smram - system mana gement ram control register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9eh 9eh size: 8 bit default: 02h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 413 intel ? ep80579 integrated processor 16.1.1.27 offset 9fh: exsmramc - expansion system management ram control register the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mbyte. 16.1.1.28 offset b8h: imch_mencbase - ia/asu shared non-coherent (aioc- direct) memory base address register table 16-29. offset 9fh: exsmramc - expansion system management ram control register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 9fh 9fh size: 8 bit default: 07h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 e_smerr invalid smram access: 0 = cpu has not accessed the defined memory ranges in extended smram. 1 = this bit is set when cpu has accessed the defined memory ranges in extended smram (high memory and t-segment) while not in smm space and with the d-open bit = 0. it is software?s responsibility to clear this bit. this bit is cleared by software writing a 1 to the bit location. 0b rwc 06 : 03 reserved reserved 0h 02 sm_cache smram cacheable: this bit is forced to 1 by imch . (moved from esmramc bit 5) 1b ro 01 sm_l1 l1 cache enable for smram: this bit is forced to 1 by imch. (moved from esmramc bit 4) 1b ro 00 sm_l2 l2 cache enable for smram: this bit is forced to 1 by imch. (moved from esmramc bit 3) 1b ro table 16-30. offset b8h: imch_mencbase: ia/asu shared non-coherent (aioc-direct) memory base address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: b8h bbh size: 32 bit default: 000fffffh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 reserved reserved 000h 19 : 00 mencbase ia/asu shared non-coherent memory base address bits[31:12]: specifies the address of the lower boundary of the ia/asu shared non-coherent window in 32-bit system address space. the window is 4kb-aligned and inclusive of this address. this register field specifies bits[31:12] of the address; bits[11:0] are assumed zeros given 4kb alignment. fffffh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 414 order number: 320066-003us 16.1.1.29 offset bch: imch_menclimit - ia/asu shared non-coherent (aioc- direct) memory limit address register 16.1.1.30 offset c4h: tolm - top of low memory register this register contains the maximum address below 4 gbyte that must be treated as a memory access and is defined on a 128 mbyte boundary. usually it is below the areas configured for pci express, nsi, and pci memory. the memory address found in drb3 reflects the amount of total memory populated. table 16-31. offset bch: imch_menclimit - ia/asu shared non-coherent (aioc-direct) memory limit address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: bch bfh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 reserved reserved 00h 19 : 00 menclimit ia/asu shared non-coherent memory limit address bits[31:12]: specifies the address of the upper boundary of the ia/asu shared non-coherent window in 32-bit system address space. the window is 4kb-aligned and inclusive of this address. this register field specifies bits[31:12] of the address; bits[11:0] are assumed ones. setting imch_menclimit less than imch_mencbase indicates a zero-sized window and thus that all memory is coherent. 00000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 415 intel ? ep80579 integrated processor table 16-32. offset c4h: tolm - top of low memory register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: c4h c5h size: 16 bit default: 0800h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 tolm top of low memory: this register corresponds to bits 31 to 27 of the system address which is 1 greater than the maximum dram location below 4 gbyte. configuration software must set this value to either the maximum amount of memory in the system or to the minimum address allocated for pci memory or the graphics aperture, whichever is smaller. address bits 26:00 are assumed to be 0 for the purposes of address comparison. addresses equal to or greater than the tolm, and less than 4 g, are treated as non-memory accesses. all accesses less than the tolm are treated as dram accesses (except for the 15?16 mbyte or pam gaps). this register must be set to at least 0800h, for a minimum of 128 mbyte of dram. there is also a minimum of 128 mbyte of pci space, since this register is on a 128 mbyte boundary. configuration software must set this value to either the maximum amount of memory in the system (same as drb3), or to the lower 128 mbyte boundary of the memory mapped io range, whichever is smaller. programming example: 1100_0b = 3 gbyte (assuming that dbr7 is set > 4 gbyte): an access to 0_c000_0000h or above (but <4 gbyte) is considered above the tolm and therefore not to dram. it may go to one of the pea ports or nsi or be subtracted and decoded to nsi. an access to 0_bfff_ffffh and below is considered below the tolm and go to dram. 00001b rw 10 : 00 reserved reserved 000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 416 order number: 320066-003us 16.1.1.31 offset c6h: remapbase - remap base address register note: this register should not be enabled since the ia-32 core only supports 32-bit addressing. 16.1.1.32 offset c8h: remaplimit ? remap limit address register note: this register should not be enabled since the ia-32 core only supports 32-bit addressing. table 16-33. offset c6h: remapbas e - remap base address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: c6h c7h size: 16 bit default: 03ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 : 00 remapbase remap base address bits [35:26]: the value in this register defines the lower boundary of the remap window. the remap window is inclusive of this address. in the decoder a[25:0] of the remap base address are assumed to be 0s. thus the bottom of the defined memory range is aligned to a 64 mbyte boundary. when the value in this register is greater than the value programmed into the remap limit register, the remap window is disabled. this field defaults to 3ff. 3ffh rw table 16-34. offset c8h: remaplimit ? remap limit address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: c8h c9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 : 00 remaplimit remap limit address bits [35:26]: the value in this register defines the upper boundary of the remap window. the remap window is inclusive of this address. in the decoder a[25:00] of the remap limit address are assumed to be fs. thus the top of the defined range is one less than a 64 mbyte boundary. when the value in this register is less than the value programmed into the remap base register, the remap window is disabled. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 417 intel ? ep80579 integrated processor 16.1.1.33 offset cah: remapoffset - remap offset register this register contains the difference between the remapbase and tolm.note: this register should not be enabled since the ia-32 core only supports 32-bit addressing. 16.1.1.34 offset cch: tom - top of memory register this register contains the effective size of memory. the value in this register hides any dimms that can?t be directly addressed. bios determines the memory size reported to the os using this register. table 16-35. offset cah: remapoffset - remap offset register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: cah cbh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 : 00 remapoffst remap offset: this register contains the difference between the remapbase and tolm. this register value corresponds to address bits 35:26. it is used to translate the physical fsb address to the system memory address for accesses to the remap region. 000h rw table 16-36. offset cch: tom - top of memory register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: cch cdh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 9 reserved reserved 00h 08 : 00 tom top of memory: this register reflects the effective size of memory. these bits correspond to address bits 35:27. (128 mbyte granularity) bits 26:00 are assumed to be 0. 000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 418 order number: 320066-003us 16.1.1.35 offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register configuration software reads this register to determine where the 256 mbyte range of addresses resides for this particular host bridge. this register contains the base address of enhanced configuration memory. 16.1.1.36 offset d8h: cachectl0 - write cache control 0 register table 16-37. offset ceh: hecbase - pci express port a (pea) enhanced configuration base address register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: ceh cfh size: 16 bit default: e000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 12 hecbase pea enhanced configuration base: this register contains the address that corresponds to bits 31 to 28 of the base address for pea enhanced configuration space below 4 gbyte. configuration software reads this register to determine where the 256 mbyte range of addresses resides for this particular host bridge. bios needs to write this register at boot time. settings 0 and f are not valid. when any byte or combination of bytes of this register is written, the register value locks down and cannot be further updated. 1110b rwo 11 : 00 reserved reserved. 000h table 16-38. offset d8h: cachectl0 - write cache control 0 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: d8h d8h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved reserved for other customer visible features. 00h ro 00 wcflush write cache flush: 0 = cleared by hardware when flush is complete. 1 = all entries in the write cache are flushed to dram with high priority. the arbiter no longer accepts requests until the write cache has been flushed. software can poll this bit to determine when the flush is complete. 0b rws
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 419 intel ? ep80579 integrated processor 16.1.1.37 offset deh: skpd - scratchpad data register 16.1.1.38 offset f6h: imch_tst2 - imch test byte 2 register table 16-39. offset deh: skpd - scratchpad data register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: deh dfh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 scrtch scratchpad: these bits are simply read/write storage bits that have no effect on the imch functionality. bios typically programs this register to the revision id of the memory reference code. 0000h rw table 16-40. offset f6h: imch_tst2 - imch test byte 2 register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: f6h f6h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved 0b 06 sysmmren system memory mmr enable: 0 = this bar is hardwired to all zeros (effectively disabling this memory space). 1 = the sm memory mapped register space and corresponding base address register (b:d:f:r 0,0,0,14h) is visible. section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? 0b rw 05 nsimmren nsi mmr enable: 0 = the nsi memory mapped register space is disabled, and does not claim any memory. (the nsibar register is still read/write accessible.) 1 = the nsi memory mapped register space is visible, and memory mapped accesses are claimed and decoded appropriately. (b:d:f:r 0,0,0,4ch) section 16.1.1.12, ?offset 4ch: nsibar - root complex block address register? 0b rw 04 reserved reserved. 0b 03 reserved reserved 0b 02 reserved reserved 0b 01 reserved reserved 0b 00 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 420 order number: 320066-003us 16.1.1.39 offset 60h: drb[0-3] ? dram row [3:0] boundary register dram row boundary register defines the upper boundary address for each dram row with a granularity of 64mb. each row has its own single byte drb register. the value in a given drb corresponds to the cumulative memory size including that row. for example, a value of 1 (0000 0001) in drb0 (address lines 33 to 26) indicates that 64 mbytes of dram has been populated in the first row. drb0 = total memory in row0 (64 mbyte increments) drb1 = total memory in row0 + row1 (64 mbyte increments) drb2 = total memory in row0 + row1 + row2 (64 mbyte increments) drb3 = total memory in row0 + row1+ row2 + row3 (64 mbyte increments) the functionality of drb3 is somewhat different than drb[2:0]. in order to avoid a 64mbyte ?hole? at the top of memory, a value of 0x00 in drb3, is interpreted as 0x100. in practice, this 0x00 value should not be set, since it implies addressing more memory than the ep80579 supported. note: the memory controller does not implement any hardware checks to prevent accesses to dram locations beyond what is populated in the drb3 register. such accesses are software programming errors and will result in unreliable operation. ta b l e 1 6 - 4 1 shows the drbx to dimm mapping. please note that before populating the dimm?s, all limitation described in section 11.3.1, ?rules for populating dimm slots? need to be followed. rules for programming the drbx registers: ? drb1 and drb3 are unused and reserved. ? drb1 and drb3 should be programmed to be the same value as what was programmed in the even row. (drb1 = drb0, drb3 = drb2). ? unpopulated rows must be programmed with a value of the last populated slot. this guarantees the unpopulated row will not be selected. ? depending upon the configuration and amount of memory populated in each row, drb0 and drb2 should be programmed. this will correspond to on the ep80579, cs0# and cs1#. ? single rank, 1 dimm system programs drb0 with the encoding for memory capacity in row 0. further, drb1 = drb2 = drb3 = drb0. ? single ranks in a 2 dimm system programs drb0 with the encoding for memory capacity in row 0 and drb2 with the encoding for memory capacity in row 0 + row 1 + row 2. further, drb1 = drb0 and drb3 = drb2. table 16-41. drb to dimm designation even row odd row row/drb number address or drb row/drb number address or drb dimm0 drb0 60h drb2 62h dimm1 drb2 62h na na
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 421 intel ? ep80579 integrated processor ? single dimm with dual ranks should program drb0 with the encoding for memory capacity in row 0 and drb2 with the encoding for memory capacity in row 0 + row 1 + row 2. further, drb1 = drb0 and drb3 = drb2. ? it must always be the case with the ep80579 memory controller that for single rank, 1 dimm systems, drb0 = drb1 = drb2 = drb3 and for all other configurations, drb0 = drb1 < drb2 = drb3. table 11-7, ?supported rank configurations in single and dual dimm mode? on page 293 shows the mapping of the chip selects in the different legal rank populations on the ep80579. note: drb0=dram row 0, drb1=dram row 1, etc. 16.1.1.40 offset 70h: dra[0-1] ? dram row [0:1] attribute register the dram row attribute register defines the dram technology. dra is used to calculate the address mapping for column and row addresses as a function of dram technology specified in the dtype, dw and dimmtech fields. ? dra0 describes characteristics of rows 0 (even) and 1 (odd). ? dra1 describes characteristics of rows 2 (even) and 3 (odd). ? due to the rules of the ep80579 ddr configuration, many fields of dra0 and dra1 are not meaningful (they exist only for backward compatibility). for most configurations, the values in dra0[dw_even] and dra0[dimmtech_even] are used. an exception is dra1[dimmtech_even] which is used to select the size of the devices on the second dimm of a two dimm system. see ta b l e 1 6 - 4 3 for details. ? bit fields that are not valid because the rank (or row) is not populated should not be changed. for such fields the reset value should be the benign state. ? the controller determines which of rows are populated after decoding the drb registers. please see section 16.1.1.39, ?offset 60h: drb[0-3] ? dram row [3:0] boundary register? for more details. note: all fields of the dra[1:0] register need to be consistent or else unreliable operation will occur. for example the value programmed in nc_odd should be consistent with the dimmtech_odd field. the number of columns depends on the device technology. table 16-42. offset 60h: drb[0-3] - dram row [3:0] boundary register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 60h at 1h 60h at 1h size: 8 bit default: ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 dram_rba dram row boundary address: this 8 bit value defines the upper address for each row of dram rows. this 8 bit value is compared against a set of address lines to determine the upper address limit of a particular row. this field corresponds to bits 33:26of the system address. nffh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 422 order number: 320066-003us table 16-43. dra[1:0] field selection case dra0 [dtype_ msb] address value used for dimmtech value used for num_column /num_row value used for dw value used for dtype 1 dimm, single rank 0 (single rank) any address up to drb0 limit dra0 [dimmtech_ev en] dra0 [nc_even/ nr_even] dra0 [dw_even] dra0 [dtype] 1 dimm, dual rank 1 (dual rank) any address up to drb0 limit dra0 [dimmtech_ev en] dra0 [nc_even/ nr_even] dra0 [dw_even] dra0 [dtype] 1 (dual rank) any address between drb0 and drb2 limit dra0 [dimmtech_ev en] dra0 [nc_even/ nr_even] dra0 [dw_even] dra0 [dtype] 2 dimms, (one rank each) 0 (single rank per dimm) any address up to drb0 limit dra0 [dimmtech_ev en] dra0 [nc_even/ nr_even] dra0 [dw_even] dra0 [dtype] 0 (single rank per dimm) any address between drb0 and drb2 limit dra1 [dimmtech_ev en] dra1 [nc_even/ nr_even] dra0 [dw_even] dra0 [dtype] table 16-44. offset 70h: dra[0-1] - dram row [0:1] attribute register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 70h at 4h 73h at 4h size: 32 bit default: 00000515h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :29 nr_odd number of rows for odd numbered row. functionality and encoding is exactly the same as nr_even n 000b rw 28 :26 nc_odd number of columns for odd numbered row. functionality and encoding is exactly the same as nc_even n 000b rw 25 :23 nr_even number of rows for even numbered row: this information is used by the mbist engine. note that this field should be programmed to be consistent with the dimmtech fields of the dra register. n 000b rw 000 8192 001 16,384 010 32,768 011 65,536 others reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 423 intel ? ep80579 integrated processor 22 :20 nc_even number of columns for even numbered row. this information is used by the mbist engine. note that this field should be programmed to be consistent with the dimmtech fields of the dra register. n 000b rw 19 :18 reserved reserved n 00b ro 17 :14 dtype device type: bios sets these bits according to information read pertaining to the dimms installed bit 17: single or dual rank dimm (0=single rank per dimm) bit 16: ddr2 (0=ddr2) bit 15: 32 or 64 bit ddr populated (0=64bits) bit 14: unbuffered or registered dimm (0=unbuffered) n 0000b rw 13 :12 reserved reserved n 00b ro 11 :10 dwodd device width for odd-numbered row: functionality and encoding is exactly the same as dweven. this value should be set to exactly the same as dweven. n 01b rw 09 :06 dimmtech_od d dimm technology for odd-numbered row. functionality and encoding is exactly the same as dimmtech_even (bits 3:0) n 0100b rw 05 :04 dweven device width for even-numbered row: bios sets this bit according to the width of the ddr2 sdram devices populated in this row. this is used to determine the page size and the dqs to dq signal mapping. 00 = reserved 01 = x8 ddr2 (1 strobe pair per byte) 10 = reserved 11 = reserved n 01b rw 03 :00 dimmtech_ev en dimm technology for even-numbered row: bios sets this bit according to the density of the ddr devices populated in this row. this is used along with the device width and the dtype to determine the page size and the dqs to dq signal mapping. 0000 = reserved 0011 = 2gb dimm 0100 = 1gb dimm 0101 = 512mb dimm 0110 = 256mb dimm others - reserved n 0101b rw table 16-44. offset 70h: dra[0-1] - dram row [0:1] attribute register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 70h at 4h 73h at 4h size: 32 bit default: 00000515h power well: core bit range bit acronym bit description sticky bit reset value bit access 000 1024 001 2048 010 4096 011 8192 others reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 424 order number: 320066-003us 16.1.1.41 offset 78h: drt0 - dram timing register 0 the drt register defines the dram timing parameter. for the ep80579, there are 2 drt registers that need to be programmed ba sed on the external capabilities of the memory devices, number of ranks/dimm?s, supported ep80579 memory configurations etc. for details about the drt1 register see ?offset 64h: drt1 ? dram timing register 1? on page 431 . table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 1 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :29 btbrwta back-to-back read-write turn around: this field determines the minimum number of cmdclk on the dq bus between read-write commands. it applies to rd-wr pairs to any destinations (in same or different rows). the purpose of this bit is to control the turnaround time on the dq bus. the encoding below will be translated by the hardware into a number of cmdclk?s that will be inserted between read write commands. n 001b rw encoding command clocks per frequency 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 425 intel ? ep80579 integrated processor 28 :26 btbrta back to back read turn around : this field determines the minimum number of cmdclk on the dq bus between two reads destined to different ranks. the purpose of these bits is to control the turnaround time on the dq bus. the encoding below will be translated by the hardware into a number of cmdclk?s that will be inserted between read write commands. n 001b rw 25 :23 bbwrta back to back write-read turn around : this field determines the minimum number of cmdclk on the dq bus between write-read commands. the purpose of these 3 bits are to control the turnaround time on the dq bus. the encoding below will be translated by the hardware into a number of cmdclk?s that will be inserted between read write commands. command clocks apart based on the following encoding: n 000b rw table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 2 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding command clocks per frequency 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 encoding command clocks per frequency 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 426 order number: 320066-003us 22 :20 trrd row delay: the required row delay period between two activate commands accessing the same cs of a dimm in tck cycles. jedec recommendation for this parameter is based on the device width. x8 devices = 7.5ns n 010b rw 19 :17 twr write recovery delay: the required write recovery delay before being able to issue a precharge to the same page accessing the same cs/bank of a dimm in tck cycles. jedec recommendation for this parameter is 15ns min. n 101b rw table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 3 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding number of cmdclk delays 000 no delay 001 1 010 2 011 3 100 4 101 5 110 6 111 7 encoding number of cmdclk delays 000 2 001 3 010 4 011 5 100 6 101 7 110 8 111 9
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 427 intel ? ep80579 integrated processor 16 :12 trc this bit controls the number of dram clocks to enforce as the ras cycle time. n 01101b rw table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 4 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding number of cmdclk delays 00000 11 00001 12 00010 13 00011 14 00100 15 00101 16 00110 17 00111 18 01000 19 01001 20 01010 21 01011 22 01100 23 01101 24 01110 25 01111 26 10000 27 10001 28 10010 29 others reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 428 order number: 320066-003us 11 :09 trcd dram ras# to cas# delay: this bits controls the number of clocks inserted between a row activate command and a read or write command to that row n 001b rw 8:06 trp dram ras# precharge: time: the number of clock cycles needed to terminate access (precharge) to an open row of memory, and open access (activate) to the next row. n 010b rw table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 5 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding number of cmdclk delays 000 3 001 4 010 5 011 6 others reserved encoding number of cmdclk delays 000 3 001 4 010 5 011 6 others reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 429 intel ? ep80579 integrated processor 5:03 cl cas# latency : the number of clocks between the rising edge used by drams to sample the read command and the rising edge that is used by the dram to drive read data. ddr2 jedec spec: write latency (wl) is defined by a read latency (rl) minus one. please refer to the ddr2 jedec spec for more details. n 000b rw table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 6 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding number of cmdclk delays 000 3 001 4 010 5 011 6 others reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 430 order number: 320066-003us 2 :00 prgrpd programmable read pointer delay: this bit field determines the read delay, which is based on both dimm topology and technology. the round trip timing budget has been estimated to be about 11.5 ns. since an encoding of ?000? means less than one command clock, the encoding values in this table refer to additional delays beyond one command clock. note that the prgrpd encoding shown below is for 4 bits. the 4 bits are formed by concatenating drt1[0] and drt0[2:0]. please refer to section 16.1.1.42 for details on the drt1 register. n 000b rw table 16-45. offset 78h: drt0 - dram timing register 0 (sheet 7 of 7) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 78h 7bh size: 32 bit default: 242ad280h power well: core bit range bit acronym bit description sticky bit reset value bit access prgrpd[3:0] encoding number of cmdclk delays drt1[0], drt0[2:0] 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 others reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 431 intel ? ep80579 integrated processor 16.1.1.42 offset 64h: drt1 ? dram timing register 1 this register controls the dram timing parameters. for details about the drt1 register see ?offset 78h: drt0 - dram timing register 0? on page 424 . table 16-46. offset 64h: drt1 - dram timing register 1 (sheet 1 of 4) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 64h 67h size: 32 bit default: 12110000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 tras (time for activation / ras active strobe): time to activate a row of a bank (minimum time bank stays open before it can be closed/precharged again) sw needs to program this parameter based on the ddr speed as shown in the table below. note however that the hw will use a different tras value when the ddr commands are generated by the mbist engine. during all other modes the controller will use the tras value programmed in this field. n 0001b rw 27 :25 trtp ras to precharge (needed to calculate read autoprecharge delay) n 001b rw ddr speed encoding # of cmd clks tra s va l u e used by mbist 400 0000 8 (40ns) 12 400 0001 9 (45ns) 12 533 0100 12 (45ns) 12 667 0111 15 (45ns) 15 800 1000 16 (40ns) 18 800 1010 18 (40ns) 18 encoding number of cmdclk delays 000 2 001 3 010 4 011 5 others reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 432 order number: 320066-003us 24 :20 tfaw 8 bank device sequential bank activation restriction : no more than 4 banks may be activated in a rolling tfaw window. converting to clocks is done by dividing tfaw(ns) by tck(ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command. this field is not valid for 4 banks device technologies like 256mb x8 and 512 x8. jedec recommendations: 1kb page size = 37.5ns 2kb page size = 50ns n 00001b rw table 16-46. offset 64h: drt1 - dram timing register 1 (sheet 2 of 4) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 64h 67h size: 32 bit default: 12110000h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding number of cmdclk delays 00000 no restriction 00001 7 00010 8 00011 9 00100 10 00101 11 00110 12 00111 13 01000 14 01001 15 01010 16 01011 17 01100 18 01101 19 01110 20 others reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 433 intel ? ep80579 integrated processor 19 :18 tccd cas to cas delay note: set tccd to 2 clock delay for burst of 4 (64 bit wide data interface) or set tccd to 4 clock delay for burst of 8 (32 bit wide data interface). n 00b rw 17 :15 twtr internal write to read command delay, at least 2 x tck and independent of operating frequency jedec recommendations for ddr2 400mts = 10ns others = 7.5ns n 010b rw 14 :13 blen burst length n 00b rw table 16-46. offset 64h: drt1 - dram timing register 1 (sheet 3 of 4) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 64h 67h size: 32 bit default: 12110000h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding number of cmdclk delays 00 2 10 4 others reserved encoding number of cmdclk delays 000 no delay 001 1 010 2 011 3 100 4 101 5 others reserved encoding burst length 00 4 (ddr2 64 bit data width) 01 8 (ddr2 32 bit data width)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 434 order number: 320066-003us 12 :12 2tor1t 2t or 1t timing on the command bus to dram devices. n0b rw 11 :04 nopcnt programmable nop insertion: number of nops will be inserted between read/write commands to slow down membist activities in the same page. up to 255 clocks nops can be programmed to insert delay between read/write commands. if nops delay is programmable less than the required dram timing, overall nop delay from command to command will not be seen. n00h rw 03 :01 btbwta back-to-back write turn around: this field determines the data bubble duration between write data bursts. it applies to wr-wr pairs to different ranks, and is only expected to be used in ddr2 mode with odt enabled in the event that odt selections must change between ranks. the purpose of this field is to control the data burst spacing on the dq bus. the encoding below will be translated by the hardware into a number of cmdclk?s that will be inserted between read write commands. n 000b rw 0 :0 prgrpd_4 bit[3] of the programmable read pointer delay field. please refer to drt0[2:0] for more details on this bit field ( section 16.1.1.41 ). n0b rw table 16-46. offset 64h: drt1 - dram timing register 1 (sheet 4 of 4) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 64h 67h size: 32 bit default: 12110000h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding timing 01t 12t encoding number of cmdclk delays 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 435 intel ? ep80579 integrated processor 16.1.1.43 offset 7ch: drc ? dram controller mode register this register controls the mode of the dram controller. table 16-47. offset 7ch: drc - dram controller mode register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 7ch 7fh size: 32 bit default: 00000002h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :31 cke1 this bit controls the value that will be driven on the cke[1] pin. note however that ckepnm bit in this csr can override and force low the state of both cke[1:0] pins regardless of the state of this bit. bios can write to this csr bit to directly control the state of the cke pin. hw will update the state of this bit based on self-refresh exit command. 0 drive cke[1] low, de-activates dram devices 1 drive cke[1] asserted, activates dram devices y0b rw 30 30 cke0 this bit controls the value that will be driven on the cke[0] pin. note however that ckepnm bit in this csr can override and force low the state of both cke[1:0] pins regardless of the state of this bit. bios can write to this csr bit to directly control the state of the cke pin. hw will update the state of this bit based on self-refresh exit command. 0 drive cke[0] low, de-activates dram devices 1 drive cke[0] asserted, activates dram devices y0b rw 29 29 ic 0 = initialization complete: this bit is used for communication of software state between the memory controller and the bios. dram interface has not been initialized. 1 = dram interface has been initialized. n0b rw 28 :22 reserved reserved n 0000000b ro 21 :20 ddim dram data integrity mode: these bits select dram data integrity modes. when in non-ecc mode no ecc correction is done and no ecc errors are logged in the ferr/nerr registers. 00 non-ecc mode 01 ecc enabled 10 reserved 11 reserved n 00b rw 19 :14 reserved reserved n 0b ro 13 hlddis command/address hold disable disabling hold will allow the address and bank address pins to revert to all zeros during idle cycles. when hlddis is clear, the addresses retain the value of the last non-idle command cycle in order to reduce switching on the bus. 0 = disabled, 1 enabled y0b rw 12 cadis ddr command/address pin output disable: this bit controls address, bank address, cas, ras, we. 0 = enabled 1 = disabled y0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 436 order number: 320066-003us 11 :10 csdis ddr chip select output disable bit[11] = cs[1] bit[10] = cs[0] 0 = enabled 1 = disabled y 00b rw 9 9 reserved reserved n 0b ro 7 8 reserved_2 reserved_rw_sticky y 00b rw 06 :05 odtdis dram odt disable: bit[5] = odt[0] bit[6] = odt[1] 0 = enables the use of odt when running 1 = disables (tristates) the use of odt when running y 00b rw 04 04 ckepnm cke pin mode: 0 = force low. forces the state of cke[1:0] low. when this bit is cleared it over-rides all functionality that drives the cke pin and forces it low. sw needs to set this bit for normal operation 1 = enable cke[1:0]. bios will set this bit to a 1 for normal operating mode. y0b rw 3:0 ds the pll only supports one update of ratio (the lower nibble of this register). this register defaults to ddr2-400 this field reflects bios selection of ddr speed, which may have been ?down-binned? due to fuse settings (see sdrc.fusespeed) y 0010b rwo table 16-47. offset 7ch: drc - dram controller mode register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 7ch 7fh size: 32 bit default: 00000002h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding ddr data speed (mt/s) ddr cmd freq (mhz) 0x10 400 200 default 0x00 533 266 0111 667 333 0101 800 400 others reserve d
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 437 intel ? ep80579 integrated processor 16.1.1.44 offset 84h: eccdiag ? ecc detection/correction diagnostic register the mempen bit of this register controls if the memory controller poisons write data to the dram when it detects a parity error on its interface. by default, this bit is clear and the memory controller will not poison the write data to dram when it detects a parity error on its interface. if mempen is set, and a write transaction with bad parity is sent to memory controller from either imch or aioc, the write to ddr will be poisoned as follows: each bit of ecc will be flipped from the value otherwise calculated for that data write, based on the ?bad? data sent from either imch or aioc. table 16-48. offset 84h: eccdiag - ecc detection/correction diagnostic register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :21 reserved reserved n 000b ro 20 20 feccdt flip ecc on all data transfers: flip the designated ecc bits (bits 15:00) on all data transfers to dram. if a cacheline is in progress when this register is written, wait until the start of the next cacheline to flip parity bits. note that if feccdt and mempen is set and a bad parity is detected, the m_unit will poison and flip the ecc bits. n0b rw 19 19 reserved reserved n 0b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 438 order number: 320066-003us 18 18 mempen memory poison enable: allows for propagation of data errors not initiated by this feature to dram. error injection via bit 20 is possible regardless of this bit setting. the setting of this bit has no effect on the reporting or logging of data errors. 0 = error poisoning is disabled, data errors are not propagated, meaning that only good ecc is generated ecc mode even when bad parity is detected on its interface. 1 = error poisoning enabled when in ecc mode. the memory controller will poison the write data to dram when it detects a parity error on its interface. n0b rw 17 :16 dprsl data pair selector: this two-bit field selects which pair of quad-words in a cache line the inversion vector is applied against. regardless of what operational mode the memory subsystem is in, this field always applies to the same qw pair. qw0 corresponds to data bits 63:00, qw1 to [127:64] ? and qw7 corresponds to [511:448] 00 qw0 and qw1 01 qw2 and qw3 10 qw4 and qw5 11 qw6 and qw7 n 00b rw 15 : 00 eccbin ecc bit invert vector: this vector operates individually for every ecc bit in the selected high or low ecc block, during writes to dram. for all k between 0 and 15, when bit (k) set to 1, the value of the k ecc bit (which corresponds with the k data byte lane) is inverted. otherwise, the value the k ecc bit is not affected. in other words, bits 15:08 are applied to the ecc vector of the high qword in the selected pair, and bits 07:00 are applied to the ecc vector of the low qword in the selected pair. for example: data pair selector bits 17:16 = 00 ecc bit invert vector bits 15:08 are applied to the ecc vector for qw1 ecc bit invert vector bits 07:00 are applied to the ecc vector for qw0 n 0000h rw table 16-48. offset 84h: eccdiag - ecc detection/correction diagnostic register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 439 intel ? ep80579 integrated processor 16.1.1.45 offset 88h: sdrc ? ddr sdram secondary control register this register is used or setting memory controller parameters such as queue depths, scheduler parameters, arbiter parameters, aioc and ia-32 core stream enabling, ia-32 core parity checking, bank remapping, etc. table 16-49. offset 88h: sdrc - ddr sdram secondary control register (sheet 1 of 3) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 88h 8bh size: 32 bit default: 00000002h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :30 odtzena1 on die termination enable: these bits enable the ep80579 on die termination. odt control for the dq[71:64]/dqs[8] (ecc byte) buffers on the inbound read path. y 00b rw 29 :28 odtzena on die termination enable: these bits enable the ep80579 on die termination. odt for the dq[63:0]/dqs[7:0] buffers on the inbound read path y 00b rw 27 :26 reserved reserved y 00b 25 22 reserved reserved n 0x0b rw 21 :20 fusespeed fuse speed - read only copy of the ddr speed fuse setting 00b - ddr-800 mts 01b - ddr-667 mts 10b - ddr-533 mts 11b - ddr-400 mts nfuse ro encoding odt 00 disabled 01 60 ohms 10 120 ohms others reserved encoding odt 00 disabled 01 60 ohms 10 120 ohms others reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 440 order number: 320066-003us 19 :17 drrirr demand scrub retry (drr) injection rate regulator: this field determines the minimum rate at which drrs will be scheduled to the dram. if multiple drr?s are pending in the mc, they will be issued to the dram spaced apart by at least drrirr by the hardware. 000b - 4 ddr controller clock cycles (default) others - reserved the only supported/validated value is 000b. note: this feature should not be confused with ded retry feature that is not support by the ep80579. n 000b rw 16 16 ddrdis demand scrub retry (drr) disable: this bit by default is set to 0 to enable the demand scrub retry feature. when enabled any demand scrub writes that do not get scheduled to dram will be retried. when this bit is set, demand scrubs that are dropped will not be retried. note: this feature should not be confused with ded retry feature that is not support by the ep80579. n0b rw 15 :12 sch_wgt controls for weighted round robin scheduling when both ia and aioc requests are posted for accessing the same bank. selects the number of ia transfers consecutively selected instead of aioc transfers when requests are posted from both, and from the same bank. works in conjunction with eight 2 bit counter, one for each bank, which indicates how many ia transfers, from each bank, have been selected since the last aioc transfer was selected form that bank. xx00 = choose aioc command if aioc and ia are both present, and the last 1 command selected was ia. if no ia commands are present, choose aioc and reset 2 bit bank count of ia transfers for the selected bank. xx01 = choose aioc command if aioc and ia are both present, and the last 2 commands selected were ia. if no ia commands are present, choose aioc and reset 2 bit bank count of ia transfers for the selected bank xx11 = choose aioc command if aioc and ia are both present, and the last 3 commands selected were ia. if no ia commands are present, choose aioc and reset 2 bit bank count of ia transfers for the selected bank otherwise = reserved n 0000b rw 11 mu_enable_aio ccmd enable scheduler to pass aioc transfers to ddr n 0b rw 10 mu_enable_bc md enable scheduler to pass imch transfers to ddr n 0b rw 09 mu_enable_ecc rrwcmd enable scheduler to pass internally generated demand scrubs (upon detection of single bit ecc error) transfers to ddr. please also refer sdrc.ddrdis for the demand scrub retry feature. in order to ensure that no demand scrubs are dropped, the drr feature should be enabled. n0b rw 08 mu_enable_bsc rubcmd enable scheduler to pass internally generated background scrub transfers to ddr n0b rw table 16-49. offset 88h: sdrc - ddr sdram secondary control register (sheet 2 of 3) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 88h 8bh size: 32 bit default: 00000002h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 441 intel ? ep80579 integrated processor 16.1.1.46 offset 8ch: ckdis ? ck/ck# clock disable register this register is used to enable or disable the ck/ck# pins to the dimms. this feature is intended to reduce emi and power consumption due to clocks toggling to dimms that are not populated. 07 : 00 asu_cmdqsiz e size of command queue available to asu the scheduler implements a shared command queue which is nominally 64 entries deep. this queue is shared between asu and ia traffic. in order to reserve some queue entries for ia commands only, software is able to set an upper limit on the number of asu commands that can occupy this queue. if the number of asu commands exceeds this programmed value, subsequent aioc commands may be backed off by the memory controller, until asu commands drain to ddr, and the number in the command queue, once again, falls below the programmed value. recommended value is 0x30. do not set this field to 0. n 00000010b rw table 16-49. offset 88h: sdrc - ddr sdram secondary control register (sheet 3 of 3) description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 88h 8bh size: 32 bit default: 00000002h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-50. offset 8ch: ckdis - ck/ck# clock disable register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 8ch 8ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 7 :06 reserved reserved n 00b ro 05 :00 ckdis ck/ck# disable (sticky) each bit corresponds to a pair of ck pins. default is enabled. 0 = enable ck signals 1 = disable ck signals. when disabled, the ck/ck# signals are tristated. bit 5: enable/disable ck[5]/ck#[5] bit 4: enable/disable ck[4]/ck#[4] bit 3: enable/disable ck[3]/ck#[3] bit 2: enable/disable ck[2]/ck#[2] bit 1: enable/disable ck[1]/ck#[1] bit 0: enable/disable ck[0]/ck#[0] y 000000b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 442 order number: 320066-003us 16.1.1.47 offset 8dh: ckedis - cke clock disable register this register is used to enable or disable the cke pins to the dimms. also see section 16.1.1.43, ?offset 7ch: drc ? dram controller mode register? csr that describes the ckepnm bit that can force the cke[1:0] pins low. table 16-51. offset 8dh: ckedis - cke clock enable register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 8dh 8dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 7 :03 reserved reserved n 00000b ro 02 02 cke1dis cke1 disable (sticky) bit corresponds cke[1] pin. default is enabled. 1 = disable cke[1] signals 0 = enable cke[1] signals. when disabled, the cke[1] pin is tristated. y0b rw 01 01 reserved reserved n 0b ro 00 00 cke0dis cke0 disable (sticky) bit controls cke[0] pin. default is enabled. 1 = disable cke[0] signals 0 = enable cke[0] signals. when disabled, the cke[0] pin is tristated. y0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 443 intel ? ep80579 integrated processor 16.1.1.48 offset 90h: sparectl - spare control register this register is used to set the prescale values for the leaky bucket error counting mechanism. 16.1.1.49 offset b0h: ddr2odtc - ddr2 odt control register the ddr2odtc controls the behavior of the odt[1:0] output pins. the odt pins control the on-die termination on the ddr dram devices. (to control the odt behavior on the ep80579 please refer to section 11.4.3, ?on-die termination (odtz) on the ep80579? .) the ddr2odtc control register provides separate fields to control the odt pin behavior for each of the four possible active cases: read to rank0, read to rank1, write to rank0, and write to rank1. each field is two bits wide as there are two odt pins on the ep80579. please refer the different odt configurations that the ep80579 supports as shown in figure 11-4, ?odt timing on back-to-back reads to different slots? on page 300 and figure 11-5, ?odt timing on back-to-back writes to different slots? on page 301 . table 16-52. offset 90h: sparectl - spare control register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: 90h 93h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 dedepv ded error prescale value: prescale value ranges from 0- 255. y 00h rw 23 :16 secepv sec error prescale value: prescale value ranges from 0- 255. y 00h rw 15 :12 dedepu ded error prescale unit: 0000 never 0001 1 s 0010 1 ms 0011 1 s 0100 1 minute 0101 1 hour 0110 1 day 0111 1 week 1xxx never y 0000b rw 11 :08 secepu sec error prescale unit: 0000 never 0001 1 s 0010 1 ms 0011 1 s 0100 1 minute 0101 1 hour 0110 1 day 0111 1 week 1xxx never y 0000b rw 07 :00 reserved reserved n 00h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 444 order number: 320066-003us table 16-53. offset b0h: ddr2odtc - ddr2 odt control register description: view: pci bar: configuration bus:device:function: 0:0:0 offset start: offset end: b0h b3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :14 reserved reserved n 0000h ro 13 12 r1odtwr r1odtwr: value for logical odt[1:0] for the case of write access to logical rank 1. n 00b rw 11 10 reserved reserved n 00b ro 98 r1odtrd r1odtrd:value for logical odt[1:0] for the case of read access to logical rank 1. n 00b rw 7 6 reserved reserved n 00b ro 54 r0odtwr r0odtwr. value for logical odt[1:0] for the case of write access to logical rank 0. n 00b rw 32 reserved n 00b ro 10 r0odtrd r0odtrd. value for logical odt[1:0] for the case of read access to logical rank 0. n 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 445 intel ? ep80579 integrated processor 16.2 dram controller error reporting registers: bus 0, device 0, function 1 the dram controller error reporting registers are in bus 0, device 0, function 1. table 16-54 provides the register address map for this device and function. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 16-54. bus 0, device 0, function 1: summary of imch error reporting pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 447 8086h 02h 03h ?offset 02h: did - device identification register? on page 447 5021h 04h 05h ?offset 04h: pcicmd - pci command register? on page 448 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 448 0000h 08h 08h ?offset 08h: rid - revision identification register? on page 449 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 449 00h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 449 ffh 0dh 0dh ?offset 0dh: mlt - master latency timer register? on page 450 00h 0eh 0eh ?offset 0eh: hdr - header type register? on page 450 00h 2ch 2dh ?offset 2ch: svid - subsystem vendor identification register? on page 450 0000h 2eh 2fh ?offset 2eh: sid - subsystem identification register? on page 451 0000h 40h 43h ?offset 40h: global_ferr - global first error register? on page 451 00000000h 44h 47h ?offset 44h: global_nerr - global next error register? on page 453 00000000h 48h 4bh ?offset 48h: nsi_ferr - nsi first error register? on page 454 00000000h 4ch 4fh ?offset 4ch: nsi_nerr - nsi next error register? on page 457 00000000h 50h 53h ?offset 50h: nsi_scicmd - nsi sci command register? on page 459 00000000h 54h 57h ?offset 54h: nsi_smicmd: nsi smi command register? on page 461 00000000h 58h 5bh ?offset 58h: nsi_serrcmd - nsi serr command register? on page 464 00000000h 5ch 5fh ?offset 5ch: nsi_mcerrcmd - nsi mcerr command register? on page 466 00000000h 60h 61h ?offset 60h: fsb_ferr - fsb first error register? on page 468 0000h 62h 63h ?offset 62h: fsb_nerr - fsb next error register? on page 469 0000h 64h 65h ?offset 64h: fsb_emask - fsb error mask register? on page 470 0009h 68h 69h ?offset 68h: fsb_scicmd - fsb sci command register? on page 471 0000h 6ah 6bh ?offset 6ah: fsb_smicmd - fsb smi command register? on page 472 0000h 6ch 6dh ?offset 6ch: fsb_serrcmd - fsb serr command register? on page 473 0000h 6eh 6fh ?offset 6eh: fsb_mcerrcmd - fsb mcerr command register? on page 474 0000h 70h 70h ?offset 70h: buf_ferr - memory buffer first error register? on page 475 00h 72h 72h ?offset 72h: buf_nerr - memory buffer next error register? on page 475 00h 74h 74h ?offset 74h: buf_emask - memory buffer error mask register? on page 476 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 446 order number: 320066-003us 78h 78h ?offset 78h: buf_scicmd - memory buffer sci command register? on page 477 00h 7ah 7ah ?offset 7ah: buf_smicmd - memory buffer smi command register? on page 478 00h 7ch 7ch ?offset 7ch: buf_serrcmd - memory buffer serr command register? on page 479 00h 7eh 7eh ?offset 7eh: buf_mcerrcmd - memory buffer mcerr command register? on page 480 00h e4h e7h ?offset e4h: nsierrinjctl - nsi error injection control register? on page 481 00040000h e8h ebh ?offset e8h: berrinjctl - buffer error injection control register? on page 482 00000000h 80h 81h ?offset 80h: dram_ferr - dram first error register? on page 483 0000h 82h 83h ?offset 82h: dram_nerr - dram next error register? on page 484 0000h 84h 84h ?offset 84h: dram_emask - dram error mask register? on page 486 00h 88h 88h ?offset 88h: dram_scicmd - dram sci command register? on page 487 00h 8ah 8ah ?offset 8ah: dram_smicmd - dram smi command register? on page 488 00h 8ch 8ch ?offset 8ch: dram_serrcmd - dram serr command register? on page 489 00h 8eh 8eh ?offset 8eh: dram_mcerrcmd - dram mcerr command register? on page 490 00h 98h 99h ?offset 98h: thresh_sec0 - rank 0 sec error threshold register? on page 491 0000h 9ah 9bh ?offset 9ah: thresh_sec1 - rank 1 sec error threshold register? on page 491 0000h a0h a3h ?offset a0h: dram_secf_add - dram first single bit error correct address register? on page 492 00000000h a4h a7h ?offset a4h: dram_ded_add - dram double bit error address register? on page 492 00000000h a8h abh ?offset a8h: dram_scrb_add - dram scrub error address register? on page 493 00000000h b0h b1h ?offset b0h: dram_sec_r0 - dram rank 0 sec error counter register? on page 494 0000h b2h b3h ?offset b2h: dram_ded_r0 - dram rank 0 ded error counter register? on page 494 0000h b4h b5h ?offset b4h: dram_sec_r1 - dram rank 1 sec error counter register? on page 494 0000h b6h b7h ?offset b6h: dram_ded_r1 - dram rank 1 ded error counter register? on page 495 0000h c2h c3h ?offset c2h: thresh_ded - ded error threshold register? on page 495 0000h c4h c5h ?offset c4h: dram_secf_syndrome - dram first single error correct syndrome register? on page 496 0000h c6h c7h ?offset c6h: dram_secn_syndrome - dram next single error correct syndrome register? on page 496 0000h c8h cbh ?offset c8h: dram_secn_add - dram next single bit error correct address register? on page 497 00000000h dch ddh ?offset dch: rankthrex - rank error threshold exceeded register? on page 498 0000h ech efh ?offset ech: derrinjctl - dram error injection control register? on page 499 00000000h table 16-54. bus 0, device 0, function 1: summary of imch error reporting pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 447 intel ? ep80579 integrated processor 16.2.1 register details 16.2.1.1 offset 00h: vid - vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. 16.2.1.2 offset 02h: did - device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. table 16-55. offset 00h: vid - vendor identification register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel 8086h. 8086h ro table 16-56. offset 02h: did - device identification register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 02h 03h size: 16 bit default: 5021h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the imch host-bridge function 1. 5021h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 448 order number: 320066-003us 16.2.1.3 offset 04h: pcicmd - pci command register since imch device 0 does not physically reside on pci_a (internal bus) many of the bits are not implemented. 16.2.1.4 offset 06h: pcists - pci status register pcists is a 16-bit status register that repo rts the occurrence of error events on device 0?s pci interface. table 16-57. offset 04h: pcicmd - pci command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved 00h 08 serre serr enable: this bit is a global enable bit for device 0 serr messaging. 0 = disable, serr message is not generated by the imch for device 0, function 1. 1 = the imch is enabled to generate serr messages over the nsi for specific device 0, function 1 error conditions that are individually enabled in the errcmd registers. the imch communicates the serr condition by sending a do_serr message over nsi to the iich. if this bit is set to a 1, the imch is enabled to generate serr messages over nsi for specific device 0, func tion 1 error conditions that are individually enabled in the nsi_serrcmd, fsb_serrcmd, buf_serrcmd, and dram_serrcmd registers. the error status is reported in the pcists register as well as the corresponding ferr/nerr registers. note: reporting via serr for detected parity error which is essentially nsi poisoned tlp?s, can also be reported through by the device 0, function 0. 0b rw 07 : 00 reserved reserved 0b table 16-58. offset 06h: pcists - pci status register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 06h 07h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0b 14 sse signaled system error: 0 = serr is not generated by imch device 0, function 1 1 = imch device 0 function 1 generated a serr message over nsi for any enabled device 0, function 1 error condition. software clears this bit by writing a 1 to the bit location. 0b rwc 13 : 00 reserved reserved 000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 449 intel ? ep80579 integrated processor 16.2.1.5 offset 08h: rid - revision identification register this register contains the revision number of the imch device 0. 16.2.1.6 offset 0ah: subc - sub-class code register 16.2.1.7 offset 0bh: bcc - base class code register table 16-59. offset 08h: rid - revision identification register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the imch device 0. variable ro table 16-60. offset 0ah: subc - sub-class code register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 0ah 0ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 subc sub-class code: this value indicates the sub class code into which the imch falls. 00h = bridge 00h ro table 16-61. offset 0bh: bcc - base class code register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 0bh 0bh size: 8 bit default: ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 basec base class code: this value indicates the base class code for the imch device 0, function 1. ffh = a 'non-defined' device. since this function is used for error conditions, it does no t fall into any other class. ffh ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 450 order number: 320066-003us 16.2.1.8 offset 0dh: mlt - master latency timer register device 0 in the imch is not a pci master so this register is not implemented. 16.2.1.9 offset 0eh: hdr - header type register 16.2.1.10 offset 2ch: svid - subsystem vendor identification register this value is used to identify the vendor of the subsystem. table 16-62. offset 0dh: mlt - master latency timer register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 reserved reserved 00h table 16-63. offset 0eh: hdr - header type register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header: this value indicates the header type for the imch device 0. 00h = imch is a multi-function device with a standard header layout. 00h ro table 16-64. offset 2ch: svid - subsystem vendor identification register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subvid subsystem vendor id: this field must be programmed during boot-up to indicate the vendor of the system board. 0000h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 451 intel ? ep80579 integrated processor 16.2.1.11 offset 2eh: sid - subsystem identification register this value is used to identify a particular subsystem. 16.2.1.12 offset 40h: global_ferr - global first error register this register is used to log various error conditions at the ?unit? level. these bits are ?sticky? through reset, and are set regard less of whether or not any error messages (sci, smi, serr#, mcerr#) are enabled and generated at the unit level. specific error conditions within the various functional units are logged in the unit-specific error registers that follow. this register captures the first global fatal and the first global non-fatal errors. for these global error registers, a non-fatal error can be either an uncorrectable error which is non-fatal, or a correctable error. any future errors (next errors) are captured in the global_nerr register. no further error bits in this register are set until the existing error bit is cleared. note: if multiple errors are reported in the same clock as the first error, all errors are latched. table 16-65. offset 2eh: sid - subsystem identification register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subid subsystem id: this field must be programmed during bios initialization. 0000h rwo table 16-66. offset 40h: global_ferr - global first error register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 40h 43h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 28 reserved reserved 0b 27 dram_fe dram controller channel fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal dram i/f error. 1 = the imch detected a fatal dram interface error. y0b rwc 26 fsb_fe host (fsb) fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal fsb error. 1 = the imch detected a fatal fsb error. y0b rwc 25 nsi_fe nsi fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal nsi error. 1 = the imch detected a fatal nsi error. y0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 452 order number: 320066-003us 24 dma_fe dma controller fatal error device 1 fatal error (edma): this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal dma controller error. 1 = the imch detected a fatal dma controller error. y0b 23 pa_fe pci express* port a(0) fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal pci express port a error. 1 = the imch detected a fatal pci express port a(0) error. y0b rwc 22 pa1_fe pci express port a1 fatal error this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal pci express port a1 error. 1 = the imch detected a fatal pci express port a1 error. y0b rwc 21 : 15 reserved reserved 0b 14 buff_nfe buffer unit detected non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal buffer error. 1 = the imch detected a non-fatal buffer error. y0b rwc 13 dram_nfe dram controller non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal dram controller error. 1 = the imch detected a non-fatal dram controller error. y0b rwc 12 fsb_nfe fsb non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal fsb error. 1 = the imch detected a non-fatal fsb error. y0b rwc 11 nsi_nfe nsi non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal nsi error. 1 = the imch detected a non-fatal nsi error. y0b rwc 10 dma_nfe dma controller non-fatal error device 1 non-fatal error (edma): this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal dma controller error. 1 = the imch detected a non-fatal dma controller error. y0b 09 pa_nfe pci express port a(0) non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal pci express port a error. 1 = the imch detected a non-fatal pci express port a error. y0b rwc 08 pa1_nfe pci express port a1 non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal pci express port a1 error. 1 = the imch detected a non-fatal pci express port a1 error. y0b rwc 07 : 00 reserved reserved 00h table 16-66. offset 40h: global_ferr - global first error register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 40h 43h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 453 intel ? ep80579 integrated processor 16.2.1.13 offset 44h: global_nerr - global next error register the bit definitions are defined for global_ferr. table 16-67. offset 44h: global_nerr - global next error register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 44h 47h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 28 reserved reserved 0b 27 dram_fe dram controller channel fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal dram i/f error. 1 = the imch detected a fatal dram interface error. y0b rwc 26 fsb_fe host (fsb) fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal fsb error. 1 = the imch detected a fatal fsb error. y0b rwc 25 nsi_fe nsi fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal nsi error. 1 = the imch detected a fatal nsi error. y0b rwc 24 dma_fe dma controller fatal error device 1 fatal error (edma): this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal dma controller error. 1 = the imch detected a fatal dma controller error. y0b 23 pa_fe pci express* port a(0) fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal pci express port a error. 1 = the imch detected a fatal pci express port a(0) error. y0b rwc 22 pa1_fe pci express port a1 fatal error this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fatal pci express port a1 error. 1 = the imch detected a fatal pci express port a1 error. y0b rwc 21 : 15 reserved reserved 0b 14 buff_nfe buffer unit detected non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal buffer error. 1 = the imch detected a non-fatal buffer error. y0b rwc 13 dram_nfe dram controller non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal dram controller error. 1 = the imch detected a non-fatal dram controller error. y0b rwc 12 fsb_nfe fsb non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal fsb error. 1 = the imch detected a non-fatal fsb error. y0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 454 order number: 320066-003us 16.2.1.14 offset 48h: nsi_ferr - nsi first error register nsi errors for nsi port to iich. these errors include errors detected on the nsi link, errors from the nsi hierarchy, and errors internal to the nsi unit. 11 nsi_nfe nsi non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal nsi error. 1 = the imch detected a non-fatal nsi error. y0b rwc 10 dma_nfe dma controller non-fatal error device 1 non-fatal error (edma): this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal dma controller error. 1 = the imch detected a non-fatal dma controller error. y0b 09 pa_nfe pci express port a(0) non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal pci express port a error. 1 = the imch detected a non-fatal pci express port a error. y0b rwc 08 pa1_nfe pci express port a1 non-fatal error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no non-fatal pci express port a1 error. 1 = the imch detected a non-fatal pci express port a1 error. y0b rwc 07 : 00 reserved reserved 0b table 16-67. offset 44h: global_nerr - global next error register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 44h 47h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-68. offset 48h: nsi_ferr - nsi first error register (sheet 1 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 48h 4bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 reserved reserved 0b 29 ur unsupported request: this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = unsupported request detected. 0b rwc 28 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 455 intel ? ep80579 integrated processor 27 mtlp malformed tlp status: malformed tlp errors include: data payload length issues, byte enable rule violations, and various other illegal field settings. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = malformed tlp detected. 0b rwc 26 rovf receiver overflow status: imch checks for overflows on the following upstream queues: posted, non-posted, and completion. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = receiver overflow detected. 0b rwc 25 uec unexpected completion status: this bit is set when the device receives a completion which does not correspond to any of the outstanding requests issued by that device. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = unexpected completion detected. 0b rwc 24 ca completer abort status: if a request received violates the specific programming model of this device, but is otherwise legal, this bit is set. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = completer abort detected. 0b rwc 23 ct completion timeout status: the completion timeout timer must expire if a request is not completed in 50 ms, but must not expire earlier than 50 s. when the timer expires, this bit is set. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = completion timeout detected. y0b rwc 22 reserved reserved 0b 21 ptlp poisoned tlp status: this bit when set indicates that some portion of the tlp data payload was corrupt. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = poisoned tlp detected. 0b rwc 20 reserved reserved 0b 19 dlpe data link protocol error status: this bit is set when an ack/nak received does not specify the sequence number of an unacknowledged tlp, or of the most recently acknowledged tlp. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = data link protocol error detected. 0b rwc 18 : 16 reserved reserved 0b 15 rtto replay timer timeout status: the replay timer counts time since the last ack or nak dllp was received. when the timer expires, this bit is set. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = replay timer timeout detected. y0b rwc 14 reserved reserved 0b table 16-68. offset 48h: nsi_ferr - nsi first error register (sheet 2 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 48h 4bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 456 order number: 320066-003us 13 rnro replay_num rollover status: a 2-bit counter counts the number of times the retry buffer has been retransmitted. when this counter rolls over, this bit is set. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = replay_num rollover detected. y0b rwc 12 bdllp bad dllp status: this bit is set when the calculated dllp crc is not equal to the received value. also included are 8b/10b errors within the tlp including wrong disparity. an invalid sequence number also sets this bit. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = bad dllp detected. y0b rwc 11 btlp bad tlp status: 0 = the calculated tlp crc is equal to the received value. 1 = the calculated tlp crc is not equal to the received value. also included are 8b/10b errors within the tlp including wrong disparity, and invalid sequence numbers. y0b rwc 10 reserved reserved 0b 09 rcvre receiver error status: data is delivered over pci express via packets built out of 8b/10b symbols. this error is set for problems with the packet framing around these symbols or with symbols received outside of recognized packets. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = receiver error detected. y0b rwc 08 reserved reserved 0b 07 femr fatal error message received: 0 = no fatal error message received over the nsi link. 1 = fatal error message received over the nsi link. 0b rwc 06 nemr non-fatal error message received: non-fatal error message received over the nsi link. 0 = no non-fatal error message received over the nsi link. 1 = non-fatal error message received over the nsi link. 0b rwc 05 cemr correctable error message received: correctable error message received over the nsi link. 0 = no correctable error message received over the nsi link. 1 = correctable error message received over the nsi link. 0b rwc 04 : 03 reserved reserved 0b 02 ped parity error detected during parity conversion from ctb: parity error detected on data received from the core. 0 = no parity error detected on data received from the core. 1 = parity error detected on data received from the core. 0b rwc 01 reserved reserved 0b 00 ld link down: 0 = link has not transitioned from dl_up to dl_down. 1 = link transitioned from dl_up to dl_down. 0b rwc table 16-68. offset 48h: nsi_ferr - nsi first error register (sheet 3 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 48h 4bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 457 intel ? ep80579 integrated processor 16.2.1.15 offset 4ch: nsi_nerr - nsi next error register errors that are detected after the first error are captured by this register. table 16-69. offset 4ch: nsi_nerr - nsi next error register (sheet 1 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 4ch 4fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 reserved reserved 0b 29 ur unsupported request: this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = unsupported request detected. 0b rwc 28 reserved reserved 0b 27 mtlp malformed tlp status: malformed tlp errors include: data payload length issues, byte enable rule violations, and various other illegal field settings. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = malformed tlp detected. 0b rwc 26 rovf receiver overflow status: imch checks for overflows on the following upstream queues: posted, non-posted, and completion. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = receiver overflow detected. 0b rwc 25 uec unexpected completion status: this bit is set when the device receives a completion which does not correspond to any of the outstanding requests issued by that device. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = unexpected completion detected. 0b rwc 24 ca completer abort status: if a request received violates the specific programming model of this device, but is otherwise legal, this bit is set. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = completer abort detected. 0b rwc 23 ct completion timeout status: the completion timeout timer must expire if a request is not completed in 50 ms, but must not expire earlier than 50 s. when the timer expires, this bit is set. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = completion timeout detected. 0b rwc 22 reserved reserved 0b 21 ptlp poisoned tlp status: this bit when set indicates that some portion of the tlp data payload was corrupt. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = poisoned tlp detected. 0b rwc 20 reserved reserved 0b 19 dlpe data link protocol error status: this bit is set when an ack/nak received does not specify the sequence number of an unacknowledged tlp, or of the most recently acknowledged tlp. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = data link protocol error detected. 0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 458 order number: 320066-003us 18 : 16 reserved reserved 0b 15 rtto replay timer timeout status: the replay timer counts time since the last ack or nak dllp was received. when the timer expires, this bit is set. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = replay timer timeout detected. y0b rwc 14 reserved reserved 0b 13 rnro replay_num rollover status: a 2-bit counter counts the number of times the retry buffer has been retransmitted. when this counter rolls over, this bit is set. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = replay_num rollover detected. y0b rwc 12 bdllp bad dllp status: this bit is set when the calculated dllp crc is not equal to the received value. also included are 8b/10b errors within the tlp including wrong disparity. an invalid sequence number also sets this bit. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1= bad dllp detected. y0b rwc 11 btlp bad tlp status: 0 = the calculated tlp crc is equal to the received value. 1 = the calculated tlp crc is not equal to the received value. also included are 8b/10b errors within the tlp including wrong disparity, and invalid sequence numbers. y0b rwc 10 reserved reserved 0b 09 rcvre receiver error status: data is delivered over pci express via packets built out of 8b/10b symbols. this error is set for problems with the packet framing around these symbols or with symbols received outside of recognized packets. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = receiver error detected. y0b rwc 08 reserved reserved 0b 07 femr fatal error message received: 0 = no fatal error message received over the nsi link. 1 = fatal error message received over the nsi link. 0b rwc 06 nemr non-fatal error message received: non-fatal error message received over the nsi link. 0 = no non-fatal error message received over the nsi link. 1 = non-fatal error message received over the nsi link. 0b rwc 05 cemr correctable error message received: correctable error message received over the nsi link. 0 = no correctable error message received over the nsi link. 1 = correctable error message received over the nsi link. 0b rwc 04 : 03 reserved reserved 0b table 16-69. offset 4ch: nsi_nerr - nsi next error register (sheet 2 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 4ch 4fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 459 intel ? ep80579 integrated processor 16.2.1.16 offset 50h: nsi_scicmd - nsi sci command register this register enables various errors to generate an sci special cycle. when an error flag is set in the ferr or nerr registers, it can generate an sci special cycle when enabled in the scicmd registers. note that one and only one message type can be enabled. 02 ped parity error detected during parity conversion from ctb: parity error detected on data received from the core. 0 = no parity error detected on data received from the core. 1 = parity error detected on data received from the core. 0b rwc 01 reserved reserved 0b 00 ld link down: 0 = link has not transitioned from dl_up to dl_down. 1 = link transitioned from dl_up to dl_down. 0b rwc table 16-69. offset 4ch: nsi_nerr - nsi next error register (sheet 3 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 4ch 4fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-70. offset 50h: nsi_scicmd - nsi sci command register (sheet 1 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 50h 53h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 reserved reserved 0b 29 ur_sci generate sci for nsi error 29: generate sci whenever bit 29 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 28 reserved reserved 0b 27 mtlp_sci generate sci for nsi error 27: generate sci whenever bit 27 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 26 rovf_sci generate sci for nsi error 26: generate sci whenever bit 26 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 25 uec_sci generate sci for nsi error 25: generate sci whenever bit 25 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 460 order number: 320066-003us 24 ca_sci generate sci for nsi error 24: generate sci whenever bit 24 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 23 ct_sci generate sci for nsi error 23: generate sci whenever bit 23 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 22 reserved reserved 0b 21 ptlp_sci generate sci for nsi error 21: generate sci whenever bit 21 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 20 reserved reserved 0b 19 dlpe_sci generate sci for nsi error 19: generate sci whenever bit 19 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 18 : 16 reserved reserved 0b 15 rtto_sci generate sci for nsi error 15: generate sci whenever bit 15 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable y0b rw 14 reserved reserved 0b 13 rnro_sci generate sci for nsi error 13: generate sci whenever bit 13 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable y0b rw 12 bdllp_sci generate sci for nsi error 12: generate sci whenever bit 12 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable y0b rw 11 btlp_sci generate sci for nsi error 11: generate sci whenever bit 11 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable y0b rw 10 reserved reserved 0b 09 rcvre_sci generate sci for nsi error 9: generate sci whenever bit 9 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable y0b rw 08 reserved reserved 0b 07 femr_sci generate sci for nsi error 7: generate sci whenever bit 7 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw table 16-70. offset 50h: nsi_scicmd - ns i sci command register (sheet 2 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 50h 53h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 461 intel ? ep80579 integrated processor 16.2.1.17 offset 54h: nsi_smicmd - nsi smi command register this register enables various errors to generate an smi nsi special cycle. when an error flag is set in the ferr or nerr registers it generates an smi nsi special cycle when enabled in the smicmd register. note that one and only one message type can be enabled. 06 nemr_sci generate sci for nsi error 6: generate sci whenever bit 6 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 05 cemr_sci generate sci for nsi error 5: generate sci whenever bit 5 of nsi _ferr or nsi _nerr is set 0 = disable 1 = enable 0b rw 04 : 03 reserved reserved 0b 02 ped_sci generate sci for nsi error 2: generate sci whenever bit 2 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 01 reserved reserved 0b 00 ld_sci generate sci for nsi error 0: generate sci whenever bit 0 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw table 16-70. offset 50h: nsi_scicmd - nsi sci command register (sheet 3 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 50h 53h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-71. offset 54h: nsi_smicmd: nsi smi command register (sheet 1 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 54h 57h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 reserved reserved 0b 29 ur_smi generate smi for nsi error 29: generate smi whenever bit 29 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 28 reserved reserved 0b 27 mtlp_smi generate smi for nsi error 27: generate smi whenever bit 27 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 462 order number: 320066-003us 26 rovf_smi generate smi for nsi error 26: generate smi whenever bit 26 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 25 uec_smi generate smi for nsi error 25: generate smi whenever bit 25 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 24 ca_smi generate smi for nsi error 24: generate smi whenever bit 24 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 23 ct_smi generate smi for nsi error 23: generate smi whenever bit 23 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 22 reserved reserved 0b 21 ptlp_smi generate smi for nsi error 21: generate smi whenever bit 21 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 20 reserved reserved 0b 19 dlpe_smi generate smi for nsi error 19: generate smi whenever bit 19 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 18 : 16 reserved reserved 0b 15 rtto_smi generate smi for nsi error 15: generate smi whenever bit 15 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 14 reserved reserved 0b 13 rnro_smi generate smi for nsi error 13: generate smi whenever bit 13 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 12 bdllp_smi generate smi for nsi error 12: generate smi whenever bit 12 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 11 btlp_smi generate smi for nsi error 11: generate smi whenever bit 11 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 10 reserved reserved 0b 09 rcvre_smi generate smi for nsi error 9: generate smi whenever bit 9 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw table 16-71. offset 54h: nsi_smicmd: nsi smi command register (sheet 2 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 54h 57h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 463 intel ? ep80579 integrated processor 08 reserved reserved 0b 07 femr_smi generate smi for nsi error 7: generate smi whenever bit 6 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 06 nemr_smi generate smi for nsi error 6: generate smi whenever bit 6 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 05 cemr_smi generate smi for nsi error 5: generate smi whenever bit 5 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 04 : 03 reserved reserved 0b 02 ped_smi generate smi for nsi error 2: generate smi whenever bit 2 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 01 reserved reserved 0b 00 ld_smi generate smi for nsi error 0: generate smi whenever bit 0 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw table 16-71. offset 54h: nsi_smicmd: nsi smi command register (sheet 3 of 3) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 54h 57h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 464 order number: 320066-003us 16.2.1.18 offset 58h: nsi_serrcmd - nsi serr command register this register enables various errors to generate an serr nsi special cycle. when an error flag is set in the ferr or nerr registers it generates an serr nsi special cycle when enabled in the serrcmd register. note that one and only one message type can be enabled. table 16-72. offset 58h: nsi_serrcmd - nsi serr command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 58h 5bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 reserved reserved 0b 29 ur_serr generate serr for nsi error 29: generate serr whenever bit 29 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 28 reserved reserved 0b 27 mtlp_serr generate serr for nsi error 27: generate serr whenever bit 27 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 26 rovf_serr generate serr for nsi error 26: generate serr whenever bit 26 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 25 uec_serr generate serr for nsi error 25: generate serr whenever bit 25 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 24 ca_serr generate serr for nsi error 24: generate serr whenever bit 24 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 23 ct_serr generate serr for nsi error 23: generate serr whenever bit 23 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 22 reserved reserved 0b 21 ptlp_serr generate serr for nsi error 21: generate serr whenever bit 21 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 20 reserved reserved 0b 19 dlpe_serr generate serr for nsi error 19: generate serr whenever bit 19 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 18 : 16 reserved reserved 0b 15 rtto_serr generate serr for nsi error 15: generate serr whenever bit 15 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 465 intel ? ep80579 integrated processor 14 reserved reserved 0b 13 rnro_serr generate serr for nsi error 13: generate serr whenever bit 13 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 12 bdllp_serr generate serr for nsi error 12: generate serr whenever bit 12 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 11 btlp_serr generate serr for nsi error 11: generate serr whenever bit 11 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 10 reserved reserved 0b 09 rcvre_serr generate serr for nsi error 9: generate serr whenever bit 9 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 08 reserved reserved 0b 07 femr_serr generate serr for nsi error 7: generate serr whenever bit 7 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 06 nemr_serr generate serr for nsi error 6: generate serr whenever bit 6 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 05 cemr_serr generate serr for nsi error 5: generate serr whenever bit 5 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 04 : 03 reserved reserved 0b 02 ped_serr generate serr for nsi error 2: generate serr whenever bit 2 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 01 reserved reserved 0b 00 ld_serr generate serr for nsi error 0: generate serr whenever bit 0 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw table 16-72. offset 58h: nsi_serrcmd - nsi serr command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 58h 5bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 466 order number: 320066-003us 16.2.1.19 offset 5ch: nsi_mcerrcmd - nsi mcerr command register this register enables various errors to generate the mcerr signal on the fsb. when an error flag is set in the ferr or nerr registers it generates a mcerr when enabled in the mcerrcmd. table 16-73. offset 5ch: nsi_mcerrcmd - ns i mcerr command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 5ch 5fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 reserved reserved 0b 29 ur_mcerr generate mcerr for nsi error 29: generate mcerr whenever bit 29 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 28 reserved reserved 0b 27 mtlp_mcerr generate mcerr for nsi error 27: generate mcerr whenever bit 27 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 26 rovf_mcerr generate mcerr for nsi error 26: generate mcerr whenever bit 26 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 25 uec_mcerr generate mcerr for nsi error 25: generate mcerr whenever bit 25 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 24 ca_mcerr generate mcerr for nsi error 24: generate mcerr whenever bit 24 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 23 ct_mcerr generate mcerr for nsi error 23: generate mcerr whenever bit 23 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 22 reserved reserved 0b 21 ptlp_mcerr generate mcerr for nsi error 21: generate mcerr whenever bit 21 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 20 reserved reserved 0b 19 dlpe_mcerr generate mcerr for nsi error 19: generate mcerr whenever bit 19 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 18 : 16 reserved reserved 0b 15 rtto_mcerr generate mcerr for nsi error 15: generate mcerr whenever bit 15 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 14 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 467 intel ? ep80579 integrated processor 13 rnro_mcerr generate mcerr for nsi error 13: generate mcerr whenever bit 13 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 12 bdllp_mcerr generate mcerr for nsi error 12: generate mcerr whenever bit 12 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 11 btlp_mcerr generate mcerr for nsi error 11: generate mcerr whenever bit 11 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 10 reserved reserved 0b 09 rcvre_mcerr generate mcerr for nsi error 9: generate mcerr whenever bit 9 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 08 reserved reserved 0b 07 femr_mcerr generate mcerr for nsi error 7: generate mcerr whenever bit 7 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 06 nemr_mcerr generate mcerr for nsi error 6: generate mcerr whenever bit 6 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 05 cemr_mcerr generate mcerr for nsi error 5: generate mcerr whenever bit 5 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 04 : 03 reserved reserved 0b 02 ped_mcerr generate mcerr for nsi error 2: generate mcerr whenever bit 2 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw 01 reserved reserved 0b 00 ld_mcerr generate mcerr for nsi error 0: generate mcerr whenever bit 0 of nsi _ferr or nsi _nerr is set. 0 = disable 1 = enable 0b rw table 16-73. offset 5ch: nsi_mcerrcmd - nsi mcerr command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 5ch 5fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 468 order number: 320066-003us 16.2.1.20 offset 60h: fsb_ferr - fsb first error register this register stores the first error related to the fsb. only one error bit is set in this register. any future errors (next errors) are set in the fsb_nerr register. no further error bits in the fsb_ferr register are set until the existing error bit is cleared. these bits are sticky through reset. software clears these bits by writing a 1 to the bit location. note: if multiple errors are reported in the same clock as the first error, all errors are latched. table 16-74. offset 60h: fsb_ferr - fsb first error register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 60h 61h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 : 06 reserved reserved 0000b rwc 05 ndlock non-dram lock error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no dram lock error detected 1 = imch detected a lock operation to memory space that did not map into dram. (non-fatal) y0b rwc 04 atom fsb address above tom/tolm: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fsb address above tom/tolm detected 1 = imch has detected an address above the top of memory and above 4 gbyte.if the system has less than 4 gbyte of dram, then unclaimed addresses between tolm and 4 gbyte are sent to nsi. (non-fatal) y0b rwc 03 reserved reserved y 0b rwc 02 fsbagl fsb address strobe glitch detected: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fsb address strobe glitch detected. 1 = imch has detected a glitch one of the fsb address strobes. (fatal) y0b rwc 01 fsbdgl fsb data strobe glitch detected: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fsb data strobe glitch detected. 1 = imch has detected a glitch one of the fsb data strobes. (fatal) y0b rwc 00 reserved reserved y 0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 469 intel ? ep80579 integrated processor 16.2.1.21 offset 62h: fsb_nerr - fsb next error register table 16-75. offset 62h: fsb_nerr - fsb next error register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 62h 63h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 06 reserved reserved 0000b rwc 05 ndlock non-dram lock error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no dram lock error detected 1 = imch detected a lock operation to memory space that did not map into dram. (non-fatal) y0b rwc 04 atom fsb address above tom/tolm: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fsb address above tom/tolm detected 1 = imch has detected an address above the top of memory and above 4 gbyte.if the system has less than 4 gbyte of dram, then unclaimed addresses between tolm and 4 gbyte are sent to nsi. (non-fatal) y0b rwc 03 reserved reserved y 0b rwc 02 fsbagl fsb address strobe glitch detected: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fsb address strobe glitch detected. 1 = imch has detected a glitch one of the fsb address strobes. (fatal) y0b rwc 01 fsbdgl fsb data strobe glitch detected: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no fsb data strobe glitch detected. 1 = imch has detected a glitch one of the fsb data strobes. (fatal) y0b rwc 00 reserved reserved y 0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 470 order number: 320066-003us 16.2.1.22 offset 64h: fsb_emask - fsb error mask register this register masks the fsb unit errors from being recognized, preventing them from being logged at the unit or global level, and no interrupt/messages are generated. these bits are sticky through reset. table 16-76. offset 64h: fsb_emask - fsb error mask register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 64h 65h size: 16 bit default: 0009h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 06 reserved reserved y 0000b rw 05 ndlockm non-dram lock error mask: this bit is sticky through reset. 0 = enable non-dram lock error detection and reporting 1 = mask non-dram lock error detection and reporting y0b rw 04 atomm fsb address above tom mask: this bit is sticky through reset. 0 = enable fsb address above tom detection and reporting 1 = mask address above tom detection and reporting y0b rw 03 reserved reserved y 1b rw 02 fsbaglm fsb address strobe glitch detected mask: this bit is sticky through reset. 0 = enable fsb address strobe glitch detection and reporting 1 = mask address strobe glitch detection and reporting y0b rw 01 fsbdglm fsb data strobe glitch detected mask: this bit is sticky through reset. 0 = enable fsb data strobe glitch detection and reporting 1 = mask data strobe glitch detection and reporting y0b rw 00 reserved reserved y 1b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 471 intel ? ep80579 integrated processor 16.2.1.23 offset 68h: fsb_scicmd - fsb sci command register this register enables various errors to generate an sci nsi special cycle. when an error flag is set in the ferr or nerr registers, it generates an sci nsi special cycle when enabled in the scicmd register. note that one and only one message type can be enabled. table 16-77. offset 68h: fsb_scicmd - fsb sci command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 68h 69h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 06 reserved reserved 0000b rw 05 ndlock_sci non-dram lock error sci enable: controls whether or not an sci is generated when bit 5 of the fsb_ferr or fsb_nerr register is set. 0 = no sci generated on non-dram lock error detection 1 = enable sci generation on non-dram lock error detection 0b rw 04 atom_sci fsb address above tom sci enable: controls whether or not an sci is generated when bit 4 of the fsb_ferr or fsb_nerr register is set. 0 = no sci generated on fsb address above tom detection 1 = enable sci generation on fsb address above tom detection 0b rw 03 reserved reserved 0b rw 02 fsbagl_sci fsb address strobe glitch detected sci enable: controls whether or not an sci is generated when bit 2 of the fsb_ferr or fsb_nerr register is set. 0 = no sci generated on fsb address strobe glitch detection 1 = enable sci generation on fsb address strobe glitch detection 0b rw 01 fsbdgl_sci fsb data strobe glitch detected sci enable: controls whether or not an sci is generated when bit 1 of the fsb_ferr or fsb_nerr register is set. 0 = no sci generated on fsb data strobe glitch detection 1 = enable sci generation on fsb data strobe glitch detection 0b rw 00 reserved reserved 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 472 order number: 320066-003us 16.2.1.24 offset 6ah: fsb_smicmd - fsb smi command register this register enables various errors to generate an smi nsi special cycle. when an error flag is set in the fsb_ferr or fsb_nerr register, it generates an smi nsi special cycle when enabled in the smicmd register. note that one and only one message type can be enabled. table 16-78. offset 6ah: fsb_smicmd - fsb smi command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 6ah 6bh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 06 reserved reserved 0000b rw 05 ndlock_smi non-dram lock error smi enable: controls whether or not an smi is generated when bit 5 of the fsb_ferr or fsb_nerr register is set. 0 = no smi generated on non-dram lock error detection 1 = enable smi generation on non-dram lock error detection 0b rw 04 atom_smi fsb address above tom smi enable: controls whether or not an smi is generated when bit 4 of the fsb_ferr or fsb_nerr register is set. 0 = no smi generated on fsb address above tom detection 1 = enable smi generation on fsb address above tom detection 0b rw 03 reserved reserved 0b rw 02 fsbagl_smi fsb address strobe glitch detected smi enable: controls whether or not an smi is generated when bit 2 of the fsb_ferr or fsb_nerr register is set. 0 = no smi generated on fsb address strobe glitch detection 1 = enable smi generation on fsb address strobe glitch detection 0b rw 01 fsbdgl_smi fsb data strobe glitch detected smi enable: controls whether or not an smi is generated when bit 1 of the fsb_ferr or fsb_nerr register is set. 0 = no smi generated on fsb data strobe glitch detection 1 = enable smi generation on fsb data strobe glitch detection 0b rw 00 reserved reserved 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 473 intel ? ep80579 integrated processor 16.2.1.25 offset 6ch: fsb_serrcmd - fsb serr command register this register enables various errors to generate an serr nsi special cycle. when an error flag is set in the fsb_ferr or fsb_nerr register, it generates an serr nsi special cycle when enabled in the serrcmd register. note that one and only one message type can be enabled. table 16-79. offset 6ch: fsb_serrcmd - fsb serr command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 6ch 6dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 06 reserved reserved 0000b rw 05 ndlock_serr non-dram lock error serr enable: controls whether or not an serr is generated when bit 5 of the fsb_ferr or fsb_nerr register is set. 0 = no serr generated on non-dram lock error detection 1 = enable serr generation on non-dram lock error detection 0b rw 04 atom_serr fsb address above tom serr enable: controls whether or not an serr is generated when bit 4 of the fsb_ferr or fsb_nerr register is set. 0 = no serr generated on fsb address above tom detection 1 = enable serr generation on fsb address above tom detection 0b rw 03 reserved reserved 0b rw 02 fsbagl_serr fsb address strobe glitch detected serr enable: controls whether or not an serr is generated when bit 2 of the fsb_ferr or fsb_nerr register is set. 0 = no serr generated on fsb address strobe glitch detection 1 = enable serr generation on fsb address strobe glitch detection 0b rw 01 fsbdgl_serr fsb data strobe glitch detected serr enable: controls whether or not an serr is generated when bit 1 of the fsb_ferr or fsb_nerr register is set. 0 = no serr generated on fsb data strobe glitch detection 1 = enable serr generation on fsb data strobe glitch detection 0b rw 00 reserved reserved 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 474 order number: 320066-003us 16.2.1.26 offset 6eh: fsb_mcerrcmd - fsb mcerr command register this register enables various errors to generate the mcerr signal on the fsb. when an error flag is set in the fsb_ferr or fsb_nerr register, it generates a mcerr# when enabled in the mcerrcmd. table 16-80. offset 6eh: fsb_mcerrcmd - fsb mcerr command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 6eh 6fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h 09 06 reserved reserved 0000b rw 05 ndlock_mcer r_n non-dram lock error mcerr# enable: controls whether or not an mcerr# is generated when bit 5 of the fsb_ferr or fsb_nerr register is set. 0 = no mcerr# generated on non-dram lock error detection 1 = enable mcerr# generation on non-dram lock error detection 0b rw 04 atom_mcerr_ n fsb address above tom mcerr# enable: controls whether or not an mcerr# is generated when bit 4 of the fsb_ferr or fsb_nerr register is set. 0 = no mcerr# generated on fsb address above tom detection 1 = enable mcerr# generation on fsb address above tom detection 0b rw 03 reserved reserved 0b rw 02 fsbagl_mcer r_n fsb address strobe glitch detected mcerr# enable: controls whether or not an mcerr# is generated when bit 2 of the fsb_ferr or fsb_nerr register is set. 0 = no mcerr# generated on fsb address strobe glitch detection 1 = enable mcerr# generation on fsb address strobe glitch detection 0b rw 01 fsbdgl_mcer r_n fsb data strobe glitch detected mcerr# enable: controls whether or not an mcerr# is generated when bit 1 of the fsb_ferr or fsb_nerr register is set. 0 = no mcerr# generated on fsb data strobe glitch detection 1 = enable mcerr# generation on fsb data strobe glitch detection 0b rw 0 reserved reserved 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 475 intel ? ep80579 integrated processor 16.2.1.27 offset 70h: buf_ferr - memory buffer first error register signals errors occurring in the memory sy stem coherent posted memory write buffer (pmwb). 16.2.1.28 offset 72h: buf_nerr - memory buffer next error register table 16-81. offset 70h: buf_ferr - memory buffer first error register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 70h 70h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 dpmwb internal dram to pmwb parity error detected: 0 = parity error not detected. 1= parity error detected when a cacheline read from dram was written to the pmwb as part of a read/modify/write operation (partial write). (non-fatal) 0b rwc 02 iopmwb internal system bus or i/o to pmwb parity error detected: 0 = parity error not detected. 1 = parity error detected on a line write to pmwb. (non- fatal) 0b rwc 01 pmwbsys internal pmwb to system bus parity error detected: 0 = parity error not detected. 1 = parity error detected on data to the system bus. (non-fatal) 0b rwc 00 pmwbd internal pmwb to dram parity error detected: 0 = parity error not detected. 1 = parity error detected when pmwb is flushed to dram. (non-fatal) 0b rwc table 16-82. offset 72h: buf_nerr - memory buffer next error register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 72h 72h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 dpmwb internal dram to pmwb parity error detected: 0 = parity error not detected. 1 = parity error detected when a cacheline read from dram was written to the pmwb as part of a read/modify/ write operation (partial write). (non-fatal) 0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 476 order number: 320066-003us 16.2.1.29 offset 74h: buf_emask - memory buffer error mask register this register masks the unit errors from being recognized. because they are not recognized, they are not logged at the unit or global level and no interrupt/messages are generated. 02 iopmwb internal system bus or i/o to pmwb parity error detected: 0 = parity error not detected. 1 = parity error detected on a line write to pmwb. (non- fatal) 0b rwc 01 pmwbsys internal pmwb to system bus parity error detected: 0 = parity error not detected. 1 = parity error detected on data to the system bus. (non-fatal) 0b rwc 00 pmwbd internal pmwb to dram parity error detected: 0 = parity error not detected. 1= parity error detected when pmwb is flushed to dram. (non-fatal) 0b rwc table 16-82. offset 72h: buf_nerr - memory buffer next error register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 72h 72h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-83. offset 74h: buf_emask - memory buffer error mask register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 74h 74h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0b 03 buf_emask03 mask error bit 03: 0 = disable mask. 1 = enable mask. 0b rw 02 buf_emask02 mask error bit 02: 0 = disable mask. 1 = enable mask. 0b rw 01 buf_emask01 mask error bit 01: 0 = disable mask. 1 = enable mask. 0b rw 00 buf_emask00 mask error bit 00: 0 = disable mask. 1 = enable mask. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 477 intel ? ep80579 integrated processor 16.2.1.30 offset 78h: buf_scicmd - memory buffer sci command register this register enables various errors to generate an sci nsi special cycle. when an error flag is set in the ferr or nerr registers, it generates an sci nsi special cycle when enabled in the scicmd registers. note that one and only one message type can be enabled. table 16-84. offset 78h: buf_scicmd - memory buffer sci command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 78h 78h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 dpmwb_sci internal dram interface to pmwb parity error sci enable: generate sci when parity error detected for dram interface to pmwb when this bit is set. 0 = disable 1 = enable 0b rw 02 iopmwb_sci internal system bus or i/o to pmwb parity error sci enable: generate sci when parity error detected for internal system bus or i/o to pmwb when this bit is set. 0 = disable 1 = enable 0b rw 01 pmwbsys_sci internal pmwb to system bus parity error sci enable: generate sci when parity error detected for pmwb to system bus when this bit is set. 0 = disable 1 = enable 0b rw 00 pmwbd_sci internal pmwb to dram i/f parity error sci enable: generate sci when parity error detected for pmwb to dram i/f when this bit is set. 0 = disable 1 = enable 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 478 order number: 320066-003us 16.2.1.31 offset 7ah: buf_smicmd - memory buffer smi command register this register enables various errors to generate an smi nsi special cycle. when an error flag is set in the ferr or nerr registers, it generates an smi nsi special cycle when enabled in the smicmd register. note that one and only one message type can be enabled. table 16-85. offset 7ah: buf_smicmd - memory buffer smi command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 7ah 7ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 dpmwb_smi internal dram interface to pmwb parity error smi enable: generate smi when parity error detected for dram interface to pmwb when this bit is set. 0 = disable 1 = enable 0b rw 02 iopmwb_smi internal system bus or i/o to pmwb parity error smi enable: generate smi when parity error detected for internal system bus or i/o to pmwb when this bit is set. 0 = disable 1 = enable 0b rw 01 pmwbsys_smi internal pmwb to system bus parity error smi enable: generate smi when parity error detected for pmwb to system bus when this bit is set. 0 = disable 1 = enable 0b rw 00 pmwbd_smi internal pmwb to dram i/f parity error smi enable: generate smi when parity error detected for pmwb to dram i/f when this bit is set. 0 = disable 1 = enable 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 479 intel ? ep80579 integrated processor 16.2.1.32 offset 7ch: buf_serrcmd - memory buffer serr command register this register enables various errors to generate an serr nsi special cycle. when an error flag is set in the ferr or nerr registers, it generates an serr nsi special cycle when enabled in the serrcmd register. note that one and only one message type can be enabled. table 16-86. offset 7ch: buf_serrcmd - memory buffer serr command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 7ch 7ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 dpmwb_serr internal dram ii/f to pmwb parity error serr enable: generate serr when parity error detected for dram i/f to pmwb when this bit is set. 0 = disable 1 = enable 0b rw 02 iopmwb_serr internal system bus or i/o to pmwb parity error serr enable: generate serr when parity error detected on write port 0 when this bit is set. 0 = disable 1 = enable 0b rw 01 pmwbsys_ser r internal pmwb to system bus parity error serr enable: generate serr when parity error detected for pmwb to system bus when this bit is set. 0 = disable 1 = enable 0b rw 00 pmwbd_serr internal pmwb to dram i/f parity error serr enable: generate serr when parity error detected for pmwb to dram i/f when this bit is set. 0 = disable 1 = enable 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 480 order number: 320066-003us 16.2.1.33 offset 7eh: buf_mcerrcmd - memory buffer mcerr command register this register enables various errors to generate a mcerr signal on the fsb. when an error flag is set in the ferr or nerr registers, it generates a mcerr when enabled in the mcerrcmd register. table 16-87. offset 7eh: buf_mcerrcmd - memory buffer mcerr command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 7eh 7eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 00h 03 dpmwb_mcer r internal dram ii/f to pmwb parity error mcerr enable: generate mcerr when parity error detected for dram i/f to pmwb when this bit is set. 0 = disable 1 = enable 0b rw 02 iopmwb_mcer r internal system bus or i/o to pmwb parity error mcerr enable: generate mcerr when parity error detected on write port 0 when this bit is set. 0 = disable 1 = enable 0b rw 01 pmwbsys_mce rr internal pmwb to system bus parity error mcerr enable: generate mcerr when parity error detected for pmwb to system bus when this bit is set. 0 = disable 1 = enable 0b rw 00 pmwbd_mcer r internal pmwb to dram i/f parity error mcerr enable: generate mcerr when parity error detected for pmwb to dram i/f when this bit is set. 0 = disable 1 = enable 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 481 intel ? ep80579 integrated processor 16.2.1.34 offset e4h: nsierrinjctl - nsi error injection control register this register controls the way in which the imch handles parity errors on the interface. 16.2.1.35 offset e8h: berrinjctl - buffer error injection control register this register enables the injection of errors on data read out of the posted write buffer. the lower 16 bits are the corresponding flip parity bits for the cacheline of data. the upper bits in the register are for the use and control of the associated flip parity bits. table 16-88. offset e4h: nsierrinjctl - nsi error injection control register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: e4h e7h size: 32 bit default: 00040000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 reserved reserved 00h 19 stpscrm stop and scream bit: this is a special control for errors going to nsi, outgoing from the imch core. 0 = outgoing data errors are propagated. 1 = outgoing data errors are reported, but not propagated. 0b rw 18 endp enable data poisoning: this bit controls whether or not the imch marks data as ?poisoned? when a parity error is detected from the nsi. 0 = error checking disabled. 1 = error checking enabled. incoming data with parity errors are marked as ?poisoned? before being sent on towards its destination. 1b rw 17 : 00 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 482 order number: 320066-003us 16.2.1.36 offset 80h: dram_ferr - dram first error register this register signals the first error occurring in the memory system. refer to section 11.5, ?error handling? to understand the error handling mechanism implemented in core. this register stores the first error related to the dram controller. typically, only one error bit is set in this register. however, in the case of multiple errors in the same cycle, multiple bits can be set in this register. no further error bits in the dram_ferr register are set until the existing error bit is cleared by software. any future errors (next errors) are set in the dram_nerr register defined in ta bl e 1 6 - 9 1 . the bits defined in this register are sticky through reset. software clears these bits by writing a 1 to the bit location. the errors in this register are reported up into the global_ferr registers as either ?fatal? or ?non-fatal? errors from the memory controller as noted in the descriptions below. note: all memory controller errors are ?not-fatal?. note: logging of these errors can be masked only by setting the corresponding bit in section 16.2.1.38, ?offset 84h: dram_emask - dram error mask register? . table 16-89. offset e8h: berrinjctl - buffer error injection control register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: e8h ebh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 19 reserved reserved 00h 18 endp enable/disable data poisoning: when = ?0? , data poisoning is disabled - when a parity error is detected it is sent to memory with good parity. an interrupt will be generated if enabled and not masked. (this is the plumas/placer model) note: this creates a race condition between when data could be used vs. reporting and responding to the interrupt. when = ?1?, data poisoning is enabled - when a parity error is detected data is sent to memory with bad parity. an interrupt will be generated if enabled and not masked. (this is the new cayuse model) note: error injection is possible regardless of this bit setting. 0b rw 17 : 00 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 483 intel ? ep80579 integrated processor table 16-90. offset 80h: dram_ferr - dram first error register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 80h 81h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :08 reserved reserved 00h ro 07 mtca memory test complete: not an error condition. this bit is set by hardware to signal bios that hardware testing of the channel is complete. this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 1 = hardware-based test of dram is complete. (non-fatal) y0b rwc 06 uerra uncorrectable error on write: (uncorrectable) this bit is set on a detected error regardless of ecc mode, even if ecc is disabled. however if the error was injected via eccdiag, this bit is not set. note that the state of the eccdiag.mempen does not impact the setting of this bit. for more details please see section 16.1.1.44, ?offset 84h: eccdiag ? ecc detection/ correction diagnostic register? . this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no parity error detected on writes to dram. 1 = parity error detected on write to dram. (non-fatal) y0b rwc 05 :04 reserved reserved 00b ro 03 etda error threshold detect: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. this bit can be set by either a sec or ded event, if the corresponding error counter is set. 0 = no error threshold detected 1 = error threshold detected. (non-fatal) y0b rwc 02 usdea uncorrectable scrubber data error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no scrubber error detected 1 = scrubber error detected. (non-fatal) y0b rwc 01 urmea uncorrectable read memory error: (uncorrectable) applies to non-scrub demand (normal demand fetch) reads. this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no uncorrectable non-scrub demand read memory error 1 = uncorrectable non-scrub demand read memory error. (non-fatal) y0b rwc 00 crmea correctable read memory error: (correctable) secs (single bit error correction) detected by normal demand requests or scrub/demand fetch (normal read to memory). this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no correctable read memory error. 1 = correctable read memory error. (non-fatal) y0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 484 order number: 320066-003us 16.2.1.37 offset 82h: dram_nerr - dram next error register this register captures the errors related to the dram controller that occur after the first error is detected and captured in dram_ferr. refer to section 11.5, ?error handling? to understand the error handling mechanism implemented in the memory controller. multiple bits can be set in this register if multiple errors occur following the first error prior to software clearing the first error register. these bits are sticky through reset. software clears these bits by writing a 1 to the bit location. the errors in this register are reported up into the global_nerr registers as either ?fatal? or ?non-fatal? errors from the memory controller as noted in the descriptions below. unlike the dram_ferr register, multiple errors are accumulated in the dram_nerr register. note: all memory controller errors are ?not-fatal?. note: logging of these errors can be masked only by setting the corresponding bit in section 16.2.1.38, ?offset 84h: dram_emask - dram error mask register? . table 16-91. offset 82h: dram_nerr - dram next error register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 82h 83h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :08 reserved reserved 00h ro 07 mtca memory test complete: not an error condition. this bit is set by hardware to signal bios that hardware testing of the channel is complete. this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 1 = hardware-based test of dram is complete. (non-fatal) y0b rwc 06 uerra uncorrectable error on write: (uncorrectable) this bit is set on a detected error regardless of ecc mode, even if ecc is disabled. however if the error was injected via eccdiag, this bit is not set. note that the state of the eccdiag.mempen does not impact the setting of this bit. for more details please see section 16.1.1.44, ?offset 84h: eccdiag ? ecc detection/ correction diagnostic register? this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no parity error detected on writes to dram. 1 = parity error detected on write to dram. (non-fatal) y0b rwc 05 :04 reserved reserved 00b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 485 intel ? ep80579 integrated processor 16.2.1.38 offset 84h: dram_emask - dram error mask register this register masks the dram controller errors and events from being recognized, preventing them from being logged at either the unit level (via the dram_ferr or dram_nerr registers, see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ) or global level (via global_ferr or global_nerr)and preventing an interrupt/messages from being generated. these bits are sticky through reset. note: if etd_mask is changed from 0 to 1 and any error count is already above threshold, then the error(s) will be immediately reported via ferr/nerr. 03 etda error threshold detect: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. this bit can be set by either a sec or ded event, if the corresponding error counter is set. the bit can also set if the dram_sec current error count register is cleared, via a software diagnostic error count write. 0 = no error threshold detected 1 = error threshold detected. (non-fatal) y0b rwc 02 usdea uncorrectable scrubber data error: this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no scrubber error detected 1 = scrubber error detected. (non-fatal) y0b rwc 01 urmea uncorrectable read memory error: (uncorrectable) applies to non-scrub demand (normal demand fetch) reads. this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no uncorrectable non-scrub demand read memory error 1 = uncorrectable non-scrub demand read memory error. (non-fatal) y0b rwc 00 crmea correctable read memory error: (correctable) secs (single bit error correction) detected by normal demand requests or scrub/demand fetch (normal read to memory). this bit is sticky through reset. system software clears this bit by writing a 1 to the location. 0 = no correctable read memory error. 1 = correctable read memory error. (non-fatal) y0b rwc table 16-91. offset 82h: dram_nerr - dram next error register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 82h 83h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 486 order number: 320066-003us 16.2.1.39 offset 88h: dram_scicmd - dram sci command register this register enables the memory controller to generate an sci nsi special cycle for various error flags. when an error flag is set in either the dram_ferr or dram_nerr registers (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ), hardware generates an sci nsi special cycle when enabled in the dram_scicmd register. note that software should enable one and only one message type for a given error flag. table 16-92. offset 84h: dram_emask - dram error mask register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 84h 84h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mtc_mask memory test complete mask: this bit is sticky through reset. 0 = allow memory test complete logging and signaling. 1 = mask memory test complete logging and signaling. mask error bits 7. y0b rw 06 uerr_mask uncorrectable error detected on write to dram mask: this bit is sticky through reset. 0 = allow poisoned write to dram detection and signaling. 1 = mask poisoned write to dram detection and signaling. mask error bit 6. y0b rw 05 :04 reserved reserved 00b rw 03 etd_mask error threshold detect mask: this bit is sticky through reset. 0 = allow error threshold detection and signaling. 1 = mask error threshold detection and signaling. mask error bit 3. y0b rw 02 sde_mask scrubber data error mask: this bit is sticky through reset. 0 = allow scrubber data error detection and signaling. 1 = mask scrubber data error detection and signaling. mask error bit 2. y0b rw 01 urme_mask uncorrectable read memory error mask: this bit is sticky through reset. 0 = allow uncorrectable memory read error detection and signaling. 1 = mask uncorrectable memory read error detection and signaling. mask error bit 1. y0b rw 00 crme_mask correctable read memory error mask: this bit is sticky through reset. 0 = allow correctable memory read error detection and signaling. 1 = mask correctable memory read error detection and signaling. mask error bit 0. y0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 487 intel ? ep80579 integrated processor 16.2.1.40 offset 8ah: dram_smicm d - dram smi command register this register enables the memory controller to generate an smi nsi special cycle for various error flags. when an error flag is set in either the dram_ferr or dram_nerr registers (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ), hardware generates an smi nsi special cycle when enabled in the dram_smicmd register. note that software should enable one and on ly one message type for a given error flag. table 16-93. offset 88h: dram_scicmd - dram sci command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 88h 88h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mtc_sci memory test complete sci enable: generate sci when bit 7 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 06 pwd_sci poisoned write to dram sci enable: generate sci when bit 6 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 05 :04 reserved reserved n 00b ro 03 etd_sci error threshold detect sci enable: generate sci when bit 3 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 02 sde_sci scrubber data error sci enable: generate sci when bit 2 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 01 urme_sci uncorrectable read memory error sci enable: generate sci when bit 1 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 00 crme_sci correctable read memory error sci enable: generate sci when bit 0 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 488 order number: 320066-003us 16.2.1.41 offset 8ch: dram_serrcmd - dram serr command register this register enables the memory controller to generate an serr nsi special cycle for various error flags. when an error flag is set in either the dram_ferr or dram_nerr registers (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ), hardware generates an serr nsi special cycle when enabled in the dram_serrcmd register. note: software should enable one and only one message type for a given error flag. table 16-94. offset 8ah: dram_smicmd - dram smi command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 8ah 8ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mtc_smi memory test complete smi enable: generate smi when bit 7 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 06 pwd_smi poisoned write to dram smi enable: generate smi when bit 6 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 05 :04 reserved reserved n 00b ro 03 etd_smi error threshold detect smi enable: generate smi when bit 3 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 02 sde_smi scrubber data error smi enable: generate smi when bit 2 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 01 urme_smi uncorrectable read memory error smi enable: generate smi when bit 1 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 00 crme_smi correctable read memory error smi enable: generate smi when bit 0 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 489 intel ? ep80579 integrated processor table 16-95. offset 8ch: dram_serrcmd - dram serr command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 8ch 8ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mtc_serr memory test complete serr enable: generate serr when bit7 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 06 pwd_serr poisoned write to dram serr enable: generate serr when bit 6 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 05 :04 reserved reserved n 00b ro 03 etd_serr error threshold detect serr enable: generate serr when bit 3 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 02 sde_serr scrubber data error serr enable: generate serr when bit2 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 01 urme_serr uncorrectable read memory error serr enable: generate serr when bit 1 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 00 crme_serr correctable read memory error serr enable: generate serr when bit 0 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 490 order number: 320066-003us 16.2.1.42 offset 8eh: dram_mcerrcmd - dram mcerr command register this register enables the memory controller to generate an mcerr# signal on the fsb for various error flags. when an error flag is set in either the dram_ferr or dram_nerr registers (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ), hardware generates an mcerr# signal on the fsb when enabled in the dram_mcerrcmd register. note that software should enable one and only one message type for a given error flag. table 16-96. offset 8eh: dram_mcerrcmd - dram mcerr command register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 8eh 8eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mtc_mcerr memory test complete mcerr# enable: generate mcerr# when bit 7 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 06 pwd_mcerr poisoned write to dram mcerr# enable: generate mcerr# when bit 6 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 05 :04 reserved reserved n 00b ro 03 etd_mcerr error threshold detect mcerr# enable: generate mcerr# when bit 3 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 02 sde_mcerr scrubber data error mcerr# enable: generate mcerr# when bit 2 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 01 urm_mcerr uncorrectable read memory errormcerr# enable: generate mcerr# when bit 1 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw 00 crm_mcerr correctable read memory error mcerr# enable: generate mcerr# when bit 0 of dram_ferr or dram_nerr is set. 0 = disable 1 = enable n0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 491 intel ? ep80579 integrated processor 16.2.1.43 offset 98h: thresh_sec0 - rank 0 sec error threshold register threshold compare value for sec errors. an error threshold detect event is signaled via bit 3 of dram_ferr or dram_nerr (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ) if the rank 0 sec counter (see section 16.2.1.48, ?offset b0h: dram_sec_r0 - dram rank 0 sec error counter register? ) exceeds the value programmed into this register. the bits in this register are sticky through reset. 16.2.1.44 offset 9ah: thresh_sec1 - rank 1 sec error threshold register threshold compare value for sec errors. an error threshold detect event is signaled via bit 3 of dram_ferr or dram_nerr (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ) if the rank 1 sec counter (see section 16.2.1.50, ?offset b4h: dram_sec_r1 - dram rank 1 sec error counter register? ) exceeds the value programmed into this register. the bits in this register are sticky through reset. table 16-97. offset 98h: thresh_sec0 - rank 0 sec error threshold register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 98h 99h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 thrsh_sec0 threshold: threshold compare value for rank 0 sec errors. y 0000h rw table 16-98. offset 9ah: thresh_sec1 - rank 1 sec error threshold register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: 9ah 9bh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 thrsh_sec1 threshold: threshold compare value for rank 1 sec errors. y 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 492 order number: 320066-003us 16.2.1.45 offset a0h: dram_secf_add - dram first single bit error correct address register captures the address of the sec error occurring in the memory system (including scrubs). the value in this register is only valid if the correctable read memory error bit in the dram_ferr register has been set. the bits in this register are sticky through reset. (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? ). 16.2.1.46 offset a4h: dram_ded_add - dram double bit error address register captures the address of the first ded (uncorrectable non-scrub engine) error occurring in the memory system. the value in this register is only valid if the uncorrectable read memory error bit in the dram_ferr register or the dram_nerr register has been set. the bits in this register are sticky through reset. table 16-99. offset a0h: dram_secf_add - dram first single bit error correct address register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved 0b ro 30 :02 fsefadd first correctable error address: this field contains system address bits 34:06 for the first correctable error (dram_ferr). this field is set by hardware, and represents a physical address. this field can only be reset by a pwrgd reset. y 0000000h ro 01 :00 reserved reserved 00b ro table 16-100.offset a4h: dram_ded_add - dram double bit error address register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: a4h a7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved 0b ro 30 :02 fuerrad first uncorrectable error address: this field contains address bits 34:06 for the first uncorrectable error. this field is set by hardware, and represents a physical address. this field is only reset by a pwrgd reset. y 0000000h ro 01 :00 reserved reserved 00b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 493 intel ? ep80579 integrated processor 16.2.1.47 offset a8h: dram_scrb_add - dram scrub error address register captures the address of the first uncorrectable error encountered by the scrub engine for a periodic memory scrub. the value in this register is only valid if the uncorrectable scrubber data error bit in the dram_ferr register or dram_nerr register has been set. the bits in this register are sticky through reset. 16.2.1.48 offset b0h: dram_sec_r0 - dram rank 0 sec error counter register counter for sec errors occurring for rank 0 in the memory system. the rank counters for sec and ded errors are implemented using a leaky bucket algorithm (see section 11.4.7, ?ddr2 mr and emr settings? ). the error count returned when this register is read is not an absolute count over time, but the sum of errors during a current specified time period plus half of the accumulated errors from past time periods. when a time period expires (determined by the spare control register, (see section 16.1.1.48, ?offset 90h: sparectl - spare control register? ), the sum of the current time period accumulated errors and a value equal to half of the past accumulated errors is retained. half of this registered error value will be added to the errors accumulated during the next time period. this method is employed, because it is not the absolute number of errors that is most interesting, but the rate that errors occur. when this register is written, the counter holding the number of errors with the current time period is updated. beca use of this described structure, reading back the register will only return the same value written if no time period has expired between the write and the read. a write to this register does clears out any error residue that may exist from past time periods. the ep80579 tracks sec and ded events on a per-rank basis within the dimms installed in the system. the bits in this register are sticky through reset. note: writing this register with a value above threshold will trigger an error. table 16-101.offset a8h: dram_scrb_add - dram scrub error address register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: a8h abh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved 0b ro 30 :02 seadd scrub error address: this field is updated when an uncorrectable error is encountered by the periodic memory scrubber and that scrub error causes the dram.ferr field to be updated, i.e. if the uncorrectable scrub error is the first error after the dram_ferr register is cleared. this field is set by hardware and represents a physical address. the mapping is dram_scrb_add[30:02] = system address[34:6]. this field is only reset to zero by a pwrgr reset. y 0000000h ro 01 :00 reserved reserved 00b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 494 order number: 320066-003us 16.2.1.49 offset b2h: dram_ded_r0 - dram rank 0 ded error counter register counter for ded errors occurring for rank 0. the functionality of this counter is as described in section 16.2.1.48, ?offset b0h: dram_sec_r0 - dram rank 0 sec error counter register? but applies to ded errors. the bits in this register are sticky through reset. 16.2.1.50 offset b4h: dram_sec_r1 - dram rank 1 sec error counter register counter for sec errors occurring for rank 1. the functionality of this counter is described in section 16.2.1.48, ?offset b0h: dram_sec_r0 - dram rank 0 sec error counter register? . the bits in this register are sticky through reset. table 16-102.offset b0h: dram_sec_r0 - dram rank 0 sec error counter register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: b0h b1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 sec_dr0a count of correctable errors occurring in memory: rank 0sec count. y 0000h rw table 16-103.offset b2h: dram_ded_r0 - dram rank 0 ded error counter register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: b2h b3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 ded_dr0a count of uncorrectable errors occurring in memory: rank 0ded count. y 0000h rw table 16-104.offset b4h: dram_sec_r1 - dram rank 1 sec error counter register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: b4h b5h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 sec_r1 count of correctable errors occurring in memory: rank 1sec count. y 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 495 intel ? ep80579 integrated processor 16.2.1.51 offset b6h: dram_ded_r1 - dram rank 1 ded error counter register counter for ded errors occurring for rank 1. the functionality of this counter is as described in section 16.2.1.48, ?offset b0h: dram_sec_r0 - dram rank 0 sec error counter register? but applies to ded errors. the bits in this register are sticky through reset. 16.2.1.52 offset c2h: thresh_ded - ded error threshold register this register is the threshold compare value for ded errors. an error threshold detect is signaled via bit 3 of dram_ferr or dram_nerr (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? and section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ) if either of the ded event counters dram_ded_r0 or dram_ded_r1 (see section 16.2.1.49, ?offset b2h: dram_ded_r0 - dram rank 0 ded error counter register? or section 16.2.1.51, ?offset b6h: dram_ded_r1 - dram rank 1 ded error counter register? ) exceeds the value programmed into this register. the bits in this register are sticky through reset. the rankthrex register preserves knowledge of threshold exceeded events for software (see section 16.2.1.56, ?offset dch: rankthrex - rank error threshold exceeded register? on page 497 ). table 16-105.offset b6h: dram_ded_r1 - dram rank 1 ded error counter register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: b6h b7h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 ded_r1 count of uncorrectable errors occurring in memory: rank 1ded count. y 0000h rw table 16-106.offset c2h: thresh_ded - ded error threshold register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: c2h c3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 thrsh_ded ded error threshold: threshold compare value for ded errors. y 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 496 order number: 320066-003us 16.2.1.53 offset c4h: dram_secf_syndrome - dram first single error correct syndrome register syndrome for correctable errors occurring in the memory system. the contents of this register are set when correctable error bit (bit 0) is set in the dram_ferr register (see section 16.2.1.36, ?offset 80h: dram_ferr - dram first error register? ). syndrome is always logged for qw0/1 or qw2/3 pairs (block), if transferring the lower half of the cache line, and logged for qw4/5 or qw6/7 if transferring the upper half of the cache line. ecc is checked ? cacheline at a time. the syndrome logged in this register is for the lowest ordered qw pair. for example: if both qw0/1 and qw2/3 have correctable errors, the syndrome stored is for qw0/1. a syndrome indicates error when it is a non- zero value. the bits in this register are sticky through reset. 16.2.1.54 offset c6h: dram_secn_syndrome - dram next single error correct syndrome register syndrome for next correctable error occurring in the memory system. the contents of this register are set when correctable error bi t (bit 0) is set in the dram_nerr register (see section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ). the bits in this register are sticky through reset. table 16-107.offset c4h: dram_secf_syndrome - dram first single error correct syndrome register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: c4h c5h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 secf_synd ecc syndrome for dram_ferr correctable error : because only hardware writes to this register, it is read- only. sec mode bits 15:00 mem channel y 0000h ro table 16-108.offset c6h: dram_secn_syndrome - dram next single error correct syndrome register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: c6h c7h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 secn_synd ecc syndrome for dram_nerr correctable error indicated by dram nerr register: because only hardware writes to this register, it is read-only. details are in section 16.2.1.53 . y 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 497 intel ? ep80579 integrated processor 16.2.1.55 offset c8h: dram_secn_add - dram next single bit error correct address register captures the address of the next sec error (either normal or scrub read) occurring in the memory system. the value in this register is only valid if the correctable read memory error bit(bit 0) in the dram_nerr register (see section 16.2.1.37, ?offset 82h: dram_nerr - dram next error register? ) has been set. the bits in this register are sticky through reset. 16.2.1.56 offset dch: rankthrex - rank error threshold exceeded register preserves knowledge of dimm error thresholds exceeded on a per-rank basis. software writes bits individually to 1 to clear them. hardware sets these bits when the count of sec or ded errors transitions from being less than or equal to the defined threshold value (see the threshold registers such as section 16.2.1.52, ?offset c2h: thresh_ded - ded error threshold register? on page 495 ) to being greater than the threshold value for a particular rank. this threshold exceeded bit is cleared by software and is only rearmed once the threshold is not exceeded. in other words, if the threshold count has been exceeded and the count is still greater than the threshold, then when software clears a given indicator bit, this same bit is not automatically set again until rearmed by the time decay of the error count and the threshold exceeded event occurs again. the bits in this register are sticky through reset. table 16-109.offset c8h: dram_secn_add - dram next single bit error correct address register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: c8h cbh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved 0b ro 30 :02 retradd next correctable error address: this field contains system address bits 35:12 for the next correctable error. this field is set by hardware when the correctable read memory error bit in the dram_serr register is set. this value represents a physical address. this field can only be reset by a pwrgd reset. y 0000000h ro 01 :00 reserved reserved 0b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 498 order number: 320066-003us table 16-110.offset dch: rankthrex - rank error threshold exceeded register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: dch ddh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :06 reserved reserved 000h ro 05 rank1_ded rank 1 ded threshold exceeded: rank 1 ded threshold status. this bit is sticky through reset. software can clear this bit by writing a 1 to the bit location. 0 = threshold not exceeded 1 = threshold exceeded y0b rwc 04 rank0_ded rank 0 ded threshold exceeded: rank 0 ded threshold status. this bit is sticky through reset. software can clear this bit by writing a 1 to the bit location. 0 = threshold not exceeded 1 = threshold exceeded y0b rwc 03 :02 reserved reserved 00b ro 01 rank1_sec rank 1 sec threshold exceeded: rank 1 sec threshold status. this bit is sticky through reset. software can clear this bit by writing a 1 to the bit location. 0 = threshold not exceeded 1 = threshold exceeded y0b rwc 00 rank0_sec rank 0 sec threshold exceeded: rank 0 sec threshold status. this bit is sticky through reset. software can clear this bit by writing a 1 to the bit location. 0 = threshold not exceeded 1 = threshold exceeded y0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 499 intel ? ep80579 integrated processor 16.2.1.57 offset ech: derrinjctl - dram error injection control register this register controls the imch handling of errors on incoming data streams into the imch core from the dram interface. this register enables the injection of parity errors on incoming data streams into the core. the lower 16 bits are the corresponding flip parity bits for the cacheline of data. the upper bits in the register are for the use and control of the associated flip parity bits. the ?flip on next data transfer (bit 16)? feature is not supported in the the memory controller. derrinjctl is used to inject parity errors into the data returned to mch during data reads. the other complementary function, eccdia g is used to inject parity errors into ddr upon data writes. table 16-111.offset ech: derrinjctl - dram error injection control register description: view: pci bar: configuration bus:device:function: 0:0:1 offset start: offset end: ech efh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :19 reserved reserved n 00h ro 18 endp enable/disable data poisoning for incoming data: this bit controls whether or not the imch marks data as ?poisoned? when a parity error is detected on incoming data from the dram i/f. 0 = errors are not propagated, only good internal parity generated. 1 = error poisoning enabled. incoming data with parity errors are marked as ?poisoned? before being sent on towards its destination when in either 72-bit ecc mode via the drc register. error injection is possible regardless of this bit setting. defaults to disabled. n0b rw 17 flipadt enable/disable parity bits: flip the designated parity bits (bits 15:00) on all data transfers into the core. if a cacheline is in progress when this register is written, wait until the start of the next cacheline to flip parity bits. n0b rw 16 reserved reserved n 0b ro 15 :00 flipbits two bits of parity for each 64bits of data . 16 bits of parity for a cacheline. if the parity error injection is enabled, via setting endp and flipadt, the parity bits sent back to mch along with the cache line read data will be exclusive-or?ed with the value in this flipbits register n 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 500 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 501 intel ? ep80579 integrated processor 16.3 edma registers: bus 0, device 1, function 0 the edma registers are in bus 0, device 0, function 1. table 16-112 provides the register address map for this device and function. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. table 16-112.bus 0, device 1, function 0: summary of edma pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 502 8086h 02h 03h ?offset 02h: did - device identification register? on page 502 5023h 04h 05h ?offset 04h: pcicmd - pci command register? on page 503 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 504 0010h 08h 08h ?offset 08h: rid - revision identification register? on page 504 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 505 80h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 505 08h 0eh 0eh ?offset 0eh: hdr - header type register? on page 505 00h 10h 13h ?offset 10h: edmalbar - edma low base address register? on page 506 00000000h 2ch 2dh ?offset 2ch: svid - subsystem vendor identification register? on page 506 0000h 2eh 2fh ?offset 2eh: sid - subsystem identification register? on page 507 0000h 34h 34h ?offset 34h: capptr - capabilities pointer register? on page 507 b0h 3ch 3ch ?offset 3ch: intrline - interrupt line register? on page 507 00h 3dh 3dh ?offset 3dh: intrpin - interrupt pin register? on page 508 01h 40h 40h ?offset 40h: edmactl - edma control register? on page 508 08h 80h 83h ?offset 80h: edma_ferr - edma first error register? on page 509 00000000h 84h 87h ?offset 84h: edma_nerr - edma next error register? on page 511 00000000h 88h 88h ?offset 88h: edma_emask - edma error mask register? on page 513 00h a0h a0h ?offset a0h: edma_scicmd - edma sci command register? on page 514 00h a4h a4h ?offset a4h: edma_smicmd - edma smi command register? on page 515 00h a8h a8h ?offset a8h: edma_serrcmd - edma serr command register? on page 516 00h ach ach ?offset ach: edma_mcerrcmd - edma mcerr command register? on page 517 00h b0h b3h ?offset b0h: msicr - msi control register? on page 518 00020005h b4h b7h ?offset b4h: msiar - msi address register? on page 519 fee00000h b8h b9h ?offset b8h: msidr - msi data register? on page 520 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 502 order number: 320066-003us 16.3.1 register details 16.3.1.1 offset 00h: vid - vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies a pci device. 16.3.1.2 offset 02h: did - device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. table 16-113.offset 00h: vid - vendor identification register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel 8086h. 8086h ro table 16-114.offset 02h: did - device identification register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 02h 03h size: 16 bit default: 5023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the imch edma controller function 0. 5023h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 503 intel ? ep80579 integrated processor 16.3.1.3 offset 04h: pcicmd - pci command register table 16-115.offset 04h: pcicmd - pci command register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 00h 10 intxad intx assertion disable: controls the ability of a device to generate intx interrupt messages. this bit only applies to legacy interrupts and not msis. 0 = devices are permitted to generate intx interrupt messages. 1 = devices are prevented from generating intx interrupt messages. 0b rw 09 fb2b fast back-to-back enable: not applicable-hardwired to 0. 0b ro 08 serre serr enable: this bit is a global enable bit for device 1 serr messaging. the dma does not have an serr# signal. the dma communicates the serr condition by sending an serr message. 0 = disable. serr message is not generated for device 1. 1 = enable. generate serr messages for specific device 1 error conditions that are individually enabled in the edma_serrcmd register. the error status is reported in the edma_ferr, edma_nerr and pcists registers. note: this bit only controls serr messaging for device 1. devices 0 and 2 ? 7 have their own serr bits to control error reporting for error conditions occurring on their respective devices. the control bits are used in a logical or manner to enable the serr hi message mechanism 0b rw 07 : 02 reserved reserved 00h 01 mae memory access enable: 0 = device 1 memory space is disabled enable access to the edma controller low base address register 0b rw 00 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 504 order number: 320066-003us 16.3.1.4 offset 06h: pcists - pci status register 16.3.1.5 offset 08h: rid - revision identification register this register contains the revision number of device 1. table 16-116.offset 06h: pcists - pci status register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0b 14 sse signaled system error: 0 = device 1 has not generated a serr. software clears this bit by writing a 1 to the bit location. 1 = indicates device 1 generated an serr message for any enabled device 2 error condition. device 1 error conditions are enabled in the pcicmd and edma_serrcmd registers. device 1 error flags are read/reset from the pcists, edma_ferr, or edma_nerr registers. 0b rwc 13 : 05 reserved reserved 000h 04 clist capability list: this bit is set to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offset 34h. 1b ro 03 intx ntx status: indicates that an intx interrupt is pending internal to the device. the interrupt assertion disable bit has no affect on the setting of this bit. this bit is not set for an msi. 0 = an intx interrupt is not pending 1 = an intx interrupt is pending internal to the device 0b ro 02 : 00 reserved reserved 0h table 16-117.offset 08h: rid - revision identification register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this is an 8-bit value that indicates the revision identification number for device 1. this number must always be the same as the rid for device 0, function 0. variable ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 505 intel ? ep80579 integrated processor 16.3.1.6 offset 0ah: subc - sub-class code register 16.3.1.7 offset 0bh: bcc - base class code register 16.3.1.8 offset 0eh: hdr - header type register table 16-118.offset 0ah: subc - sub-class code register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 0ah 0ah size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 subc sub-class code: this is an 8-bit value that indicates the category of other (non-specific) system peripheral. 80h ro table 16-119.offset 0bh: bcc - base class code register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 0bh 0bh size: 8 bit default: 08h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 basec base class code: this is an 8-bit value that indicates the base class code for a system peripheral. 08h ro table 16-120.offset 0eh: hdr - header type register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header: this value indicates the header type of the imch device 1. 00h = single-function device. 00h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 506 order number: 320066-003us 16.3.1.9 offset 10h: edmalbar - edma low base address register 16.3.1.10 offset 2ch: svid - subsystem vendor identification register this value is used to identify the vendor of the subsystem. 16.3.1.11 offset 2eh: sid - subsystem identification register this value is used to identify a particular subsystem. table 16-121.offset 10h: edmalbar - edma low base address register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 upbits upper programmable base address: these bits are part of the system memory mmr region, normally set by configuration software to locate the base address of the region. 00000h rw 11 : 04 lowbits lower bits: these bits are hardwired to 0. this forces the size of the memory region to be 4 kbyte. 000h ro 03 pf prefetchable: this bit is hardwired to 0 to indicate that the system memory mmr region is non-prefetchable. 0b ro 02 : 01 type addressing type: these bits determine the addressing type and they are hardwired to 00 to indicate that the address range defined by the upper bits of this register can be located anywhere in the 32-bit address space as per the pci specification for base address registers. 00b ro 00 mspace memory space indicator: this bit is hardwired to 0 to identify the mmr range as a memory range as per the specification for pci base address registers. 0b ro table 16-122.offset 2ch: svid - subsystem vendor identification register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subvid subsystem vendor id: this field must be programmed during boot-up to indicate the vendor of the system board. when any byte or combination of bytes of this register is written, the register value locks and cannot be further updated. 0000h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 507 intel ? ep80579 integrated processor 16.3.1.12 offset 34h: capptr - capabilities pointer register the capptr provides the offset that is the pointer to the location where the first set of capabilities registers is located. 16.3.1.13 offset 3ch: intrline - interrupt line register table 16-123.offset 2eh: sid - subsystem identification register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subid subsystem id: this field must be programmed during bios initialization. when any byte or combination of bytes of this register is written, the register value locks and cannot be further updated. 0000h rwo table 16-124.offset 34h: capptr - capabilities pointer register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 34h 34h size: 8 bit default: b0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cap_ptr capabilities pointer: pointer to first capabilities structure. b0h ro table 16-125.offset 3ch: intrline - interrupt line register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intrline interrupt connection: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller is connected with this device. 00h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 508 order number: 320066-003us 16.3.1.14 offset 3dh: intrpin - interrupt pin register 16.3.1.15 offset 40h: edmactl - edma control register this register defines global operation of the edma channels. 16.3.1.16 offset 80h: edma_ferr - edma first error register this register captures the first occurrence of errors on a edma channel basis. this register only designates which channel had an error. once an error has been captured for a given channel, this register is locked and needs to be written with ones to clear it. all dma errors are considered non-fatal because they cause the dma engine to stop further processing, thus avoiding any data corruption. the errors are fatal to the process, but not to the system. table 16-126.offset 3dh: intrpin - interrupt pin register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intrpin interrupt pin: set to 01h to specify that edma always uses inta# as its interrupt pin. 01h ro table 16-127.offset 40h: edmactl - edma control register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 40h 40h size: 8 bit default: 08h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 edmaen edma engine enable: 0 = edma engine is disabled. 1 = edma engine is enabled to do transfers. whether the bit is set or clear, the registers can be programmed. 0b rw 06 : 04 reserved reserved 000b ro 03 reserved this bit must be set to 1 by bios for proper operation. 1b 02 : 01 reserved reserved 00b 00 parityen disable abort on data parity error: 0 = controller aborts on data parity error 1 = controller does not abort on data parity errors, but logs the event in the appropriate edma ferr/nerr bit 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 509 intel ? ep80579 integrated processor table 16-128.offset 80h: edma_ferr - edma first error register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 80h 83h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 channel_3_ndar_ addressing_error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 3. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 30 channel_3_ndar_ alignment_error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 3. (non-fatal) y0b rwc 29 channel_3_source _address_error the source address does not comply with the source type or range for dma channel 3. (non-fatal) y0b rwc 28 reserved reserved 0b 27 channel_3_destina tion_address_error the destination address does not comply with the destination type or range for dma channel 3. (non- fatal) y0b rwc 26 reserved reserved 0b 25 channel_3_parity_ error data parity error in reading source data from system memory for dma channel 3. (non-fatal) y0b rwc 24 channel_3_write_e rror received write to ro descriptor registers for dma channel 3. (non-fatal) y0b rwc 23 channel_2_ndar_ addressing_error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 2. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 22 channel_2_ndar_ alignment_error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 2. (non-fatal) y0b rwc 21 channel_2_source _address_error the source address does not comply with the source type or range for dma channel 2. (non-fatal) y0b rwc 20 reserved reserved 0b 19 channel_2_destina tion_address_error the destination address does not comply with the destination type or range for dma channel 2. (non- fatal) y0b rwc 18 reserved reserved 0b 17 channel_2_parity_ error data parity error in reading source data from system memory for dma channel 2. (non-fatal) y0b rwc 16 channel_2_write_e rror received write to ro descriptor registers for dma channel 2. (non-fatal) y0b rwc 15 channel_1_ndar_ addressing_error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 1. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 14 channel_1_ndar_ alignment_error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 1. (non-fatal) y0b rwc 13 channel_1_source _address_error the source address does not comply with the source type or range for dma channel 1. (non-fatal) y0b rwc 12 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 510 order number: 320066-003us 16.3.1.17 offset 84h: edma_nerr - edma next error register this register captures edma channel errors after the ferr register is locked. this register accumulates all subsequent errors for the edma channels. see table 16-129 for bit definitions. 11 channel_1_destina tion_address_error the destination address does not comply with the destination type or range for dma channel 1. (non- fatal) y0b rwc 10 reserved reserved 0b 09 channel_1_parity_ error data parity error in reading source data from system memory for dma channel 1. (non-fatal) y0b rwc 08 channel_1_write_e rror received write to ro descriptor registers for dma channel 1. (non-fatal) y0b rwc 07 channel_0_ndar_ addressing_error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 0. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 06 channel_0_ndar_ alignment_error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 0. (non-fatal) y0b rwc 05 channel_0_source _address_error the source address does not comply with the source type or range for dma channel 0. (non-fatal) y0b rwc 04 reserved reserved 0b 03 channel_0_destina tion_address_error the destination address does not comply with the destination type or range for dma channel 0. (non- fatal) y0b rwc 02 reserved reserved 0b 01 channel_0_parity_ error data parity error in reading source data from system memory for dma channel 0. (non-fatal) y0b rwc 00 channel_0_write_e rror received write to ro descriptor registers for dma channel 0. (non-fatal) y0b rwc table 16-128.offset 80h: edma_ferr - edma first error register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 80h 83h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 511 intel ? ep80579 integrated processor table 16-129.offset 84h: edma_nerr - edma next error register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 channel_3_nd ar_addressing _error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 3. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 30 channel_3_nd ar_alignment_ error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 3. (non-fatal) y0b rwc 29 channel_3_sou rce_address_er ror the source address does not comply with the source type or range for dma channel 3. (non-fatal) y0b rwc 28 reserved reserved 0b 27 channel_3_des tination_addres s_error the destination address does not comply with the destination type or range for dma channel 3. (non-fatal) y0b rwc 26 reserved reserved 0b 25 channel_3_pari ty_error data parity error in reading source data from system memory for dma channel 3. (non-fatal) y0b rwc 24 channel_3_wri te_error received write to ro descriptor registers for dma channel 3. (non-fatal) y0b rwc 23 channel_2_nd ar_addressing _error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 2. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 22 channel_2_nd ar_alignmnt_e rror the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 2. (non-fatal) y0b rwc 21 channel_2_sou rce_address_er ror the source address does not comply with the source type or range for dma channel 2. (non-fatal) y0b rwc 20 reserved reserved 0b 19 channel_2_des tination_addres s_error the destination address does not comply with the destination type or range for dma channel 2. (non-fatal) y0b rwc 18 reserved reserved 0b 17 channel_2_pari ty_error data parity error in reading source data from system memory for dma channel 2. (non-fatal) y0b rwc 16 channel_2_wri te_error received write to ro descriptor registers for dma channel 2. (non-fatal) y0b rwc 15 channel_1_nd ar_addressing _error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 1. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 14 channel_1_nd ar_alignment_ error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 1. (non-fatal) y0b rwc 13 channel_1_sou rce_address_er ror the source address does not comply with the source type or range for dma channel 1. (non-fatal) y0b rwc 12 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 512 order number: 320066-003us 16.3.1.18 offset 88h: edma_emask - edma error mask register this register masks the unit errors from being recognized and therefore not logged at the unit or global level and no interrupt/messages are generated. all channels are expected to use the same reporting structure, so only one 8-bit register is implemented. 11 channel_1_des tination_addres s_error the destination address does not comply with the destination type or range for dma channel 1. (non-fatal) y0b rwc 10 reserved reserved 0b 09 channel_1_pari ty_error data parity error in reading source data from system memory for dma channel 1. (non-fatal) y0b rwc 08 channel_1_wri te_error received write to ro descriptor registers for dma channel 1. (non-fatal) y0b rwc 07 channel_0_nd ar_addressing _error the descriptor pointer in the next descriptor address register is of incorrect type or range for dma channel 0. this includes above tom, not in a memory range, and above available address space. (non-fatal) y0b rwc 06 channel_0_nd ar_alignment_ error the descriptor pointer in the next descriptor address register is not aligned to an eight double-word boundary for dma channel 0. (non-fatal) y0b rwc 05 channel_0_sou rce_address_er ror the source address does not comply with the source type or range for dma channel 0. (non-fatal) y0b rwc 04 reserved reserved 0b 03 channel_0_des tination_addres s_error the destination address does not comply with the destination type or range for dma channel 0. (non-fatal) y0b rwc 02 reserved reserved 0b 01 channel_0_pari ty_error data parity error in reading source data from system memory for dma channel 0. (non-fatal) y0b rwc 00 channel_0_wri te_error received write to ro descriptor registers for dma channel 0. (non-fatal) y0b rwc table 16-129.offset 84h: edma_nerr - edma next error register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 513 intel ? ep80579 integrated processor table 16-130.offset 88h: edma_emask - edma error mask register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: 88h 88h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 dscpem descriptor address type/range error mask: mask bit for error bit 7, 15, 23, and 31 of edma_ferr and edma_nerr. this bit is sticky through reset. 0 = allow descriptor address type/range error logging and signaling. 1 = mask descriptor address type/range error logging and signaling. y0b rw 06 dscpae descriptor address alignment error: mask bit for error bit 6, 14, 22, and 30 of edma_ferr and edma_nerr. this bit is sticky through reset. 0 = allow descriptor address alignment error logging and signaling. 1 = mask descriptor address alignment error logging and signaling. y0b rw 05 srcem source address type/range error: mask bit for error bit 5, 13, 21, and 29 of edma_ferr and edma_nerr. this bit is sticky through reset. 0 = allow source address type/range error logging and signaling. 1 = mask source address type/range error logging and signaling. y0b rw 04 reserved reserved y0b 03 destem destination address type/range error: mask bit for error bit 3, 11, 19, and 27 of edma_ferr and edma_nerr. this bit is sticky through reset. 0 = allow destination address type/range error logging and signaling. 1 = mask destination address type/range error logging and signaling. y0b rw 02 reserved reserved y0b 01 mdparerr memory data parity error: mask bit for error bit 1, 9, 17, and 25 of edma_ferr and edma_nerr. this bit is sticky through reset. 0 = allow memory data parity error logging and signaling. 1 = mask memory data parity error logging and signaling. y0b rw 00 iwerr illegal write error: mask bit for error bit 0, 8, 16, and 24 of edma_ferr and edma_nerr. this bit is sticky through reset. 0 = allow illegal write erro r logging and signaling. 1 = mask illegal write error logging and signaling. y0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 514 order number: 320066-003us 16.3.1.19 offset a0h: edma_scicmd - edma sci command register this register enables various errors to generate an sci special cycle to the iich. when an error flag is set in the edma_ferr or edma_nerr registers, it generates an serr, smi, or sci special cycle when enabled in the serrcmd, smicmd, or scicmd registers, or a mcerr# on the fsb when enabled in the mcerrcmd, respectively. note that only one message type can be enabled. all channels are expected to use the same reporting structure, so only one 8-bit register is implemented. table 16-131.offset a0h: edma_scicmd - edma sci command register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: a0h a0h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 sci_dscperr descriptor address type/range error sci enable: generate sci if bit 7, 15, 23, or 31 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 06 sci_dscpae descriptor address alignment error sci enable: generate sci if bit 6, 14, 22, or 30 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 05 sci_srcerr source address type/range error sci enable: generate sci if bit 5, 13, 21, or 29 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 04 reserved reserved 0b 03 sci_desterr destination address type/range error sci enable: generate sci if bit 3, 11, 19, or 27 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 02 reserved reserved 0b 01 sci_mdpe1 memory data parity error sci enable: generate sci if bit 1, 9, 17, or 25 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 00 sci_iwe illegal write error sci enable: generate sci if bit 0, 8, 16, or 24 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 515 intel ? ep80579 integrated processor 16.3.1.20 offset a4h: edma_smicmd - edma smi command register this register enables various errors to generate an smi special cycle to the iich. when an error flag is set in the edma_ferr or edma_nerr registers, it generates an serr, smi, or sci special cycle when enabled in the serrcmd, smicmd, or scicmd registers, or a mcerr# on the fsb when enabled in the mcerrcmd, respectively. note that only one message type can be enabled. all channels are expected to use the same reporting structure, so only one 8-bit register is implemented. table 16-132.offset a4h: edma_smicmd - edma smi command register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: a4h a4h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 smi_dscperr descriptor address type/range error smi enable: generate smi if bit 7, 15, 23, or 31 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 06 smi_dscpae descriptor address alignment error smi enable: generate smi if bit 6, 14, 22, or 30 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 05 smi_srcerr source address type/range error smi enable: generate smi if bit 5, 13, 21, or 29 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 04 reserved reserved 0b 03 smi_dsterr destination address type/range error smi enable: generate smi if bit 3, 11, 19, or 27 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 02 reserved reserved 0b 01 smi_mdpe1 memory data parity error smi enable: generate smi if bit 1, 9, 17, or 25 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 00 smi_iwe illegal write error smi enable: generate smi if bit 0, 8, 16, or 24 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 516 order number: 320066-003us 16.3.1.21 offset a8h: edma_serrcmd - edma serr command register this register enables various errors to generate an serr special cycle to the iich. when an error flag is set in the edma_ferr or edma_nerr registers, it generates an serr, smi, or sci special cycle when enabled in the serrcmd, smicmd, or scicmd registers, or a mcerr# on the fsb when enabled in the mcerrcmd, respectively. note that only one message type can be enabled. all channels are expected to use the same reporting structure, so only one 8-bit register is implemented. table 16-133.offset a8h: edma_serrcmd - edma serr command register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: a8h a8h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 serr_dscper r descriptor address type/range error serr enable: generate serr if bit 7, 15, 23, or 31 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 06 serr_dscpae descriptor address alignment error serr enable: generate serr if bit 6, 14, 22, or 30 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 05 serr_srcerr source address type/range error serr enable: generate serr if bit 5, 13, 21, or 29 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 04 reserved reserved 0b 03 serr_dsterr destination address type/range error serr enable: generate serr if bit 3, 11, 19, or 27 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 02 reserved reserved 0b 01 serr_mdpe1 memory data parity error serr enable: generate serr if bit 1, 9, 17, or 25 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 00 serr_iwe illegal write error serr enable: generate serr if bit 0, 8, 16, or 24 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 517 intel ? ep80579 integrated processor 16.3.1.22 offset ach: edma_mcerrcmd - edma mcerr command register this register enables various errors to generate the mcerr# signal on the fsb. when an error flag is set in the edma_ferr or edma_nerr registers, it generates an serr, smi, or sci special cycle when enabled in the serrcmd, smicmd, or scicmd registers, or a mcerr# on the fsb when enabled in the mcerrcmd, respectively. note that only one message type can be enabled. all channels are expected to use the same reporting structure, so only one 8-bit register is implemented. table 16-134.offset ach: edma_mcerrcmd - edma mcerr command register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: ach ach size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mcerr_n_dsc perr descriptor address type/range error mcerr# enable: generate mcerr# if bit 7, 15, 23, or 31 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 06 mcerr_n_dsc pae descriptor address alignment error mcerr# enable: generate mcerr# if bit 6, 14, 22, or 30 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 05 mcerr_n_src err source address type/range error mcerr# enable: generate mcerr# if bit 5, 13, 21 or 29 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 04 reserved reserved 0b 03 mcerr_n_dst err destination address type/range error mcerr# enable: generate mcerr# if bit 3, 11, 19, or 27 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 02 reserved reserved 0b 01 mcerr_n_mdp e1 memory data parity error mcerr# enable: generate mcerr# if bit 1, 9, 17, or 25 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw 00 mcerr_n_iwe illegal write error mcerr# enable: generate mcerr# if bit 0, 8, 16, or 24 is set in any of the edma_ferr or edma_nerr registers. 0 = disable 1 = enable 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 518 order number: 320066-003us 16.3.1.23 offset b0h: msicr - msi control register the edma controller generates an upstream interrupt message using message signaled interrupts (msi) to the processor, bypassing the ioxapic. the msi is generated by a memory write to address 0feex_xxxxh. the msi control register (msicr), msi address register (msiar) and msi data register (msidr) support this mechanism. the default values of these registers are compatible with the default value of ioxapic. system software can reprogram these values, if required. the msi control register (msicr) contains all the information related to the capability of edma msi interrupts. table 16-135.offset b0h: msicr - msi control register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: b0h b3h size: 32 bit default: 00020005h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved. 00h 23 addcpbl indicates 64-bit address capable: hardwired to 0 to indicate that the edma controller is capable of 32-bit msi addressing only. 0b ro 22 : 20 mme multiple message enable: the software writes to this field to indicate the number of allocated messages, which is aligned to a power of two. the value programmed into this field must be less than or equal to the number requested in the multiple messages capable field. when msi is enabled, the software allocates at least one message to the device. if two msi messages are enabled, message 0 is used for normal interrupts, and message 1 is used for abort/error interrupts. if only one msi message is enabled, message 0 is used for both normal and error interrupts. 0h rw 19 : 17 mmc multiple message capable: hardwired to a value of 001b to indicate that the edma requests a capability for two messages. 001b ro 16 msie msi enable: interrupts are generated for the conditions as described in the descriptor control register for each channel. if none of these conditions are selected, software must poll for status since no interrupts of either type are generated. 0 = legacy interrupts are generated. 1 = msi is generated. 0b rw 15 : 08 nxt_ptr next pointer: pointer to the next item in the capabilities list. hardwired to 00h to indicate that msi is the last item in the capabilities list. 00h ro 07 : 00 cap_id capability id: hardwired to 05h to indicate that the edma controller is msi capable. 05h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 519 intel ? ep80579 integrated processor 16.3.1.24 offset b4h: msiar - msi address register the msi address register (msiar) contains all the address related information to route msi interrupts. table 16-136.offset b4h: msiar - msi address register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: b4h b7h size: 32 bit default: fee00000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 msiadd address: most significant 12 bits of the 32-bit address. feeh rw 19 : 12 msidid destination id: should reflect the 63:56 bits of ioxapic redirection table entry. 00h rw 11 : 04 msiedid extended destination id: should reflect the 55:48 bits of ioxapic redirection table entry. 00h rw 03 rdrctid redirection hint: allows the interrupt message to be redirected. 0 = direct. message is delivered to the agent listed in bits 19:12 1 = redirect. message is delivered to an agent with a lower interrupt priority. this can be derived from bits 10:08 of the data field 0b rw 02 dstmd destination mode: used only if the redirection hint bit is set to 1. 0 = physical 1 = logical 0b rw 01 : 00 reserved reserved. 00b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 520 order number: 320066-003us 16.3.1.25 offset b8h: msidr - msi data register the msi data register (msidr) contains all the data-related information to route msi interrupts. table 16-137.offset b8h: msidr - msi data register description: view: pci bar: configuration bus:device:function: 0:1:0 offset start: offset end: b8h b9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 trgmd trigger mode: software must set this to be the same as the corresponding bit in the i/o redirection table for that interrupt. 0 = edge 1 = level 0b rw 14 dlvsts delivery status: if using edge-triggered interrupts, this is always 1, since only the assertion is sent. if using level- triggered interrupts, then this bit indicates the state of the interrupt input. 0b rw 13 : 12 reserved reserved 00b 11 dstnmd destination mode: software must set this to be the same as bit 2 of msiar. 0 = physical 1 = logical 0b rw 10 : 08 dlvmd delivery mode: software must set this to be the same as the corresponding bits in the i/o redirection table for that interrupt. 000 fixed 001 lowest priority 010 smi/pmi 011 reserved 100 nmi 101 init 110 reserved 111 extint 0h rw 07 : 00 intrptv interrupt vector: software must set this to be the same as the corresponding bits in the i/o redirection table for that interrupt. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 521 intel ? ep80579 integrated processor 16.4 pci express* port a standa rd and enhanced registers: bus 0, devices 2 and 3, function 0 bus 0, device 2, function 0 is the pci express* port a (in x8 mode) or port a0 (in x4 mode) virtual pci-to-pci bridge. the registers described here include both the standard configuration space and the enhanced configuration space (starting at offset 100h). device 3 is the pci express* port a1 virtual pci-to-pci bridge. device 2 is pci express* port a (in x8 mode) or a0 (in x4 mode). port a1?s associated pci express* link has a maximum lane width of x4. when device 2 is configured as a x8 pci express* link, device 3 is not available. the registers described here include both the standard configuration space and the enhanced configuration space (starting at offset 100h). except for the registers listed below, all registers for device 3 are exactly the same as for device 2. note: all registers are located in the core power well. note: for platforms not using pcie should also disable pci express* logic per section 9.2.1.1, ?low power sku with pci express ports removed?
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 522 order number: 320066-003us table 16-138.bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers (sheet 1 of 3) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 527 8086h 02h 03h ?offset 02h: did - device identification register? on page 527 5024h 04h 05h ?offset 04h: pcicmd - pci command register? on page 528 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 530 0010h 08h 08h ?offset 08h: rid - revision identification register? on page 531 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 532 04h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 532 06h 0ch 0ch ?offset 0ch: cls - cache line size register? on page 533 00h 0eh 0eh ?offset 0eh: hdr - header type register? on page 533 01h 18h 18h ?offset 18h: pbusn - primary bus number register? on page 534 00h 19h 19h ?offset 19h: sbusn - secondary bus number register? on page 534 00h 1ah 1ah ?offset 1ah: subusn: subordinate bus number register? on page 535 00h 1ch 1ch ?offset 1ch: iobase - i/o base address register? on page 535 f0h 1dh 1dh ?offset 1dh: iolimit - i/o limit address register? on page 536 00h 1eh 1fh ?offset 1eh: secsts - secondary status register? on page 536 0000h 20h 21h ?offset 20h: mbase - memory base address register? on page 538 fff0h 22h 23h ?offset 22h: mlimit - memory limit address register? on page 539 0000h 24h 25h ?offset 24h: pmbase - prefetchable memory base address register? on page 540 fff1h 26h 27h ?offset 26h: pmlimit - prefetchable memory limit address register? on page 540 0001h 28h 28h ?offset 28h: pmbasu - prefetchable memory base upper address register? on page 541 0fh 2ch 2ch ?offset 2ch: pmlmtu - prefetchable memory limit upper address register? on page 541 00h 34h 34h ?offset 34h: capptr - capabilities pointer register? on page 542 50h 3ch 3ch ?offset 3ch: intrline - interrupt line register? on page 542 00h 3dh 3dh ?offset 3dh: intrpin - interrupt pin register? on page 543 01h 3eh 3eh ?offset 3eh: bctrl - bridge control register? on page 543 00h 44h 44h ?offset 44h: vscmd0 - vendor specific command byte 0 register? on page 545 00h 45h 45h ?offset 45h: vscmd1 - vendor specific command byte 1 register? on page 546 00h 46h 46h ?offset 46h: vssts0 - vendor specific status byte 0 register? on page 547 00h 47h 47h ?offset 47h: vssts1 - vendor specific status byte 1 register? on page 547 00h 48h 48h ?offset 48h: vscmd2 - vendor specific command byte 2 register? on page 548 00h 50h 50h ?offset 50h: pmcapid - power management capabilities structure register? on page 548 01h 51h 51h ?offset 51h: pmnptr - power management next capabilities pointer register? on page 549 58h 52h 53h ?offset 52h: pmcapa - power management capabilities register? on page 549 c822h 54h 55h ?offset 54h: pmcsr - power management status and control register? on page 550 0000h 56h 56h ?offset 56h: pmcsrbse - power management status and control bridge extensions register? on page 551 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 523 intel ? ep80579 integrated processor 58h 58h ?offset 58h: msicapid - msi capabilities structure register? on page 551 05h 59h 59h ?offset 59h: msinptr - msi next capabilities pointer register? on page 552 64h 5ah 5bh ?offset 5ah: msicapa - msi capabilities register? on page 553 0002h 5ch 5fh ?offset 5ch: msiar - msi address for pci express register? on page 553 fee00000h 60h 61h ?offset 60h: msidr - msi data register? on page 554 0000h 64h 64h ?offset 64h: peacapid - pci express features capabilities id register? on page 555 10h 65h 65h ?offset 65h: peanptr - pci express next capabilities pointer register? on page 556 00h 66h 67h ?offset 66h: peacapa - pci express features capabilities register? on page 556 0041h 68h 6bh ?offset 68h: peadevcap - pci express device capabilities register? on page 557 00000001h 6ch 6dh ?offset 6ch: peadevctl - pci express device control register? on page 558 0000h 6eh 6fh ?offset 6eh: peadevsts - pci express device status register? on page 560 0000h 70h 73h ?offset 70h: pealnkcap - pci express link capabilities register? on page 561 0203e481h 74h 75h ?offset 74h: pealnkctl - pci express link control register? on page 562 0001h 76h 77h ?offset 76h: pealnksts - pci express link status register? on page 564 1001h 78h 7bh ?offset 78h: peasltcap - pci express slot capabilities register? on page 565 00000000h 7ch 7dh ?offset 7ch: peasltctl - pci express slot control register? on page 568 01c0h 7eh 7fh ?offset 7eh: peasltsts - pci express slot status register? on page 569 0040h 80h 83h ?offset 80h: pearpctl - pci express root port control register? on page 570 00000000h 84h 87h ?offset 84h: pearpsts - pci express root port status register? on page 571 00000000h 100h 103h ?offset 100h: enhcapst - enhanced capability structure register? on page 571 00010001h 104h 107h ?offset 104h: uncerrsts - uncorrectable error status register? on page 572 00000000h 108h 10bh ?offset 108h: uncerrmsk - uncorrectable error mask register? on page 574 00000000h 10ch 10fh ?offset 10ch: uncerrsev - uncorrectable error severity register? on page 575 00062010h 110h 113h ?offset 110h: corerrsts - correctable error status register? on page 576 00000000h 114h 117h ?offset 114h: corerrmsk - correctable error mask register? on page 578 00000000h 118h 11bh ?offset 118h: aercacr - advanced error capabilities and control register? on page 579 00000000h 11ch 11fh ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? on page 580 00000000h 120h 123h ?offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register? on page 580 00000000h 124h 127h ?offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register? on page 581 00000000h 128h 12bh ?offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register? on page 581 00000000h 12ch 12fh ?offset 12ch: rperrcmd - root (port) error command register? on page 582 00000000h 130h 133h ?offset 130h: rperrmsts - root (port) error message status register? on page 583 00000000h 134h 137h ?offset 134h: errsid - error source id register? on page 585 00000000h 140h 143h ?offset 140h: peauniterr - pci express unit error register? on page 586 00000000h 144h 147h ?offset 144h: peamaskerr - pci express unit mask error register? on page 588 0000e000h 148h 14bh ?offset 148h: peaerrdocmd - pci express error do command register? on page 589 00000000h table 16-138.bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers (sheet 2 of 3) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 524 order number: 320066-003us 14ch 14fh ?offset 14ch: uncedmask - uncorrectable error detect mask register? on page 591 00000000h 150h 153h ?offset 150h: coredmask - correctable error detect mask register? on page 592 00000000h 158h 15bh ?offset 158h: peaunitedmask - pci express unit error detect mask register? on page 594 00000000h 160h 163h ?offset 160h: peaferr - pci express first error register? on page 595 00000000h 164h 167h ?offset 164h: peanerr - pci express next error register? on page 597 00000000h 168h 16bh ?offset 168h: peaerrinjctl - error injection control register? on page 597 00000000h table 16-138.bus 0, device 2, function 0: summary of pci express port a standard and enhanced pci configuration registers (sheet 3 of 3) offset start offset end register id - description default value table 16-139.bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers (sheet 1 of 3) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor identification register? on page 527 8086h 02h 03h ?offset 02h: did - device identification register? on page 528 5025h 04h 05h ?offset 04h: pcicmd - pci command register? on page 528 0000h 06h 07h ?offset 06h: pcists - pci status register? on page 530 0010h 08h 08h ?offset 08h: rid - revision identification register? on page 531 variable 0ah 0ah ?offset 0ah: subc - sub-class code register? on page 532 04h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 532 06h 0ch 0ch ?offset 0ch: cls - cache line size register? on page 533 00h 0eh 0eh ?offset 0eh: hdr - header type register? on page 533 01h 18h 18h ?offset 18h: pbusn - primary bus number register? on page 534 00h 19h 19h ?offset 19h: sbusn - secondary bus number register? on page 534 00h 1ah 1ah ?offset 1ah: subusn: subordinate bus number register? on page 535 00h 1ch 1ch ?offset 1ch: iobase - i/o base address register? on page 535 f0h 1dh 1dh ?offset 1dh: iolimit - i/o limit address register? on page 536 00h 1eh 1fh ?offset 1eh: secsts - secondary status register? on page 536 0000h 20h 21h ?offset 20h: mbase - memory base address register? on page 538 fff0h 22h 23h ?offset 22h: mlimit - memory limit address register? on page 539 0000h 24h 25h ?offset 24h: pmbase - prefetchable memory base address register? on page 540 fff1h 26h 27h ?offset 26h: pmlimit - prefetchable memory limit address register? on page 540 0001h 28h 28h ?offset 28h: pmbasu - prefetchable memory base upper address register? on page 541 0fh 2ch 2ch ?offset 2ch: pmlmtu - prefetchable memory limit upper address register? on page 541 00h 34h 34h ?offset 34h: capptr - capabilities pointer register? on page 542 50h 3ch 3ch ?offset 3ch: intrline - interrupt line register? on page 542 00h 3dh 3dh ?offset 3dh: intrpin - interrupt pin register? on page 543 01h 3eh 3eh ?offset 3eh: bctrl - bridge control register? on page 543 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 525 intel ? ep80579 integrated processor 44h 44h ?offset 44h: vscmd0 - vendor specific command byte 0 register? on page 545 00h 45h 45h ?offset 45h: vscmd1 - vendor specific command byte 1 register? on page 546 00h 46h 46h ?offset 46h: vssts0 - vendor specific status byte 0 register? on page 547 00h 47h 47h ?offset 47h: vssts1 - vendor specific status byte 1 register? on page 547 00h 48h 48h ?offset 48h: vscmd2 - vendor specific command byte 2 register? on page 548 00h 50h 50h ?offset 50h: pmcapid - power management capabilities structure register? on page 548 01h 51h 51h ?offset 51h: pmnptr - power management next capabilities pointer register? on page 549 58h 52h 53h ?offset 52h: pmcapa - power management capabilities register? on page 549 c822h 54h 55h ?offset 54h: pmcsr - power management status and control register? on page 550 0000h 56h 56h ?offset 56h: pmcsrbse - power management status and control bridge extensions register? on page 551 00h 58h 58h ?offset 58h: msicapid - msi capabilities structure register? on page 551 05h 59h 59h ?offset 59h: msinptr - msi next capabilities pointer register? on page 552 64h 5ah 5bh ?offset 5ah: msicapa - msi capabilities register? on page 553 0002h 5ch 5fh ?offset 5ch: msiar - msi address for pci express register? on page 553 fee00000h 60h 61h ?offset 60h: msidr - msi data register? on page 554 0000h 64h 64h ?offset 64h: peacapid - pci express features capabilities id register? on page 555 10h 65h 65h ?offset 65h: peanptr - pci express next capabilities pointer register? on page 556 00h 66h 67h ?offset 66h: peacapa - pci express features capabilities register? on page 556 0041h 68h 6bh ?offset 68h: peadevcap - pci express device capabilities register? on page 557 00000001h 6ch 6dh ?offset 6ch: peadevctl - pci express device control register? on page 558 0000h 6eh 6fh ?offset 6eh: peadevsts - pci express device status register? on page 560 0000h 70h 73h ?offset 70h: pea1lnkcap - pci express link capabilities register? on page 561 0303e441h 74h 75h ?offset 74h: pealnkctl - pci express link control register? on page 562 0001h 76h 77h ?offset 76h: pealnksts - pci express link status register? on page 564 1001h 78h 7bh ?offset 78h: pea1sltcap - pci express slot capabilities register? on page 566 00000000h 7ch 7dh ?offset 7ch: peasltctl - pci express slot control register? on page 568 01c0h 7eh 7fh ?offset 7eh: peasltsts - pci express slot status register? on page 569 0040h 80h 83h ?offset 80h: pearpctl - pci express root port control register? on page 570 00000000h 84h 87h ?offset 84h: pearpsts - pci express root port status register? on page 571 00000000h 100h 103h ?offset 100h: enhcapst - enhanced capability structure register? on page 571 00010001h 104h 107h ?offset 104h: uncerrsts - uncorrectable error status register? on page 572 00000000h 108h 10bh ?offset 108h: uncerrmsk - uncorrectable error mask register? on page 574 00000000h 10ch 10fh ?offset 10ch: uncerrsev - uncorrectable error severity register? on page 575 00062010h 110h 113h ?offset 110h: corerrsts - correctable error status register? on page 576 00000000h 114h 117h ?offset 114h: corerrmsk - correctable error mask register? on page 578 00000000h table 16-139.bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers (sheet 2 of 3) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 526 order number: 320066-003us 118h 11bh ?offset 118h: aercacr - advanced error capabilities and control register? on page 579 00000000h 11ch 11fh ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? on page 580 00000000h 120h 123h ?offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register? on page 580 00000000h 124h 127h ?offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register? on page 581 00000000h 128h 12bh ?offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register? on page 581 00000000h 12ch 12fh ?offset 12ch: rperrcmd - root (port) error command register? on page 582 00000000h 130h 133h ?offset 130h: rperrmsts - root (port) error message status register? on page 583 00000000h 134h 137h ?offset 134h: errsid - error source id register? on page 585 00000000h 140h 143h ?offset 140h: peauniterr - pci express unit error register? on page 586 00000000h 144h 147h ?offset 144h: peamaskerr - pci express unit mask error register? on page 588 0000e000h 148h 14bh ?offset 148h: peaerrdocmd - pci express error do command register? on page 589 00000000h 14ch 14fh ?offset 14ch: uncedmask - uncorrectable error detect mask register? on page 591 00000000h 150h 153h ?offset 150h: coredmask - correctable error detect mask register? on page 592 00000000h 158h 15bh ?offset 158h: peaunitedmask - pci express unit error detect mask register? on page 594 00000000h 160h 163h ?offset 160h: peaferr - pci express first error register? on page 595 00000000h 164h 167h ?offset 164h: peanerr - pci express next error register? on page 597 00000000h 168h 16bh ?offset 168h: peaerrinjctl - error injection control register? on page 597 00000000h table 16-139.bus 0, device 3, function 0: summary of pci express port a1 standard and enhanced pci configuration registers (sheet 3 of 3) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 527 intel ? ep80579 integrated processor 16.4.1 register details 16.4.1.1 offset 00h: vid - vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. 16.4.1.2 offset 02h: did - device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. note that the device id changes for each of the pci express* ports, starting with 5024h for device 2. table 16-140.offset 00h: vid - vendor identification register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 00h 01h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification device: this is a 16-bit value assigned to intel. 8086h ro table 16-141.offset 02h: did - device identification register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 02h 03h size: 16 bit default: 5024h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the imch device 2, function 0. 5024h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 528 order number: 320066-003us 16.4.1.3 offset 02h: did - device identification register 16.4.1.4 offset 04h: pcicmd - pci command register many of these bits are not applicable since the primary side of this device is not an actual pci bus. table 16-142.offset 02h: did - device identification register description: view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 02h 03h size: 16 bit default: 5025h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the imch device 3, function 0. 5025h ro table 16-143.offset 04h: pcicmd - pci command register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 04h 05h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved. 00h 10 intxd intx assertion disable: controls the ability of thepci express* device to assert intx interrupts. when set, devices are prevented from asserting intx. this bit only applies to legacy interrupts and not msis. also this bit has no affect on pci express* messages that are converted to legacy interrupts. these are only internal, device generated interrupts. 0 = enable intx assertion 1 = disable intx assertion 0b rw 09 fb2b fast back-to-back enable: not applicable-hardwired to 0. 0b ro 08 serre serr enable: this bit is a global enable bit for device serr messaging. the imch does not have an serr# signal. the imch communicates the serr# condition by sending an serr message to the iich via nsi. 0 = no serr message is generated by the imch for device (unless enabled through enhanced configuration registers). 1 = enable serr, sci, or smi messages or asserting mcerr# for specific device error conditions. 0b rw 07 adstep address/data stepping: not applicable. 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 529 intel ? ep80579 integrated processor 06 perre parity error enable: this bit determines the device behavior on detection of a parity error. see the pci express* interface specification, rev 1.0a , for details. 0 = parity errors are logged in the status register, but no other action is taken. 1 = normal action is taken upon detection of parity error, as well as logging. 0b rw 05 vps vga palette snoop: not applicable. 0b ro 04 mwie memory write and invalidate enable: not applicable. 0b ro 03 sce special cycle enable: not applicable. 0b ro 02 bme bus master enable: this bit controls the pci express* port?s ability to issue memory and i/o read/write requests on behalf of subordinate devices. msi interrupt messages are in-band memory writes, and clearing this bit disables msi interrupt messages. 0 = disable. the port does not respond to any i/o or memory transaction originating on the secondary interface. 1 = enable. 0b rw 01 mae memory access enable: controls access to the memory and prefetchable memory address ranges. 0 = disable all of device memory space 1 = enable 0b rw 00 ioae io access enable: controls access to the i/o address range defined in the iobase and iolimit registers. 0 = disable device i/o space 1 = enable 0b rw table 16-143.offset 04h: pcicmd - pci command register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 04h 05h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 530 order number: 320066-003us 16.4.1.5 offset 06h: pcists - pci status register pcists is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the ?virtual? pci-pci bridge embedded within the imch. table 16-144.offset 06h: pcists - pci status register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 06h 07h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: parity is supported on the primary side of this device. since the parity is not checked on the downstream side from the core, this bit can never be set. 0 = no parity error detected 0b ro 14 sse signaled system error: indicates whether or not a nsi serr message was generated by this device. for the root port the fatal and non-fatal messages can be either received or virtual messages that are forwarded for reporting. 0 = serr message not generated by this device. 1 = this device was the source of fatal or non-fatal error that has been enabled for generation of a system error. software clears this bit by writing a ?1? to the bit location. 0b rwc 13 rmas received master abort status: indicates whether or not this pci express* device received a completion with unsupported request completion status. 0 = no master abort received. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device receives a completion with unsupported request completion status. 0b rwc 12 rtas 0 = received target abort status: indicates whether or not this pci express* device received a completion with completer abort completion status. no target abort received. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device receives a completion with completer abort completion status. 0b rwc 11 stas signaled target abort status: not applicable to the primary side. 0 = this pci express* device has not completed a request using completer abort completion status. 1 = this pci express* device completed a request using completer abort completion status. 0b ro 10 : 09 devt devsel# timing: not applicable. hardwired to 0. 00b ro 08 dpd 0 = master data parity error detected: parity is supported on the primary side of this device. no master parity error detected. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device receives a completion marked poisoned, or when this device poisons a write request. this bit can only be set if the parity error enable bit is set. 0b rwc 07 fb2b fast back-to-back: not applicable 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 531 intel ? ep80579 integrated processor 16.4.1.6 offset 08h: rid - revision identification register this register contains the revision number of the device. 06 reserved reserved 0b 05 c66m capable 66mhz: not applicable 0b ro 04 capl capabilities list: hardwired to 1 to indicate the presence of an extended capability list item. 1b ro 03 intxs intx status: this bit does not get set for interrupts forwarded up from downstream devices, or for messages converted to interrupts by the root port. the intx assertion disable bit has no effect on the setting of this bit. this bit is not set for an msi. 0 = an intx interrupt is not pending internal to this device. 1 = an intx interrupt is pending internal to this device. 0b ro 02 : 00 reserved reserved 00h table 16-144.offset 06h: pcists - pci status register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 06h 07h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-145.offset 08h: rid - revision identification register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 08h 08h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the device 2. it is always the same as the value in device 0 rid. variable ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 532 order number: 320066-003us 16.4.1.7 offset 0ah: subc - sub-class code register this register contains the sub-class code for the device. 16.4.1.8 offset 0bh: bcc - base class code register this register contains the base class code of the imch device 2. table 16-146.offset 0ah: subc - sub-class code register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 0ah 0ah view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 0ah 0ah size: 8 bit default: 04h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 subc sub-class code: this value indicates the category of bridge into which device falls.04h = pci to pci bridge. 04h ro table 16-147.offset 0bh: bcc - base class code register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 0bh 0bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 0bh 0bh size: 8 bit default: 06h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 basec base class code: this value indicates the base class code for the device. 06h = bridge device. 06h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 533 intel ? ep80579 integrated processor 16.4.1.9 offset 0ch: cls - cache line size register this register is normally set by system firmware and os to the system cache line size. 16.4.1.10 offset 0eh: hdr - header type register this register identifies the header layout of the configuration space. table 16-148.offset 0ch: cls - cache line size register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 0ch 0ch view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 0ch 0ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cls cache line size: this register is set by bios or os to the system cache line size. implemented as read-write field only for compatibility reasons. it has no effect on the device?s functionality. 00h rw table 16-149.offset 0eh: hdr - header type register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 0eh 0eh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 0eh 0eh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr header type register: this value indicates the header type of the device. 01h = single-function device with bridge layout. 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 534 order number: 320066-003us 16.4.1.11 offset 18h: pbusn - primary bus number register this register identifies that ?virtual? pci-to-pci bridge is connected to bus 0. 16.4.1.12 offset 19h: sbusn - secondary bus number register this register identifies the bus number assigned to the second bus side of the ?virtual? pci-to-pci bridge (the pci express* connection). this number is programmed by the pci configuration software to allow mapping of configuration cycles to a second bridge device connected to pci express*. table 16-150.offset 18h: pbusn - primary bus number register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 18h 18h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 18h 18h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 busn primary bus number: configuration software typically programs this field with the number of the bus on the primary side of the bridge. since device 2 is an internal device and its primary bus is always 0, these bits are hardwired to 0. 00h ro table 16-151.offset 19h: sbusn - secondary bus number register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 19h 19h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 19h 19h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 busn secondary bus number: this field is programmed by configuration software with the lowest bus number of the pci express* port. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 535 intel ? ep80579 integrated processor 16.4.1.13 offset 1ah: subusn - subordinate bus number register this register is programmed by pci configuration software to the highest numbered subordinate bus (if any) that resides below another bridge device below the secondary pci express* interface. 16.4.1.14 offset 1ch: iobase - i/o base address register the iobase and iolimit registers control the processor-to-pci express* i/o access routing based on the following formula: io_base =< address =< io_limit only the upper four bits are programmable. for the purpose of address decode address bits a[11:00] are treated as 0. thus the bottom of the defined i/o address range is aligned to a 4 kbyte boundary. table 16-152.offset 1ah: subusn: subordinate bus number register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 1ah 1ah view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 1ah 1ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 busn subordinate bus number: this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device bridge. 00h rw table 16-153.offset 1ch: iobase - i/o base address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 1ch 1ch view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 1ch 1ch size: 8 bit default: f0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 iobase i/o address base: corresponds to a[15:12] of the i/o addresses passed by the device bridge to pci express*. fh rw 03 : 00 iobm i/o addressing mode: these bits are hardwired to 0. 0h = 16-bit i/o addressing all other bit combinations are not supported. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 536 order number: 320066-003us 16.4.1.15 offset 1dh: iolimit - i/o limit address register this register controls the cpu to pci express* i/o access routing based on the following formula: io_base =< address =< io_limit only the upper four bits are programmable. for the purpose of address decode address bits a[11:00] are assumed to be fffh. thus, the top of the defined i/o address range is at the top of a 4 kbyte aligned address block. 16.4.1.16 offset 1eh: secsts - secondary status register secsts is a 16-bit status register that reports the occurrence of error conditions associated with the secondary side (e.g., pci express* side) of the ?virtual? pci-pci bridge embedded within imch. table 16-154.offset 1dh: iolimit - i/o limit address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 1dh 1dh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 1dh 1dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 iolimt i/o address limit: corresponds to a[15:12] of the i/o address limit of device. devices between this upper limit and iobase2 are passed to pci express*. 0h rw 03 : 00 iolm i/o addressing mode: these bits are hardwired to 0. 0h = 16-bit i/o addressing all other bit combinations are not supported. 0h ro table 16-155.offset 1eh: secsts - secondary status register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 1eh 1fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 1eh 1fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 2dpe detected parity error: this bit is set by the pci express* port logic when the secondary side receives a poisoned tlp, regardless of the state of the parity error enable bit. software clears this bit by writing a ?1? to the bit location. see the pci express* interface specification, rev 1.0a for details. 0 = no parity error detected. 1 = parity error detected (poisoned tlp received). 0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 537 intel ? ep80579 integrated processor 14 2rse received system error: indicates whether or not an err_fatal or err_nonfatal message was received via pci express*. 0 = error message not received by this device. 1 = this device received fatal or non-fatal error message via pci express*. software clears this bit by writing a ?1? to the bit location. this bit is not set for virtual messages. 0b rwc 13 2rmas received master abort status: indicates whether or not this pci express* device received a completion with unsupported request completion status. 0 = no master abort received. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device receives a completion with unsupported request completion status. 0b rwc 12 2rtas received target abort status: indicates whether or not this pci express* device received a completion with completer abort completion status. 0 = no target abort received. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device receives a completion with completer abort completion status. 0b rwc 11 stas signaled target abort status: indicates whether or not this pci express* device completed a request using completer abort completion status. 0 = no target abort signaled. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device completes a request using completer abort completion status. 0b rwc 10 : 09 devt devsel# timing: not applicable 00b ro 08 dpd master data parity error detected: parity is supported on the secondary side of this device. 0 = no master parity error detected. software clears this bit by writing a ?1? to the bit location. 1 = set when this pci express* device receives a completion marked poisoned, or when this device poisons a write request. this bit can only be set if the parity error enable bit is set. 0b rwc 07 fb2b fast back-to-back: hardwired to 0. not applicable to pci express*. 0b ro 06 reserved reserved 0b ro 05 cap66 capability 66 mhz: not applicableto pci express*. hardwired to 0. 0b ro 04 : 00 reserved reserved 00h ro table 16-155.offset 1eh: secsts - secondary status register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 1eh 1fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 1eh 1fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 538 order number: 320066-003us 16.4.1.17 offset 20h: mbase - memory base address register this register controls the processor to pci express* non-prefetchable memory access routing based on the following formula: memory_base =< address =< memory_limit note: the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return zeroes when read. th is register must be initialized by the configuration software. for the purpose of address decode address bits a[19:00] of the memory base address are assumed to be 0. similarly, the bridge assumes that the lower 20 bits of the memory limit address (a[19:00]) are f_ffffh. thus, the bottom of the defined memory address range are aligned to a 1 mbyte boundary, and the top of the defined memory range is at the top of a 1 mbyte memory block. memory range covered by mbase and mlimit registers are used to map non-prefetchable pci express* address ranges (typically where control/status memory-mapped i/o data structures of the graphics controller resides) and pmbase and pmlimit are used to map prefetchable address ranges (typically graphics local memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved pci express* memory access performance. configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the va lues that provide exclusive address ranges (for example, to prevent overlap with each other and/or with the ranges covered with the main memory). there is no provision in the cmi hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. 16.4.1.18 offset 22h: mlimit - memory limit address register this register controls the processor to pci express* non-prefetchable memory access routing based on the following formula: memory_base =< address =< memory_limit table 16-156.offset 20h: mbase - memory base address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 20h 21h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 20h 21h size: 16 bit default: fff0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 mbase memory address base: corresponds to a[31:20] of the lower limit of the memory range that are passed by the device 2 bridge to pci express*. fffh rw 03 : 00 reserved reserved 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 539 intel ? ep80579 integrated processor the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return zeroes when read. this register must be initialized by configuration software. for the purpose of address decode address bits a[19:00] are assumed to be fffffh. thus, the top of the defined memory address range is at the top of a 1 mbyte aligned memory block. note: memory range covered by mbase and mlimit registers, are used to map non- prefetchable pci express* address ranges (typically where control/status memory- mapped i/o data structures of the graphics controller reside) and pmbase and pmlimit are used to map prefetchable address ranges (typically graphics local memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved pci express* memory access performance. configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges; for example, to prevent overlap with each other and/or with the ranges covered with the main memory. there is no provision in the cmi hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. 16.4.1.19 offset 24h: pmbase - prefetchable memory base address register this pmbase and pmlimit register controls the processor to pci express* prefetchable memory accesses. the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. for the purpose of address decode, bits a[19:00] of the prefetchable memory base address are assumed to be 0. similarly, the bridge assumes that the lower 20 bits of the prefetchable memory limit address (a[19:00]) are f_ffffh. thus, the bottom of the defined memory address range are aligned to a 1 mbyte boundary, and the top of the defined memory range are at the top of a 1 mbyte memory block. the bottom 4 bits of both the prefetchable memory base and prefetchable memory limit registers are read-only, contain the same value, and encode whether or not the bridge supports 64-bit addresses. if these four bits have the value 0h, then the bridge supports only 32 bit addresses. if these four bits have the value 01h, then the bridge supports 64-bit addresses and the prefetchable base upper 32 bits and prefetchable limit upper 32 bits registers hold the rest of the 64-bit prefetchable base and limit addresses respectively. all other encodings are reserved. table 16-157.offset 22h: mlimit - memory limit address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 22h 23h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 22h 23h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 milimit memory address limit: corresponds to a[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that are passed by the device bridge to pci express*. 000h rw 03 : 00 reserved reserved 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 540 order number: 320066-003us 16.4.1.20 offset 26h: pmlimit - prefetchable memory limit address register this register controls the processor to pci express* prefetchable memory accesses. the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. for the purpose of address decode, bits a[19:00] are assumed to be fffffh. thus, the top of the defined memory address range are at the top of a 1 mbyte aligned memory block. table 16-158.offset 24h: pmbase - prefetchable memory base address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 24h 25h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 24h 25h size: 16 bit default: fff1h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 pmbase prefetchable memory address base: corresponds to a[31:20] of the lower limit of the address range passed by bridge device across pci express*. fffh rw 03 : 01 mamb memory addressing mode. these bits are read-only with a value of zero, all other values are reserved. 0h ro 00 mbuae memory base upper address enabled: 0 = disabled 1 = enabled - indicates that the base address is further defined by the upper address bits of the memory base upper address register. 1h ro table 16-159.offset 26h: pmlimit - prefetchable memory limit address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 26h 27h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 26h 27h size: 16 bit default: 0001h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 pmlimit prefetchable memory address limit: corresponds to a[31:20] of the upper limit of the address range passed by bridge device 2 across pci express*. 000h rw 03 : 01 maml memory addressing mode. these bits are read-only with a value of zero, all other values are reserved. 0h ro 00 mluae memory limit upper address enabled: 0 = disabled 1 = enabled - indicates that the limit address is further expanded/defined by the upper address bits of the memory limit upper address register. 1h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 541 intel ? ep80579 integrated processor 16.4.1.21 offset 28h: pmbasu - prefetchable memory base upper address register these register expands the prefetchable memory base address by four bits. all other bits are reserved. 16.4.1.22 offset 2ch: pmlmtu - prefetchable memory limit upper address register these register expands the prefetchable memory limit address by four bits. all other bits are reserved. table 16-160.offset 28h: pmbasu - prefetchable memory base upper address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 28h 28h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 28h 28h size: 8 bit default: 0fh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 : 00 bua base upper address bits: these four bits expands the prefetchable address base to 36 bits. corresponds to a[35:32] of the lower limit of the address range passed by bridge device across the pci express* interface. fh rw table 16-161.offset 2ch: pmlmtu - prefetchable memory limit upper address register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 2ch 2ch view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 2ch 2ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 : 00 lua limit upper address bits: these four bits expands the prefetchable address limit to 36 bits. corresponds to a[35:32] of the upper limit of the address range passed by bridge device across the pci express* interface. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 542 order number: 320066-003us 16.4.1.23 offset 34h: capptr - capabilities pointer register the capptr provides the offset that is the pointer to the location where the first set of capabilities registers is located. 16.4.1.24 offset 3ch: intrline - interrupt line register table 16-162.offset 34h: capptr - capabilities pointer register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 34h 34h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 34h 34h size: 8 bit default: 50h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cap_ptr capabilities pointer: pointer to first pci express* capabilities structure register block, which is the first of the chain of capabilities. 50h ro table 16-163.offset 3ch: intrline - interrupt line register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 3ch 3ch view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intrc interrupt connection: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller that connects this device. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 543 intel ? ep80579 integrated processor 16.4.1.25 offset 3dh: intrpin - interrupt pin register 16.4.1.26 offset 3eh: bctrl - bridge control register this register provides extensions to the pcicmd register that are specific to pci-pci bridges. the bctrl provides additional control for the secondary interface (e.g. pci express*) and some bits that affect the overall behavior of the ?virtual? pci-pci bridge embedded within, e.g. vga compatible address range mapping. table 16-164.offset 3dh: intrpin - interrupt pin register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 3dh 3dh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intrp interrupt pin: set to ?01h? to indicate pci express* always uses inta# as its interrupt pin. once this register is written, the register value locks and cannot be further updated. 01h rwo table 16-165.offset 3eh: bctrl - bridge control register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 3eh 3eh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 3eh 3eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved 0b 06 sreset secondary bus reset: 0 = no hot reset is triggered on the link for the corresponding pci express* port and the pci express* hierarchy domain subordinate to the port. 1 = setting this bit triggers a hot reset on the link for the corresponding pci express* port and the pci express* hierarchy domain subordinate to the port. this sends the ltssm into the training (or link) control reset state, which necessarily implies a reset to the downstream device and all subordinate devices. once this bit has been cleared, and the minimum transmission requirement has been met, the detect state is entered by both ends of the link. note also that a secondary bus reset does not in general reset the primary side configuration registers of the targeted pci express* port. this is necessary to allow software to specify special training configuration, such as entry into loopback mode. 0b rw 05 : 04 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 544 order number: 320066-003us 16.4.1.27 offset 44h: vscmd0 - vendor specific command byte 0 register this register is for vendor specific commands. hot plug is not supported. note: it appears as a reserved register, except for device 2 which implement this hot plug specific register. 03 vgaen vga enable: controls the routing of processor initiated transactions targeting vga compatible i/o and memory address ranges. 0 = disable 1 = enable note: only one of device 2?3?s vgaen bits are allowed to be set. this must be enforced via software. 0b rw 02 isaen isa enable: modifies the response by the imch to an i/o access issued by the processor that target isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions are mapped to pci express*. 1 = imch does not forward to pci express* any i/o transactions addressing the last 768 bytes in each 1 kbyte block even if the addresses are within the range defined by the iobase and iolimit registers. instead, these cycles are forwarded to nsi where they can be subtractively or positively claimed by the isa bridge. 0b rw 01 2serre serr enable: this bit enables or disables forwarding of err_cor, err_nonfatal, and err_fatal messages from pci express* to nsi, where they can be converted into interrupts that are eventually delivered to the processor. 0 = disable 1 = enable 0b rw 00 2perre parity error response enable: controls response to poisoned tlps on pci express*. 0 = disable 1 = enable 0b rw table 16-165.offset 3eh: bctrl - bridge control register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 3eh 3eh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 3eh 3eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 545 intel ? ep80579 integrated processor table 16-166.offset 44h: vscmd0 - vendor specific command byte 0 register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 44h 44h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 44h 44h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 pdpi presence detect polarity invert: 0 = presence detect normal polarity. 1 = the polarity of the presence detect input received from the iox is inverted. 0b rw 06 appi attention pushbutton polarity invert: 0 = attention pushbutton normal polarity. 1 = the polarity of the attention pushbutton input received from the iox is inverted. 0b rw 05 pfpi power fault polarity invert: 0 = power fault normal polarity. 1 = the polarity of the power fault input received from the iox is inverted. 0b rw 04 mpi mrl polarity invert: 0 = mrl normal polarity. 1 = the polarity of the mrl input received from the iox is inverted. 0b rw 03 pcpi power control polarity invert: 0 = power control normal polarity. 1 = the polarity of the power control input received from the iox is inverted. 0b rw 02 ipi indicator polarity invert: 0 = attention and power indicators normal polarity. 1 = the polarity of the attention and power indicators presented to the iox is inverted. 0b rw 01 : 00 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 546 order number: 320066-003us 16.4.1.28 offset 45h: vscmd1 - vendor specific command byte 1 register hot plug is not supported. this register is for vendor specific commands. table 16-167.offset 45h: vscmd1 - vendor specific command byte 1 register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 45h 45h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 45h 45h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0b 03 ctod completion to timer disable: 0 = the completion timeout timer is enable. 1 = the completion timeout timer is disabled. 0b rw 02 hgd hot plug is not supported bios must set this bit to ?1? hot plug gpe disable: 0 = enables reporting of hot plug interrupts via the legacy gpe mechanism. 1 = disables reporting of hot plug interrupts via the legacy gpe mechanism. this bit must be set when hot plug interrupts are to be reported via the interrupt (intx or msi) signaling mechanism. 0b rw 01 tcle training control loopback enable: 0 = disabled 1 = enabled - if this bit is a 1 when the ts1/ts2 ordered- sets are transmitted, the ?enable loopback? bit is set in the training control symbol 0b rw 00 pmetor pme turn off request: 0 = cleared by hardware when the acknowledge is returned from the link. the bit is also cleared when the link layer is in the dl_down state. 1 = set by software if link layer is in the dl_up state. 0b rws
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 547 intel ? ep80579 integrated processor 16.4.1.29 offset 46h: vssts0 - vendor specific status byte 0 register this register is for vendor specific status. 16.4.1.30 offset 47h: vssts1 - vendor specific status byte 1 register this register is for vendor specific status. table 16-168.offset 46h: vssts0 - vendor specific status byte 0 register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 46h 46h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 46h 46h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 00h 03 smb_busy this signal indicates that the bus is busy, but that this master is not involved in the traffic. 0 = ready 1 = busy 0b ro 02 reserved reserved 0b 01 reserved 1 = reserved 0b ro 00 reserved 1 = reserved 0b ro table 16-169.offset 47h: vssts1 - vendor specific status byte 1 register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 47h 47h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 47h 47h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 00h 01 la link active: bit reports whether transactions are being sent or aborted by the downstream transaction control, which is determined by the ?link_active? status from the link layer reflected in this status bit. 0 = link down 1 = link up 0b ro 00 pmetoa pme turn off acknowledge: 0 = software writes a 1 to this bit to clear it. the bit will also be cleared when the link layer is in the dl_down state 1 = set by hardware when pmetor is on and the acknowledge is returned from the link. when this bit is set, the turn off request bit clears. 0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 548 order number: 320066-003us 16.4.1.31 offset 48h: vscmd2 - vendor specific command byte 2 register this register is for vendor specific commands. 16.4.1.32 offset 50h: pmcapid - power management capabilities structure register this register identifies the capability structure and points to the next structure. table 16-170.offset 48h: vscmd2 - vendor specific command byte 2 register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 48h 48h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 48h 48h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved reserved 00h 00 dpssen note: this register bit must always be disabled or undefined behavior will result. 0 = disable 1 = enable 0b rw table 16-171.offset 50h: pmcapid - power ma nagement capabilities structure register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 50h 50h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 50h 50h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cap_id this field has the value 01h to identify the cap_id assigned by the pci sig for vendor dependent capability pointers. 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 549 intel ? ep80579 integrated processor 16.4.1.33 offset 51h: pmnptr - power management next capabilities pointer register this register identifies the capability structure and points to the next structure. 16.4.1.34 offset 52h: pmcapa - power management capabilities register this register identifies the capabilities for pm. table 16-172.offset 51h: pmnptr - power management next capabilities pointer register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 51h 51h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 51h 51h size: 8 bit default: 58h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 ncr next capability pointer: this field points to the next capability id in this device which is the msi. 58h ro table 16-173.offset 52h: pmcapa - power management capabilities register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 52h 53h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 52h 53h size: 16 bit default: c822h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pmes_pmcapa pme support: identifies power states which assert pme. bits 15, 14 and 11 must be set to '1' for pci-pci bridge structures representing ports on root complexes. the definition of these bits is taken from the pci bus power management interface specification revision 1.1. bit(11) xxxx1b pme# can be asserted from d0 bit(12) xxx1xb pme# can be asserted from d1 (imch does not support) bit(13) xx1xxb pme# can be asserted from d2 (imch does not support) bit(14) x1xxxb pme# can be asserted from d3 hot (imch does not support) bit(15) 1xxxxb pme# can be asserted from d3 cold (imch does not support) note: d3 is not supported, default value shows incorrect support for d3 11001b ro 10 d2s d2 support: this bit is hardwired to ?0? to indicate the power management state d2 is not supported. 0b ro 09 d1s d1 support: this bit is hardwired to ?0? to indicate the power management state d1 is not supported. 0b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 550 order number: 320066-003us 16.4.1.35 offset 54h: pmcsr - power management status and control register this register contains the control and status bits for power management. 08 : 06 auxcc auxc current: aux current required for function. hardwired to 000b to indicate a self-powered device. 000b ro 05 dsi dsi: device specific initialization is required. 1b ro 04 reserved reserved 0b 03 pmec pme clock: this bit is hardwired to ?0? to indicate no pci clock is required for pme. 0b ro 02 : 00 ver version: hardwired to 010b to indicate compliance with pci bus power management interface specification, rev 1.1 . 010b ro table 16-173.offset 52h: pmcapa - power manage ment capabilities register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 52h 53h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 52h 53h size: 16 bit default: c822h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-174.offset 54h: pmcsr - power ma nagement status and control register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 54h 55h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 54h 55h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pmes_pmcsr pme status: this bit is hardwired to ?0? to indicate this field is not supported by imch. y0b ro 14 :09 reserved reserved 00b 08 pmee pme enable: controls pme# assertion. this bit is sticky through reset. writes to this field have no effect. this bit is sticky. 0 = this device does not assert pme# 1 = enables this device to assert pme# y0b rw 07 : 02 reserved reserved 00h 01 : 00 ps power state: since the pci express* bridge device supports only the d0 state, writes to this field have no effect. 00h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 551 intel ? ep80579 integrated processor 16.4.1.36 offset 56h: pmcsrbse - power management status and control bridge extensions register this register identifies the capabilities for power management. 16.4.1.37 offset 58h: msicapid - msi capabilities structure register this register identifies the msi capability structure. table 16-175.offset 56h: pmcsrbse - power management status and control bridge extensions register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 56h 56h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 56h 56h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved 0b ro 06 reswerd b2/b3 support: reserved 0b ro 05 : 00 reserved reserved 00h table 16-176.offset 58h: msicapid - msi capabilities structure register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 58h 58h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 58h 58h size: 8 bit default: 05h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cap_id this field has the value 05h to identify the cap_id assigned by the pci sig for a message signaled interrupts capability list. 05h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 552 order number: 320066-003us 16.4.1.38 offset 59h: msinptr - msi next capabilities pointer register this register points to the next capability structure. 16.4.1.39 offset 5ah: msicapa - msi capabilities register the pci express* controller generates upstream interrupt message using msi to the processor bypassing ioxapic. the msi is generated by a memory write to address 0feex_xxxxh. three 32-bit registers are required in the pci express* controller to support this mechanism. the default values of these registers are compatible to the default value of ioxapic. the software can reprogram these registers to required value. the three registers are msi control register (msicr), msi address register (msiar) and msi data register (msidr). depending on system requirement each pci express* channel can have a msi block (provides better flexibility) or the pci express* controller as a whole has one msi block and all channels raise hardware interrupts to this block. the msi control register (msicr) contains all the information related to the capability of pci express* msi interrupts. the msicr register has been broken down into its components, msicapid, msinptr, and msicapa for purposes of separate register definitions. table 16-177.offset 59h: msinptr - msi next capabilities pointer register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 59h 59h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 59h 59h size: 8 bit default: 64h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 msi_ncp next capability pointer: this field points to the next capability id in this device, which is the hot plug controller. 64h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 553 intel ? ep80579 integrated processor 16.4.1.40 offset 5ch: msiar - m si address for pci express* register the msi address register (msiar) contains all the address related information to route msi interrupts. table 16-178.offset 5ah: msicapa - msi capabilities register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 5ah 5bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 5ah 5bh size: 16 bit default: 0002h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 reserved reserved 00h 07 64ac indicates 64-bit address capable: hardwired to ?0? to indicate that the pci express* bridge is capable of 32-bit msi addressing. 0b ro 06 : 04 mme multiple message enable: the software writes this field to indicate the number of allocated messages, which is aligned to a power of two. when msi is enabled, the software allocates at least one message to the device. 0h rw 03 : 01 mmc multiple message capable: the pci express* requests a capability for two messages by initializing this field to a value of 001b. 001b ro 00 msie msi enable: software sets this bit to select the method of interrupt delivery. if no interrupts are enabled, software must poll for status since no interrupts of either type are generated. 0 = legacy interrupts are generated. 1 = message signaled interrupts (msi) are generated. 0b rw table 16-179.offset 5ch: msiar - msi address for pci express register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 5ch 5fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 5ch 5fh size: 32 bit default: fee00000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 msia address: most significant 12 bits of 32-bit address. feeh rw 19 : 12 desid destination id: should reflect the 63:56 bits of ioxapic redirection table entry. the imch may substitute other values in this field when redirecting to the system bus. y 00h rw 11 : 04 exdid extended destination id: should reflect the 55:48 bits of ioxapic redirection table entry. 00h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 554 order number: 320066-003us 16.4.1.41 offset 60h: msidr - msi data register the msi data register (msidr) contains all the data elated information to route msi interrupts. 03 rh redirection hint: used by the imch to allow the interrupt message to be redirected. 0 = direct 1 = redirect 0b rw 02 dmmsia destination mode: used only if redirection hint is set to ?1?. 0 = physical 1 = logical 0b rw 01 : 00 reserved reserved 0b table 16-179.offset 5ch: msiar - msi address for pci express register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 5ch 5fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 5ch 5fh size: 32 bit default: fee00000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-180.offset 60h: msidr - msi data register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 60h 61h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 60h 61h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 tm trigger mode: same as the corresponding bit in the i/o redirection table for that interrupt. 0 = edge 1 = level 0b rw 14 dvs delivery status: if using edge-triggered interrupts, this is always a 1, since only assertion is sent. if using level- triggered interrupts, then this bit indicates the state of the interrupt input. 0b rw 13 : 12 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 555 intel ? ep80579 integrated processor 16.4.1.42 offset 64h: peacapid - pci express* features capabilities id register this register identifies the pci express* features capability structure. 11 dmmsid destination mode: same as bit 2 of msiar. 0 = physical 1 = logical 0b rw 10 : 08 delm delivery mode: same as the corresponding bits in the i/o redirection table for that interrupt. 000= fixed 100=nmi 001= lowest priority 101=init 010= smi/pmi 110=reserved 011= reserved 111=extint 0h rw 07 : 00 iv interrupt vector: same as the corresponding bits in the i/o redirection table for that interrupt. 00h rw table 16-180.offset 60h: msidr - msi data register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 60h 61h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 60h 61h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-181.offset 64h: peacapid - pci express features capabilities id register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 64h 64h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 64h 64h size: 8 bit default: 10h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cap_id this field has the value 10h to identify the cap_id assigned by the pci sig for pci express* capability structure. 10h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 556 order number: 320066-003us 16.4.1.43 offset 65h: peanptr - pci express* next capabilities pointer register this register identifies the next pci express* capability structure. 16.4.1.44 offset 66h: peacapa - pci express* features capabilities register this register identifies pci express* device type and associated capabilities. table 16-182.offset 65h: peanptr - pci ex press next capabilities pointer register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 65h 65h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 65h 65h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pea_ncp next capability pointer: this field contains that value 00b to indicate that there are no additional capability structures. 00h ro table 16-183.offset 66h: peacapa - pci ex press features capabilities register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 66h 67h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 66h 67h size: 16 bit default: 0041h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 14 reserved reserved 00b 13 : 09 cimn capability interrupt message number: if the function is allocated more than one msi interrupt number, this field contains the offset between the base message data and the msi message that is generated when any of the status bits in either the slot status or root port status registers of this capability structure are set. hardware updates this field so that it is correct if the number of msi messages assigned to the device (based on the setting of the multiple message enable bits in the msi capabilities register). 00000b ro 08 simp slot implemented: bios must set this bit at boot time if the pci express* link associated with this port is connected to a slot (as compared to being connected to a motherboard component, or being disabled). 0 = slot not implemented. 1 = slot implemented. 0b rwo 07 : 04 dpt device/port type: hardwired to a value of ?4? hex to indicate a root port. 4h ro 03 : 00 capv capability version: hardwired to 1h to indicate compliance with the pci express* interface specification, rev 1.0a . 1h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 557 intel ? ep80579 integrated processor 16.4.1.45 offset 68h: peadevcap - pci express* device capabilities register this register identifies the device capabilities for pci express*. table 16-184.offset 68h: peadevcap - pci express device capabilities register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 68h 6bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 68h 6bh size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 28 reserved reserved 0h 27 : 26 cspls captured slot power limit scale (upstream ports only): specifies the scale used for the slot power limit value. 00b = 1.0x (25.5 ? 255) 01b = 0.1x (2.55 ? 25.5) 10b = 0.01x (0.255 ? 2.55) 11b = 0.001x (0.0 ? 0.255) 00b ro 25 : 18 csplv captured slot power limit value (upstream ports only): in combination with the slot power limit scale value, this register specifies the upper limit on power supplied by slot. power limit (in watts) calculated by multiplying the value in this fi eld by the value in the slot power limit scale field. this value is set by the set_slot_power_limit. 00h ro 17 : 06 reserved reserved 000b 05 etfs extended tag field supported: hardwired to 0b, indicating 5 bits, as required for a root port. 0b ro 04 : 03 pfs phantom functions supported: hardwired to 00b as required for root ports, indicating that devices may implement all function numbers. 00b ro 02 : 00 mpss note: max payload size supported: hardwired to 001b to indicate a maximum 256b payload size. note that this refers to an inbound payload size, since the outbound payload size is restricted to a cacheline size to a value of 64 b. 001b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 558 order number: 320066-003us 16.4.1.46 offset 6ch: peadevctl - pci express* device control register this register pci express* device specific parameters. table 16-185.offset 6ch: peadevctl - pci express device control register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 6ch 6dh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 6ch 6dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0b 14 : 12 mrrs max read request size: this field sets maximum read request size for the device as a requester. the imch does not generate read requests with size exceeding the set value. defined encodings for this field are: note: 000b=128 b100b=2 kbyte 001b=256 b101b=4 kbyte 010b=512 b110b=reserved 011b=1 kbyte111b=reserved 000b rw 11 ens enable no snoop: permits the device to set the no snoop bit in the requester attributes of transactions that do not require hardware enforced cache coherency. even when this bit is set, the device can only set the no snoop attribute on a transaction when the address of the transaction is not stored on any cache in the system. 0 = disable 1 = enable software override on usage of the ?no snoop? attribute. the imch hard-wires this bit to 0, as it never issues transactions with that attribute set. 0b ro 10 auxppe auxiliary (aux) power pm enable: not applicable. 0b ro 09 pfe phantom functions enable: not applicable. 0b ro 08 etfe extended tag field enable: not applicable 0b ro 07 : 05 maxps max payload size: this field sets maximum tlp payload size for the device. as a receiver, the device must handle tlps as large as the set value; as transmitter, the device must not generate tlps exceeding the set value. permissible values that can be programmed are indicated by the max_payload_size supported in the device capabilities register. note: encodings above 256b are not supported. rw functionality is only maintained for compliance testing of all register bits. defined encodings for this field are: 000b = 128 b 100b = 2 kbyte 001b = 256 b 101b = 4 kbyte 010b = 512 b 110b = reserved 011b = 1 kbyte 111b = reserved 000b rw 04 ero enable relaxed ordering: if this bit is set the device is permitted to set the relaxed ordering bit in the attributes field of transactions it issues that do not require strong write ordering. hard-wired to ?0? in the imch, as no such transaction attributes are ever used on outbound requests. 0 = disable 1 = enable 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 559 intel ? ep80579 integrated processor 03 urre unsupported request reporting enable: this bit enables reporting of unsupported requests when set. default is ?0? with reporting disabled. note that the reporting of error messages (err_corr, err_nonfatal, err_fatal) received by root port is controlled exclusively by root port control register. 0 = disable reporting of unsupported request errors 1 = enable reporting of unsupported request errors 0b rw 02 fere fatal error reporting enable: this bit controls the reporting of fatal errors. note that the reporting of fatal errors is internal to the root. no external err_fatal message is generated. pcicmd[serre] when set can also enable reporting of both internal and external errors to be reported. 0 = disable fatal error reporting 1 = enable fatal error reporting 0b rw 01 nfere non-fatal error reporting enable: this bit controls the reporting of nonfatal errors. note that the reporting of nonfatal errors is internal to the root. no external err_nonfatal message is generated. pcicmd[serre] when set can also enable reporting of both internal and external errors to be reported. 0 = disable nonfatal error reporting 1 = enable nonfatal error reporting 0b rw 00 cere correctable error reporting enable: this bit controls the reporting of correctable errors. note that the reporting of correctable errors is internal to the root. no external err_corr message is generated. 0 = disable correctable error reporting 1 = enable correctable error reporting 0b rw table 16-185.offset 6ch: peadevctl - pci express device control register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 6ch 6dh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 6ch 6dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 560 order number: 320066-003us 16.4.1.47 offset 6eh: peadevsts - pci express* device status register this register provides information about pci express* device specific parameters. table 16-186.offset 6eh: peadevsts - pci express device status register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 6eh 6fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 6eh 6fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 06 reserved reserved 000h 05 tp transactions pending: indicates that the device has transactions pending. 0 = cleared by hardware only when all pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1 = set by hardware to indicate that transactions are pending (including completions for any outstanding non-posted requests for all used traffic classes). 0b ro 04 reserved reserved 0b 03 urs unsupported request detected: indicates that an unsupported request has been detected. this bit is set upon unsupported request detection regardless of whether or not error reporting is enabled in the device control register. software clears this bit by writing a ?1? to the bit location. 0 = no unsupported request detected 1 = unsupported request detected 0b rwc 02 fed fatal error detected: indicates that a fatal error has been detected. this bit is set upon fatal error detection regardless of whether or not error reporting is enabled in the device control register. software clears this bit by writing a ?1? to the bit location. 0 = no fatal error detected 1 = fatal error detected 0b rwc 01 nfed non-fatal error detected: indicates that a nonfatal error has been detected. this bit is set upon nonfatal error detection regardless of whether or not error reporting is enabled in the device control register. software clears this bit by writing a ?1? to the bit location. 0 = no nonfatal error detected 1 = nonfatal error detected 0b rwc 00 ced correctable error detected: indicates that a correctable error has been detected. this bit is set upon correctable error detection regardless of whether or not error reporting is enabled in the device control register. software clears this bit by writing a ?1? to the bit location. 0 = no correctable error detected 1 = correctable error detected 0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 561 intel ? ep80579 integrated processor 16.4.1.48 offset 70h: pealnkcap - pci express* link capabilities register this register identifies pci express* link specific capabilities. 16.4.1.49 offset 70h: pea1lnkcap - pci express* link capabilities register this register defines the capabilities of the link. table 16-187.offset 70h: pealnkcap - pci express link capabilities register description: view: pci bar: configuration bus:device:function: 0:2:0 offset start: offset end: 70h 73h size: 32 bit default: 0203e481h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 pn port number: this field indicates the pci express* port number for the associated pci express* link. 02h ro 23 : 18 reserved reserved 00h 17 : 15 reserved reserved 111b 14 : 12 reserved reserved 110b 11 : 10 aspm cmi does not support optional l1 aspm. active state pm: 01 l0s entry supported 01b ro 09 : 04 mlw maximum link width: this field indicates the maximum width of the pci express* link. device 2 reports a value of 001000b, indicating a maximum link width of x8. however, if two separate devices are connected to port a (device 2) and port a1 (device 3), the maximum link width for both ports is x4. 001000b ro 03 : 00 mls maximum link speed: 0001b 2.5 gb/s supported all other settings are reserved. 0001b ro table 16-188.offset 70h: pea1lnkcap - pci express link capabilities register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:3:0 offset start: offset end: 70h 73h size: 32 bit default: 0303e441h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 pn port number: this field indicates the pci express* port number for the associated pci express* link. 03h ro 23 : 18 reserved reserved 00h 17 : 15 reserved reserved 111b 14 : 12 reserved reserved 110b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 562 order number: 320066-003us 16.4.1.50 offset 74h: pealnkctl - pci express* link control register this register controls pci express* link specific parameters. 11 : 10 reserved reserved 01b 09 : 04 mlw maximum link width: this field indicates the maximum width of the pci express* link. device 3 reports a value of 000100b indicating a maximum link width of x4. all other encodings are reserved. 000100b ro 03 : 00 mls maximum link speed: 0001b 2.5 gb/s supported all other settings are reserved. 0001b ro table 16-188.offset 70h: pea1lnkcap - pci express link capabilities register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:3:0 offset start: offset end: 70h 73h size: 32 bit default: 0303e441h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-189.offset 74h: pealnkctl - pci expr ess link control register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 74h 75h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 74h 75h size: 16 bit default: 0001h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 reserved reserved 00h 07 es extended synch: provides external devices monitoring the link with additional time for to achieve bit and symbol lock before the link enters l0 state and resumes communication. 0 = normal 1 = reserved. 0b rw 06 ccc common clock configuration: 0 = this component and the component at the opposite end of the link are operating with asynchronous reference clocks. 1 = this component and the component at the opposite end of the link are operating with a distributed common reference clock. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 563 intel ? ep80579 integrated processor 05 rl retrain link: 0 = link retraining not initiated. this bit always returns 0 when read. 1 = link retraining initiated note: link retraining does not force a ?link down? condition, it merely invokes ?recovery.? 0b wo 04 ld link disable: disables/enables the associated pci express* link. 0 = enable 1 = disable 0b rw 03 rcb read request return parameter ?r? control: hardwired to ?0?, indicating ?rcb? capability of 64b. this is also known as read completion boundary. 0b ro 02 reserved reserved 0b 01 : 00 aslpmc active state link pm control: controls the level of active state power management supported on the associated pci express* link. defined encodings are: 00b disabled 01b l0s entry supported 10b reserved 11b reserved 01b rw table 16-189.offset 74h: pealnkctl - pci express link control register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 74h 75h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 74h 75h size: 16 bit default: 0001h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 564 order number: 320066-003us 16.4.1.51 offset 76h: pealnksts - pci express* link status register this register provides information about pci express* link specific parameters . table 16-190.offset 76h: pealnksts - pci express link status register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 76h 77h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 76h 77h size: 16 bit default: 1001h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 labs link autonomous bandwidth status ? this bit is set by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through dl_down status, for reasons other than to attempt to correct unreliable link operation. this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change 0b rw1c 14 lbms link bandwidth management status ? this bit is set by hardware to indicate that either of the following has occurred without the port transitioning through dl_down status: a link retraining has completed following a write of 1b to the retrain link bit note: this bit is set following any write of 1b to the retrain link bit, including when the link is in the process of retraining for some other reason. hardware has changed link speed or width to attempt to correct unreliable link operation, either through an ltssm timeout or a higher level process this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change. 0b rw1c 13 dllla data link layer link active ? this bit indicates the status of the data link control and management state machine. 1b = in dl_active state 0b = not in dl_active state 0b ro 12 scc slot clock configuration: this bit indicates that the component uses the same physical reference clock that the platform provides on the connector.the read function is only allowed after software/bios initialized the bit.. 0 = the component in the slot uses an independent reference clock, irrespective of the presence of a reference on the connector. 1 = the component in the slot uses the same physical reference clock provided on the connector. 1b rwo 11 lt link training: this read-only bit indicates that link training is in progress (physical layer ltssm in configuration or recovery state); hardware clears this bit once link training is successfully trained to the l0 state. 0 = cleared by hardware once link training is complete 1 = set by hardware when link training is in progress 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 565 intel ? ep80579 integrated processor 16.4.1.52 offset 78h: peasltcap - pci express* slot capabilities register this register identifies pci express* slot specific capabilities. hot plug is not supported. 10 reserved reserved: 0b ro 09 : 04 nw negotiated width: note that reset value is reserved, and this field remains undefined until bit 11 (link training) has been cleared by hardware. if training never completes, this field remains undefined. 000001b = x1 000100b = x4 001000b = x8 all other encodings are reserved 00h ro 03 : 00 ls link speed: value of 1h indicates 2.5 gbytes/s link. 1h ro table 16-190.offset 76h: pealnksts - pci express link status register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 76h 77h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 76h 77h size: 16 bit default: 1001h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-191.offset 78h: peasltcap - pci express slot capabilities register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:2:0 offset start: offset end: 78h 7bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 19 psn physical slot number: this hardware initialized field indicates the physical slot number attached to this port. this field must be hardware initialized to a value that assigns a slot number that is globally unique within the chassis. this field must be initialized to 0 for ports connected to devices that are either integrated on the motherboard. 000h rwo 18 : 17 reserved reserved 00b 16 : 15 spls slot power limit scale: specifies the scale used for the slot power limit value. 00b = 1.0x (25.5?255) 01b = 0.1x (2.55?25.5) 10b = 0.01x (0.255?2.55) 11b = 0.001x (0.0?0.255) 00b rwo 14 : 07 splv slot power limit value: in combination with the slot power limit scale value, this register specifies the upper limit on power supplied by slot. power limit (in watts) calculated by multiplying the value in this field by the value in the slot power limit scale field. this field must be programmed at boot. writing to this field triggers a set_slot_power_limit inband pci express* message. 00h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 566 order number: 320066-003us 16.4.1.53 offset 78h: pea1sltcap - pci express* slot capabilities register this register identifies pci express* slot specific capabilities. note: hot plug is not supported. 06 hotpc hot plug is not supported biosmust set to 0. 0b rwo 05 hotps hot plug surprise: not supported. . 0b ro 04 pip hot plug not supported. biosmust set to 0 0b rwo 03 aip hot plug not supported. biosmust set to 0 0b rwo 02 msp hot plug not supported. biosmust set to 0 0b rwo 01 pcp hot plug not supported. biosmust set to 0 0b rwo 00 abp hot plug not supported. biosmust set to 0 0b rwo table 16-191.offset 78h: peasltcap - pci expre ss slot capabilities register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:2:0 offset start: offset end: 78h 7bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-192.offset 78h: pea1sltcap - pci expre ss slot capabilities register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:3:0 offset start: offset end: 78h 7bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 19 psn physical slot number: this hardware initialized field indicates the physical slot number attached to this port. this field must be hardware initialized to a value that assigns a slot number that is globally unique within the chassis. this field must be initialized to 0 for ports connected to devices that are integrated on the motherboard. 000h rwo 18 : 17 reserved reserved 00b 16 : 15 spls slot power limit scale specifies the scale used for the slot power limit value. 00b = 1.0x (25.5?255) 01b = 0.1x (2.55?25.5) 10b = 0.01x (0.255?2.55) 11b = 0.001x (0.0?0.255) 00b rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 567 intel ? ep80579 integrated processor 14 : 07 splv slot power limit value in combination with the slot power limit scale value, this register specifies the upper limit on power supplied by slot. power limit (in watts) calculated by multiplying the value in this field by the value in the slot power limit scale field. this field must be programmed at boot. writing to this field triggers a set_slot_power_limit inband pci express* message. 00h rwo 06 hotpc hot plug is not supported hot plug capable: 0b ro 05 hotps hot plug is not supported. hot plug surprise: 0b ro 04 pip hot plug is not supported power indicator present: 0b ro 03 aip hot plug is not supported attention indicator present: 0b ro 02 msp hot plug is not supported mrl sensor present: 0b ro 01 pcp hot plug is not supported power controller present: . 0b ro 00 abp hot plug is not supported attention button present: 0b ro table 16-192.offset 78h: pea1sltcap - pci express slot capabilities register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:3:0 offset start: offset end: 78h 7bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 568 order number: 320066-003us 16.4.1.54 offset 7ch: peasltctl - pci express* slot control register this register controls pci express* slot specific parameters. hot plug is not supported. table 16-193.offset 7ch: peasltctl - pci express slot control register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 7ch 7dh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 7ch 7dh size: 16 bit default: 01c0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 00h 10 pcc hot plug not supported. power controller control 0b rw 09 : 08 pic hot plug not supported. power indicator control 01b rw 07 : 06 aic hot plug not supported. attention indicator control 11b rw 05 hpie hot plug is not supported. hot plug interrupt enable bios must leave this bit at 0 0b rw 04 ccie hot plug not supported. command complete interrupt enable 0b rw 03 pdcie hot plug not supported. presence detect changed interrupt enable . 0b rw 02 mscie hot plug not supported. mrl sensor changed interrupt enable 0b rw 01 pfdie hot plug not supported. power fault detected interrupt enable 0b rw 00 abdie hot plug not supported. attention button pressed interrupt enable: 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 569 intel ? ep80579 integrated processor 16.4.1.55 offset 7eh: peasltsts - pci express* slot status register this register provides information about pci express* slot specific parameters. hot plug is not supported. table 16-194.offset 7eh: peasltsts - pci express slot status register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 7eh 7fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 7eh 7fh size: 16 bit default: 0040h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 07 reserved reserved 000h 06 pds hot plug not supported. presence detect state 1b ro 05 mss hot plug not supported. mrl sensor state 0 = mrl closed 1 = mrl open 0b ro 04 comc hot plug not supported. command completed 0b rwc 03 pdc hot plug not supported. presence detect changed 0b rwc 02 msc hot plug not supported. mrl sensor changed 0b rwc 01 pfd hot plug not supported. power fault detected 0b rwc 00 atbp hot plug not supported. attention button pressed 0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 570 order number: 320066-003us 16.4.1.56 offset 80h: pearpctl - pci express* root port control register this register enables the forwarding of error messages based on messages received. table 16-195.offset 80h: pearpctl - pci express root port control register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 80h 83h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 80h 83h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 reserved reserved 0000000h 03 epi enable pme interrupt: enables/disables interrupt generation upon receipt of a pme message as reflected in the pme status register bit. a pme interrupt is also generated if the pme status register bit is already set when this bit is set from a cleared state. 0 = disable pme interrupt (mchpme#) generation 1 = enable pme interrupt (mchpme#) generation 0b rw 02 esefe enable system error on fatal error: controls the root complex?s response to fatal errors reported by any of the devices in the hierarchy associated with this root port. system error generation based on fatal errors also enabled by pcicmd[serre]. 0 = disable system error generation in response to fatal errors reported on this port. 1 = enable system error generation in response to fatal errors reported on this port. 0b rw 01 esenfe enable system error on non-fatal error: controls the root complex?s response to nonfatal errors reported by any of the devices in the hierarchy associated with this root port. system error generation based on non-fatal errors also enabled by pcicmd[serre]. 0 = disable system error generation in response to nonfatal errors reported on this port. 1 = enable system error generation in response to nonfatal errors reported on this port. 0b rw 00 esece enable system error on correctable error: controls the root complex?s response to correctable errors reported by any of the devices in the hierarchy associated with this root port. 0 = disable system error generation in response to correctable errors reported on this port. 1 = enable system error generation in response to correctable errors reported on this port. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 571 intel ? ep80579 integrated processor 16.4.1.57 offset 84h: pearpsts - pci express* root port status register this register supports power management events. 16.4.1.58 offset 100h: enhcapst - enhanced capability structure register this register identifies the capability structure and points to the next structure. this enhanced configuration structure by definition starts at configuration offset 100h. table 16-196.offset 84h: pearpsts - pci express root port status register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 84h 87h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 18 reserved reserved 0000h 17 pmep pme pending: 0 = cleared by hardware when no more pmes are pending. 1 = indicates that another pme is pending when the pme status bit is set. 0b ro 16 pmes pme status: 0 = cleared by software writing a ?1? to the bit location. 1 = pme has been asserted by the requestor indicated in the pme requestor id field. note: subsequent pmes are kept pending until cleared by software. 0b rwc 15 : 00 pmerid pme requestor id: indicates the pci requestor id of the last pme requestor. 0000h ro table 16-197.offset 100h: enhcapst - enhanced capability structure register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 100h 103h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 100h 103h size: 32 bit default: 00010001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 ncp next capability pointer: this field is hardwired to 000h to indicate that there are no other items in the capability list. 000h ro 19 : 16 cv capability version: hardwired to 1h, to indicate pci express* interface specification, rev 1.0a . 1h ro 15 : 00 extended_cap_ id hardwired to 0001h, to indicate advanced error reporting capability. 0001h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 572 order number: 320066-003us 16.4.1.59 offset 104h: uncerrsts - uncorrectable error status register the uncorrectable error status register reports the status of individual error sources on the pci express* device. an individual error status bit that is set indicates that a particular error occurred. software may clear an error status bit by writing a ?1? to the bit location. these bits are sticky through reset. table 16-198.offset 104h: uncerrsts - uncorrectable error status register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 104h 107h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 104h 107h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 21 reserved reserved 000h 20 usr_uncerrs ts unsupported request this error, if the first uncorrectable error, loads the he ader log. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = unsupported request detected. y0b rwc 19 ees ecrc error status. note: ecrc is not supported for the ep80579. y0b ro 18 mts malformed tlp status. this error, if the first uncorrectable error, loads the header log. malformed tlp errors include: data payload length issues, byte enable rule violations, and various other illegal field settings. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = malformed tlp detected y0b rwc 17 ros receiver overflow status optional pci express* specification bit, implemented for imch. this error, if the first uncorrectable error, loads the header log. imch checks for overflows on the following upstream queues: posted, non-posted, and completion. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = receiver overflow detected. y0b rwc 16 ucs unexpected completion status. this bit is set when the device receives a completion which does not correspond to any of the outstanding requests issued by that device. this error, if the first uncorrectable error, loads the header log. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = unexpected completion detected. y0b rwc 15 cas completer abort status optional pci express* specification bit, implemented for imch. if a request received violates the specific programming model of this device, but is otherwise legal, this bit is set. this error, if the first uncorrectable error, load the header log. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = completer abort detected. y0b rwc 14 cts completion timeout status the completion timeout timer must expire if a request is not completed in 50 ms, but must not expire earlier than 50 s. when the timer expires, this bit is set. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = completion timeout detected. y0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 573 intel ? ep80579 integrated processor 13 fcpes flow control protocol error status optional pci express* specification bit, implemented for imch. 0 = cleared by writing a ?1? to the bit location. 1 = flow control protocol error detected. cmi asserts this bit for one of two conditions: ? an fc update has been received which describes header or data credits for p, np, or cpl which were originally advertised as infinite during initialization but are now advertised with non-zero or non-infinite values. ? the number of credits advertised in an update is less than the number of credits in the previous update. the hardware accepts this flow control update, as it cannot determine if this update or the previous one was in error. note: this bit is sticky through reset. y0b rwc 12 pts poisoned tlp status this bit when set indicates that some portion of the tlp data payload was corrupt. this error, if the first uncorrectable error, loads the header log. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = poisoned tlp detected. y0b rwc 11 : 05 reserved reserved 00h 04 dlpes data link protocol error status this bit is set when an ack/nak received does not specify the sequence number of an unacknowledged tlp, or of the most recently acknowledged tlp. this bit is sticky through reset. 0 = cleared by writing a ?1? to the bit location. 1 = data link protocol error detected. y0b rwc 03 : 00 reserved reserved 000b table 16-198.offset 104h: uncerrsts - uncorrectable error status register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 104h 107h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 104h 107h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 574 order number: 320066-003us 16.4.1.60 offset 108h: uncerrmsk - uncorrectable error mask register the uncorrectable error mask register controls reporting of individual errors by device to the pci express* root complex via a pci express* error message. a masked error (respective bit set in mask register) is not reported to the pci express root complex by an individual device. however, masked errors are still logged in the uncorrectable error status register. there is one mask bit corresponding to every implemented bit in the uncorrectable error status register. these bits are sticky through reset. table 16-199.offset 108h: uncerrmsk - uncorrectable error mask register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 108h 10bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 108h 10bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 21 reserved reserved 000h 20 usr_uncerrm sk unsupported request: 0 = report unsupported request error 1 = mask unsupported request error y0b rw 19 eem ecrc error mask: note: ecrc is not supported for the ep80579. y0b ro 18 mtm malformed tlp mask: 0 = report malformed tlp error 1 = mask malformed tlp error y0b rw 17 rom receiver overflow mask: optional pci express* specification bit, implemented for. 0 = report receiver overflow error 1 = mask receiver overflow error y0b rw 16 ucm unexpected completion mask : 0 = report receiver overflow error 1 = mask receiver overflow error y0b rw 15 cam completer abort mask: optional pci express* specification bit, implemented for . 0 = report completer abort error 1 = mask completer abort error y0b rw 14 ctm completion timeout mask: 0 = report completion timeout error 1 = mask completion timeout error y0b rw 13 fcpem flow control protocol error mask: optional pci express* specification bit, implemented for . 0 = report flow control protocol error 1 = mask flow control protocol error y0b rw 12 ptm poisoned tlp mask: 0 = report poisoned tlp error 1 = mask poisoned tlp error y0b rw 11 : 05 reserved reserved 00h 04 dlpem data link protocol error mask: 0 = report data link protocol error 1 = mask data link protocol error y0b rw 03 : 00 reserved reserved 000b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 575 intel ? ep80579 integrated processor 16.4.1.61 offset 10ch: uncerrsev - uncorrectable error severity register the uncorrectable error severity register controls whether an individual error is reported as a nonfatal or fatal error. an error is reported as fatal when the corresponding error bit in the severity register is set. if the bit is cleared, the corresponding error is considered nonfatal. these bits are sticky through reset. table 16-200.offset 10ch: uncerrsev - uncorrectable error severity register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 10ch 10fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 10ch 10fh size: 32 bit default: 00062010h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 21 reserved reserved 000h 20 usr_uncerrs ev unsupported request: 0 = nonfatal 1 = fatal y0b rw 19 eesev ecrc error severity: note: ecrc is not supported for the ep80579. y0b ro 18 mtsev malformed tlp severity: 0 = nonfatal 1 = fatal y1b rw 17 rosev receiver overflow severity: optional pci express* specification bit, implemented for imch. 0 = nonfatal 1 = fatal y1b rw 16 ucsev unexpected completion severity: 0 = nonfatal 1 = fatal y0b rw 15 casev completer abort severity [sticky]: optional pci express* specification bit, implemented for imch. 0 = nonfatal 1 = fatal y0b rw 14 ctsev completion timeout severity: 0 = nonfatal 1 = fatal y0b rw 13 fcpesev flow control protocol error severity: optional pci express* specification bit, implemented for imch. 0 = nonfatal 1 = fatal y1b rw 12 ptsev poisoned tlp severity: 0 = nonfatal 1 = fatal y0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 576 order number: 320066-003us 16.4.1.62 offset 110h: corerrsts - co rrectable error status register the correctable error status register reports the status of individual error sources on the pci express* device. an individual error status bit that is set indicates that a particular error occurred. software may clear an error status bit by writing a ?1? to the bit location. these bits are sticky through reset. 11 : 05 reserved reserved 00h 04 dlpesev data link protocol error severity: 0 = nonfatal 1 = fatal y1b rw 03 : 00 reserved reserved 000b ro table 16-200.offset 10ch: uncerrsev - uncorrectable error severity register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 10ch 10fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 10ch 10fh size: 32 bit default: 00062010h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-201.offset 110h: corerrsts - correctable error status register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 110h 113h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 110h 113h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 13 reserved reserved 00000h 12 rtts replay timer timeout status: the replay timer counts time since the last ack or nak dllp was received. when the timer expires, this bit is set. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = replay timer timeout detected. y0b rwc 11 : 09 reserved reserved 000b 08 rnrs replay_num rollover status: a 2-bit counter counts the number of times the retry buffer has been retransmitted. when this counter rolls over, this bit is set. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = replay_num rollover detected. y0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 577 intel ? ep80579 integrated processor 07 bds bad dllp status: this bit is set when the calculated dllp crc is not equal to the received value. this bit is sticky through system reset. 0 = cleared by writing a ?1? to the bit location. 1 = bad dllp detected. y0b rwc 06 bts bad tlp status: 0 = tlp status good. 1 = this bit is set when the calculated tlp crc is not equal to the received value. also included are invalid sequence numbers. y0b rwc 05 : 01 reserved reserved 000b 00 res receiver error status: optional pci express* specification bit, implemented for imch. data is delivered over pci express* via packets built out of 8b/10b symbols. receiver error status register is set for 8b/10b errors received, framing errors received irrespective of the packet boundaries. 0 = cleared by writing a ?1? to the bit location. 1 = receiver error detected. y0b rwc table 16-201.offset 110h: corerrsts - correctable error status register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 110h 113h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 110h 113h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 578 order number: 320066-003us 16.4.1.63 offset 114h: corerrmsk - correctable error mask register the correctable error mask register controls re porting of individual errors by device to the pci express* root complex via a pci express* error message. a masked error (respective bit set in mask register) is not reported to the pci express* root complex by an individual device. however, masked errors are still logged in the correctable error status register. there is one mask bit corresponding to every implemented bit in the correctable error status register. these bits are sticky through reset. table 16-202.offset 114h: corerrmsk - correctable error mask register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 114h 117h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 114h 117h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 13 reserved reserved 00000h 12 rttm replay timer timeout mask: this bit is sticky through system reset. 0 = report replay timer timeout error. 1 = mask replay timer timeout error. y0b rw 11 : 09 reserved reserved 000b 08 rnrm replay_num rollover mask: this bit is sticky through system reset. 0 = report replay_num rollover 1 = mask replay_num rollover. y0b rw 07 bdm bad dllp mask: this bit is sticky through system reset. 0 = report bad dllp error. 1 = mask bad dllp error. y0b rw 06 btm bad tlp mask: this bit is sticky through system reset. 0 = report bad tlp error. 1 = mask bad tlp error. y0b rw 05 : 01 reserved reserved 0000b 00 rem receiver error mask: this bit is sticky through system reset. 0 = report receiver error. 1 = mask receiver error. y0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 579 intel ? ep80579 integrated processor 16.4.1.64 offset 118h: aercacr - advanced error capabilities and control register this register identifies the capability structure and points to the next structure. the first error pointer rearms after the unmasked errors have been cleared. software after clearing the errors must read the register again to ensure that it is indeed cleared. if it finds that another error occurred, it can not rely on the pointer or header, unless it detects that the error pointer changed from the last time it was read for the previous error. bits in this register also declare the ecrc capability of this device. these bits are sticky through reset. table 16-203.offset 118h: aercacr - advanced error capabilities and control register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 118h 11bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 118h 11bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 09 reserved reserved 000000h 08 ece ecrc check enable note: ecrc is not supported for the ep80579. y0b ro 07 ec ecrc check capable note: ecrc is not supported for the ep80579. 0b ro 06 ege ecrc generation enable note: ecrc is not supported for the ep80579. y0b ro 05 egc ecrc generation capable note: ecrc is not supported for the ep80579. 0b ro 04 : 00 fep first error pointer identifies the bit position of the first error reported in the uncorrectable error status register. however, if a subsequent uncorrectable error occurs with a higher severity, this field is over-written with the bit position of the subsequent error status bit. also, if multiple errors of equal severity are logged simultaneously, this field identifies the bit position of the most significant (leftmost) bit that has been set in the uncorrectable error status register. in the event of simultaneous errors, the pointer indicates the least significant bit of the group. this bit is sticky through system reset. y 00000b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 580 order number: 320066-003us 16.4.1.65 offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register this register contains the first 32 bits of the header log locked down when the first uncorrectable error occurs that saves the header. to rearm this register all report uncorrectable errors must be cleared from the register. software after clearing the errors must read the register again to ensure that it is indeed cleared. if it finds that another error occurred, it can not rely on the pointer or header, unless it detects that the error pointer changed from the last time it was read for the previous error. byte 0 of the header is located in byte 3 of the header log register 0, byte 1 of the header is in byte 2 of the header log register 0 and so forth. for 12 byte headers, only the first three of the four header log registers are used, and values in hdrlog3 are undefined. these bits are sticky through reset. 16.4.1.66 offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register the function of the header log registers is described in section 16.4.1.65, ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? . header log dw1 contains the second 32 bits of the header. byte 4 of the header is located in byte 3 of the header log register 1, byte 5 of the header is in byte 2 of the header log register 1 and so forth. these bits are sticky through reset. table 16-204. offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 11ch 11fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 11ch 11fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 hl0 header log 0 a masked error (respective bit set to ?1? in mask register) is not logged in the header log register, does not update the first error pointer, and is not reported to the pci express* root complex by an individual device. y 00000000h ro table 16-205.offset 120h: hdrlog1 - header log dw 1 (2nd 32 bits) register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 120h 123h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 120h 123h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 hl1 header log 1 a masked error (respective bit set to ?1? in mask register) is not logged in the header log register, does not update the first error pointer, and is not reported to the pci express* root complex by an individual device. these bits are sticky through system reset. y 00000000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 581 intel ? ep80579 integrated processor 16.4.1.67 offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register the function of the header log registers is described in section 16.4.1.65, ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? . header log dw2 contains the third 32 bits of the header. byte 8 of the header is located in byte 3 of the header log register 2, byte 9 of the header is in byte 2 of the header log register 2 and so forth. these bits are sticky through reset. 16.4.1.68 offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register the function of the header log registers is described in section 16.4.1.65, ?offset 11ch: hdrlog0 - header log dw 0 (1st 32 bits) register? . header log dw3 contains the fourth 32 bits of the header. for 16-byte headers, byte 12 of the header is located in byte 3 of the header log register 3, byte 13 of the header is in byte 2 of the header log register 3 and so forth. for 12 byte headers, values in this register are undefined. these bits are sticky through reset. table 16-206.offset 124h: hdrlog2 - header log dw 2 (3rd 32 bits) register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 124h 127h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 124h 127h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 hl2 header log 2 a masked error (respective bit set to ?1? in mask register) is not logged in the header log register, does not update the first error pointer, and is not reported to the pci express* root complex by an individual device. these bits are sticky through system reset. y 00000000h ro table 16-207.offset 128h: hdrlog3 - header log dw 3 (4th 32 bits) register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 128h 12bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 128h 12bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 hl3 header log 3 a masked error (respective bit set to ?1? in mask register) is not logged in the header log register, does not update the first error pointer, and is not reported to the pci express* root complex by an individual device. these bits are sticky through system reset. y 00000000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 582 order number: 320066-003us 16.4.1.69 offset 12ch: rperrcmd - root (port) error command register this register controls the generation of interrupts (beyond the basic root complex capability to generate system errors) upon detection of errors. system error generation in response to pci express* error messages may be turned off by system software using the pci express* capability struct ure when advanced error reporting via interrupts is enabled. these bits are sticky through reset. table 16-208.offset 12ch: rperrcmd - root (port) error command register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 12ch 12fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 12ch 12fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 03 reserved reserved 0000000h 02 feie fatal error interrupt enable: enables the generation of an interrupt when a fatal error is reported by any of the devices in the hierarchy associated with this root port. this bit is sticky through reset. 0 = disable interrupt generation on fatal error. 1 = enable interrupt generation on fatal error. y0b rw 01 neie nonfatal error interrupt enable: enables the generation of an interrupt when an nonfatal error is reported by any of the devices in the hierarchy associated with this root port. this bit is sticky through reset. 0 = disable interrupt generation on nonfatal error. 1 = enable interrupt generation on nonfatal error. y0b rw 00 ceie correctable error interrupt enable: enables the generation of an interrupt when a correctable error is reported by any of the devices in the hierarchy associated with this root port. this bit is sticky through reset. 0 = disable interrupt generation on correctable error. 1 = enable interrupt generation on correctable error. y0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 583 intel ? ep80579 integrated processor 16.4.1.70 offset 130h: rperrmsts - root (port) error message status register this register reports the status of errors received by the root complex. each correctable and uncorrectable (nonfatal and fatal) error source has a first error bit and a next error bit. when an error is received by the root complex, the associated first error bit is set and the requestor id is logged in the error source identification register. software may clear an error status bit by writing a ?1? to the bit location. if software does not clear the first reported error before another error is received, the next error status bit is set, but the requestor id of the subsequent error message is discarded. these bits are sticky through reset. table 16-209.offset 130h: rperrmsts - root (port) error message status register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 130h 133h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 130h 133h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 27 aeimn advanced error interrupt message number: if this function has been allocated more than one msi interrupt number, this field reflects the offset between the base message data and the msi message that is generated when any of the status bits of this capability are set. 0h ro 26 : 07 reserved reserved 000000h 06 femd fatal error messages detected: this bit is used by error handling software to determine whether fatal errors are outstanding in the hierarchy. in hardware, this bit along with bits 4 and 2 is used to clear fatal error escalation. these bits are sticky through system reset. 0 = software clears this bit by writing a ?1? to the bit location. 1 = fatal error message detected. y0b rwc 05 nfemd non-fatal error messages detected: this bit is used by error handling software to determine whether non-fatal errors are outstanding in the hierarchy. in hardware, this bit along with bits 4 and 2 is used to clear non-fatal error escalation. these bits are sticky through system reset. 0 = software clears this bit by writing a ?1? to the bit location. 1 = non-fatal error message detected. y0b rwc 04 fuff first uncorrectable fatal flag: this bit captures the nature of the first uncorrectable error message detected (and logged in the error source id register). these bits are sticky through system reset. 0 = first uncorrectable error is non-fatal. 1 = first uncorrectable error is fatal. software uses this flag to determine whether the uncorrectable error source id belongs to the fatal or non- fatal error handler routine in the event that the two are independent. y0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 584 order number: 320066-003us 03 muemd multiple uncorrectable error messages detected in the unlikely event of two first errors occurring during the same clock period, only the first uncorrectable error message bit is set. it takes an error to occur in a subsequent clock to set this bit. these bits are sticky through system reset. 0 = software clears this bit by writing a ?1? to the bit location. 1 = set when either a fatal or nonfatal error is received, and the first uncorrectable error detected bit is already set. this indicates that one or more message requestor ids were lost. y0b rwc 02 fuemd first uncorrectable error message detected the root error status bit reports status of error messages (err_nonfatal and err_fatal) received by the root complex, and of errors detected/reported (not masked) by the root port itself. these bits are sticky through system reset. 0 = software clears this bit by writing a ?1? to the bit location. 1 = set when the first fatal or nonfatal error is received. y0b rwc 01 mcemd multiple correctable error messages detected in the unlikely event of two first errors occurring during the same clock period, only the first correctable error message bit is set. it takes an error to occur in a subsequent clock to set this bit. these bits are sticky through system reset. 0 = software clears this bit by writing a ?1? to the bit location. 1 = set when a correctable error is received, and the first correctable error detected bit is already set. this indicates that one or more message requestor ids were lost. y0b rwc 00 fcemd first correctable error message detected the root error status bit reports status of error messages (err_cor) received by the root complex, and of errors detected/reported (not masked) by the root port itself. these bits are sticky through system reset. 0 = software clears this bit by writing a ?1? to the bit location. 1 = set when the first correctable error is received. y0b rwc table 16-209.offset 130h: rperrmsts - root (port) error message status register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 130h 133h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 130h 133h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 585 intel ? ep80579 integrated processor 16.4.1.71 offset 134h: errsid - error source id register this register reports the source (requestor id) of the first correctable and uncorrectable (fatal or nonfatal) errors reported in the root error status register. this register is updated regardless of the settings of the root control register and the root error command register. these bits are sticky through reset. 16.4.1.72 offset 140h: peauniterr - pci express* unit error register this register is specific to the imch. it captures the non-pci express* unit errors (those beyond the scope of the bus specification). the unit error mechanism is parallel to that used by ?compatible? error registers and masks, but cannot feed back into standard registers because that would confuse standardized error handling software (which would not understand the extracurricular error bits). escalation is controlled via the peaerrdocmd register (d2, f0:140-143h) for both standard and -specific error types. uncorrectable fatal errors feed into the fatal reporting select, uncorrectable non- fatal errors feed into the non-fatal reporting select, and correctable errors feed into the correctable reporting select. the lower nibble is for hpc related errors. table 16-210.offset 134h: errsid - error source id register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 134h 137h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 134h 137h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 uesid uncorrectable error source id requestor id of the source when an uncorrectable error (fatal or nonfatal) is received, and the first uncorrectable error detected bit is not already set. since this id could be for an internally detected error or from a message received from the other end of the link, in the event of errors detected in the same clock, priority is given to the error received from the link, and that id is what is logged. these bits are sticky through system reset. y 0000h ro 15 : 00 cesid correctable error source id requestor id of the source when an correctable error is received, and the first correctable error detected bit is not already set. since this id could be for an internally detected error or from a message received from the other end of the link, in the event of errors detected in the same clock, priority is given to the error received from the link, and that id is what is logged. these bits are sticky through system reset. y 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 586 order number: 320066-003us table 16-211.offset 140h: peauniterr - pci express unit error register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 140h 143h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 140h 143h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved for future additions. 0000h 15 upqos upstream posted queue overflow status: this bit is one of the components of the receiver overflow status bit in the uncerrsts register. even though this bit can be set, it is only reported through the receiver overflow bit in the uncerrsts register. the setting of this bit is never logged in the local ferr/nerr registers or subsequently the global ferr/nerr registers, nor does it cause a sci/ smi/serr or mcerr message. at most, when the report mask, is disabled, it could affect the unit error pointer. this functionality is provided as an aid to debug. 0 = software clears this bit by writing a ?1? to the bit position. 1 = overflow occurred for one of the posted header or data queues. y0b rwc 14 unpqos upstream non-posted queue overflow status: this bit is set if an overflow occurs for the non-posted header queue. there is no upstream non-posted data queue. it is one of the components of the receiver overflow status bit in the uncerrsts register. even though this bit can be set, it is only reported through the receiver overflow bit in the uncerrsts register. the setting of this bit is never logged in the local ferr/nerr registers or subsequently the global ferr/nerr registers, nor is it a cause for a sci/ smi/serr or mcerr message. at most, when the report mask, is disabled, it could affect the unit error pointer. this functionality is provided as an aid to debug. 0 = software clears this bit by writing a ?1? to the bit position. 1 = overflow occurred for the non-posted header queues. y0b rwc 13 ucqos upstream completion queue overflow status [sticky]: this bit is set if an overflow occurs for either the completion header or data queues it is one of the components of the receiver overflow status bit in the uncerrsts register. even though this bit can be set, it is only reported through the receiver overflow bit in the uncerrsts register. the setting of this bit is never logged in the local ferr/nerr registers or subsequently the global ferr/nerr registers, nor is it a cause a sci/smi/ serr or mcerr message. this functionality is provided as an aid to debug. 0 = software clears this bit by writing a ?1? to the bit position. 1 = overflow occurred for one of the completion header or data queues. y0b rwc 12 lpe 0 = lle protocol error [sticky]: this bit is set when the transaction layer detects a protocol error on the receiver interface from the lle. such an event should cause retraining eventually, but not necessarily immediately. the transaction with a problem is dropped. software clears this bit by writing a ?1? to the bit position. 1 = transaction layer detected a protocol error on the receiver interface from the lle y0b rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 587 intel ? ep80579 integrated processor 11 lde 0 = link down error [sticky]: software clears this bit by writing a ?1? to the bit position. 1 = set when the link transitions from dl_up to dl_down. y0b rwc 10 ddqpe downstream data queue parity error [sticky]: a parity error occurred in the downstream data queue. 0 = software clears this bit by writing a ?1? to the bit position. 1 = parity error occurred in the downstream data queue. y0b rwc 09 reserved reserved 0b 08 reserved reserved 0b 07 reserved reserved 0b 06 reserved reserved 0b 05 reserved reserved. 0b 04 commblkpar common block parity error [sticky]: indicates that a parity error occurred on a configuration register within the common block. 0 = no parity error 1 = parity error occurred. y0b rwc 03 reserved reserved. 0b 02 smbclto smb clock low timeout [sticky]: . 0 = software clears this bit by writing a ?1? to the bit position. 1 = smb clk low greater than 25 ms. y0b rwc 01 uesmbn unexpected nak on smb [sticky] : 0 = software clears this bit by writing a ?1? to the bit position. 1 = unexpected nak on smb detected. y0b rwc 00 smbla smb lost bus arbitration. (correctable) [sticky]: this bit is sticky through reset. 0 = software clears this bit by writing a ?1? to the bit position. 1 = smb lost bus arbitration. y0b rwc table 16-211.offset 140h: peauniterr - pci express unit error register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 140h 143h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 140h 143h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 588 order number: 320066-003us 16.4.1.73 offset 144h: peamaskerr - pci express* unit mask error register this register is used for selecting the global error reporting method for the various error conditions. table 16-212.offset 144h: peamaskerr - pci express unit mask error register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 144h 147h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 144h 147h size: 32 bit default: 0000e000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved for future additions. 0000h 15 upqom upstream posted queue overflow mask: defaults to masked, normally reported through pci express* receive overflow status bit. 0 = enable upstream posted queue overflow reporting. 1 = disable upstream posted queue overflow reporting. y1b rw 14 unpqom upstream non-posted queue overflow mask: defaults to masked, normally reported through pci express* receive overflow status bit. 0 = enable upstream non-posted queue overflow reporting. 1 = disable upstream non-posted queue overflow reporting. y1b rw 13 ucqom upstream completion queue overflow mask: defaults to masked, normally reported through pci express* receive overflow status bit. 0 = enable upstream completion queue overflow reporting. 1 = disable upstream completion queue overflow reporting. y1b rw 12 lpem lle protocol error mask: 0 = enable lle protocol error reporting. 1 = disable lle protocol error reporting. y0b rw 11 ldem link down error mask: mask reporting of detected link transitions from dl_up to dl_down. 0 = enable link down error mask reporting. 1 = disable link down error mask reporting. y0b rw 10 ddqperm downstream data queue parity error reporting mask: 0 = enable 1 = disable y0b rw 09 reserved reserved 0b 08 reserved reserved 0b 07 reserved reserved 0b 06 reserved reserved 0b 05 reserved reserved 0b 04 commblk- parrm common block parity reporting mask : 0 = enable commblkpar reporting. 1 = disable commblkpar reporting. y0b rw 03 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 589 intel ? ep80579 integrated processor 16.4.1.74 offset 148h: peaerrdocmd - pci express* error do command register this register supports pci express* error commands for doing various signaling. do_sci, do_smi, and do_ mcerr , do_serr must further be enabled by the pci express* host do command register. 02 smbcltorm smbclto reporting mask]: 0 = enable smbclto reporting. 1 = disable smbclto reporting. y0b rw 01 uesmbnrm uesmbn reporting mask : 0 = enable uesmbn reporting. 1 = disable uesmbn reporting. y0b rw 00 smblarm smbla reporting mask : 0 = enable smbla reporting. 1 = disable smbla reporting. y0b rw table 16-212.offset 144h: peamaskerr - pci express unit mask error register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 144h 147h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 144h 147h size: 32 bit default: 0000e000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-213.offset 148h: peaerrdocmd - pci express error do command register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 148h 14bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 148h 14bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 reserved reserved 000b 28 : 24 fepupce first error pointer for unmasked pci express* correctable errors this pointer is rearmed when all unmasked errors have been cleared. in the event of simultaneous errors, the pointer indicates the least significant bit of the group. these bits are sticky. y 00h ro 23 : 21 reserved reserved 000b 20 : 16 feppe first error pointer for pci express*-unit errors this pointer is locked once any units errors are logged in the peaferr. it is rearmed when all peaunit errors have been cleared. in the event of simultaneous errors, the pointer indicates the least significant bit of the group. this pointer is only valid for an error that is enabled for reporting. these bits are sticky. y 00h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 590 order number: 320066-003us 15 ehlulpe enable header log use for lle protocol error: the header log is used by pci express* uncorrectable errors. this feature is used to capture the header log for the lle protocol error in the unit error register during debug. 0 = disable 1 = enable 0b rw 14 pure pci express* unit report enable: this bit enables reporting of fatal or non-fatal or correctable unit errors. 0 = disable 1 = enable 0b rw 13 : 12 pursfe pci express* unit report steering for fatal errors: 00b= sci 10b=serr 01b= smi 11b=mcerr 00b rw 11 : 10 pursnfe pci express* unit report steering for non-fatal errors: 00b=sci 10b=serr 01b= smi 11b=mcerr 00b rw 09 : 08 pursce pci express* unit report steering for correctable errors: 00b=sci 10b=serr 01b= smi 11b=mcerr 00b rw 07 : 06 reserved reserved 00b 05 : 04 rprsfe root port report steering for fatal errors: if the system error on fatal error bit in the root port control register is set, all fatal root port errors are reported via serr regardless of the setting of this register. msi enable takes precedence for this capability feature. 00b= sci 10b=serr 01b= smi 11b=mcerr 00b rw 03 : 02 rprsnfe root port report steering for non-fatal errors: if the system error on nonfatal error bit in the root port control register is set, all nonfatal root port errors are reported via serr regardless of the setting of this register. msi enable takes precedence for this capability feature. 00b= sci 10b=serr 01b= smi 11b=mcerr 00b rw 01 : 00 rprsce root port report steering for correctable errors: if the system error on correctable error bit in the root port control register is set, all correctable root port errors are reported via serr regardless of the setting of this register. note that msi enable takes precedence for this capability feature. 00b= sci 10b=serr 01b= smi 11b=mcerr 00b rw table 16-213.offset 148h: peaerrdocmd - pci express error do command register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 148h 14bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 148h 14bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 591 intel ? ep80579 integrated processor 16.4.1.75 offset 14ch: uncedmask - unco rrectable error detect mask register the uncorrectable error detect mask register controls detection of the individual errors. an error event that is masked in this register, is treated as though the error never happened, and is subsequently not logged in the uncorrectable error status register, nor is it ever reported. there is one mask bit corresponding to every implemented bit in the uncorrectable error status register. this register is specific to the imch. these bits are sticky through reset. table 16-214.offset 14ch: uncedmask - uncorrectable error detect mask register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 14ch 14fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 14ch 14fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 21 reserved reserved 00000000000b 20 uredm unsupported request error detect mask. [sticky]: 0 = detect unsupported request error 1 = disable unsupported request error detection y0b rw 19 reserved note: reserved y 0b ro 18 mtedm malformed tlp error detect mask. [sticky]: 0 = detect malformed tlp error 1 = disable malformed tlp error detection y0b rw 17 roedm receiver overflow error detect mask. [sticky]: optional 0 = detect receiver overflow error 1 = disable receiver overflow error detection y0b rw 16 ucedm unexpected completion error detect mask. [sticky]: 0 = detect unexpected completion error 1 = disable unexpected completion error detection y0b rw 15 caedm completer abort error detect mask. [sticky]: optional 0 = detect completer abort error 1 = disable completer abort error detection y0b rw 14 ctedm completion timeout error detect mask. [sticky]: 0 = detect completion timeout error 1 = disable completion timeout error detection y0b rw 13 fcpedm flow control protocol error detect mask. [sticky]: optional 0 = detect flow control protocol error 1 = disable flow control protocol error detection y0b rw 12 ptedm poisoned tlp error detect mask. [sticky]: 0 = detect poisoned tlp error 1 = disable poisoned tlp error detection y0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 592 order number: 320066-003us 16.4.1.76 offset 150h: coredmask - correctable error detect mask register the correctable error detect mask register controls detection of the individual errors. an error event that is masked in this regi ster is not logged in the correctable error status register, and is never reported. there is one mask bit corresponding to every implemented bit in the correctable error status register. these bits are sticky through reset. 11 : 05 reserved reserved 0000000b 04 dlpedm data link protocol error detect mask. [sticky]: 0 = detect data link protocol error 1 = disable data link protocol error detection y0b rw 03 :00 reserved reserved 0000b ro table 16-214.offset 14ch: uncedmask - uncorrectable error detect mask register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 14ch 14fh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 14ch 14fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-215.offset 150h: coredmask - correctable error detect mask register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 150h 153h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 150h 153h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 13 reserved reserved 00000h 12 rttedm replay timer timeout error detect mask. this bit is sticky through system reset. 0 = detect replay timer timeout error. 1 = disable replay timer timeout error detection. y0b rw 11 : 09 reserved reserved 000b 08 rnredm replay_num rollover error detect mask this bit is sticky through system reset. 0 = detect replay_num rollover 1 = disable replay_num rollover detection. y0b rw 07 bdedm bad dllp error detect mask this bit is sticky through system reset. 0 = detect bad dllp error. 1 = disable bad dllp error detection. y0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 593 intel ? ep80579 integrated processor 06 btedm bad tlp error detect mask optional. this bit is sticky through system reset. 0 = detect bad tlp error. 1 = disable bad tlp error detection. y0b rw 05 : 01 reserved reserved 0000b 00 redm receiver error detect mask optional. this bit is sticky through system reset. 0 = detect receiver error. 1 = disable receiver error error detection. y0b rw table 16-215.offset 150h: coredmask - correcta ble error detect mask register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 150h 153h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 150h 153h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 594 order number: 320066-003us 16.4.1.77 offset 158h: peaunitedmask - pci express* unit error detect mask register this register is specific to the imch, and controls detection of the pci express* functional unit error conditions. these bits are sticky through reset. table 16-216.offset 158h: peaunitedmask - pci express unit error detect mask register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 158h 15bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 158h 15bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0000h 15 upqodm upstream posted queue overflow detect mask. this bit is sticky through reset. 0 = enable upstream posted queue overflow detection. 1 = disable upstream posted queue overflow detection. y0b rw 14 unpqodm upstream non-posted queue overflow detect mask. this bit is sticky through reset. 0 = enable upstream non-posted queue overflow detection. 1 = disable upstream non-posted queue overflow detection. y0b rw 13 ucqodm upstream completion queue overflow detect mask this bit is sticky through reset. 0 = enable completion queue overflow detection. 1 = disable completion queue overflow detection. y0b rw 12 llepedm lle protocol error detect mask this bit is sticky through reset. 0 = enable lle protocol error detection. 1 = disable lle protocol error detection. y0b rw 11 mdlt mask detection of link transitions from dl_up to dl_down: 0 = enable link down error detection. 1 = disable link down error detection. 0b rw 10 ddqpedm downstream data queue parity error detect mask this bit is sticky through reset. 0 = enable downstream data queue parity error detection. 1 = disable downstream data queue parity error detection. y0b rw 09 reserved reserved 0b 08 reserved reserved 0b 07 reserved reserved 0b 06 reserved reserved 0b 05 reserved reserved. 0b 04 : 03 reserved reserved 0b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 595 intel ? ep80579 integrated processor 16.4.1.78 offset 160h: peaferr - pci express* first error register locks after first error. 02 mscltedm mask smb clock low timeout error detect mask this bit is sticky through reset. 0 = enable smb clock low timeout error detection. 1 = disable smb clock low timeout error detection. y0b rw 01 munsedm mask unexpected nak on smb error detect mask this bit is sticky through reset. 0 = enable unexpected nak on smb error detection. 1 = disable unexpected nak on smb error detection. y0b rw 00 mslbaedm mask smb lost bus arbitration error detect mistakes bit is sticky through reset. 0 = enable smb arbitration loss detection. 1 = disable smb arbitration loss detection. y0b rw table 16-216.offset 158h: peaunitedmask - pci express unit error detect mask register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 158h 15bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 158h 15bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-217.offset 160h: peaferr - pci express first error register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 160h 163h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 160h 163h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 09 reserved reserved 000000h 08 dfed device fatal error detected [sticky]: this bit is for internally detected fatal errors. 0 = no error detected 1 = error detected y0b rwc 07 dnfed device non-fatal error detected [sticky]: this bit is for internally detected non-fatal errors. 0 = no error detected 1 = error detected y0b rwc 06 dced device correctable error detected [sticky]: this bit is for internally detected correctable errors. 0 = no error detected 1 = error detected y0b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 596 order number: 320066-003us 05 usfed unit specific fatal error detected [sticky]: this bit is for fatal errors not in the pci express* specification as logged by the peauniterr register. the peamaskerr register only prevents reporting of the unit errors, but does not prevent the logging of errors in this register. 0 = no error detected 1 = error detected y0b rwc 04 usnfed unit specific non-fatal error detected [sticky]: this bit is for non-fatal errors not in the pci express* specification as logged by the peauniterr register. the peamaskerr register only prevents reporting of the unit errors, but does not prevent the logging of errors in this register. 0 = no error detected 1 = error detected y0b rwc 03 usced unit specific correctable error detected [sticky]: this bit is for correctable errors not in the pci express* specification as logged by the peauniterr register. the peamaskerr register only prevents reporting of the unit errors, but does not prevent the logging of errors in this register. 0 = no error detected 1 = error detected y0b rwc 02 femr fatal error message received [sticky]: this bit is not set for internally detected fatal errors a.k.a. virtual fatal messages. these received fatal error messages can be masked by the serr enable bit in the bridge control register, if the serr enable bit is a 0. 0 = no err_fatal message received 1 = an err_fatal message is received. y0b rwc 01 nfemr non-fatal error message received [sticky]: this bit is not set for internally detected non-fatal errors a.k.a. virtual non-fatal messages. these received non-fatal error messages can be masked by the serr enable bit in the bridge control register, if the serr enable bit is a 0. 0 = no err_nonfatal message received 1 = an err_nonfatal message is received. y0b rwc 00 cemr correctable error message received [sticky]: this bit is not set for internally detected correctable errors a.k.a. virtual correctable messages. these received correctable error messages can be masked by the serr enable bit in the bridge control register, if the serr enable bit is a 0. 0 = no err_cor message received 1 = an err_cor message is received. y0b rwc table 16-217.offset 160h: peaferr - pci express first error register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 160h 163h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 160h 163h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 597 intel ? ep80579 integrated processor 16.4.1.79 offset 164h: peanerr - pci express* next error register logs errors after ferr register is locks. 16.4.1.80 offset 168h: peaerrinjctl - error injection control register this register enables the injection of errors on incoming data streams into the core. the lower 16 bits are the corresponding flip parity bits for the cacheline of data. the upper bits in the register are for the use and control of the associated flip parity bits. table 16-218.offset 164h: peanerr - pci express next error register description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 164h 167h view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 164h 167h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access see section 16.4.1.78, ?offset 160h: peaferr - pci express* first error register? for bit definitions. table 16-219.offset 168h: peaerrinjctl - error injection control register (sheet 1 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 168h 16bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 168h 16bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 reserved reserved 00h 19 ssb stop and scream bit: this is a special control for errors going to pci express*, outgoing from the core. otherwise outgoing data errors are propagated. not supported for pci express*. 0 = data errors are propagated. 1 = data errors are not propagated only reported 0b ro 18 eddp enable/disable data poisoning: 0 = disable data poisoning - errors won?t be propagated, only good parity is generated. 1 = enable data poisoning. error injection is possible regardless of this bit setting. 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 598 order number: 320066-003us 17 ftdp flip the designated parity bits: 0 = no flip 1 = flip the designated parity bits (bits 15:00) on all data transfers into the core. if a cacheline is in progress when this register is written, wait until the start of the next cacheline to flip parity bits. 0b rw 16 ftpbndt flip the parity bits on just the next data transfer: 0 = no flip 1 = flip the designated parity bits (bits 15:00) in only the next data transfer into the core. if a cacheline is in progress when this register is written, wait until the start of the next cacheline to flip parity bits, in order to ensure all bits flipped are within the same cacheline. hardware clears this when the injection has been performed. it is possible that the error injection desired did not occur because the next data transfer was not a complete cacheline, and the error to inject was in a different portion of the cl than was transferred. the hardware still clears the inject error once bit in this case. for completions which do not have the complete address, they are assumed to be 16b aligned addresses and only use implied address bits 03:02 to steer the parity error injection to the appropriate dw. note: since read completions are a maximum of 32b, half of the injection bits are not utilized. 0b rws 15 : 00 pi parity inject bits: two bits of parity for each 64 b of data, 16 bits of parity for a cacheline. 0000h rw table 16-219.offset 168h: peaerrinjctl - error injection control register (sheet 2 of 2) description: view: pci 1 bar: configuration bus:device:function: 0:2:0 offset start: offset end: 168h 16bh view: pci 2 bar: configuration bus:device:function: 0:3:0 offset start: offset end: 168h 16bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 599 intel ? ep80579 integrated processor 16.5 memory mapped i/o registers for dram controller table 16-220.bus 0, device 0, function 0: summary of imch smrbase registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: notespad - note (sticky) pad for bios support register? on page 601 0000h 02h 03h ?offset 02h: notepad - note pad for bios support register? on page 601 0000h 40h 43h ?offset 40h: dcalcsr ? dcal control and status register? on page 602 00000000h 44h 47h ?offset 44h: dcaladdr - dcal address register? on page 606 00000000h 48h at 1h 48h at 1h ?offset 48h: dcaldata[0-71] - dram calibration data register? on page 607 00000000h 94h 96h ?offset 94h: rcvenac - receiver enable algorithm control register? on page 611 180810h 98h 9bh ?offset 98h: dsretc - dram self-refresh (sr) extended timing and control register? on page 611 5c141400h 9ch 9ch ?offset 9ch: dqsfail1 - dqs failure configuration register 1? on page 612 00h a0h a3h ?offset a0h: dqsfail0 - dqs failure configuration register 0? on page 613 00000000h a4h a7h ?offset a4h: drrtc00 - receive enable reference output timing control register? on page 615 06060606h a8h abh ?offset a8h: drrtc01 - receive enable reference output timing control register? on page 616 06060606h c4h c4h ?offset c4h: drrtc02 - receive enable reference output timing control register? on page 616 06h b4h b7h ?offset b4h: dqsofcs00 - dqs calibration register? on page 617 00000000h b8h bbh ?offset b8h: dqsofcs01 - dqs calibration register? on page 617 00000000h c6h c6h ?offset c6h: dqsofcs02 - dqs calibration register? on page 618 00h bch bfh ?offset bch: dqsofcs10 - dqs calibration register? on page 618 00000000h c0h c3h ?offset c0h: dqsofcs11 - dqs calibration register? on page 619 00000000h c7h c7h ?offset c7h: dqsofcs12 - dqs calibration register? on page 619 00h cch cfh ?offset cch: wptrtc0 - write pointer timing control register? on page 620 00000000h d0h d0h ?offset d0h: wptrtc1 - write pointer timing control 1 register? on page 621 00h d4h d7h ?offset d4h: ddqscvdp0 - dqs delay calibration victim pattern 0 register? on page 621 aaaa0a05h d8h dbh ?offset d8h: ddqscvdp1 - dqs delay calibration victim pattern 1 register? on page 622 5b339c5dh dch dfh ?offset dch: ddqscadp0 - dqs delay calibration aggressor pattern 0 register? on page 622 aaabffffh e0h e3h ?offset e0h: ddqscadp1 - dqs delay calibration aggressor pattern 1 register? on page 623 db339ce1h f0h f3h ?offset f0h: diomon - ddr i/o monitor register? on page 623 00000000h f8h fbh ?offset f8h: dramisctl - miscellaneous dram ddr cluster control register? on page 624 1011h c8h cah ?offset c8h: dramdllc - ddr i/o dll control register? on page 625 0db6c0h e8h ebh ?offset e8h: fivesreg - fixed 5s pattern register? on page 625 55555555h ech efh ?offset ech: aaaareg - fixed a pattern register? on page 626 aaaaaaaah 140h 143h ?offset 140h: mbcsr - membist control register? on page 626 00000000h 144h 147h ?offset 144h: mbaddr - memory test address register? on page 629 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 600 order number: 320066-003us 148h at 4h 14ch at 4h ?offset 148h: mbdata[0:9] - memory test data register? on page 629 00h 19ch 19fh ?offset 19ch: mb_start_addr - memory test start address register? on page 632 00h 1a0h 1a3h ?offset 1a0h: mb_end_addr - memory test end address register? on page 632 00h 1a4h 1a7h ?offset 1a4h: mblfsrsed - memory test circular shift and lfsr seed register? on page 633 00h 1a8h 1abh ?offset 1a8h: mbfaddrptr - memory test failure address pointer register? on page 633 00h 1b0h 1b3h ?offset 1b0h: mb_err_data00 - memory test error data 0? on page 634 00h 1b4h 1b7h ?offset 1b4h: mb_err_data01 - memory test error data 0? on page 634 00h 1b8h 1bbh ?offset 1b8h: mb_err_data02 - memory test error data 0? on page 634 00h 1bch 1bfh ?offset 1bch: mb_err_data03 - memory test error data 0? on page 635 00h 1c0h 1c1h ?offset 1c0h: mb_err_data04 - memory test error data 0? on page 635 00h 1c4h 1c7h ?offset 1c4h: mb_err_data10 - memory test error data 1? on page 635 00h 1c8h 1cbh ?offset 1c8h: mb_err_data11 - memory test error data 1? on page 636 00h 1cch 1cfh ?offset 1cch: mb_err_data12 - memory test error data 1? on page 636 00h 1d0h 1d3h ?offset 1d0h: mb_err_data13 - memory test error data 1? on page 636 00h 1d4h 1d5h ?offset 1d4h: mb_err_data14 - memory test error data 1? on page 637 00h 1d8h 1dbh ?offset 1d8h: mb_err_data20 - memory test error data 2? on page 637 00h 1dch 1dfh ?offset 1dch: mb_err_data21 - memory test error data 2? on page 637 00h 1e0h 1e3h ?offset 1e0h: mb_err_data22 - memory test error data 2? on page 638 00h 1e4h 1e7h ?offset 1e4h: mb_err_data23 - memory test error data 2? on page 638 00h 1e8h 1e9h ?offset 1e8h: mb_err_data24 - memory test error data 2? on page 638 00h 1ech 1efh ?offset 1ech: mb_err_data30 - memory test error data 3? on page 639 00h 1f0h 1f4h ?offset 1f0h: mb_err_data31 - memory test error data 3? on page 639 00h 1f4h 1f7h ?offset 1f4h: mb_err_data32 - memory test error data 3? on page 639 00h 1f8h 1fbh ?offset 1f8h: mb_err_data33 - memory test error data 3? on page 640 00h 1fch 1fdh ?offset 1fch: mb_err_data34 - memory test error data 3? on page 640 00h 260h 263h ?offset 260h: ddriomc0 - ddrio mode register control register? on page 641 00000078h 264h 267h ?offset 264h: ddriomc1 - ddrio mode register control register 1? on page 642 52520000h 268h 26bh ?offset 268h: ddriomc2 - ddrio mode control register 2? on page 645 039e6000h 284h at 4h 294h at 4h ?offset 284h: wl_cntl[4:0] - write levelization control register? on page 647 00000000h 298h 29bh ?offset 298h: wdll_misc - dll miscellaneous control? on page 649 00000000h table 16-220.bus 0, device 0, function 0: summary of imch smrbase registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 601 intel ? ep80579 integrated processor 16.5.1 detailed register description 16.5.1.1 offset 00h: notespad - note (sticky) pad for bios support register this dedicated 16-bit register is provided for bios. this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. 16.5.1.2 offset 02h: notepad - note pad for bios support register this dedicated 16 bit register is provided for bios. table 16-221.offset 00h: notespad - note (sticky) pad for bios support register description: view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 00h 01h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 bsr bios sticky register [sticky]: this register is used by bios. it is sticky through reset. y 0000h rw table 16-222.offset 02h: notepad - note pad for bios support register description: view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 02h 03h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 bnsr bios register: this register is used by bios. n 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 602 order number: 320066-003us 16.5.1.3 offset 40h: dcalcsr ? ddr calibration control and status register this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. note: dcalcsr is used only for calibration. mbcsr is used for memory test. table 16-223.offset 40h: dcalcsr ? dcal cont rol and status register (sheet 1 of 2) description: dcalcsr - dcal control and status register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 40h 43h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 start start operation when set to 1 by software, the operation selected by the dcalcsr.opcode is initiated. hardware clears this bit when the operation is complete. n0b rws 30 :28 fail completion status 1xx = fail, 0xx = pass note: best practice is to rely on membist following calibration to confirm a reliable dram interface. n 000b rw 27 baspat basic data pattern enable: this controls which data pattern is used for the dqs delay calibration. setting this field enables the use of the basic data pattern selected by the dcalcsr.pattern bits. when cleared, the extended data pattern specified in the ddqscvdp and ddqscadp registers is used. note: extended data pattern mode is not to be used in 2t configurations. n0b rw 26 rstregss reset registers in single step mode: reset dcaldata csr in single step calibration mode. this bit should be set during the first step of a single step calibration. it will enable hardware to clear all registers and status bits during the calibration step the same way hardware does on the first step of an automatic ?all passes? calibration. n0b rw 25 :24 reserved reserved n 00b ro 23 sglstp single step calibration operation: applies only to receive enable and dqs cal. ?1? = single step - a single step of the algorithm selected by the dcalcsr.opcode is run by hardware. no data analysis is run. ?0? = all passes - all steps of the algorithm selected by the daclcsr.opcode is run by hardware including data analysis. n0b rw 22 :21 cs chip select: this field corresponds to the chip select outputs: cs[1:0]. this field applies to nop, refresh, precharge all, and mrs/emrs commands. it also applies to receive enable, and dqs delay cal in single step mode. 01: select rank 0 10: select rank 1 00: reserved 11: reserved note: set cs to 01 for self refresh entry. hardware will automatically detect presence of a second rank/dimm and sequence self refresh entry via both chip selects if necessary. n 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 603 intel ? ep80579 integrated processor 20 :19 reserved reserved n 00b ro 18 :16 pat data pattern: for dqs cal. this sets the burst length 4 pattern for a nibble of data. the pattern is repeated for bl8. this pattern is replicated on all nibbles of the data bus. ?000? = f > 0 > f > 0 ?001? = 0 > f > 0 > f ?010? = a > 5 > a > 5 ?011? = 5 > a > 5 > a ?100? = c > 3 > c > 3 ?101? = 3 > c > 3 > c ?110? = 9 > 6 > 9 > 6 ?111? = 6 > 9 > 6 > 9 n000b rw 15 darwpr disable fifo reset: in single pass mode. applies only to receiver enable and dqs cal. when set to 1, this bit inhibits the core to ddr cluster reset signal generated during the calibration modes. this prevents the ddr cluster synchronizer fifo write pointer and data latches from being reset so that they can be read out of the cluster using the error monitor function. the reset signal can only be disabled in single step mode. when the dcalcsr.sglstp bit is set to 0, the darwpr bit has no effect. n0b rw 14 :04 opmods operation modifiers: see table 16-224 , table 16-224 , table 16-227 , and table 16-235 for details n 000h rw 3:00 opcode opcode: ?0000? = nop ?0001? = refresh (see table 16-226 ) ?0010? = pre-charge ?0011? = mrs/emrs ?0100? = self-refresh-exit (see table 16-226 ) ?0101? = automatic dqs delay calibration ?0110?= reserved ?0111? = dll bist ?1100? = automatic receive enable calibration ?1101? = self-refresh entry (see table 16-226 ) ?1110? = error monitor/read ddrio fifo ?1111? = zq calibration all other settings are reserved n 0000b rw table 16-223.offset 40h: dcalcsr ? dcal control and status register (sheet 2 of 2) description: dcalcsr - dcal control and status register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 40h 43h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 604 order number: 320066-003us table 16-224.dcalcsr.opmods in receive enable mode table 16-225.dcalcsr.opmods in zq calibration mode table 16-226.rules about issuing self-refresh and refresh commands using dcalcsr.opcode bit description 14:7 drrtc override value to use in single step mode 6:4 test point repeat number: the number of times each receive enable delay value is tested in order to reduce the effects of noise when near a timing threshold. when set to zero, hardware will repeat each step 8 times, the maximum number possible. bit description 14:3 ignored 4 =0 zq calibration long =1 zq calibration short 1 the hardware does not enforce blocking of commands for trfc period when a refresh cycle is launched using the dcalcsr.opcode. sw is responsible for ensuring that the refresh cycle time requirement is met. 2 hardware will update drc.cke[1:0] bits with a self-refresh (sr) entry or exit command is issued using dcalcsr.opcode. 3 when issuing a self-refresh entry command using dcalcsr.opcode, the dcalcsr.cs needs to be set appropriately. the self-refresh entry commands will be issued on a per rank basis. 4 when issuing a self-refresh exit command using dcalcsr.opcode, the dcalcsr.cs will be ignored. hardware will issue the second sr exit command if a second rank is present. also note that a a self- refresh exit command using the dcalcsr.opcode can be issued only once per reset cycle. hardware does support an additional mechanism through which a self-refresh command can be issued via drc.cke[1:0] (please refer to section 11.4.5, ?self-refresh? on page 302 for more details)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 605 intel ? ep80579 integrated processor table 16-227.dcalcsr.opmods in dqs cal mode table 16-228.dcalcsr.opmods in error monitor/read ddrio fifo mode bit description 14:12 single step fine dll delay: this is equivalent to dramdllc.slvlen[4:0] when running dqs cal in single step mode 11:8 single step coarse dll delay: this is equivalent to dqsofcs when running dqs cal in single step mode. 6:4 test point repeat number: the number of times each delay value is tested in order to reduce the effects of noise when near a timing threshold. when the dcalcsr.baspat bit is set to select the basic data pattern, this field sets the number of times to repeat, with zero setting a max repeat value of 8. when the extended data pattern is selected, the max repeat value becomes 15. the max repeat is still selected with a value of zero, and other values result in a number of repeats equal to 2x-1. bit description 14:3 reserved 2:0 ddrio fifo entry number. 000: entry 0 001: entry 1 010: entry 2 011: entry 3 100: entry 4 others: reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 606 order number: 320066-003us 16.5.1.4 offset 44h: dcaladdr - ddr calibration address register table 16-229.offset 44h: dcaladdr - dcal address register description: dcaladdr - dcal address register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 44h 47h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 dcaladdr dcal address and other information based on dcalcsr.opcode. see table 16-230 . n 00000000h rw table 16-230.interpretation of dcaladdr (sheet 1 of 2)based on dcalcsr.opcode bit nop, refresh, pre-charge, mrs/emrs, and self-refresh entry commands initiated by dcalcsr receive enable dqs delay cal 31 dram address bus 15:0 row address 15:0 row address 15:0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 607 intel ? ep80579 integrated processor 16.5.1.5 offset 48h: dcaldata[0-71] - dram calibration data registers 15 column address 15 to 11 & 9 to 2 column address 15 to 11 & 9 to 2 14 13 12 11 10 9 8 7 6 5 4 3 2 dram bank address bus 2:0 bank address 2:0 bank address 2:0 in dcalcsr.baspat=1 mode, not used in dcalcsr.baspat=0 mode 1 0 table 16-231.offset 48h: dcaldata[0-71] - dram calibration data register description: dcaldata - dram calibration data registers view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 48h at 1h 48h at 1h size: 8 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 dcaldata dcal data and other information based on dcalcsr.opcode. see table 16-232 . n 00h rw table 16-230.interpretation of dcaladdr (sheet 2 of 2)based on dcalcsr.opcode bit nop, refresh, pre-charge, mrs/emrs, and self-refresh entry commands initiated by dcalcsr receive enable dqs delay cal
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 608 order number: 320066-003us table 16-232.dcaldata based on dcalcsr.opcode byte receive enable dqs cal error monitor/read ddrio fifo 71 not used 70 69 preamble status dqs8 rank1 max delay dqs8 rank1 68 first edge position dqs8 rank1 min delay dqs8 rank1 67 66 65 preamble status dqs7 rank1 max delay dqs7 rank1 64 first edge position dqs7 rank1 min delay dqs7 rank1 63 62 61 preamble status dqs6 rank1 max delay dqs6 rank1 60 first edge position dqs6 rank1 min delay dqs6 rank1 59 58 57 preamble status dqs5 rank1 max delay dqs5 rank1 56 first edge position dqs5 rank1 min delay dqs5 rank1 55 54 53 preamble status dqs4 rank1 max delay dqs4 rank1 52 first edge position dqs4 rank1 min delay dqs4 rank1 51 50 49 preamble status dqs3 rank1 max delay dqs3 rank1 48 first edge position dqs3 rank1 min delay dqs3 rank1 47 46 45 preamble status dqs2 rank1 max delay dqs2 rank1 44 first edge position dqs2 rank1 min delay dqs2 rank1 43 42 41 preamble status dqs1 rank1 max delay dqs1 rank1 40 first edge position dqs1 rank1 min delay dqs1 rank1 39 38 37 preamble status dqs0 rank1 max delay dqs0 rank1 36 first edge position dqs0 rank1 min delay dqs0 rank1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 609 intel ? ep80579 integrated processor 35 even or early 72 bits of read data from the ddrio fifo 34 33 preamble status dqs8 rank0 max delay dqs8 rank0 32 first edge position dqs8 rank0 min delay dqs8 rank0 31 30 29 preamble status dqs7 rank0 max delay dqs7 rank0 28 first edge position dqs7 rank0 min delay dqs7 rank0 27 26 odd or late 72 bits of read data from the ddrio fifo 25 preamble status dqs6 rank0 max delay dqs6 rank0 24 first edge position dqs6 rank0 min delay dqs6 rank0 23 22 21 preamble status dqs5 rank0 max delay dqs5 rank0 20 first edge position dqs5 rank0 min delay dqs5 rank0 19 18 17 preamble status dqs4 rank0 max delay dqs4 rank0 not used 16 first edge position dqs4 rank0 min delay dqs4 rank0 15 14 13 preamble status dqs3 rank0 max delay dqs3 rank0 12 first edge position dqs3 rank0 min delay dqs3 rank0 11 10 9 preamble status dqs2 rank0 max delay dqs2 rank0 8 first edge position dqs2 rank0 min delay dqs2 rank0 7 6 5 preamble status dqs1 rank0 max delay dqs1 rank0 4 first edge position dqs1 rank0 min delay dqs1 rank0 3 2 1 preamble status dqs0 rank0 max delay dqs0 rank0 0 first edge position dqs0 rank0 min delay dqs0 rank0 byte receive enable dqs cal error monitor/read ddrio fifo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 610 order number: 320066-003us dcaldata receiver enable ?first edge position? byte detail bit description 7:0 at the end of a successful calibration, this register holds the drrtc setting that enables the dqs receiver as close as possible to but no earlier than the first rising dqs transiti on after the preamble. at the start of the calibration, this register is loaded with a value of 0xff. during the calibration, while the ?strobe toggle status? bit is low, this register wil l be updated with the drrtc value for the current calibration step if the dqs is found to have a value of zero. after ?strobe toggle status? goes high, this register will be updated with the drrtc value when the dqs is found to have a value of one at a calibration step. this register will no longer be updated after the ?preamble found status? bit goes high, so that it will retain the position of the rising dqs edge following immediately after the preamble. dcaldata receiver enable ?preamble status? byte detail bit description 7 strobe toggle status. hardware sets this bit if a valid high pulse is found in the strobe waveform. the requirement is (dcaldata.first_edge_position - last receiver enable delay value) > rcvenac.hwidth 6 preamble found status. hardware sets this bit if the ?pre amble found? bit asserts at any time during the calibration. 5 preamble found. last receiver enable delay value meets or exceeds the preamble width requirement setting. hardware sets this bit if: (dcaldata.first_edge_position - last receiver enable delay value) > rcvenac.pwidth 4:0 count of ?lows? minus count of ?highs? found during one set of repeated tests at the last receiver enable delay setting. see dcalcsr opmods field for a description of the repeat test function. dcaldata dqs cal min delay detail bit description 7:6 reserved 5:0 at the end of a successful calibration, this field will hold the minimum dqs delay setting that results in correct data capture in the ddr i/o capture flop. this is the left edge of the dq data eye. during the ca libration, this field is updated with the dqs delay setting of the current calibration step, until correct data capture is found. after this point no further updates are made. dcaldata dqs cal max delay detail bit description 7:6 reserved 5:0 at the end of a successful calibration, this field will hold the maximum dqs delay setting that results in correct data capture in the ddr i/o capture flop. this is the right edge of the dq data eye. during the calibration, this field is updated with the dqs delay setting at each calibration step until the minimum delay setting is found and a subsequent failure to capture correct read data occurs.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 611 intel ? ep80579 integrated processor 16.5.1.6 offset 94h: rcvenac - receiver enable algorithm control register this register contains controls for the preamble detection algorithm of the automatic receiver enable logic. rcvenac.pwidth is used to determine if a ?low? pulse in a dqs waveform is wide enough to be a preamble. rcvenac.poffset is subtracted from the dcaldata first edge position result and programmed into the drrtc registers 16.5.1.7 offset 98h: dsretc - dram self-refresh (sr) extended timing and control this register implements bits fields that control self-refresh entry and exit mechanisms that are required for acpi s3 mode of operation. table 16-233.offset 94h: rcvenac - receiver enable algorithm control register description: rcvenac: receiver enable algorithm control view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 94h 96h size: 24 bit default: 180810h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 :16 pwidth minimum preamble width limit , used to detect if a low pulse in a dqs waveform is wide enough to be a valid preamble. the default corresponds to 3/4 of a dram clock cycle y 18h rw 15 :14 reserved reserved 00b ro 13 :08 hwidth minimum high pulse width limi t, used to detect if a high pulse in a dqs waveform is wide enough to indicate a strobe is toggling in a valid manner. the default corresponds to 1/4 of a dram clock cycle. y 08h rw 7 :06 reserved reserved 00b ro 5:00 poffset preamble center offset from first rising edge, used to position the dqs receiver enable relative to the preamble edge location recorded in the dcaldata registers. the default value corresponds to 1/2 of a dram clock cycle. y 10h rw table 16-234.offset 98h: dsretc - dram self-refresh (sr) extended timing and control register description: dsretc: dram self-refresh (sr) extended timing and control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 98h 9bh size: 32 bit default: 5c141400h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 txsnr exit self-refresh to non-read command timing. number of controller cycles for which accesses to the dimms need to be blocked by memory controller. y 01011100b rw 23 :16 drsrent dual rank self-refresh (sr) entry and exit timing - stagger of self refresh commands between ranks. staggering of the sr commands result is in the power intensive refresh operations to be staggered between the 2 ranks. y 00010100b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 612 order number: 320066-003us 16.5.1.8 offset 9ch: dqsfail1 - dqsfail1 configuration register there are two dqsfail registers that contain a total of 18 individual dqs failure status bits. there is one status bit for each dqs on each rank. these bits are set automatically by hardware during the receiver enable calibration if a valid dqs waveform is not detected. hardware will not clear any bits that are set prior to the calibration even if a valid waveform is detected. hardware uses the dqsfail information to exclude calibration data during the data gathering portion and/or the data analysis portion of the both the receiver enable and dqs delay calibrations as well as mbist. this prevents a failed dqs pin from corrupting the calibration of neighboring functional dqs pins that may share internal logic resources with a failing dqs pin. for normal calibration, initialize all dqsfail bits to 0. 15 :08 drartim dual rank auto-refresh timing - stagger of commands between ranks prior to self-refresh entry. y 00010100b rw 7 :1 reserved reserved n 0000000b ro 0 0 ensrexit enable self-refresh (sr) exit state machine. this bit needs to be set by bios upon power-up from an s3 event. n0b rw table 16-234.offset 98h: dsretc - dram self-refresh (sr) extended timing and control register description: dsretc: dram self-refresh (sr) extended timing and control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 98h 9bh size: 32 bit default: 5c141400h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-235.offset 9ch: dqsfail1 - dqs failure configuration register 1 description: dqsfail1: dqs failure configuration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 9ch 9ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :04 reserved reserved n 0h ro 03 03 reserved_r1dq s17 reserved y 0b rw 02 02 r1dqs08 rank 1 dqs08 y0b rw 01 01 reserved_r1dq s16 reserved y 0b rw 00 00 r1dqs07 rank 1 dqs07 y0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 613 intel ? ep80579 integrated processor 16.5.1.9 offset a0h: dqsfail0 - dqsfail0 configuration register see description for dqsfail1 ( section 16.5.1.8 ). see table 16-236.offset a0h: dqsfail0 - dqs failure configuration register 0 description: dqsfail0: dqs failure configuration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved_r1dq s15 reserved y 0b rw 30 r1dqs06 rank 1 dqs06 y0b rw 29 reserved_r1dq s14 reserved y 0b rw 28 r1dqs05 rank 1 dqs05 y0b rw 27 reserved_r1dq s13 reserved y 0b rw 26 r1dqs04 rank 1 dqs04 y0b rw 25 reserved_r1dq s12 reserved y 0b rw 24 r1dqs03 rank 1 dqs03 y0b rw 23 reserved_r1dq s11 reserved y 0b rw 22 r1dqs02 rank 1 dqs02 y0b rw 21 reserved_r1dq s10 reserved y 0b rw 20 r1dqs01 rank 1 dqs01 y0b rw 19 reserved_r1dq s09 reserved y 0b rw 18 r1dqs00 rank 1 dqs00 y0b rw 17 reserved_r0dq s17 reserved y 0b rw 16 r0dqs08 rank 0 dqs08 y0b rw 15 reserved_r0dq s16 reserved y 0b rw 14 r0dqs07 rank 0 dqs07 y0b rw 13 reserved_r0dq s15 reserved y 0b rw 12 r0dqs06 rank 0 dqs06 y0b rw 11 reserved_r0dq s14 reserved y 0b rw 10 r0dqs05 rank 0 dqs05 y0b rw 9 reserved_r0dq s13 reserved y 0b rw 8 r0dqs04 rank 0 dqs04 y0b rw 7 reserved_r0dq s12 reserved y 0b rw 6 r0dqs03 rank 0 dqs03 y0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 614 order number: 320066-003us 16.5.1.10 drrtc: receive enable reference output timing control registers note: these registers have to be saved and restored on s3. the drrtc is a set of three registers with dqs receiver enable window timing control for each byte on the ddr data bus. there is a single control for each byte for both ranks. a correct register setting will delay the start of the enable window so that it coincides with the middle of the dqs pre-amble. enabling the window before or after the pre-amble would cause valid dqs edges to be missed or invalid edges or noise to be received. the range of the enable delay, controlled by the drrtc registers, is eight cycles, with a granularity defined by the ddriomc2.mastcntl register (controls setting for the master dll). the delay is measured from the memory controller clock edge that launches a ?read? command on the ddr command bus. the minimum delay is equal to the ddr sdram read latency defined in the drt0.cl register field. the maximum delay is the read latency plus eight cycles. in order words the drrtc registers can introduce up to 8 cycles of delay. this drrtc delay does not included the contributions of cl and registered dimm to the total read latency. in addition to these major sources of delay, there is also a small ?uncompensated delay? as shown in the formulas below. the rcven fields of the drrtc register control the delay as follows: bits [7:5] control whole clock increments, bits [4:3] control in quarter clock increments, and bits [2:0] control the sub-quarter cycle increments. setting rcven to 0x0 produces the minimum delay, and 0xff sets the maximum delay. the sub-quarter cycle delay is defined by the equations and ?rcven_out? lookup table below: delay_uncomp = 100ps; note: estimate only delay element = (quarter cmdclk period - delay_uncomp) / (mastcntl + 0.5) sub quarter cycle delay = delay_uncomp + (delay element * rcven_out[2:0]) 5 reserved_r0dq s11 reserved y 0b rw 4 r0dqs02 rank 0 dqs02 y0b rw 3 reserved_r0dq s10 reserved y 0b rw 2 r0dqs01 rank 0 dqs01 y0b rw 1 reserved_r0dq s09 reserved y 0b rw 0 r0dqs00 rank 0 dqs00 y0b rw table 16-236.offset a0h: dqsfail0 - dqs failure configuration register 0 description: dqsfail0: dqs failure configuration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 615 intel ? ep80579 integrated processor for example, if the ddriomc2.mastcntl is set to 0x7, the receiver enable delay can be varied over eight cycle in 256 steps, one step for each drrtc rcven setting. if ddriomc2.mastcntl is set to 0x3, however, the number of steps is reduced to 128, such that half of the drrtc rcven settings do not produce an increase in delay from the previous setting. 16.5.1.11 offset a4h: drrtc00 - receive enable reference output timing control register this register determines dqs 3, 2, 1, & 0 input buffer enable timing delay rcven_out lookup table ddriomc2 [mastcntl] drrtc rcven [2:0] 76543210 7 76543210 6 65543210 5 54432110 4 44332110 3 33221100 2 22211000 1 11110000 0 00000000 table 16-237.offset a4h: drrtc00 - receive enable reference output timing control register description: drrtc00: receive enable reference output timing control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: a4h a7h size: 32 bit default: 06060606h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rcven03 receiver enable delay for dqs3 y 06h rw 23 :16 rcven02 receiver enable delay for dqs2 y 06h rw 15 :08 rcven01 receiver enable delay for dqs1 y 06h rw 7 :00 rcven00 receiver enable delay for dqs0 y 06h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 616 order number: 320066-003us 16.5.1.12 offset a8h: drrtc01 - receive enable reference output timing control register this register determines dqs 7, 6, 5, & 4 input buffer enable timing delay. 16.5.1.13 offset c4h: drrtc02 - receive enable reference output timing control register this register determines dqs 8 input buffer enable timing delay. 16.5.1.14 dqs calibration registers the dqsofcs is a group of six registers that control the fine delay used to center dqs edges to the dq data eye during read operations. there is a delay entry for each nibble of the ddr data bus for each rank. the coarse delay is controlled by the dramdllc register. the equations for the fine and coarse delays are shown below. note that ?delay element? and ?delay_uncomp? are defined in the drrtc register section. also note that there is a separate coarse delay control for each ?chunk? of the ddr i/o cluster as defined in the dramdllc register section. note: these registers may have to be saved and restored on s3 table 16-238.offset a8h: drrtc01 - receive enable reference output timing control register description: drrtc01: receive enable reference output timing control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: a8h abh size: 32 bit default: 06060606h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rcven07 receiver enable delay for dqs7 y 06h rw 23 :16 rcven06 receiver enable delay for dqs6 y 06h rw 15 :08 rcven05 receiver enable delay for dqs5 y 06h rw 7 :00 rcven04 receiver enable delay for dqs4 y 06h rw table 16-239.offset c4h: drrtc02 - receive enable reference output timing control register description: drrtc02: receive enable reference output timing control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: c4h c4h size: 8 bit default: 06h power well: core bit range bit acronym bit description sticky bit reset value bit access 7 :00 rcven08 receiver enable delay for dqs8 y 06h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 617 intel ? ep80579 integrated processor 16.5.1.15 offset b4h: dqsofcs00 - dqs calibration register this register determines dqs3, 2, 1, & 0 fine dqs delay when reading from rank 0. 16.5.1.16 offset b8h: dqsofcs01 - dqs calibration register this register determines dqs7, 6, 5, & 4 fine dqs delay when reading from rank 0. table 16-240.offset b4h: dqsofcs00 - dqs calibration register description: dqsofcs00: dqs calibration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: b4h b7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 reserved reserved n 0h ro 27 :24 dqs03 rank 0 dqs03: fine delay y0h rw 23 :20 reserved reserved n 0h ro 19 :16 dqs02 rank 0 dqs02: fine delay y0h rw 15 :12 reserved reserved n 0h ro 11 :08 dqs01 rank 0 dqs01: fine delay y0h rw 07 :04 reserved reserved n 0h ro 03 :00 dqs00 rank 0 dqs00: fine delay y0h rw table 16-241.offset b8h: dqsofcs01 - dqs calibration register description: dqsofcs01: dqs calibration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: b8h bbh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 reserved reserved n 0h ro 27 :24 dqs07 rank 0 dqs07: fine delay y0h rw 23 :20 reserved reserved n 0h ro 19 :16 dqs06 rank 0 dqs06: fine delay y0h rw 15 :12 reserved reserved n 0h ro 11 :08 dqs05 rank 0 dqs05: fine delay y0h rw 7 :04 reserved reserved n 0h ro 3 :00 dqs04 rank 0 dqs04: fine delay y0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 618 order number: 320066-003us 16.5.1.17 offset c6h: dqsofcs02 - dqs calibration register this register determines dqs 8 fine dqs delay when reading from rank 0. 16.5.1.18 offset bch: dqsofcs10 - dqs calibration register this register determines dqs 3, 2, 1, & 0 fine dqs delay when reading from rank 1. table 16-242.offset c6h: dqsofcs02 - dqs calibration register description: dqsofcs02: dqs calibration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: c6h c6h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :04 reserved reserved n 0h ro 03 :00 dqs08 rank 0 dqs08: fine delay y0h rw table 16-243.offset bch: dqsofcs10 - dqs calibration register description: dqsofcs10: dqs calibration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: bch bfh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 reserved reserved n 0h ro 27 :24 dqs03 rank 1 dqs03: fine delay y0h rw 23 :20 reserved reserved n 0h ro 19 :16 dqs02 rank 1 dqs02: fine delay y0h rw 15 :12 reserved reserved n 0h ro 11 :08 dqs01 rank 1 dqs01: fine delay y0h rw 07 :04 reserved reserved n 0h ro 03 :00 dqs00 rank 1 dqs00: fine delay y0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 619 intel ? ep80579 integrated processor 16.5.1.19 offset c0h: dqsofcs11 - dqs calibration register this register determines dqs7, 6, 5, & 4 fine dqs delay when reading from rank 1 . 16.5.1.20 offset c7h: dqsofcs12 - dqs calibration register this register determines dqs 8 fine dqs delay when reading from rank 1 table 16-244.offset c0h: dqsofcs11 - dqs calibration register description: dqsofcs11: dqs calibration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: c0h c3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 reserved reserved n 0h ro 27 :24 dqs07 rank 1 dqs07: fine delay y0h rw 23 :20 reserved reserved n 0h ro 19 :16 dqs06 rank 1 dqs06: fine delay y0h rw 15 :12 reserved reserved n 0h ro 11 :08 dqs05 rank 1 dqs05: fine delay y0h rw 07 :04 reserved reserved n 0h ro 03 :00 dqs04 rank 1 dqs04: fine delay y0h rw table 16-245.offset c7h: dqsofcs12 - dqs calibration register description: dqsofcs12: dqs calibration register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: c7h c7h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :04 reserved reserved n 0h ro 03 :00 dqs08 rank 1 dqs08: fine delay y0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 620 order number: 320066-003us 16.5.1.21 wptrtc ddr i/o write pointer timing the two wptrtc registers control the fine delay of the ddr i/o fifo write pointers. the formulas for delay shown in the dqsofcs and drrtc register sections are identical to the write pointer delay formulas. to find the wptrtc portion of write pointer delay, use the dqsofcs formulas, and substitute wptrtc fields for all the dqsofcs fields. the only difference in the application of these formulas is that there is only one wptrtc field per byte of the ddr i/o, whereas the dqsofcs has a field per byte per rank. the total write pointer delay, measured from the same reference point as the dqs receiver enable timing, is equal to the dqs receiver enable timing, including the quarter clock and sub-quarter clock delays, plus one full clock cycle, plus the coarse and fine dramdllc.slvlen/wptrtc delays calculated with the formulas from the dqsofcs register section. 16.5.1.22 offset cch: wptrtc0 - write pointer timing control 0 register this register determines the ddr i/o fifo write pointer fine delay timing for all dqs signals except dqs8 when reading from rank 0 or rank 1. table 16-246.offset cch: wptrtc0 - write pointer timing control register description: wptrtc0: write pointer timing control view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: cch cfh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 dqs07 dqs7 write pointer fine delay y0h rw 27 :24 dqs06 dqs6 write pointer fine delay y0h rw 23 :20 dqs05 dqs5 write pointer fine delay y0h rw 19 :16 dqs04 dqs4 write pointer fine delay y 0h rw 15 :12 dqs03 dqs3 write pointer fine delay y0h rw 11 :08 dqs02 dqs2 write pointer fine delay y0h rw 7 :04 dqs01 dqs1 write pointer fine delay y0h rw 3 :00 dqs00 dqs0 write pointer fine delay y0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 621 intel ? ep80579 integrated processor 16.5.1.23 offset d0h: wptrtc1 - write pointer timing control 1 register this register determines the ddr i/o fifo write pointer fine delay timing for dqs8 signals when reading from rank 0 or rank 1 16.5.1.24 ddqscvdp and ddqscadp this set of 4 registers defines two 64 bit long data patterns used in the dqs delay calibration. they are only used when dcalcsr.baspat is low. the 64 bit patterns cover a data burst that is 32 dram clock cycles long. the ddqscvdp registers define the ?victim? pattern, and the ddqscadp defines the ?aggressor? pattern. the victim pattern is applied to one bit of each byte of the ddr data bus for 32 clock cycles, and the aggressor pattern is applied to all other bi ts. the victim pattern is applied in turn to each bit of each byte, creating a complete data pattern that is 8*32 data cycles long. 16.5.1.25 offset d4h: ddqscvdp0 - dq s delay calibration victim pattern 0 register this register defines the last 32 bits of the 64 bit long ?victim? data pattern. table 16-247.offset d0h: wptrtc1 - write pointer timing control 1 register description: wptrtc1: write pointer timing control view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: d0h d0h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 7 :04 reserved reserved 0h ro 3 :00 dqs08 dqs8 write pointer fine delay y0h rw table 16-248.offset d4h: ddqscvdp0 - dqs delay calibration victim pattern 0 register description: ddqscvdp0: dqs delay cal pattern view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: d4h d7h size: 32 bit default: aaaa0a05h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 vp0 victim pattern 0 aaaa0a05h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 622 order number: 320066-003us 16.5.1.26 offset d8h: ddqscvdp1 - dqs delay calibration victim pattern 1 register this register defines the first 32 bits of the 64 bit long ?victim? data pattern. 16.5.1.27 offset dch: ddqscadp0 - dqs delay calibration aggressor pattern 0 register this register defines the last 32 bits of the 64 bit long ?aggressor? data pattern. 16.5.1.28 offset e0h: ddqscadp1 - dqs delay calibration aggressor pattern 1 register this register defines the first 32 bits of the 64 bit long ?aggressor? data pattern. table 16-249.offset d8h: ddqscvdp1 - dqs delay calibration victim pattern 1 register description: ddqscvdp1: dqs delay cal pattern view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: d8h dbh size: 32 bit default: 5b339c5dh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 vp1 victim pattern 1 5b339c5dh rw table 16-250.offset dch: ddqscadp0 - dqs delay calibration aggressor pattern 0 register description: ddqscadp0: dqs delay cal pattern view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: dch dfh size: 32 bit default: aaabffffh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 ap0 aggressor pattern 0 aaabffffh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 623 intel ? ep80579 integrated processor 16.5.1.29 offset f0h: diomon - ddr i/o monitor register this register monitors the legsel output of the ddr i/o and controls the a/d converter in ddr i/o used to monitor analog voltage levels. table 16-251.offset e0h: ddqscadp1 - dqs delay calibration aggressor pattern 1 register description: ddqscadp1: dqs delay cal pattern view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: e0h e3h size: 32 bit default: db339ce1h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 ap1 aggressor pattern 1 db339ce1h rw table 16-252.offset f0h: diomon - ddr i/o monitor register description: diomon: ddr i/o monitor view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: f0h f3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 25 reserved reserved n 00000000b ro 24 24 dsamp causes the analog to digital converter to sample the analog input selected by biasssel y0b rw 23 16 vresult a/d converter output of ddr i/o y 00000000b ro 15 15 enable enable a/d converter for the ddr io bias logic. also enables updates to the following fields of this csr: vresult, dqlegselout, diopwr, calegselout n0b rw 14 :11 biassel a/d converter input selection y 0000b rw 10 07 dqlegselout dq legsel output of ddr i/o. sets the driver strength for dq io buffers. y 0000b ro 06 06 diopwr nopwr = 0 if vccddr is off or in burnin mode. during normal operation it?s set to 1. y0b ro 05 :04 reserved reserved n 00b ro 03 :00 calegselout cmd/addr legsel output of ddr i/o sets the driver strength for cmd/addr io buffers. y 0000b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 624 order number: 320066-003us 16.5.1.30 offset f8h: dramisctl - miscellaneous dram ddr cluster control register table 16-253.offset f8h: dramisctl - miscel laneous dram ddr cluster control register description: dramisctl: miscellaneous dram ddr cluster control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: f8h fbh size: 32 bit default: 1011h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :13 reserved reserved n 0b ro 12 12 reserved reserved y 1b rw 11 11 reserved reserved n 0b rw 10 8 reserved_rw reserved for future use. these bits are rw but sw should not change the default reset value of these bits. n000b rw 7:0 vrefsel vref selection: adjustable vref voltage at receivers. the threshold voltage at receiver can be raised or lowered to allow the noise margin on the data from memory be skewed. vref is estimated with the following equation vref = (squ * vccddr + (sqd ? squ) * 0.45) / (squ + sqd) + voff where, squ = sqrt(4*vrefsel<7> + 2*vrefsel<6> + vrefsel<5> + 8*vrefsel<4>) sqd = sqrt(4*vrefsel<3> + 2*vrefsel<2> + vrefsel<1> + 8*vrefsel<0>) voff = offset, varying for each chip, nominal value is 0 but can be up to +/- 0.1v examples with vccddr=1.8v and voff=0 .vrefsel. vref (v) 00010001 0.9 00010011 0.887 00010101 0.875 00011001 0.855 11101001 0.840 11001001 0.823 10001001 0.779 00110001 0.913 01010001 0.925 10010001 0.945 10011110 0.960 10011100 0.977 10011000 1.021 y 11h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 625 intel ? ep80579 integrated processor 16.5.1.31 offset c8h: dramdllc - ddr i/o dll control register the formulas that show how the slvlen fields affect dqs delay timing are shown in the dqsofcs register definition section. the slvlen fields are set by hardware during the dqs delay calibration. there are five slvlen fields, one for each two bytes of the ddr i/o dq pins. the slvbyp bit can be toggled to reset the master dll?s in the ddr i/o. 16.5.1.32 offset e8h: fivesreg - fixed 5s pattern register constant value used for debug. table 16-254.offset c8h: dramdllc - ddr i/o dll control register description: dramdllc: ddr i/o dll control view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: c8h cah size: 24 bit default: 0db6c0h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 :22 reserved reserved n 00b ro 21 slvbyp dqs delay bypass y0b rw 20 :18 slvlen4 dqs 8 coarse dqs delay y 011b rw 17 :15 slvlen3 dqs 7 & 6 coarse dqs delay y 011b rw 14 :12 slvlen2 dqs 5 & 4 coarse dqs delay y 011b rw 11 :09 slvlen1 dqs 3 & 2 coarse dqs delay y 011b rw 8 :06 slvlen0 dqs1 & 0 coarse dqs delay y 011b rw 5 :00 reserved reserved n 000000b ro table 16-255.offset e8h: fivesreg - fixed 5s pattern register description: fivesreg: fixed 5s pattern view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: e8h ebh size: 32 bit default: 55555555h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 fives hardwired to 5s for read-return n 55555555h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 626 order number: 320066-003us 16.5.1.33 offset ech: aaaareg - fixed as pattern register constant value used for debug. 16.5.1.34 memory bist registers the following set of registers cover the membist logic which is used for testing the external ddr devices, as well as the connections between the ep80579 and the ddr chips. the following must be complete prior to running membist: ? memory controller internal csrs are set to match external ddr configuration. ? jedec ddrii/iii initialization sequence. ? ep80579 ddr pad (receive enable and dqs) calibration. the csr?s following this csr are the memory-mapped registers for the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. 16.5.1.35 offset 140h: mbcsr - membist control register table 16-256.offset ech: aaaareg - fixed a pattern register description: aaaareg: fixed a pattern view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: ech efh size: 32 bit default: aaaaaaaah power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 aaaa hardwired to as for read-return n aaaaaaaah ro table 16-257.offset 140h: mbcsr - membist control register (sheet 1 of 3) description: mbcsr: top level control register for ddr membist. view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 140h 143h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 start start operation: 1 => set this bit to begin membist execution. 0 => hardware will clear this bit when membist execution is completed. n0b rws
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 627 intel ? ep80579 integrated processor 30 pf fail/pass indicator: write to 0 when start membist. hardware will set to 1 when a failure is detected. 0 => pass 1 => fail n0b rw 29 halt halt on error: 0 => operation will not halt due to a detected error. 1 => operation will halt after read-compare data error is detected. membist will complete the current transaction before halting. this may result in multiple errors being logged. n0b rw 28 abort membist test abort . when test abort bit is set, mbcsr bit 31 (start operation, rws) needs to be set to "0" at the same time to avoid restarting membist. 0 => normal operation. 1 => need to abort the test during membist operation. if there is any following membist test after the abort test, bit [28] needs to be cleared. the write to set mbcsr.abort must occur at least trfc after the write to set mbcsr.start. otherwise subsequent membist operations may fail. n0b rw 27 spare reserved n 00b ro 26 :24 algo 000b: only support setting n000b rw 23 :22 reserved reserved n 00b ro 21 :20 cs chip select [1:0] selection in membist mode 01: select rank 0 10: select rank 1 00: reserved 11: reserved n 00b rw 19 inv 0b: only supported setting n0h rw 18 :16 fx fixed : fixed data pattern selection for membist operation 000 => 0 001 => f 010 => a 011 => 5 100 => c 101 => 3 110 => 9 111 => 6 n000b rw 15 en288 0b: only supported setting n0b rw table 16-257.offset 140h: mbcsr - membist control register (sheet 2 of 3) description: mbcsr: top level control register for ddr membist. view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 140h 143h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 628 order number: 320066-003us 14 mbdata mbdata : selects use of mbdata for error log field for lfsr, circular shift and user defined data modes. this field has no effect on fixed data patterns. 0 => use mbdata0/1/2/3/8 for failure data bit location accumulator. 1 => use mbdata0/1/2/3/8 to log 5 failure addresses. n0b rw 13 abar 0: only supported setting n0b rw 12 adir adir: address decode direction 0 => address increments 1 => address decrements n0b rw 11 :10 fast fast address sequencing 00: only supported setting n 00b rw 9:08 dtype data type selection: 00 => fixed data pattern, selected by mbcsr bits 18:16 01 => 144 bits user defined data 10 => circular shift data based on seed in mblfsrsed 11 => lfsr data, seeded from 32 bit lfsr seed register. note: circular shift data and lfsr data type should not be used for single address operation (atype = 01). note: circular shift data and lfsr data type only for 72- bit mode n 00b rw 7:06 atype address type : 00 => reserved 01 => single physical address operation, contained in mbaddr row/column/bank. 10 => start/end physical address range defined in mb_start_addr & mb_end_addr registers. 11 => full address range of the dimm as defined in dra/drb registers which specifies the number of banks, rows, and columns. ? n 00b rw 5:04 cmd command execution : 00 => read only without data comparison 01 => write only 10 => read with data comparison 11 => write followed by read with data comparison n 00b rw 3 :00 reserved reserved n 0000b ro table 16-257.offset 140h: mbcsr - membist control register (sheet 3 of 3) description: mbcsr: top level control register for ddr membist. view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 140h 143h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 629 intel ? ep80579 integrated processor 16.5.1.36 offset 144h: mbaddr - memory test address register the register is used by membist only when testing to a single memory location. (mbcsr.atype = 2b?01) 16.5.1.37 offset 148h: mbdata[0:9] - memory test data register table 16-258.offset 144h: mbaddr - memory test address register description: mbaddr: memory test address view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 144h 147h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 row row address 15:0 y 0000h rw 15 spare reserved. must write as ?0? y 0b rw 14 :03 col column address bl8[14:3] <==> dram column address 15:11,9:3 bl4[14:3] <==> dram column address 14:11,9:2 y 0000h rw 2 :00 ba bank address 2:0 y 000b rw table 16-259.offset 148h: mbdata[0:9] - memory test data register description: mbaddr[0:9]: memory test data view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 148h at 4h 14ch at 4h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 mbdata usage varies by mode, refer to table below for details y 00000000h rw reg bit offset description by mode fixed data pattern 144 bit user defined pattern circular shift lfsr mbdata9 31:0 16ch 5th fail address user defined late data [71:64] & early data [71:64] word4 circular shift data lfsr random late data [71:64] & early data [71:64] mbdata8 31:0 168h late data [71:64] & early data [71:64] failure bit location accumulator 5th fail address or late data [71:64] & early data [71:64] failure bit location accumulator 5th fail address or late data [71:64] & early data [71:64] failure bit location accumulator 5th fail address or late data [71:64] & early data [71:64] failure bit location accumulator
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 630 order number: 320066-003us note: in the later half part of data burst length 8 test, 144 bits user -defined data pattern will be repeat as the same sequence of burst length 4. mbdata7 31:0 164h fail address 4 user defined late data [63:32] dw3 circular shift data lfsr random late data [63:32] mbdata6 31:0 160h fail address 3 user defined late data [31:0] dw2 circular shift data lfsr random late data [31:0] mbdata5 31:0 15ch fail address 2 user defined early data [63:32] dw1 circular shift data lfsr random early data [63:32] mbdata4 31:0 158h fail address 1 user defined early data [31:0] dw0 circular shift data lfsr random early data [31:0] mbdata3 31:0 154h late data [63:32] failure bit location accumulator fail address 4 or late data [63:32] failure bit location accumulator fail address 4 or late data [63:32] failure bit location accumulator fail address 4 or late data [63:32] failure bit location accumulator mbdata2 31:0 150h late data [31:0] failure bit location accumulator fail address 3 or late data [31:0] failure bit location accumulator fail address 3 or late data [31:0] failure bit location accumulator fail address 3 or late data [31:0] failure bit location accumulator mbdata1 31:0 14ch early data [63:32] failure bit location accumulator fail address 2 or early data [63:32] failure bit location accumulator fail address 2 or early data [63:32] failure bit location accumulator fail address 2 or early data [63:32] failure bit location accumulator mbdata0 31:0 148h early data [31:0] failure bit location accumulator fail address 1 or early data [31:0] failure bit location accumulator fail address 1 or early data [31:0] failure bit location accumulator fail address 1 or early data [31:0] failure bit location accumulator reg bit offset description by mode fixed data pattern 144 bit user defined pattern circular shift lfsr
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 631 intel ? ep80579 integrated processor 16.5.1.37.1 mbdata failure address mapping to compress the failure address into 32 bits, bits that are always zero are removed from the logging. these removed bits include autoprecharge column address [10] and least significant bits assumed by burst length. bl4: 1 bit chunk indicates the location of 2 failure burst data chunks. the above column plus chunk is equal to dram column address as the following: ? where the auto-precharge address bit 10 is assumed zero. ? since data is logged in 144 bits (two chunks), address bit zero is not needed. bl8: 2 bit chunk indicates the location of 4 failure burst data chunks. the above column plus chunk is equal to dram column address as the following: ? where the auto-precharge address bit 10 is assumed zero. ? since data is logged in 144 bits (two chunks), data chunk address bit zero is not needed. 16.5.1.38 offset 19ch: mb_start_addr - memory test start address register mb_end_addr row and column address must be larger than mb_start_addr row and column address in either increasing or deceasing address mode. during fastx, fasty and fastxy operation, only one memory bank is tested. specify the desired bank in mb_start_addr[2:0]. mb_end_addr[2:0] is ignored. in xzy address mode, bank address wraps around either in the 4 banks or 8 banks case. in xzy mode, mb_end_addr bank address may be smaller than mb_start_addr bank address. this register is only used when mbcsr.atype = 2b?10, and when mbcsr.algo is non- zero. table 16-260.mbdata failure address register correspondence to dram address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0151413121110 9 8 7 6 5 4 3 2 1 0 see description below bank row column and chunk table 16-261.bl4 column and chunk correspondence to dram address register bit location 121110 9 8 7 6 5 4 3 2 1 0 dram col address 14131211 9 8 7 6 5 4 3 2 data chunk 1x table 16-262.bl8 column and chunk correspondence to dram address register bit location 121110 9 8 7 6 5 4 3 2 1 0 dram col address 14131211 9 8 7 6 5 4 3 data chunk 2 1 x
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 632 order number: 320066-003us 16.5.1.39 offset 1a0h: mb_end_addr - memory test end address register this register is only used when mbcsr.atype = 2b?10, and when mbcsr.algo is non- zero. table 16-263.offset 19ch: mb_start_addr - memory test start address register description: mb_start_addr: memory test start address view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 19ch 19fh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 row membist start row address 15:0 y 0000h rw 15 reserved reserved 0b ro 14 :03 col membist start column address bl8[14:3] <==> dram column address 15:11,9:3 bl4[14:3] <==> dram column address 14:11,9:2 y 0000h rw 02 :00 ba membist start bank address 2:0 y 000b rw table 16-264.offset 1a0h: mb_end_addr - memory test end address register description: mb_end_addr: memory test end address view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1a0h 1a3h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 row membist end row address 15:0 y 0000h rw 15 reserved reserved n 0b ro 14 :03 col membist end column address bl8[14:3] <==> dram column address 15:11,9:3 bl4[14:3] <==> dram column address 14:11,9:2 y 0000h rw 02 :0 ba membist end bank address 2:0 y 000b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 633 intel ? ep80579 integrated processor 16.5.1.40 offset 1a4h: mblfsrsed - memory test circular shift and lfsr seed register note: if lfsr operation is selected, seed value of all 1s will not be able to generate random numbers. pattern will remain all 1s. 16.5.1.41 offset 1a8h: mbfaddrptr - memory test failure address pointer register table 16-265.offset 1a4h: mblfsrsed - memory test circular shift and lfsr seed register description: mblfsrsed: memory test circular shift and lfsr seed view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1a4h 1a7h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 mblfsrsed membist lfsr seed this 32 bit register will be used as the initial data seed for lfsr or circular shift data pattern. y0h rw table 16-266.offset 1a8h: mbfaddrptr - memory test failure address pointer register description: mbfaddrptr: memory test failure address pointer register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1a8h 1abh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 mbfaddrptr this 32 bit register designates which membist failures to log in the available failure address locations. the default value of this register is zero. it means membist always logs beginning with the first failure. if it is programmed to hex a (10 in decimal), membist will log failures starting from the11th failure. the corresponding mb_err_data0/1/2/3 registers will log corrupted data in the first through fourth designated failure addresses. note: this register does not affect the mbdata failure bit location accumulators. y 00000000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 634 order number: 320066-003us 16.5.1.42 offset 1b0h: mb_err_data00 - memory test error data 0 stores the first 32 bits of the 1st 144 bit failure data. 16.5.1.43 offset 1b4h: mb_err_data01 - memory test error data 0 stores the second 32 bits of the 1st 144 bit failure data 16.5.1.44 offset 1b8h: mb_err_data02 - memory test error data 0 stores the third 32 bits of the 1st 144 bit failure data table 16-267.offset 1b0h: mb_err_data00 - memory test error data 0 description: mb_err_data00 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1b0h 1b3h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [31:0] y 00000000h rw table 16-268.offset 1b4h: mb_err_data01 - memory test error data 0 description: mb_err_data01 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1b4h 1b7h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [63:32] y 00000000h rw table 16-269.offset 1b8h: mb_err_data02 - memory test error data 0 description: mb_err_data02 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1b8h 1bbh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [31:0] y 00000000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 635 intel ? ep80579 integrated processor 16.5.1.45 offset 1bch: mb_err_data03 - memory test error data 0 stores the fourth 32 bits of the 1st 144 bit failure data 16.5.1.46 offset 1c0h: mb_err_data04 - memory test error data 0 stores the last 16 bits of the 1st 144 bit failure data. 16.5.1.47 offset 1c4h: mb_err_data10 - memory test error data 1 stores the first 32 bits of the 2nd 144 bit failure data table 16-270.offset 1bch: mb_err_data03 - memory test error data 0 description: mb_err_data03 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1bch 1bfh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [63:32] y 00000000h rw table 16-271.offset 1c0h: mb_err_data04 - memory test error data 0 description: mb_err_data04 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1c0h 1c1h size: 16 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 data late failure data [71:64] & early failure data [71:64] y 0000h rw table 16-272.offset 1c4h: mb_err_data10 - memory test error data 1 description: mb_err_data10 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1c4h 1c7h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [31:0] y 00000000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 636 order number: 320066-003us 16.5.1.48 offset 1c8h: mb_err_data11 - memory test error data 1 stores the second 32 bits of the 2nd 144 bit failure data 16.5.1.49 offset 1cch: mb_err_data12 - memory test error data 1 stores the third 32 bits of the 2nd 144 bit failure data 16.5.1.50 offset 1d0h: mb_err_data13 - memory test error data 1 stores the fourth 32 bits of the 2nd 144 bit failure data table 16-273.offset 1c8h: mb_err_data11 - memory test error data 1 description: mb_err_data11 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1c8h 1cbh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [63:32] y 00000000h rw table 16-274.offset 1cch: mb_err_data12 - memory test error data 1 description: mb_err_data12 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1cch 1cfh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [31:0] y 00000000h rw table 16-275.offset 1d0h: mb_err_data13 - memory test error data 1 description: mb_err_data13 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1d0h 1d3h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [63:32] y 00000000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 637 intel ? ep80579 integrated processor 16.5.1.51 offset 1d4h: mb_err_data14 - memory test error data 1 stores the last 16 bits of the 2nd 144 bit failure data 16.5.1.52 offset 1d8h: mb_err_data20 - memory test error data 2 stores the first 32 bits of the 3rd 144 bit failure data 16.5.1.53 offset 1dch: mb_err_data21 - memory test error data 2 stores the second 32 bits of the 3rd 144 bit failure data table 16-276.offset 1d4h: mb_err_data14 - memory test error data 1 description: mb_err_data14 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1d4h 1d5h size: 16 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 data late failure data [71:64] & early failure data [71:64] y 0000h rw table 16-277.offset 1d8h: mb_err_data20 - memory test error data 2 description: mb_err_data20 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1d8h 1dbh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [31:0] y 00000000h rw table 16-278.offset 1dch: mb_err_data21 - memory test error data 2 description: mb_err_data21 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1dch 1dfh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [63:32] y 00000000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 638 order number: 320066-003us 16.5.1.54 offset 1e0h: mb_err_data22 - memory test error data 2 stores the third 32 bits of the 3rd 144 bit failure data 16.5.1.55 offset 1e4h: mb_err_data23 - memory test error data 2 stores the fourth 32 bits of the 3rd 144 bit failure data 16.5.1.56 offset 1e8h: mb_err_data24 - memory test error data 2 stores the last 16 bits of the 3rd 144 bit failure data table 16-279.offset 1e0h: mb_err_data22 - memory test error data 2 description: mb_err_data22 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1e0h 1e3h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [31:0] y 00000000h rw table 16-280.offset 1e4h: mb_err_data23 - memory test error data 2 description: mb_err_data23 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1e4h 1e7h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [63:32] y 00000000h rw table 16-281.offset 1e8h: mb_err_data24 - memory test error data 2 description: mb_err_data24 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1e8h 1e9h size: 16 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 data late failure data [71:64] & early failure data [71:64] y 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 639 intel ? ep80579 integrated processor 16.5.1.57 offset 1ech: mb_err_data30 - memory test error data 3 stores the first 32 bits of the 4th 144 bit failure data 16.5.1.58 offset 1f0h: mb_err_data31 - memory test error data 3 stores the second 32 bits of the 4th 144 bit failure data 16.5.1.59 offset 1f4h: mb_err_data32 - memory test error data 3 stores the third 32 bits of the 4th 144 bit failure data table 16-282.offset 1ech: mb_err_data30 - memory test error data 3 description: mb_err_data30 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1ech 1efh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [31:0] y 00000000h rw table 16-283.offset 1f0h: mb_err_data31 - memory test error data 3 description: mb_err_data31 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1f0h 1f4h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data early failure data [63:32] y 00000000h rw table 16-284.offset 1f4h: mb_err_data32 - memory test error data 3 description: mb_err_data32 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1f4h 1f7h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [31:0] y 00000000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 640 order number: 320066-003us 16.5.1.60 offset 1f8h: mb_err_data33 - memory test error data 3 stores the fourth 32 bits of the 4th 144 bit failure data 16.5.1.61 offset 1fch: mb_err_data34 - memory test error data 3 stores the last 16 bits of the 4th 144 bit failure data. 16.5.1.62 offset 260h: ddriomc0 - ddr io mode control register 0 this register controls functionality of the ddrio. this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. one function of ddriomc0 is to control the voltage crossing (vox) analog control loop used to minimize any mismatch between the clock to output (tco) on a low-to-high or high-to-low transition. table 16-285.offset 1f8h: mb_err_data33 - memory test error data 3 description: mb_err_data33 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1f8h 1fbh size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 data late failure data [63:32] y 00000000h rw table 16-286.offset 1fch: mb_err_data34 - memory test error data 3 description: mb_err_data34 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 1fch 1fdh size: 16 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 data late failure data [71:64] & early failure data [71:64] y 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 641 intel ? ep80579 integrated processor 16.5.1.63 offset 264h: ddriomc1 - ddr io mode control register 1 this register controls functionality of the ddrio. this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. table 16-287.offset 260h: ddriomc0 - ddrio mode register control register description: view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 260h 263h size: 32 bit default: 00000078h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 13 reserved reserved n 000000000000 0000000b ro 12 9 dqvoxadj bits to configure dq buffer tco balancing y 0000b rw 88 ddrvoxctl1 combine this bit with ddrvoxctl0 (defined below) encodings: 00 : dq and ca buffers are in vox cross reference mode 01: bypass dq and ca vox cross reference mode (default) 10: vox bypass mode 11: reset vox mode y0b rw 7 7 reserved reserved n 0b ro 6 4 reserved reserved n 111b rw 33 ddrvoxctl0 this is the least significant bit of ddrvoxctl. for encoding details, see ddrvoxctl1 above y1b rw 2 0 reserved reserved y 000b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 642 order number: 320066-003us table 16-288.offset 264h: ddriomc1 - ddrio mode register control register 1 (sheet 1 of 2) description: ddriomc1: ddrio mode control register 1 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 264h 267h size: 32 bit default: 52520000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 24 caslew caslew: the digital slew override 8-bit control allow for balancing of pull-up and pull-down slew rates t for ca/clk buffers. the format of these controls and recommended reset value is given below: y 01010010b rw 23 16 dqslew dqslew: the digital slew override 8-bit control allow for balancing of pull-up and pull-down slew rates t for ca/clk buffers. the format of these controls and recommended reset value is given below: y 01010010b rw 15 7 reserved reserved n 000000000b ro bits function 7 ddr2selection. ddr2 = 0 6:5 fast corner falling slew rate trim 4:2 slow corner falling slew rate trim 1:0 fast corner rising slew rate trim bits function 7 ddr2 selection. ddr2 = 0 6:5 fast corner falling slew rate trim 4:2 slow corner falling slew rate trim 1:0 fast corner rising slew rate trim
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 643 intel ? ep80579 integrated processor 6 5 dempdq de-emphasis mode select bit for dq/dqs pins. this mode can be used to reduce power and enhance data eyes. when de-emphasis is enable for a given group of i/os, subsequent driver values that are the same have their strength reduced by half it is recommended that this be controllable by the bios in case there are unwanted side effects of this feature. y 00b rw 43 dempca de-emphasis mode select bit for command/clock pins. this mode can be used to reduce power and enhance data eyes. when de-emphasis is enable for a given group of i/os, subsequent driver values that are the same have their strength reduced by half. it is recommended that this be controllable by the bios in case there are unwanted side effects of this feature. for instance, de-emphasis should be off before entering self- refresh mode of the dram to prevent the cke from exceeding the jedec threshold once self-refresh is entered. y 00b rw 2 2 reserved reserved y 0b rw 10 fastslew bit[0] controls the control bits bit[1] controls the data bits y 00b rw table 16-288.offset 264h: ddriomc1 - ddrio mode register control register 1 (sheet 2 of 2) description: ddriomc1: ddrio mode control register 1 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 264h 267h size: 32 bit default: 52520000h power well: core bit range bit acronym bit description sticky bit reset value bit access encoding description 00 disabled 01 weakly enabled 10 full enabled others reserved encoding description 00 disabled 01 weakly enabled 10 full enabled others reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 644 order number: 320066-003us 16.5.1.64 offset 268h: ddriomc2 - ddr io mode control register 2 this register controls functionality of the ddrio. this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. acceptable values for legoverride[4:0] are 0-30d example(r_dq, dynamic): assume rext = 249 ohms r_dq = rext*2/(31-legoverride[4:0]) when legoverride[4:0] = 00000, r_dq = (249*2)/(31-0) = 16.1 ohms when legoverride[4:0] = 11110, r_dq = (249*2)/(31-30) = 498 ohms table 16-289.legoverride details mode (select via legoverride[5:4]) legoverride[9:6], [4:0] details static: legoverride[5:4] = 10b [9:6] static impedance control setting of cmd/add/clk see gray code below (valid for 1 to 10) [3:0] static impedance control setting of dq/dm/dqs see gray code below (valid for 1 to 10) dynamic: legoverride[5] = 0b [9:6] dynamic impedance control setting of cmd/add/clk r_ca = r_dq * 6.154 / legoveride[9:6] or r_min_ca (ohm) where, rext is the external r connected to ddr_drvcres pin and rmin is impedance when all the driver legs are selected. rmin is process/voltage/temp dependent. [4:0] dynamic impedance control setting of dq/dm/dqs r_dq = rext*2 / (31- legoverride[3:0]) or r_min_dq (ohm) where, rext is the external r connected to ddr_drvcres pin and rmin is impedance when all the driver legs are selected. rmin is process/voltage/temp dependent. table 16-290.legoverride - gray code csr value for static impedance control (binary) desired value for impedance control (decimal) 1000 15 1001 14 1011 13 1010 12 1110 11 1111 10 1101 9
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 645 intel ? ep80579 integrated processor : 1100 8 0100 7 0101 6 0111 5 0110 4 0010 3 00011 2 0001 1 0000 0 table 16-290.legoverride - gray code csr value for static impedance control (binary) desired value for impedance control (decimal) table 16-291.offset 268h: ddriomc2 - ddrio mode control register 2 description: ddriomc2: ddrio mode control register 2 view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 268h 26bh size: 32 bit default: 039e6000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 reserved reserved n 0000b ro 27 26 phsel core phase to command/address relationship. y 00b rw 25 16 legoverride digital impedance control for rcomp of ddr pads. see legoverride table above. do not use the default setting please refer to section 11.4.6, ?rcomp? for more details. y 1110011110b rw 15 15 fifowptrclr this bit clears the ddrio receive fifo read and write pointers. the write pointer of this fifo is generated by the ddrio logic based on dqs while the read pointer is generated by the memory controller. the ddrio receive fipo read/write pointers need to be cleared after dcal or mbist operations are completed and before issuing any functional dram r/w operations. unlike sdrc.ddrrfrs this register will reset only the read/write pointers of the ddrio receive fifo. it will not reset the dll?s. please see section 16.1.1.45, ?offset 88h: sdrc ? ddr sdram secondary control register? for more details. n0b rw 14 :12 mastcntl coarse delay of dqs master dll y 110b rw 11 :00 reserved reserved n 000000000000 b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 646 order number: 320066-003us 16.5.1.65 offset 284h: wl_cntl[4:0] - write levelization[4:0] control register this register controls functionality of write levelization (wl). the ep80579 implements 5 csr?s to control wl. the mapping of each of these csr?s to the byte lane is shown in table 16-292 . . this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. table 16-292.mapping of dq and dqs/# byte lanes to wl_cntl[4:0] csr?s csr name wl_cntl csr # generate dqs/# pulse [csr bits] latch dq feedback data [csr bits] byte 0 dqs/#[0] dq[7:0] wl_cntl[0] odd_drv_wl_pulse odd_wl_data[7:0] byte 1 dqs/#[1] dq[15:8] even_dr_wl_pulse even_wl_data[7:0] byte 2 dqs/#[2] dq[23:16] wl_cntl[1] odd_drv_wl_pulse odd_wl_data[7:0] byte 3 dqs/#[0] dq[31:24] even_dr_wl_pulse even_wl_data[7:0] byte 4 dqs/#[0] dq[39:32] wl_cntl[2] odd_drv_wl_pulse odd_wl_data[7:0] byte 5 dqs/#[0] dq[47:40] even_dr_wl_pulse even_wl_data[7:0] byte 6 dqs/#[6] dq[55:48] wl_cntl[3] odd_drv_wl_pulse odd_wl_data[7:0] byte 7 dqs/#[7] dq[63:56] even_dr_wl_pulse even_wl_data[7:0] byte 8 dqs/#[8] dq[71:64] wl_cntl[4] odd_drv_wl_pulse odd_wl_data[7:0]
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 647 intel ? ep80579 integrated processor table 16-293.offset 284h: wl_cntl[4:0] - write levelization control register description: wl_cntl[4:0]: write levelization control register view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 284h at 4h 294h at 4h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved n 0000h ro 15 :14 reserved reserved n 00b rw 13 :12 reserved reserved n 00b ro 11 :8 wl_cntrl delay select see table 16-294 y 0000b rw 7:2 wdll_cntl length controls for slave write dll (wdll). a delay of 0 up to 3/8 of clk1x can be programmed using this csr. y 00000b rw 1:1 wdll_clkg control bit for clock gating of dq/dqs. 0? disable clock gating for dq/dqs 1? enable clock gating for dq/dqs note: for wl_cntl[4], wdll_clkg must be equal to 0 y0b rw 0:0 byp_wdll bypass write dll. this bit is used only for centering dqs to the dq eye. for write leveling, see table 16-294 . 0 ? bypass dll 1 ? output with wdll before enabling/setting this bit to 1, software needs to first program the appropriate values in dramdllc.slvlen & wl_cntl[x].wdll_cntl. y0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 648 order number: 320066-003us 16.5.1.65.1 control of delay for dq/dqs there are two methods to control delay: ? adding portions of a clock cycle ? adding portions of a clock cycle as well as delay from the wdll the full control is encoded by combining the appropriate bit of wdll_misc.wl_phsel_mode with wl_cntl[x].wl_cntrl as shown in ta b l e 1 6 - 2 9 4 16.5.1.65.2 formula to calculate delay through dll delay_uncomp = 100 ps (approximate value) delay_element = (1/4 clk period - delay_uncomp) / (ddriomc2.mastcntl + 1/ 2) wdll_dly = (delay_element * wl_cntl.wdll_cntl)/8 16.5.1.66 offset 298h: wdll_misc - dll miscellaneous control this register controls miscellaneous functions of the ddrio dll. this csr is in the memory-mapped io region of bus 0, device 0, function 0 of the memory controller. the smrbase register described in section 16.1.1.9, ?offset 14h: smrbase - system memory rcomp base address register? on page 395 , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the value for bar for all registers in this section is bar14h. table 16-294. delay of dq/dqs wdll_misc.wl_phsel_mode, wl_cntl[x].wl_cntrl delay 00xxx 0 01000 wdll_dly 01011 1/4 clk + wdll_dly 01100 1/2 clk + wdll_dly 01101 3/4 clk + wdll_dly 10xxx 0 11001 1/4 clk 11000 1/2 clk 11011 3/4 clk 11100 1 clk
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 649 intel ? ep80579 integrated processor : table 16-295.offset 298h: wdll_misc - dll miscellaneous control description: wdll_misc- dll miscellaneous control view: pci bar: smrbase bus:device:function: 0:0:0 offset start: offset end: 298h 29bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :25 reserved reserved n 0000000b ro 24 :24 wlckdly 0: delay ecc/dqs[8]/dqs_l[8] only, clocks not delayed 1: delay ecc/dqs[8]/dqs_l[8] and ck[2:0]/ck_l[2:0] (normal setting for ddr2) y0b rw 23 :23 reserved reserved n 0b ro 22 :16 wl_phsel_mo de see table 16-294 for dq/dqs connectivity: [22] cs, odt, cke [21] ck[5:3], ck_l[5:3] [20] wl_cntl[0] (dq[15:0], dqs/dqs_l[1:0]) [19] wl_cntl[1] (dq[31:16], dqs/dqs_l[3:2]) [18] wl_cntl[4] (ecc[7:0], dqs/dqs_l[8],ck[2:0], ck_l[2:0]) [17] wl_cntl[2] (dq[47:32], dqs/dqs_l[5:4]) [16] wl_cntl[3] (dq[63:48], dqs/dqs_l[7:6]) y 0000000b rw 15 :12 reserved reserved n 0000000b ro 11 :8 wl_cntrl delay select for ck[5:3] and ck_l[5:3]: 0xxx: no delay 1001: delay 1/4 clk1x 1000: delay 1/2 clk1x 1011: delay 3/4 clk1x 1100: delay 1 clk1x othersreserved y 0000b rw 7 :4 wl_cntrl_a delay select for cs, odt and cke 0xxx: no delay 1001: delay 1/4 clk1x 1000: delay 1/2 clk1x 1011: delay 3/4 clk1x 1100: delay 1 clk1x othersreserved y 0000b rw 3 :3 reserved reserved n 0b ro 2 :0 wl_cmd_dly reserved to intel encoded additional delay for cs, cke, odt delay introduced = (~100ps * wl_cmd_dly) y 000b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 650 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 651 intel ? ep80579 integrated processor 16.6 memory mapped i/o for edma registers the edma is a reuse module capable of 64-bit addressing on both source and destination interfaces. for the ep80579 the edma will only be used in 32-bit addressing mode this section describes the memory-mapped registers for the edma controller. the edmalbar register, described in section 16.3.1.9, ?offset 10h: edmalbar - edma low base address register? , provides the base address for these registers. the offsets listed for the following registers are relative to this base address. the bar value for all registers in this section is bar10h. each dma channel consists of twelve 32-bit registers contiguous in memory mapped address space. the first of the four sets is described in detail, the others are copies at different offsets for the other channels. the abbreviations for the other channel register names replace the 0 at the end of the name with the appropriate channel number 1, 2, or 3.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 652 order number: 320066-003us table 16-296.bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: ccr0 - channel 0 channel control register? on page 653 00000000h 04h 07h ?offset 04h: csr0 - channel 0 channel status register? on page 656 00000000h 08h 0bh ?offset 08h: cdar0 - channel 0 current descriptor address register? on page 657 00000000h 0ch 0fh ?offset 0ch: cduar0 - channel 0 current descriptor upper address register? on page 658 00000000h 10h 13h ?offset 10h: sar0 - channel 0 source address register? on page 658 00000000h 14h 17h ?offset 14h: suar0 - channel 0 source upper address register? on page 659 00000000h 18h 1bh ?offset 18h: dar0 - channel 0 destination address register? on page 659 00000000h 1ch 1fh ?offset 1ch: duar0 - channel 0 destination upper address register? on page 660 00000000h 20h 23h ?offset 20h: ndar0 - channel 0 next descriptor address register? on page 661 00000000h 24h 27h ?offset 24h: nduar0 - channel 0 next descriptor upper address register? on page 662 00000000h 28h 2bh ?offset 28h: tcr0 - channel 0 transfer count register? on page 662 00000000h 2ch 2fh ?offset 2ch: dcr0 - channel 0 descriptor control register? on page 663 00000000h 40h 43h ?offset 40h: ccr1 - channel 1 channel control register? on page 665 00000000h 44h 47h ?offset 44h: csr1 - channel 1 channel status register? on page 665 00000000h 48h 4bh ?offset 48h: cdar1 - channel 1 current descriptor address register? on page 665 00000000h 4ch 4fh ?offset 4ch: cduar1 - channel 1 current descriptor upper address register? on page 666 00000000h 50h 53h ?offset 50h: sar1 - channel 1 source address register? on page 666 00000000h 54h 57h ?offset 54h: suar1 - channel 1 source upper address register? on page 666 00000000h 58h 5bh ?offset 58h: dar1 - channel 1 destination address register? on page 667 00000000h 5ch 5fh ?offset 5ch: duar1 - channel 1 destination upper address register? on page 667 00000000h 60h 63h ?offset 60h: ndar1 - channel 1 next descriptor address register? on page 667 00000000h 64h 67h ?offset 64h: nduar1 - channel 1 next descriptor upper address register? on page 668 00000000h 68h 6bh ?offset 68h: tcr1 - channel 1 transfer count register? on page 668 00000000h 6ch 6fh ?offset 6ch: dcr1 - channel 1 descriptor control register? on page 668 00000000h 80h 83h ?offset 80h: ccr2 - channel 2 channel control register? on page 669 00000000h 84h 87h ?offset 84h: csr2 - channel 2 channel status register? on page 669 00000000h 88h 8bh ?offset 88h: cdar2: channel 2 current descriptor address register? on page 669 00000000h 8ch 8fh ?offset 8ch: cduar2 - channel 2 current descriptor upper address register? on page 670 00000000h 90h 93h ?offset 90h: sar2 - channel 2 source address register? on page 670 00000000h 94h 97h ?offset 94h: suar2 - channel 2 source upper address register? on page 670 00000000h 98h 9bh ?offset 98h: dar2 - channel 2 destination address register? on page 671 00000000h 9ch 9fh ?offset 9ch: duar2 - channel 2 destination upper address register? on page 671 00000000h a0h a3h ?offset a0h: ndar2 - channel 2 next descriptor address register? on page 671 00000000h a4h a7h ?offset a4h: nduar2 - channel 2 next descriptor upper address register? on page 672 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 653 intel ? ep80579 integrated processor 16.6.1 register details 16.6.1.1 offset 00h: ccr0 - channel 0 channel control register the channel control register (ccr) is cleared to zero on power-on or system reset. the ccr specifies the overall operating environment for the channel. software initializes this register only after initializing the chain descriptors in system memory, and the next address registers as pointer to the first chain descriptor in memory. ccr can be written when the dma channel is active. the ccr is a read/write register. a8h abh ?offset a8h: dcr2 - channel 2transfer control register? on page 672 00000000h ach afh ?offset ach: dcr2 - channel 2 descriptor control register? on page 672 00000000h c0h c3h ?offset c0h: ccr3 - channel 3 channel control register? on page 673 00000000h c4h c7h ?offset c4h: csr3 - channel 3 channel status register? on page 673 00000000h c8h cbh ?offset c8h: cdar3 - channel 3 current descriptor address register? on page 673 00000000h cch cfh ?offset cch: cduar3 - channel 3 current descriptor upper address register? on page 674 00000000h d0h d3h ?offset d0h: sar3 - channel 3 source address register? on page 674 00000000h d4h d7h ?offset d4h: suar3 - channel 3 source upper address register? on page 674 00000000h d8h dbh ?offset d8h: dar3 - channel 3 destination address register? on page 675 00000000h dch dfh ?offset dch: duar3 - channel 3 destination upper address register? on page 675 00000000h e0h e3h ?offset e0h: ndar3 - channel 3 next descriptor address register? on page 675 00000000h e4h e7h ?offset e4h: nduar3 - channel 3 next descriptor upper address register? on page 676 00000000h e8h ebh ?offset e8h: tcr3 - channel 3 transfer count register? on page 676 00000000h ech efh ?offset ech: dcr3 - channel 3 descriptor control register? on page 677 00000000h 100h 103h ?offset 100h: dcgc - edma controller global command? on page 677 00000000h 104h 107h ?offset 104h: dcgs - edma controller global status? on page 678 00000000h table 16-296.bus 0, device 1, function 0: summary of edma configuration registers mapped through edmalbar memory bar (sheet 2 of 2) offset start offset end register id - description default value table 16-297.offset 00h: ccr0 - channel 0 channel control register (sheet 1 of 3) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 00h 03h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 reserved reserved 000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 654 order number: 320066-003us 03 crsm channel resume: 0 = cleared when: ? the channel completes a dma transfer and the next descriptor address register is not zero. in this case, the channel proceeds to the next descriptor in the chain (resumes). ? the channel is idle or the channel completes a dma transfer and the next descriptor address register is zero. 1 = causes the channel to resume chaining by re- reading the current descriptor located in local system memory and reloading the next descriptor address register when the channel is idle (the channel active bit in the csr is clear) or when the channel completes execution of the current descriptor. once set, software cannot clear this bit. the imch prevents this bit from being set when either the stopped or aborted bit is set in the csr. software must clear the csr stopped and aborted bits before attempting to resume the current descriptor chain. if the csr end of chain bit was set, the dma channel clears the end of chain bit when the current descriptor chain resumes. refer to chapter 12.0, ?enhanced direct memory access controller (edma)? for details on the suspend and resume function. 0b rws 02 stpdma stop: 0 = cleared only by the imch, once the channel active bit is cleared and the dma stopped bit is set. 1 = causes the current dma transfer to stop. the channel does not request the bus on the source side. any data in the queue is emptied to the destination side, and all relevant bits in the ccr (bits 03:00) and csr (channel active bit) are cleared. this bit has priority over the suspend dma bit. once set, this bit cannot be cleared by the software. software must be very careful in setting this bit since any dma transfer, once stopped, cannot be restarted from that point. 0b rws 01 susdma suspend: this has no effect on the channel active bit. 0 = software clears this bit once the dma suspended bit is set. clearing this bit restarts the dma transfer from the point it was suspended, and clears the dma suspended bit in the csr. refer to chapter 12.0, ?enhanced direct memory access controller (edma)? of for details on the dma suspend function. 1 = allows the current descriptor to finish, but suspends channel chaining. the channel continues to request the bus on the source side for the current descriptor. when the data in the queue for this descriptor is emptied to the destination side, the channel sets the dma suspended bit in the csr. 0b rw table 16-297.offset 00h: ccr0 - channel 0 channel control register (sheet 2 of 3) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 00h 03h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 655 intel ? ep80579 integrated processor 00 strtdma start: 0 = cleared by the imch when the dma transfer is complete, when the dma is stopped by software, or when the dma encounters any unrecoverable error. the imch prevents this bit from being set when the stopped or aborted bit is set in the csr. the dma channel must be idle and software must clear the csr before starting the dma channel with a new descriptor chain. 1 = channel is enabled for dma transfer. once set, this bit cannot be cleared by software. 0b rws table 16-297.offset 00h: ccr0 - channel 0 channel control register (sheet 3 of 3) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 00h 03h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 656 order number: 320066-003us 16.6.1.2 offset 04h: csr0 - channel 0 channel status register the channel status register (csr) contains status flags that indicate the channel status. the register is read by application software to get the current channel status and to examine the source of an interrupt. table 16-298 shows the format for the csr. table 16-298.offset 04h: csr0 - channel 0 channel status register (sheet 1 of 2) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 04h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 06 reserved reserved 0000000h 05 cactv channel active: 0 = channel is inactive and available to be configured for dma transfer by software. 1 = set by the imch, indicates the channel is in use and actively performing dma data transfers. the channel active flag is set by the imch when: ? software initiates a dma transfer by setting the start bit of ccr and the dma channel in response loads the chain descriptor from the local system memory ? software initiates a dma transfer by setting the channel resume bit of the ccr and the ndar/ nduar point to a legal non-null address in memory. 0b ro 04 dabrt aborted: 0 = software clears this bit by writing a 1 to the bit location. 1 = indicates that the current dma transfer for this channel encountered an unrecoverable error. if the aborted interrupt enable bit in the dcr is set, this generates an interrupt to the processor. software polls this bit if an interrupt is not enabled. error details are logged in the dma_ferr and dma_nerr registers. 0b rwc 03 dstp stopped: 0 = software clears this bit by writing a 1 to the bit location. 1 = indicates that the current transfer for this channel has been stopped by software setting the stop bit in the ccr. if the stopped interrupt enable bit in the dcr is set, this generates an interrupt to the processor. software can use this bit for polling if interrupts are not enabled. 0b rwc 02 dsus suspended: 0 = cleared when software clears the suspend bit in the ccr. 1 = indicates that the current transfer for this channel has been stopped by software setting the suspend bit in the ccr. if the suspended interrupt enable bit in the dcr is set, this generates an interrupt to the processor. software can use this bit for polling if interrupts are not enabled. 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 657 intel ? ep80579 integrated processor 16.6.1.3 offset 08h: cdar0 - channel 0 current descriptor address register the current descriptor address register (cdar) contains the lower 32-bit address of the current chain descriptor in local system memory. this register is loaded by the imch when a new chain descriptor is read. all chain descriptors are aligned on an eight double-word (32-bit) boundary. 01 eot end of transfer: 0 = software clears this bit by writing a ?1? to the bit location. 1 = indicates that the channel has successfully completed an error-free dma transfer of at least one descriptor. if the end of transfer interrupt enable bit in the dcr is set, this generates an interrupt to the processor. software can use this bit for polling if interrupts are not enabled. 0b rwc 00 eoc end of chain: 0 = software clears this bit by writing a ?1? to the bit location. 1 = indicates that the channel has successfully completed an error-free dma transfer, and it is the last descriptor in a chain descriptor. if the end of chain interrupt enable bit in the dcr is set, this generates an interrupt to the processor. software can use this bit for polling if interrupts are not enabled. 0b rwc table 16-298.offset 04h: csr0 - channel 0 channel status register (sheet 2 of 2) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 04h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-299.offset 08h: cdar0 - channel 0 current descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 08h 0bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 05 cdadd current descriptor address: lower 32 bits of the local system memory address of the current chain descriptor that is read by the channel. the descriptor address must be eight double-word aligned. 0000000h ro 04 : 00 reserved reserved 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 658 order number: 320066-003us 16.6.1.4 offset 0ch: cduar0 - channel 0 current descriptor upper address register the upper address will not be used in the ep80579, which is limited to 32bit addressing. the current descriptor upper address register (cduar) contains the upper 32-bit address of the current chain descriptor in local system memory. this register is loaded by the imch when a new chain descriptor is read. note: because the ep80579 supports 32 bit addressing only, this register needs to be set to ?0? at all times. 16.6.1.5 offset 10h: sar0 - channel 0 source address register the source address register (sar) contains the lower 32-bit source address for the current dma transfer. this register is loaded by the imch when the source address field of a new chain descriptor is read. table 16-300.offset 0ch: cduar0 - channel 0 current descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 0ch 0fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 cduar0 current descriptor address: the upper 32-bit local system memory address of the current chain descriptor that is read by the channel. 0000000h ro table 16-301.offset 10h: sar0 - channel 0 source address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 sar0 current source address: the lower 32-bit source memory address for the current dma transfer. 0000000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 659 intel ? ep80579 integrated processor 16.6.1.6 offset 14h: suar0 - channel 0 source upper address register the upper address will not be used in the ep80579, which is limited to 32bit addressing the source upper address register (suar) contains the upper 32-bit source address for the current dma transfer. this register is loaded by the imch when the source upper address field of a new chain descriptor is read. note: because the ep80579 supports 32 bit addressing only, this register needs to be set to ?0? at all times. 16.6.1.7 offset 18h: dar0 - channel 0 destination address register the destination address register (dar) contains the lower 32-bit destination address for the current dma transfer. this register is loaded by the imch when the destination address field of a new chain descriptor is read. table 16-302.offset 14h: suar0 - channel 0 source upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 14h 17h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 suar0 current source address: the upper 32-bit source memory address for the current dma transfer. 0000000h ro table 16-303.offset 18h: dar0 - channel 0 destination address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 18h 1bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 dar0 current destination address: the lower 32-bit destination memory address for the current dma transfer. 0000000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 660 order number: 320066-003us 16.6.1.8 offset 1ch: duar0 - channel 0 destination upper address register the upper address will not be used in the ep80579, which is limited to 32bit addressing. the destination upper address register (duar) contains the upper 32-bit destination address for the current dma transfer. this register is loaded by the imch when the destination upper address field of a new chain descriptor is read. note: because the ep80579 supports 32 bit addressing only, this register needs to be set to ?0? at all times. table 16-304.offset 1ch: duar0 - channel 0 destination upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 1ch 1fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 duar0 current destination address: the upper 32-bit destination memory address for the current dma transfer. 0000000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 661 intel ? ep80579 integrated processor 16.6.1.9 offset 20h: ndar0 - channel 0 next descriptor address register the next descriptor address register (ndar) contains the lower 32-bit address of the next descriptor chain in the local system memory. this register is loaded when the next descriptor address field of a new chain descriptor is read. additionally, software writes this register with the address of the first chain descriptor in local memory. all chain descriptors are required to be aligned on an eight double-word (32-bit) boundary or the cmi flags an error. note: software must make sure that the start bit in the ccr and the channel active bit in the csr are clear prior to writing to the ndar. the imch prevents writing to this register when these bits are not clear. writing zero into the ndar and nduar by software does not start a dma transfer. 16.6.1.10 offset 24h: nduar0 - channel 0 next descriptor upper address register the upper address will not be used in the ep80579, which is limited to 32bit addressing. the next descriptor upper address register (nduar) contains the upper 32-bit address of the next descriptor chain in the local system memory. this register is loaded when the next descriptor address field of a new chain descriptor is read. additionally, software writes this register with the address of the first chain descriptor in local memory. note: software must make sure that the start bit in the ccr and the channel active bit in the csr are clear prior to writing to the next descriptor upper address register (ndar). the imch prevents writing to this register when these bits are not clear. writing zero into the ndar and nduar by application software does not start a dma transfer. note: because the ep80579 supports 32 bit addressing only, this register needs to be set to ?0? at all times. table 16-305.offset 20h: ndar0 - channel 0 next descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 20h 23h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ndladd next descriptor lower address: lower 32 bits of the local system memory address of the next chain descriptor in memory to be read by the channel. the address must be aligned on an eight dword (32-bit) boundary or else the imch flags an error. this field can only be written when the start bit in the ccr and the channel active bit in the csr are clear. 0000000h rwl
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 662 order number: 320066-003us 16.6.1.11 offset 28h: tcr0 - channel 0 transfer count register the transfer count register (tcr) contains the number of bytes it transfers. this register is loaded when the transfer count field of the chain descriptor is read from memory. the maximum allowed value for the tcr is 16 mbytes. values greater than 16 mbytes are truncated to 16 mbytes and no error is reported. a value of zero is valid and results in no data being transferred and no cycles are generated on the source or destination buses and an interrupt is generated if enabled. during transfers, this register contains the remaining byte bytes to be written to the destination. table 16-306.offset 24h: nduar0 - channel 0 next descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 24h 27h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 nduadd next descriptor upper address: the upper 32-bit address of the next descriptor chain in memory to be read by the channel. this field can only be written when the start bit in the ccr and the channel active bit in the csr are clear. 0000000h rwl table 16-307.offset 28h: tcr0 - channel 0 transfer count register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 28h 2bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 0000000h 23 : 00 tcr0 transfer count: set by the imch when the transfer count field of the chain descriptor is read from memory. it reflects the number of bytes for a dma transfer. a value of 0 results in no data being transferred. the maximum value that can be programmed to this register is 16 mbytes. larger values written in the transfer count field of the chain descriptor are truncated, and no error is reported. refer to dcr0[18:17] for additional programming requirements when in constant address mode. 000000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 663 intel ? ep80579 integrated processor 16.6.1.12 offset 2ch: dcr0 - channel 0 descriptor control register the descriptor control register (dcr) contains control values for the dma transfer on a per descriptor basis. this register is loaded when the descriptor control field of the chain descriptor is read from memory. the value for this register may vary from chain descriptor to chain descriptor. table 16-308.offset 2ch: dcr0 - channel 0 descriptor control register (sheet 1 of 2) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 2ch 2fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 tc pci express a-segment traffic class: this field is used to set the traffic class field on the pci express bus for transactions. this field has no effect on memory to memory transactions. 000b ro 28 : 19 reserved reserved 000h 18 : 17 granularity destination granularity: 00 1 byte granularity 01 2 byte granularity (dar[0] and tcr[0] ignored) 10 4 byte granularity (dar[1:0] and tcr[1:0] ignored) 11 reserved these bits are loaded by the descriptor fetch only. this field is ignored unless bits 15:14 are 01b (selecting constant destination mode). when this field is enabled, the destination address and transfer count register must contain an integer multiple of the granularity. 00b ro 16 reserved reserved 0b 15 : 14 daddm destination processing mode: 00 increment mode 01 constant mode (bits 18:17 set the granularity) 10 reserved 11 reserved these bits are loaded by the descriptor fetch only. 00b ro 13 : 12 saddm source processing mode: 00 increment mode 01 decrement mode 10 buffer initialization 11 reserved these bits are loaded by the descriptor fetch only. 00b ro 11 : 09 reserved reserved 000b 08 srcc source coherency: 0 = source is a non-coherent address space 1 = source is a coherent address space 0b ro 07 dstc destination coherency: 0 = destination is a non-coherent address space 1 = destination is a coherent address space for pci-e writes (i/o), this bit inversely reflects the state of the snoop not required attribute header bit: 0 = snoop not required attribute bit = 1 1 = snoop not required attribute bit = 0 0b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 664 order number: 320066-003us 06 srct source type: hardwired to 0: 0 = indicates the source address points to local system memory. 1 = indicates that the source address points to i/o memory. although an i/o source type is not supported, this bit will reflect the actual source type as written by software. the imch flags an error if the source address range is not valid, and ignores the value of this bit. 0b ro 05 dstt destination type: 0 = destination address points to local system memory 1 = destination address points to i/o space an error is signaled by the imchif the destination address type read from the descriptor does not match this setting. 0b ro 04 dabrtie aborted interrupt enable: indicates whether or not an interrupt is generated when the dma aborted (dabrt) bit in the csr is set. 0 = disable 1 = enable 0b ro 03 dstpie stopped interrupt enable: indicates whether or not an interrupt is generated when the dma stopped (dstp) bit in the csr is set. 0 = disable 1 = enable 0b ro 02 dsusie suspended interrupt enable: indicates whether or not an interrupt is generated when the dma suspended (dsus) bit in the csr is set. 0 = disable 1 = enable 0b ro 01 eotie end of transfer interrupt enable: indicates whether or not an interrupt is generated when the end of transfer (eot) bit in the csr is set. 0 = disable 1 = enable 0b ro 00 eocie end of chain interrupt enable: indicates whether or not an interrupt is generated when the end of chain (eoc) bit in the csr is set. 0 = disable 1 = enable 0b ro table 16-308.offset 2ch: dcr0 - channel 0 de scriptor control register (sheet 2 of 2) description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 2ch 2fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 665 intel ? ep80579 integrated processor 16.6.1.13 offset 40h: ccr1 - channel 1 channel control register 16.6.1.14 offset 44h: csr1 - channel 1 channel status register 16.6.1.15 offset 48h: cdar1 - channel 1 current descriptor address register table 16-309.offset 40h: ccr1 - channel 1 channel control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 40h 43h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those described for ccr0 in section 16.6.1.1 . table 16-310.offset 44h: csr1 - channel 1 channel status register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 44h 47h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those described for csr0 in section 16.6.1.2 . table 16-311.offset 48h: cdar1 - channel 1 current descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 48h 4bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those described for cdar0 in section 16.6.1.3 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 666 order number: 320066-003us 16.6.1.16 offset 4ch: cduar1 - channel 1 current descriptor upper address register 16.6.1.17 offset 50h: sar1 - channel 1 source address register 16.6.1.18 offset 54h: suar1 - channel 1 source upper address register table 16-312.offset 4ch: cduar1 - channel 1 current descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 4ch 4fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those described for cduar0 in section 16.6.1.4 . table 16-313.offset 50h: sar1 - channel 1 source address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 50h 53h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those described for sar0 in section 16.6.1.5 . table 16-314.offset 54h: suar1 - channel 1 source upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 54h 57h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for suar0 described in section 16.6.1.6 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 667 intel ? ep80579 integrated processor 16.6.1.19 offset 58h: dar1 - channel 1 destination address register 16.6.1.20 offset 5ch: duar1 - channel 1 destination upper address register 16.6.1.21 offset 60h: ndar1 - channel 1 next descriptor address register table 16-315.offset 58h: dar1 - channel 1 destination address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 58h 5bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those described for dar0 in section 16.6.1.7 . table 16-316.offset 5ch: duar1 - channel 1 destination upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 5ch 5fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for duar0 described in section 16.6.1.8 . table 16-317.offset 60h: ndar1 - channel 1 next descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 60h 63h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for ndar0 described in section 16.6.1.9 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 668 order number: 320066-003us 16.6.1.22 offset 64h: nduar1 - channel 1 next descriptor upper address register 16.6.1.23 offset 68h: tcr1 - channel 1 transfer count register 16.6.1.24 offset 6ch: dcr1 - channel 1 descriptor control register table 16-318.offset 64h: nduar1 - channel 1 next descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 64h 67h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for nduar0 described in section 16.6.1.10 . table 16-319.offset 68h: tcr1 - channel 1 transfer count register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 68h 6bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for tcr0 described in section 16.6.1.11 . table 16-320.offset 6ch: dcr1 - channel 1 descriptor control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 6ch 6fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for dcr0 described in section 16.6.1.12 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 669 intel ? ep80579 integrated processor 16.6.1.25 offset 80h: ccr2 - channel 2 channel control register 16.6.1.26 offset 84h: csr2 - channel 2 channel status register 16.6.1.27 offset 88h: cdar2 - channel 2 current descriptor address register table 16-321.offset 80h: ccr2 - channel 2 channel control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 80h 83h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for ccr0 described in section 16.6.1.1 . table 16-322.offset 84h: csr2 - channel 2 channel status register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for csr0 described in section 16.6.1.2 . table 16-323.offset 88h: cdar2: channel 2 current descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 88h 8bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for cdar0 described in section 16.6.1.3 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 670 order number: 320066-003us 16.6.1.28 offset 8ch: cduar2 - channel 2 current descriptor upper address register 16.6.1.29 offset 90h: sar2 - channel 2 source address register 16.6.1.30 offset 94h: suar2 - channel 2 source upper address register table 16-324.offset 8ch: cduar2 - channel 2 current descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 8ch 8fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for cduar0 described in section 16.6.1.4 . table 16-325.offset 90h: sar2 - channel 2 source address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 90h 93h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for sar0 described in section 16.6.1.5 . table 16-326.offset 94h: suar2 - channel 2 source upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 94h 97h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for suar0 described in section 16.6.1.6 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 671 intel ? ep80579 integrated processor 16.6.1.31 offset 98h: dar2 - channel 2 destination address register 16.6.1.32 offset 9ch: duar2 - channel 2 destination upper address register 16.6.1.33 offset a0h: ndar2 - channel 2 next descriptor address register table 16-327.offset 98h: dar2 - channel 2 destination address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 98h 9bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for dar0 described in section 16.6.1.7 . table 16-328.offset 9ch: duar2 - channel 2 destination upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 9ch 9fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for duar0 described in section 16.6.1.8 . table 16-329.offset a0h: ndar2 - channel 2 next descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for ndar0 described in section 16.6.1.9 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 672 order number: 320066-003us 16.6.1.34 offset a4h: nduar2 - channel 2 next descriptor upper address register 16.6.1.35 offset a8h: tcr2 - channel 2 transfer count register 16.6.1.36 offset ach: dcr2 - channel 2 descriptor control register table 16-330.offset a4h: nduar2 - channel 2 next descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: a4h a7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for nduar0 described in section 16.6.1.10 . table 16-331.offset a8h: dcr2 - channel 2transfer control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: a8h abh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for dcr0 described in section 16.6.1.11 . table 16-332.offset ach: dcr2 - channel 2 descriptor control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: ach afh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for dcr0 described in section 16.6.1.12 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 673 intel ? ep80579 integrated processor 16.6.1.37 offset c0h: ccr3 - channel 3 channel control register 16.6.1.38 offset c4h: csr3 - channel 3 channel status register 16.6.1.39 offset c8h: cdar3 - channel 3 current descriptor address register table 16-333.offset c0h: ccr3 - channel 3 channel control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: c0h c3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for ccr0 described in section 16.6.1.1 . table 16-334.offset c4h: csr3 - channel 3 channel status register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: c4h c7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for csr0 described in section 16.6.1.2 . table 16-335.offset c8h: cdar3 - channel 3 current descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: c8h cbh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for cdar0 described in section 16.6.1.3 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 674 order number: 320066-003us 16.6.1.40 offset cch: cduar3 - channel 3 current descriptor upper address register 16.6.1.41 offset d0h: sar3 - channel 3 source address register 16.6.1.42 offset d4h: suar3 - channel 3 source upper address register table 16-336.offset cch: cduar3 - channel 3 current descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: cch cfh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for cduar0 described in section 16.6.1.4 . table 16-337.offset d0h: sar3 - channel 3 source address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: d0h d3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for sar0 described in section 16.6.1.5 . table 16-338.offset d4h: suar3 - channel 3 source upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: d4h d7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for suar0 described in section 16.6.1.6 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 675 intel ? ep80579 integrated processor 16.6.1.43 offset d8h: dar3 - channel 3 destination address register 16.6.1.44 offset dch: duar3 - channel 3 destination upper address register 16.6.1.45 offset e0h: ndar3 - channel 3 next descriptor address register table 16-339.offset d8h: dar3 - channel 3 destination address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: d8h dbh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for dar0 described in section 16.6.1.7 . table 16-340.offset dch: duar3 - channel 3 destination upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: dch dfh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for duar0 described in section 16.6.1.8 . table 16-341.offset e0h: ndar3 - channel 3 next descriptor address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: e0h e3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for ndar0 described in section 16.6.1.9 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 676 order number: 320066-003us 16.6.1.46 offset e4h: nduar3 - channel 3 next descriptor upper address register 16.6.1.47 offset e8h: tcr3 - channel 3 transfer count register table 16-342.offset e4h: nduar3 - channel 3 next descriptor upper address register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: e4h e7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for nduar0 described in section 16.6.1.10 . table 16-343.offset e8h: tcr3 - channel 3 transfer count register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: e8h ebh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for tcr0 described in ssection 16.6.1.11 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 677 intel ? ep80579 integrated processor 16.6.1.48 offset ech: dcr3 - channel 3 descriptor control register 16.6.1.49 offset 100h: dcgc - edma controller global command this register controls enabling and designation of priority channel. table 16-344.offset ech: dcr3 - channel 3 descriptor control register description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: ech efh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access the bit descriptions for this register are identical to those for dcr0 described in section 16.6.1.12 . table 16-345.offset 100h: dcgc - edma controller global command description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 100h 103h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 03 reserved reserved 0 02 pcenbl priority channel enable: 0 = no priority channel. the priority channel select bits are ignored. 1 = enable the priority channel as programmed by the priority channel select. 0b rw 01 : 00 pcslt priority channel selects: when priority channel enable is set, the dma channel selected by this field has a higher priority than the others. 00 channel 0 is the priority channel 01 channel 1 is the priority channel 10 channel 2 is the priority channel 11 channel 3 is the priority channel 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 678 order number: 320066-003us 16.6.1.50 offset 104h: dcgs - edma controller global status this register is accessed by the device driver to determine the source of an interrupt from the edma controller. table 16-346.offset 104h: dcgs - edma controller global status description: view: pci bar: edmalbar bus:device:function: 0:1:0 offset start: offset end: 104h 107h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 26 reserved reserved 00h 25 nic3 normal interrupt condition from channel 3: 0 = no channel 3 normal interrupt is generated. 1 = a channel 3 normal interrupt has been generated. 0b ro 24 eic3 error interrupt condition from channel 3: 0 = no channel 3 error interrupt is generated. 1 = a channel 3 error interrupt has been generated. the channel is in abort status. 0b ro 23 : 18 reserved reserved 00h 17 nic2 normal interrupt condition from channel 2: 0 = no channel 2 normal interrupt is generated. 1 = a channel 2 normal interrupt has been generated. 0b ro 16 eic2 error interrupt condition from channel 2: 0 = no channel 2 error interrupt is generated. 1 = a channel 2 error interrupt has been generated. the channel is in abort status. 0b ro 15 : 10 reserved reserved 00h 09 nic1 normal interrupt condition from channel 1: 0 = no channel 1 normal interrupt is generated. 1 = a channel 1 normal interrupt has been generated. 0b ro 08 eic1 error interrupt condition from channel 1: 0 = no channel 1 error interrupt is generated. 1 = a channel 1 error interrupt has been generated. the channel is in abort status. 0b ro 07 : 02 reserved reserved 00h 01 nic0 normal interrupt condition from channel 0: 0 = no channel 0 normal interrupt is generated. 1 = a channel 0 normal interrupt has been generated. 0b ro 00 eic0 error interrupt condition from channel 0: 0 = no channel 0 error interrupt is generated. 1 = a channel 0 error interrupt has been generated. the channel is in abort status. 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 679 intel ? ep80579 integrated processor 16.7 memory mapped i/o for nsi registers this section describes the memory-mapped registers for the north south interface (nsi). the nsibar register, described in section 16.1, ?imch registers: bus 0, device 0, function 0? provides the base address for these registers. the offsets listed for the following registers are relative to this base address. this root complex register block (rcrb) controls cmi?s internal serial interconnect bus.. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 16-347.bus 0, device 0, function 0: summary of imch configuration registers mapped through nsibar memory bar offset start offset end register id - description default value 00h 03h ?offset 00h: snsivcech - nsi virtual channel enhanced capability header register? on page 680 04010002h 04h 07h ?offset 04h: nsipvccap1 - nsi port vc capability register 1? on page 680 00000000h 08h 0bh ?offset 08h: nsipvccap2 - port vc capability register 2? on page 681 00000001h 0ch 0dh ?offset 0ch: nsipvcctl - nsi port vc control register? on page 682 0000h 10h 13h ?offset 10h: nsivc0rcap - nsi vc0 resource capability register? on page 682 00000001h 14h 17h ?offset 14h: nsivc0rctl - nsi vc0 resource control register? on page 683 800000ffh 1ah 1bh ?offset 1ah: nsivc0rsts - nsi vc0 resource status register? on page 684 0002h 80h 83h ?offset 80h: nsircilcech - nsi root complex internal link control enhanced capability header register? on page 684 00010006h 84h 87h ?offset 84h: nsilcap - nsi link capabilities register? on page 685 0003a041h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 680 order number: 320066-003us 16.7.1 register details 16.7.1.1 offset 00h: nsivcech - nsi virtual channel enhanced capability header register this register indicates nsi virtual channel capabilities. 16.7.1.2 offset 04h: nsipvccap1 - nsi port vc capability register 1 this register describes the configuration of pci express virtual channels associated with this port. table 16-348.offset 00h: snsivcech - nsi vi rtual channel enhanced capability header register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 00h 03h size: 32 bit default: 04010002h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 pnc pointer to next capability: this field contains the offset to the next pci express capability structure in the linked list of capabilities (link declaration capability). bits [21:20] are reserved and software must mask them to allow for future uses of these bits. 040h ro 19 : 16 pcievcc pci express virtual channel capability version: hardwired to 1 to indicate compliances with the 1.0 version of the pci express specification. 1h ro 15 : 00 ecid extended capability id: value of 0002h identifies this linked list item (capability structure) as being for pci express virtual channel registers. 0002h ro table 16-349.offset 04h: nsipvccap1 - nsi port vc capability register 1 (sheet 1 of 2) description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 04h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 07 reserved reserved 0000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 681 intel ? ep80579 integrated processor 16.7.1.3 offset 08h: nsipvccap2 - port vc capability register 2 this register describes the configuration of pci express virtual channels associated with this port. 06 : 04 lpevcc low priority extended vc count: indicates the number of (extended) virtual channels in addition to the default vc belonging to the low-priority vc (lpvc) group that has the lowest priority with respect to other vc resources in a strict-priority vc arbitration. the value of 0 in this field implies strict vc arbitration. 000b ro 03 reserved reserved 0b 02 : 00 evcc extended vc count: indicates the number of (extended) virtual channels in addition to the default vc supported by the device. the private virtual channel is not included in this count. only vc0 is supported. 000b ro table 16-349.offset 04h: nsipvccap1 - nsi port vc capability register 1 (sheet 2 of 2) description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 04h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 16-350.offset 08h: nsipvccap2 - port vc capability register 2 description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 08h 0bh size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 00h 23 : 08 reserved reserved 0000h 07 : 00 vcarbc vc arbitration capability: indicates that the only possible vc arbitration scheme is hardware fixed (in the root complex). 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 682 order number: 320066-003us 16.7.1.4 offset 0ch: nsipvcctl - nsi port vc control register 16.7.1.5 offset 10h: nsivc0rcap - nsi vc0 resource capability register table 16-351.offset 0ch: nsipvcctl - nsi port vc control register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 0ch 0dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 reserved reserved 000h 03 : 01 vcarbsel vc arbitration select: this field is programmed by software to the only possible value as indicated in the vc arbitration capability field. the value 000b when written to this field indicates the vc arbitration scheme is hardware fixed (in the root complex). this field cannot be modified when more than one vc in the lpvc group is enabled. 000b rw 00 reserved reserved 0b table 16-352.offset 10h: nsivc0rcap - nsi vc0 resource capability register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 10h 13h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 00h 15 rsnpt reject snoop transactions: 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = any transaction without the no snoop bit set within the tlp header is rejected as an unsupported request. 0b ro 14 : 08 reserved reserved 00h 07 : 00 parbc port arbitration capability: having only bit 0 set indicates that the only supported arbitration scheme for this vc is non-configurable hardware-fixed. 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 683 intel ? ep80579 integrated processor 16.7.1.6 offset 14h: nsivc0rctl - nsi vc0 resource control register this register controls the resources associated with pci express virtual channel 0. table 16-353.offset 14h: nsivc0rctl - nsi vc0 resource control register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 14h 17h size: 32 bit default: 800000ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 vc0en vc0 enable: hardwired to 1. vc0 can never be disabled. 1b ro 30 : 27 reserved reserved 0h 26 : 24 vc0id vc0 id: assigns a vc id to the vc resource. for vc0 this is hardwired to 0 and read only. 000b ro 23 : 20 reserved reserved 0h 19 : 17 parbsel port arbitration select: configures the vc resource to provide a particular port arbitration service. valid value for this field is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. because only bit 0 of that field is asserted. this field is always programmed to ?1?. 0h rw 16 : 08 reserved reserved 000h 07 : 01 tcvc0m tc/vc0 map: indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 7fh rw 00 tc0vc0m tc0/vc0 map: traffic class 0 is always routed to vc0. thus is will always read as 1b. 1b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 684 order number: 320066-003us 16.7.1.7 offset 1ah: nsivc0rsts - nsi vc0 resource status register this register reports the virtual channel specific status. 16.7.1.8 offset 80h: nsircilcech - nsi root complex internal link control enhanced capability header register this capability contains controls for the root complex internal link known as nsi. table 16-354.offset 1ah: nsivc0rsts - nsi vc0 resource status register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 1ah 1bh size: 16 bit default: 0002h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 02 reserved reserved 0000h 01 vc0np vc0 negotiation pending: 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by default on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on link. 1b ro 00 reserved reserved 0b table 16-355.offset 80h: nsircilcech - nsi root complex internal link control enhanced capability header register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 80h 83h size: 32 bit default: 00010006h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 pntnc pointer to next capability: this value terminates the pci express extended capabilities list associated with this rcrb. 000h ro 19 : 16 lnkdc link declaration capability version: hardwired to 1 to indicate compliances with the 1.0 version of the pci express specification. 1h ro 15 : 00 extcid extended capability id: value of 0006h identifies this linked list item (capability structure) as being for pci express internal link control capability. 0006h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 685 intel ? ep80579 integrated processor 16.7.1.9 offset 84h: nsilcap - nsi link capabilities register this register indicates nsi specific capabilities. table 16-356.offset 84h: nsilcap - nsi link capabilities register description: view: pci bar: nsibar bus:device:function: 0:0:0 offset start: offset end: 84h 87h size: 32 bit default: 0003a041h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 18 reserved reserved 00h 17 : 15 l1elat l1 exit latency: indicates the length of time this port requires to complete the transition from l1 to l0. the value 010 b indicate more than 64 s. both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 111b rwo 14 : 12 reserved reserved 010b 11 : 10 aslpms active state link pm support: reserved 00b 09 : 04 mxlw maximum link width: hardwired to indicate x4. 04h ro 03 : 00 mxls maximum link speed: hardwired to indicate 2.5 gbytes/s. 1h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 686 order number: 320066-003us
order number: 320066-003us integrated i/o controller hub, volume 3 of 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 688 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 689 intel ? ep80579 integrated processor 17.0 bridging and configuration 17.1 root complex memory-mapped configuration register details this section describes all registers and base functionality that are related to configuration and not a specific interface (such as lpc). it contains the root complex register block, which describes the behavior of the upstream internal link. the root complex register block is mapped into memory space using register rcba (see section 19.2.7.1, ?offset f0h: rcba: root complex base address register? ). accesses in this space must be limited to 32-bit (dword) quantities. burst accesses are not allowed. note: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failures or undetermined behavior. for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? ). table 17-1. bus 0, device 31, function 0: summary of root complex configuration registers mapped through rcba memory bar (sheet 1 of 2) offset start offset end register id - description default value 0000h 0003h ?offset 0000h: vch - virtual channel capability header register? on page 691 10010002h 0004h 0007h ?offset 0004h: vcap1 - virtual channel capability 1 register? on page 691 0801h 0008h 000bh ?offset 0008h: vcap2 - virtual channel capability 2 register? on page 692 0001h 000ch 000dh ?offset 000ch: pvc - port virtual channel control register? on page 692 0h 000eh 000fh ?offset 000eh: pvs -port virtual channel status register? on page 693 0h 0010h 0013h ?offset 0010h: v0cap - virtual channel 0 resource capability register? on page 693 00000001h 0014h 0017h ?offset 0014h: v0ctl - virtual channel 0 resource control register? on page 694 800000ffh 001ah 001bh ?offset 001ah: v0sts - virtual channel 0 resource status register? on page 695 0h 0100h 0103h ?offset 0100h: rctcl - root complex topology capabilities list register? on page 696 1a010005h 0104h 0107h ?offset 0104h: esd - element self description register? on page 696 00000102h 0110h 0113h ?offset 0110h: uld - upstream link description register? on page 697 0001h 0118h 011fh ?offset 0118h: ulba - upstream link base address register? on page 697 00000000000 00000h 01a0h 01a3h ?offset 01a0h: ilcl - internal link capabilities list register? on page 698 00010006h 01a4h 01a7h ?offset 01a4h: lcap - link capabilities register? on page 698 0012441h 01a8h 01a9h ?offset 01a8h: lctl - link control register? on page 699 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 690 order number: 320066-003us 01aah 01abh ?offset 01aah: lsts - link status register? on page 700 0041h 3108h 310bh ?offset 3108h: d29ip - device 29 interrupt pin register? on page 702 10004321h 3140h 3141h ?offset 3140h: d31ir - device 31 interrupt route register? on page 702 3210h 3144h 3145h ?offset 3144h: d29ir - device 29 interrupt route register? on page 703 3210h 31ffh 31ffh ?offset 31ffh: oic - other interrupt control register? on page 704 0h 3400h 3403h ?offset 3400h: rc - rtc configuration register? on page 704 0h 3404h 3407h ?offset 3404h: hptc - high performance precision timer configuration register? on page 705 0h 3410h 3413h ?offset 3410h: gcs - general control and status register? on page 706 variable 3414h 3417h ?offset 3414h: buc - backed up control register? on page 708 variable 3418h 341bh ?offset 3418h: fd - function disable register? on page 709 00000080h 341ch 341fh ?offset 341ch: prc - power reduction control register clock gating? on page 711 0h table 17-1. bus 0, device 31, function 0: summary of root complex configuration registers mapped through rcba memory bar (sheet 2 of 2) offset start offset end register id - description default value table 17-2. rcba base address registers in the ia f view offset start offset end register id - description default value 3000h 3001h ?offset 3000h: tctl - tco control register? on page 700 0h 3100h 3103h ?offset 3100h: d31ip - device 31 interrupt pin register? on page 701 00042210h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 691 intel ? ep80579 integrated processor 17.1.1 vc configuration registers 17.1.1.1 offset 0000h: vch - virtual channel capability header register 17.1.1.2 offset 0004h: vcap1 - virtual channel capability 1 register table 17-3. offset 0000h: vch - virtual channel capability header register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0000h 0003h size: 32 bit default: 10010002h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :20 nco next capability offset: indicates the next item in the list. 100h ro 19 :16 cv capability version: indicates this is version 1 of the capability structure by the pci sig. 1h ro 15 :00 cid capability id: indicates this is the virtual channel capability item. 0002h ro table 17-4. offset 0004h: vcap1 - virtual channel capability 1 register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0004h 0007h size: 32 bit default: 0801h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :12 reserved reserved 0h 11 :10 reserved reserved 10b 09 :08 rc reference clock: fixed at 100 ns for this version of the pci express specification . 00b ro 07 reserved reserved 0h 06 :04 lpevc low priority extended vc count: indicates that there are no additional vcs of low priority with extended capabilities. 0h ro 03 reserved reserved 0h 02 :00 reserved reserved. 001h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 692 order number: 320066-003us 17.1.1.3 offset 0008h: vcap2 - virtual channel capability 2 register 17.1.1.4 offset 000ch: pvc - port virtual channel control register table 17-5. offset 0008h: vcap2 - virtual channel capability 2 register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0008h 000bh size: 32bit default: 0001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 ato vc arbitration table offset: indicates that no table is present for vc arbitration since it is fixed. 00h ro 23 :08 reserved reserved 0h 07 :00 ac vc arbitration capability: indicates that the vc arbitration is fixed in the root complex. 01h ro table 17-6. offset 000ch: pvc - port virtual channel control register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 000ch 000dh size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :04 reserved reserved 000h 03 :01 as vc arbitration select: indicates which vc must be programmed in the vc arbitration table. the root complex takes no action on the setting of this field since there is no arbitration table. 0h rw 00 lat load vc arbitration table: indicates that the table programmed must be loaded into the vc arbitration table. this bit is defined as read/write with always returning 0 on reads. since there is no vc arbitration table in the root complex, this bit can be built as read-only. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 693 intel ? ep80579 integrated processor 17.1.1.5 offset 000eh: pvs - port virtual channel status register 17.1.1.6 offset 0010h: v0cap - virtual channel 0 resource capability register table 17-7. offset 000eh: pvs -port virtual channel status register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 000eh 000fh size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :01 reserved reserved 0000h 00 vas vc arbitration table status: indicates the coherency status of the vc arbitration table when it is being updated. this field is hardwired to 0 in the root complex since there is no vc arbitration table. 0h ro table 17-8. offset 0010h: v0cap - virtual channel 0 resource capability register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0010h 0013h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 at port arbitration table offset: this vc implements no port arbitration table since the arbitration is fixed. 00h ro 23 reserved reserved 0h 22 :16 mts maximum time slots: this vc implements fixed arbitration, and therefore this field is not used. 00h ro 15 rts reject snoop transactions: this vc must be able to take snoopable transactions. 0h ro 14 aps advanced packet switching: this vc is capable of all transactions, not just advanced packet switching transactions. 0h ro 13 :08 reserved reserved 0h 07 :00 pac port arbitration capability: indicates that this vc uses fixed port arbitration. 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 694 order number: 320066-003us 17.1.1.7 offset 0014h: v0ctl - virtual channel 0 resource control register table 17-9. offset 0014h: v0ctl - virtual channel 0 resource control register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0014h 0017h size: 32 bit default: 800000ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 en virtual channel enable: enables the vc when set. disables the vc when cleared. 0 = disables the vc 1 = enables the vc 1h ro 30 :27 reserved reserved 0h 26 :24 id virtual channel identifier: indicates the id to use for this virtual channel. 0h ro 23 :20 reserved reserved 0h 19 :17 pas port arbitration select: indicates which port table is being programmed. the root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. 0h rw 16 lat load port arbitration table: the root complex does not implement an arbitration table for this virtual channel. 0h ro 15 :08 reserved reserved 00h 07 :01 tcvc0m transaction class / virtual channel 0 map: indicates which transaction classes are mapped to this virtual channel. 0 = this transaction class is not mapped to the virtual channel 0. 1 = this transaction class is mapped to the virtual channel 0. 7fh rw 00 tc0vc0m transaction class 0/virtual channel 0 map: indicates that transaction class 0 is always mapped to vc0. 1h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 695 intel ? ep80579 integrated processor 17.1.1.8 offset 001ah: v0sts - virtual channel 0 resource status register table 17-10. offset 001ah: v0sts - virtual channel 0 resource status register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 001ah 001bh size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :02 reserved reserved 0000h 01 np vc negotiation pending: 0 = indicates the virtual channel is not being negotiated with ingress ports. 1 = indicates the virtual channel is still being negotiated with ingress ports. 0h ro 00 ats port arbitration table status: there is no port arbitration table for this vc so this bit is reserved at 0. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 696 order number: 320066-003us 17.1.2 root complex topology capability structure registers the following registers follow the pci express capability list structure as defined in the pci express* specification , to indicate the capabilities of nsi. 17.1.2.1 offset 0100h: rctcl- - root complex topology capabilities list register 17.1.2.2 offset 0104h: es - element self description register table 17-11. offset 0100h: rctcl - root complex topology capabilities list register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0100h 0103h size: 32 bit default: 1a010005h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :20 next next capability: indicates next item in the list. 1a0h ro 19 :16 cv capability version: indicates the version of the capability structure. 1h ro 15 :00 cid capability id: indicates this is a pci express link capability section of an rcrb. 0005h ro table 17-12. offset 0104h: esd - element self description register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0104h 0107h size: 32 bit default: 00000102h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 pn port number: a value of 0 to indicate the egress port for the iich. 00h ro 23 :16 cid component id: indicates the component id assigned to this element by software. this is written once by platform bios and is locked until a platform reset. 00h rwo 15 :08 nle number of link entries: indicates that one link entry (corresponding to nsi) is described by this rcrb. 01h ro 07 :04 reserved reserved 0h 03 :00 et element type: indicates that the element type is a root complex internal link. 2h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 697 intel ? ep80579 integrated processor 17.1.2.3 offset 0110h: uld - upstream link description register 17.1.2.4 offset 0118h: ulba - upstream link base address register table 17-13. offset 0110h: uld - upstream link description register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0110h 0113h size: 32 bit default: 0001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 pn target port number: this field is programmed by platform bios to match the port number of the imch . rcrb that is attached to this rcrb. 00h rwo 23 :16 tcid target component id: this field is programmed by platform bios to match the component id of the imch . rcrb that is attached to this rcrb. 00h rwo 15 :02 reserved reserved 0h 01 lt link type: indicates that the link points to the imch rcrb. 0h ro 00 lv link valid: indicates that this link entry is valid. 1h ro table 17-14. offset 0118h: ulba - upstream link base address register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 0118h 011fh size: 64 bit default: 0000000000000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :32 bau base address upper: this field is programmed by platform bios to match the upper 32-bits of base address of the imch. rcrb that is attached to this rcrb. 00000000h rwo 31 :00 bal base address lower: this field is programmed by platform bios to match the lower 32-bits of base address of the imch . rcrb that is attached to this rcrb. 00000000h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 698 order number: 320066-003us 17.1.3 internal link configuration registers 17.1.3.1 offset 01a0h: ilcl - internal link capabilities list register 17.1.3.2 offset 01a4h: lcap - link capabilities register table 17-15. offset 01a0h: ilcl - internal link capabilities list register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 01a0h 01a3h size: 32 bit default: 00010006h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :20 next next capability: indicates this is the last item in the list. 000h ro 19 :16 cv capability version: indicates the version of the capability structure. 1h ro 15 :00 cid capability id: indicates this is the capability for nsi. 0006h ro table 17-16. offset 01a4h: lcap - link capabilities register (sheet 1 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 01a4h 01a7h size: 32 bit default: 0012441h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :18 reserved reserved 0h 17 :15 el1 the ep80579 does not support l0s or l1. l1 exit latency: indicates that the exit latency is 2 s to 4 s. 010b ro 14 :12 el0 the ep80579 does not support l0s or l1. l0s exit latency: this field is read/write and updatable by bios. it defaults to 128 ns to less than 256 ns, assuming a common-clock configuration between iich and imch. if a unique clock value is used, it is recommended that bios update this field to 100 (512 ns to less than 1 s). when bios set sets this field, it must also update nsi's dbg.nfts field, located at offset 2024h in configuration space. 010b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 699 intel ? ep80579 integrated processor 17.1.3.3 offset 01a8h: lctl - link control register 11 :10 apms the ep80579 does not support l0s or l1. active state link pm support: indicates the level of active state power management on nsi. bits definition 00 neither l0s nor l1 supported 01 l0s entry supported (per pci express spec, l0s must be supported, but the ep80579 has defeatured l0s.) 10 reserved: l1 entry not supported on nsi 11 reserved: l1 entry not supported on nsi 1h rwo 09 :04 mlw maximum link width: indicates the maximum link width is four ports. 4h ro 03 :00 mls maximum link speed: indicates the link speed is 2.5 gbits/s. 1h ro table 17-17. offset 01a8h: lctl - link control register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 01a8h 01a9h size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :08 reserved reserved 00h 07 :07 reserved 0 06 :02 reserved reserved 0h 01 :00 apmc l0s has been defeatured on wl, and aspm must never be turned on. active state link pm control: indicates whether nsi must enter l0s or l1 or both. bits definition 00 disabled 01 l0s entry enabled 10 l1 entry enabled 11 l0s and l1 entry enabled 0h rw table 17-16. offset 01a4h: lcap - link capabilities register (sheet 2 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 01a4h 01a7h size: 32 bit default: 0012441h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 700 order number: 320066-003us 17.1.3.4 offset 01aah: lsts - link status register 17.1.4 tco configuration 17.1.4.1 offset 3000h: tctl - tco control register table 17-18. offset 01aah: lsts - link status register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 01aah 01abh size: 16 bit default: 0041h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :10 reserved reserved 00h 09 :04 nlw negotiated link width: minimum negotiated link width is a x4 port. the contents of this register are undefined if the link has not successfully trained. 4h ro 03 :00 ls link speed: link is 2.5 gbits/s. 1h ro table 17-19. offset 3000h: tctl - tco control register (sheet 1 of 2) description: view: ia f base address: rcba offset start: offset end: 3000h 3001h size: 8 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ie tco irq enable: 0 = tco irq is disabled. 1 = tco irq is enabled, as selected by the tco_irq_sel field. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 701 intel ? ep80579 integrated processor 17.1.5 interrupt conf iguration registers 17.1.5.1 offset 3100h: d31ip - device 31 interrupt pin register 06 : 03 reserved reserved 0h 02 : 00 is tco irq select: specifies on which irq the tco internally appears. if not using the apic, the tco interrupt must be routed to irq9-11, and that interrupt is not sharable with the serirq stream, but it can be shared with other pci interrupts. if using the apic, the tco interrupt can also be mapped to irq20-23 and can be shared with other interrupt. bits sci map 000 irq9 001 irq10 010 irq11 011 reserved 100 irq20 (only if apic enabled) 101 irq21 (only if apic enabled) 110 irq22 (only if apic enabled) 111 irq23 (only if apic enabled) when setting these bits, the ie bit must be cleared to prevent glitches. when the interrupt is mapped to apic interrupts 9, 10, or 11, the apic must be programmed for active-high reception. when the interrupt is mapped to apic interrupts 20 through 23, the apic must be programmed for active-low reception. 000h rw table 17-20. offset 3100h: d31ip - device 31 interrupt pin register description: view: ia f base address: rcba offset start: offset end: 3100h 3103h size: 32 bit default: 00042210h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h 15 : 12 smip sm bus pin: see the cip description. this field applies to the sm bus controller. 2h rw 11 : 08 sip sata pin: see the cip description. this field applies to the sata controller. 2h rw 07 : 04 reserved reserved 1h 03 : 00 pip pci bridge pin: see the cip description. this field applies to the pci bridge. currently, the pci bridge does not generate an interrupt so this field is read-only and ?0?. 0h ro table 17-19. offset 3000h: tctl - tco control register (sheet 2 of 2) description: view: ia f base address: rcba offset start: offset end: 3000h 3001h size: 8 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 702 order number: 320066-003us 17.1.5.2 offset 3108h: d29ip - device 29 interrupt pin register 17.1.5.3 offset 3140h: d31ir - device 31 interrupt route register table 17-21. offset 3108h: d29ip - device 29 interrupt pin register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3108h 310bh size: 32 bit default: 10004321h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 28 eip ehci pin: indicates which pin the ehci controller drives as its interrupt. bits pin bits pin 0h no interrupt 1h inta# 2h intb# 3h intc# 4h intd# 5h?fh reserved 1h rw 27 : 16 reserved reserved 0h 15 : 12 reserved reserved 4h 11 : 08 reserved reserved 3h 07 : 04 rsvd reserved. 2h rw 03 : 00 u0p uhci 0 pin: see the eip description. applies to uchi controller 0 (ports 0 and 1). 1h rw table 17-22. offset 3140h: d31ir - device 31 interrupt route register (sheet 1 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3140h 3141h size: 16 bit default: 3210h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0h 14 : 12 idr interrupt d pin route: indicates which physical pin on th e iich is connected to the intd# pin reported for device 31 functions. bits pin 0h pirqa# 1h pirqb# 2h pirqc# 3h pirqd# 3h rw 11 reserved reserved 0h 10 : 08 icr interrupt c pin route: see the idr description. this field applies to intc#. 2h rw 07 reserved reserved 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 703 intel ? ep80579 integrated processor 17.1.5.4 offset 3144h: d29ir - device 29 interrupt route register 06 : 04 ibr interrupt b pin route: see the idr description. this field applies to intb#. 1h rw 03 reserved reserved 0h 02 : 00 iar interrupt a pin route: see the idr description. this field applies to inta#. 0h rw table 17-23. offset 3144h: d29ir - device 29 interrupt route register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3144h 3145h size: 16 bit default: 3210h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0h 14 : 12 idr interrupt d pin route: indicates which physical pin on the iich is connected to the intd# pin reported for device 29 functions. bits pin 0h pirqa# 1h pirqb# 2h pirqc# 3h pirqd# 3h rw 11 reserved reserved 0h 10 : 08 icr interrupt c pin route: see the idr description. this field applies to intc#. 2h rw 07 reserved reserved 0h 06 : 04 ibr interrupt b pin route: see the idr description. this field applies to intb#. 1h rw 03 reserved reserved 0h 02 : 00 iar interrupt a pin route: see the idr description. this field applies to inta#. 0h rw table 17-22. offset 3140h: d31ir - device 31 interrupt route register (sheet 2 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3140h 3141h size: 16 bit default: 3210h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 704 order number: 320066-003us 17.1.5.5 offset 31ffh: oic - other interrupt control register 17.1.6 general configuration registers 17.1.6.1 offset 3400h: rc - rtc configuration register table 17-24. offset 31ffh: oic - other interrupt control register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 31ffh 31ffh size: 8 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 0h 01 cen coprocessor error enable: 0 = ferr# does not generate irq13 nor ignne#. 1 = if ferr# is low, the iich generates irq13 internally and holds it until an i/o port f0h write. it also drives ignne# active. 0h rw 00 aen apic enable: 0 = the internal ioxapic is disabled. 1 = enables the internal ioxapic and its address decode. 0h rw table 17-25. offset 3400h: rc - rtc configuration register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3400h 3403h size: 32 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 05 reserved reserved 0h ro 04 ul upper 128 byte lock: 0 = bytes 38h-3fh in the upper 128-byte bank of rtc ram are not locked and can be accessed. writes are not dropped and reads return any guaranteed data. 1 = bytes 38h-3fh in the upper 128-byte bank of rtc ram are locked and cannot be accessed. writes are dropped and reads do not return any guaranteed data. bit reset on system reset. 0h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 705 intel ? ep80579 integrated processor 17.1.6.2 offset 3404h: hptc - high performance precision timer configuration register this register specifies the base address in memory space at which the high performance precision timer registers from section 32.2.1, ?register descriptions? materialize. 03 ll lower 128 byte lock: 0 = bytes 38h-3fh in the lower 128-byte bank of rtc ram are not locked and can be accessed. writes are not dropped and reads return any guaranteed data. 1 = bytes 38h-3fh in the lower 128-byte bank of rtc ram are locked and cannot be accessed. writes are dropped and reads do not return any guaranteed data. bit reset on system reset. 0h rwo 02 ue upper 128 byte enable: 0 = the upper 128-byte bank of rtc ram can not be accessed. 1 = the upper 128-byte bank of rtc ram can be accessed. 0h rw 01 : 00 reserved reserved 0h table 17-25. offset 3400h: rc - rtc configuration register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3400h 3403h size: 32 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access table 17-26. offset 3404h: hptc - high performance precision timer configuration register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3404h 3407h size: 32 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 08 reserved reserved 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 706 order number: 320066-003us 17.1.6.3 offset 3410h: gcs: general control and status register 07 ae address enable: 0 = the iich does not decode the high performance timer memory address range selected by bits 01:00. 1 = the iich decodes the high performance timer memory address range selected by bits 01:00. 0h rw 06 : 02 reserved reserved 0h 01 : 00 as address select: this 2-bit field selects one of four possible memory address ranges for the high performance timer functionality. the encodings are: bits memory address range 00 fed0_0000h - fed0_03ffh 01 fed0_1000h - fed0_13ffh 10 fed0_2000h - fed0_23ffh 11 fed0_3000h - fed0_33ffh 0h rw table 17-26. offset 3404h: hptc - high performance precision timer configuration register description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3404h 3407h size: 32 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access table 17-27. offset 3410h: gcs - general control and status register (sheet 1 of 3) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3410h 3413h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 00h 23 : 16 bds bist_delay_sel: this field determines the amount of time, measured in 125 mhz clocks, waits to deassert the init# signal after sending the cpu_reset_done_ack message. notes: 1 this field only has meaning if the bist_en bit (bit 2 in the buc register) is also set. 2 a value of 00h or 01h in this field is not permitted. 3 a 1 clock variation permitted in the actual-time the init# signal goes inactive. 4 this field is in the core well. 5 this field is not reset by a cf9 reset with value 06h. implementation choice: this register does not need to be reset by any reset. xxh rw 15 12 reserved reserved 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 707 intel ? ep80579 integrated processor 11 : 10 bbs boot bios straps: this field determines the destination of accesses to the bios memory range. 00 = spi 01 = reserved 10 = reserved. 11 = lpc ? when spi or lpc is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. the value in this field can be overwritten by software as long as the bios interface lock-down (bit 0) is not set. strap rw special 09 serm server error reporting mode: 0 =the iich is the final target of all errors. the imch sends a do_serr messages to the iich for the purpose of generating nmi. 1 = the imch is the final target of all errors from pci express and nsi. in this mode, if the iich detects a fatal, non-fatal, or correctable error on nsi, it sends one of err_fatal, err_nonfatal, or err_corr to imch. 0h rw 08 : 07 reserved reserved 0h 06 fme ferr# mux enable: this bit enables ferr# to be a cpu break event indication. 0 = does not examine ferr# during a c2, or c4 state as a break event. 1 = iich examines ferr# during a c2, or c4 state as a break event. 0h rw 05 nr no reboot: this bit is set when the ?no reboot? strap is sampled high on pwrok. this bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates ?no reboot?. 0 = the tco timer does not count down and generate the smi# on the first timeout, but reboots on the second timeout. 1 = the tco timer counts down and generates the smi# on the first timeout, but does not reboot on the second timeout. strap rw 04 ame alternate access mode enable: 0 = read-only registers cannot be written, and write-only registers cannot be read. see section 27.6 for details. 1 = read-only registers can be written, and write-only registers can be read. see section 27.6 for details. 0h rw 03 reserved reserved 0b ro table 17-27. offset 3410h: gcs - general control and status register (sheet 2 of 3) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3410h 3413h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 708 order number: 320066-003us 17.1.6.4 offset 3414h: buc - backed up control register all bits in this register are in the rtc well and only cleared by rtest. 02 rpr reserved page route: determines where to send the reserved page registers. these addresses are sent to pci or lpc for the purpose of generating post codes. the i/o addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8ch, 8dh, and 8eh. 0 = writes are forwarded to lpc, shadowed within the iich, and reads are returned from the internal shadow. 1 = writes are forwarded to pci, shadowed within the iich, and reads are returned from the internal shadow. note: if some writes are done to lpc/pci to these i/o ranges, and then this bit is flipped, such that writes now go to the other interface, the reads do not return what was last written. shadowing is performed on each interface. the aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9ch, 9dh, and 9eh, are always decoded to lpc. 0h rw 01 reserved reserved 0h 00 tsld top swap lock-down: 0 = this bit can only be written from 0 to 1 once. buc.ts can be changed. 1 = prevents buc.ts from being changed. 0h rwo table 17-27. offset 3410h: gcs - general control and status register (sheet 3 of 3) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3410h 3413h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access table 17-28. offset 3414h: buc - backed up control register (sheet 1 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3414h 3417h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 709 intel ? ep80579 integrated processor 17.1.6.5 offset 3418h: fd - function disable register when disabling usb1 host controllers, the usb 2.0 ehci structural parameters registers must be updated with coherent information in ?number of companion controllers? and ?n_ports? fields. when disabling a function, only the configuration space is disabled. software must ensure that all functionality within a controller that is not desired (such as memory spaces, i/o spaces, and dma engines) is disabled prior to disabling the function. 02 cbe cpu bist enable: 0 = the init# signal is not driven active when cpurst# is active. 1= the init# signal is driven active when cpurst# is active. init# goes inactive with the same timings as the other cpu interface signals (hold time after cpurst# inactive). this bit is in the resume well and is reset by rsmrst#, but not pcirst# nor cf9h writes. 0h rw 01 reserved reserved 0h 00 ts top swap: 0 = iich does not invert a16. 1 = iich inverts a16 for cycles going to the bios space (but not the feature space) in the fwh. if the iich is strapped for top-swap (gnt[6]# is low at rising edge of pwrok), then this bit cannot be cleared by software. the strap jumper must be removed and the system rebooted. strap rw table 17-28. offset 3414h: buc - backed up control register (sheet 2 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3414h 3417h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access table 17-29. offset 3418h: fd - function disable register (sheet 1 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3418h 341bh size: 32 bit default: 00000080h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 reserved reserved 0h ro 19 reserved reserved 0h ro 18 reserved reserved 0h ro 17 reserved reserve d 0h ro 16 reserved reserv ed 0h ro 15 u2d usb 2.0 disable: 0 = the usb 2.0 host controller is enabled. 1 = the usb 2.0 host controller is disabled. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 710 order number: 320066-003us 14 lbd lpc bridge disable: 0 = the lpc bridge is enabled. 1 = the lpc bridge is disabled. unlike the other disables in this register, the following additional spaces no longer are decoded by the lpc bridge: ? memory cycles below 16 mbytes (1000000h) ? i/o cycles below 64 kbytes (10000h) ? the internal i/oxapic at fec0_0000 to fecf_ffff ? memory cycles in the lpc bios range below 4 gbyte are still decoded when this bit is set, but the aliases at the top of 1 mbyte (the e and f segment) are no longer decoded. 0h rw 13 : 12 reserved reserved 0h ro 11 reserved reserved 0h ro 10 reserved reserved 0h ro 09 reserved reserved 0h ro 08 u1d usb1 #1 disable: 0 = when reset, the first usb 1.1 controller (ports 0 and 1) is enabled. 1 = when set, the first usb 1.1 controller (ports 0 and 1) is disabled. 0h rw 07 reserved reserved 1h ro 06 reserved reserved 0h ro 05 reserved reserved 0h ro 04 reserved reserved 0h ro 03 sd sm bus disable: 0 = the sm bus controller is enabled. 1 = the sm bus controller is disabled. 0h rw 02 sad serial ata disable: 0 = the serial ata controller is enabled. 1 = the serial ata controller is disabled 0h rw 01 reserved reserved 0h rw 00 reserved reserved table 17-29. offset 3418h: fd - function disable register (sheet 2 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3418h 341bh size: 32 bit default: 00000080h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 711 intel ? ep80579 integrated processor 17.1.6.6 offset 341ch: prc - power reduction control register clock gating table 17-30. offset 341ch: prc - power reduction control register clock gating description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 341ch 341fh size: 32 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 01 reserved reserved 0h 00 reserved reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 712 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 713 intel ? ep80579 integrated processor 18.0 system management 18.1 overview the cmi provides various functions to make a system easier to manage and lower the total cost of ownership (tco) of the system. features and functions can be augmented via external a/d converters and gpio, as well as an external microcontroller. the following features and functions are supported by cmi: ? first timer to generate smi# after programmable time. ? first timeout causes smi#; allows for smm-based recovery from operating system lockup. ? operating system-based software agent accesses cmi to periodically reload timer. ? ability for smm handler to generate ?tco? interrupt to operating system. ? allows for operating system-based code augmentation. ? ability for operating system to generate smi#. ? call-back from operating system to tco code in smm handler. ? second hard coded timeout to generate reboot. ? used only after first timeout occurs. ? second timeout allows for automatic system reset and reboot if hardware error detected. various system states are preserved via this special reset to allow for possible error detection and correction. ? reset associated with reboot may attempt to preserve some registers for diagnostic purposes. ? smi# handler must reload the main timer within 2.4 s to prevent the second timer from causing a reboot (timeout du ring smi is assumed as broken cpu or stuck hardware). ? option to prevent reset if second timeout occurs. ? processor present detection. ? detects if processor fails to fetch the first instruction after reset. ? if cpu failure detected, option to pulse a gpio or send smbus message. the smbus message can be used to indicate to an external lan controller to send a distress message. the gpio can control an led with optional blink. ? ability to handle various errors (such as ecc errors) indicated by the imch. ? can generate smi# or tco interrupt. ? intruder detect input. ? can generate tco interrupt or smi# when the system cover is removed. ? ability for tco messages to coexist with standard smbus devices. ? detection of bad fwh programming.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 714 order number: 320066-003us ? detects if data on first read is ffh (indicates unprogrammed firmware hub). 18.2 tco i/o-mapped configuration register details the tco logic is accessed via registers mapped to the pci configuration space (device 31, function 0) and the system i/o space. for tco pci configuration registers, see section 19.0, ?lpc interface: bus 0, device 31, function 0? . note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero va lues and are read only. writes to reserved locations may cause system failure and unpredictable results. note: reserved bits are read only. table 18-1. bus 0, device 31, function 0: summary of tco configuration registers mapped through tcobase i/o bar? offset start offset end register id - description default value 00h 01h ?offset 00h: trld - tco timer reload and current value register? on page 715 0000h 02h 02h ?offset 02h: tdi - tco data in register? on page 715 00h 03h 03h ?offset 03h: tdo - tco data out register? on page 716 00h 04h 04h ?offset 04h: tsts1 - tco 1 status register? on page 716 0000h 06h 07h ?offset 06h: tsts2 - tco 2 sts register? on page 718 0000h 08h 09h ?offset 08h: tctl1 - tco 1 control register? on page 720 0000h 0ah 0bh ?offset 0ah: tctl2 - tco 2 control register? on page 721 0008h 0ch at 01h 0ch at 01h ?offset 0ch: tmsg[1-2] - tco message register? on page 721 00h 0eh 0eh ?offset 0eh: twds - tco watchdog status register? on page 722 00h 10h 10h ?offset 10h: le - legacy elimination register? on page 722 03h 12h 13h ?offset 12h: ttmr - tco timer initial value register? on page 723 0004h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 715 intel ? ep80579 integrated processor 18.2.1 tco pci configuration registers see chapter 19.0, ?lpc interface: bus 0, device 31, function 0.? allows setting of the base address for the i/o space and routing of the tco interrupt. 18.2.2 bus 0, device 31, function 0: tco configuration register (i/o- mapped via abase bar) summary table the tco i/o registers reside in a 32-byte range that starts 96 bytes above the power management (acpi) i/o space ( section 19.2.2.1, ?offset 40h: abase: acpi base address register? ). thus tcobase (io) =abase (io) + 60h in the pci configuration space. ta bl e 1 8 - 2 shows the mapping of the registers within that 32-byte range. each register is described in the following sections. 18.2.2.1 offset 00h: trld - tco timer reload and current value register 18.2.2.2 offset 02h: tdi - tco data in register table 18-2. offset 00h: trld - tco timer reload and current value register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 00h 01h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved . 00h ro 09 : 00 trld tco timer value: reading this register returns the current count of the tco timer. writing any value to this register reloads the timer to prevent the timeout. 000h rw table 18-3. offset 02h: tdi - tco data in register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 02h 02h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 tdi this data register field is used for passing commands from the operating system to the smi handler. writes to this register cause an smi and set the os_tco_smi bit in the tco_sts register (d31, f0, 04h). 00h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 716 order number: 320066-003us 18.2.2.3 offset 03h: tdo - tco data out register 18.2.2.4 offset 04h: tsts1 - tco 1 status register unless otherwise indicated, these bits are ?s ticky? and are cleared by writing a one to the corresponding bit position. table 18-4. offset 03h: tdo - tco data out register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 03h 03h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 tdo this data register field is used for passing commands from the smi handler to the operating system. writes to this register sets the tco_int_sts bit in the tco_sts register. it also causes an interrupt, as selected by the tco_irq_sel bits. 00h rw table 18-5. offset 04h: tsts1 - tco 1 status register (sheet 1 of 3) description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 04h 04h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 13 reserved reserved 000h ro 12 mchserr_sts 0 = software clears this bit by writing a 1 to it. 1 = the imch sent a special cycle message nsi indicating that it wants to cause an serr#. the software must read the imch to determine the reason for the serr#. 0h rwc 11 reserved reserved. 0h ro 10 mchsmi_sts 0 = software clears this bit by writing a 1 to it. 1 = imch sends a special cycle message indicating that it wants to cause an smi. the software must read the imch to determine the reason for the smi. 0h rwc 09 mchsci_sts 0 = software clears this bit by writing a 1 to it. 1 = imch sends a special cycle message indicating that it wants to cause an sci. the software must read the imch to determine the reason for the sci. 0h rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 717 intel ? ep80579 integrated processor 08 bioswr_sts 0 = software clears this bit by writing a 1 to it. 1 = the cmi sets this bit and generates and smi# to indicate an illegal attempt to write to the bios. this occurs when either: a) the bioswp bit is changed from 0 to 1 and the bld bit is also set, or b) any write is attempted to the bios and the bioswp bit is also set. note: on write cycles attempted to the 4 mbyte lower alias to the bios space, the bioswr_sts is not set. 0h rwc 07 newcentury_ sts this bit is in the rtc well. 0 = cleared by writing a 1 to the bit position or by rtest# going active. 1 = this bit is set when the year byte (index offset 09h) rolls over from 1999 to 2000. if the bit is already 1, it remains 1. when this bit is set, an smi# is generated. however, this is not a wake event (i.e., if the system is in a sleeping state when the newcentury_sts bit is set, the system does not wake up). note: the newcentury_sts is not valid when the rtc battery is first installed (or if the rtc battery does not provide sufficient power when the system is unplugged). software can determine that the rtc well was not maintained by checking the rtc_pwr_sts bit (d31:f0:a4, bit 2) or by other means (such as doing a checksum on the rtc ram array). if the rtc power is determined to not have been maintained, the bios must set the time to a legal value and then clear the newcentury_sts bit. the newcentury_sts bit may take up to 3 rtc clocks for the bit to be cleared when a 1 is written to the bit to clear it. after writing a 1 to the newcentury_sts bit, software must not exit the smi handler until verifying that the bit has actually been cleared. this ensures that the smi is not reentered. 0h rwc 06 : 04 reserved reserved 0h ro 03 timeout 0 = software clears this bit by writing a 1 to it. 1 = set to indicate that the smi was caused by the tco timer reaching 0. note: the smi handler must clear this bit to prevent an immediate reentry to the smi handler. 0h rwc table 18-5. offset 04h: tsts1 - tco 1 status register (sheet 2 of 3) description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 04h 04h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 718 order number: 320066-003us 18.2.2.5 offset 06h: tsts2 - tco 2 sts register 02 tco_int_sts 0 = software clears this bit by writing a 1 to it. 1 = smi handler caused the interrupt by writing to the tco_dat_out register (tcobase + 03h). 0h rwc 01 os_tco_smi 0 = software clears this bit by writing a 1 to it. 1 = software caused an smi# by writing to the tco_dat_in register (tcobase + 02h). 0h rwc 00 nmi2smi_sts 0 = cleared by clearing the associated nmi# status bit. 1 = set when an smi# occurs because an event occurred that would otherwise have caused an nmi#. note: the nmi2smi_sts bit must not be ?sticky bit?. it must be a simple or gate to indicate that one of the nmi sources has caused the smi. each of the nmi sources already has its own sticky bit feeding the or gate. note: writes to this bit have no effect. 0h rwc table 18-6. offset 06h: tsts2 - tco 2 sts register (sheet 1 of 2) description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 06h 07h size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 05 reserved reserved 000h ro 04 smlink_ slave_ smi_sts allows the software to go directly into predetermined sleep state. this avoids race conditions. software clears this bit by writing a 1 to it. 0 = the bit is reset by rsmrst#, but not due to the pci reset associated with exit from s3?s5 states. 1 = the cmi sets this bit to 1 when it receives the smi message (encoding 08h in the command type) on the smlink's slave interface. this bit is in the resume well. it is reset by rsmrst#? 0h rwc 03 bad_bios this bit is not intended to be read by the bios or software. it is only used for sending the tco messages to an external lan controller. 0 = the first bios read is not ffh. this is detected when the initial read returns ffh from the fwh. reads to this bit always return 0 and writes have no effect. 1 = ffh is detected on the first bios read (i.e., the bios is bad). 0h ro table 18-5. offset 04h: tsts1 - tco 1 status register (sheet 3 of 3) description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 04h 04h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 719 intel ? ep80579 integrated processor 02 doacpu_ sts 0 = cleared based on rsmrst# or by software writing a 1 to this bit. software must first clear the second_to_sts bit before writing a 1 to clear the boot_sts bit. 1 = set to 1 when the second_to_sts bit goes from 0 to 1 and the processor has not fetched the first instruction. if rebooting due to a second_to_sts bit set (= 1) and the doacpu_sts bit is: 0 = the bios can conclude that the system rebooted due to some lockup (such as on nsi), but not due to a processor booting issue. 1 = reboots using the ?safe? multiplier (1111). this allows the system to recover from a processor frequency multiplier that is too high, and allows the bios to check the doacpu_sts bit at boot. if the bit is set and the frequency multiplier is 1111, then the bios knows that the processor has been programmed to an illegal multiplier. note: software must clear the second_to_sts bit first, then the doacpu_sts bit (use two separate i/o write operations). 0h rwc 01 second_ to_sts 0 = software clears this bit by writing a 1 to it or by a rsmrst#. 1 = sets this bit to 1 to indicate that the timeout bit had been (or is currently) set and a second timeout occurred before the tco_rld register was written. if this bit is set and the no_reboot configuration bit is 0, then reboots the system after the second timeout. the reboot is done by asserting pltrst#. 0h rwc 00 intrd_det intruder detect. this bit resides in the rtc well. 0 = software clears this bit by writing a 1 to this bit or by rtest#. 1 = set to indicate that an intrusion was detected. this bit is latched. the intruder# signal must be asserted for a minimum of 1 ms to guarantee that the intrd_det bit is set. this bit has a recovery time. after writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 s before it is read as a 0. software must be aware of this recovery time when reading this bit after clearing it. if the intruder# signal is active when the software attempts to clear the intrd_det bit, the bit remains one, and the smi# is generated again immediately. the smi handler can clear the intrd_sel bits (tcobase + 0ah, bits 2:1) to avoid further smis. however, if the intruder# signals goes inactive and then active again, there is not further smis (because the intrd_sel bits would select that no smi# be generated). if the intruder# signal goes inactive some point after the intrd_det bit is written as a 1, then the intrd_det signal goes to a 0 when intruder# input signal goes inactive. this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. 0h rwc table 18-6. offset 06h: tsts2 - tco 2 sts register (sheet 2 of 2) description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 06h 07h size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 720 order number: 320066-003us 18.2.2.6 offset 08h: tctl1 - tco 1 control register table 18-7. offset 08h: tctl1 - tco 1 control register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 08h 09h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 13 reserved reserved 000h ro 12 tco_lock 0 = a core well reset is required to change this bit from 1 to 0. this bit defaults to 0. 1 = this bit prevents writes from changing the tco_en bit (in offset 30h of power management i/o space). once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. 0h rw 11 tco_tmr_ halt 0 = the tco timer is enabled to count. 1 = the tco timer halts. it does not count, and thus cannot reach a value that causes an smi# or set the second_to_sts bit. when set, this bit prevents rebooting. 0h rw 10 send_now 0 = clears this bit when it has completed sending the message. warning: software must not set this bit to 1 again until the cmi has set it back to 0. 1 = set the send_now bit and causes the lan controller to reset, which can have unpredictable side-effects. unless software protects against these side-effects, software must not set or otherwise use the send_now bit. 0h rw 09 nmi2smi_en 0 = normal nmi functionality 1 = setting this bit 1 forces all nmis to instead cause an smi#, and is reported in the tco1_sts register. nmi2smi_en bit is set and the nmi_en bit is set, the nmi# is routed to cause an smi#. no nmi is caused. however, if the gbl_smi_en bit is not set, then no smi# is generated, either. if nmi2smi_en is set but the nmi_en bit is not set, then no nmi or smi# is generated. the following table shows the possible combinations: 0h rw 08 nmi_now 0 = software clears this bit by writing a 1 to it. the nmi handler is expected to clear this bit. another nmi is not generated until the bit is cleared. 1 = writing a 1 to this bit causes an nmi. this allows the bios or smi handler to force an entry to the nmi handler. 0h rwc 07 : 00 reserved reserved 00h ro nmi_en gbl_smi _en description 0b 0b no smi# at all because gbl_smi_en = 0 0b 1b smi# is caused due to nmi events 1b 0b no smi# at all because gbl_smi_en = 0 1b 1b no smi# due to nmi because nmi_en = 1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 721 intel ? ep80579 integrated processor 18.2.2.7 offset 0ah: tctl2 - tco 2 control register 18.2.2.8 offset 0ch: tmsg[1-2] - tco message register note: the following table represents two registers. table 18-8. offset 0ah: tctl2 - tco 2 control register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 0ah 0bh size: 16 bit default: 0008h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 06 reserved reserved 000h ro 05 : 04 os_policy operating system-based software writes to these bits to select the policy that the bios uses after the platform resets due the wdt. the following convention is recommended for the bios and operating system: 00 boot normally 01 shut down 10 do not load operating system. hold in preboot state and use lan to determine next step 11 reserved note: these are scratchpad bits. they must not be reset when the tco logic resets the platform due to watchdog timer. 00h rw 03 gpio11_ alert_ disable at reset (via rsmrst# asserted) this bit is set and gpi[11] alerts are disabled. 0 = enable 1 = disable gpi[11]/smbalert# as an alert source for the smbus slave 1rw 02 : 01 intrd_sel this field selects the action to take if the intruder# signal goes active. 00 no interrupt or smi# 01 interrupt (as selected by tco_int_sel). 10 smi# 11 reserved 00h rw 00 reserved reserved 0h ro table 18-9. offset 0ch: tmsg[1-2] - tco message register description: offset: tmsg[1] = 0ch-0ch; tmsg[2] = 0dh-0dh view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 0ch at 01h 0ch at 01h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 tmsg the value written into this register is sent out in the message field of the smbus event messages. bios can write to this register to indicate its boot progress which can be monitored externally. 00h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 722 order number: 320066-003us 18.2.2.9 offset 0eh: twds - tco watchdog status register 18.2.2.10 offset 10h: le - legacy elimination register table 18-10. offset 0eh: twds - tco watchdog status register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 twds the value written to this register is passed via smbus to an external lan controller. it can be used by the bios or system management software to indicate more details on the boot progress. the register is reset to 00h based on a rsmrst# (but not pci reset). 00h rw table 18-11. offset 10h: le - legacy elimination register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 10h 10h size: 8 bit default: 03h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 00h ro 01 irq12_cause 0 = when software sets the bit to 0, irq12 is low (not asserted). 1 = when software sets the bit to 1, irq12 is high (asserted). 1rw 00 irq1_cause 0 = when software sets the bit to 0, irq1 is low (not asserted). 1 = when software sets the bit to 1, irq1 is high (asserted). 1rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 723 intel ? ep80579 integrated processor 18.2.2.11 offset 12h: ttmr - tco timer initial value register 18.3 tco signal usage 18.3.1 intruder# signal this signal can be used to detect the chassis being opened. the activation of this signal can be used to cause an smi#, and is reported via the event mechanism. if smi# is desired, the signals level can be read, so this can be used as a type of general purpose input. 18.3.2 pin straps some of the tco functions are decided at power up (rising edge of pwrok). see the pinlist for specific assignments of pin straps. 18.3.3 smlink signals the cmi supports tco compatible mode connectivity. theiichsupports external lan controllers. an external lan controller can be used to receive or retrieve tco message or information on host smbus if needed. in legacy tco mode messages are driven via smlink. for the cmi, messages on this link use smbus protocol at the rates described in chapter 24.0, ?smbus controller functional description: bus 0, device 31, function 3,? for tco compatible mode. 18.4 tco theory of operation 18.4.1 overview the system management functions are designed to allow the system to diagnose failing subsystems. the intent of this logic is that the system management functionality be provided without the aid of an external micro controller. the cmi?s system management logic allows for diagnostic and recovery software to be distributed between an smi handler and operating system-based code. table 18-12. offset 12h: ttmr - tco timer initial value register description: view: pci bar: tcobase (io) bus:device:function: 0:31:0 offset start: offset end: 12h 13h size: 16 bit default: 0004h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 10 reserved reserved 00h ro 09 : 00 ttmr value that is loaded into the timer each time the tco_rld register is written. values of 0000h or 0001h are ignored and must not be attempted. the timer is clocked at approximately 0.6 s, and thus allows timeouts ranging from 1.2 s to 613.8 s. note: the timer has an error of +/- 1 tick (0.6 s). the tco timer only counts down in the s0 state. 004h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 724 order number: 320066-003us 18.4.2 detecting a doa cpu or system when the processor is reset, it is expected to fetch its first instruction. if the processor fails to fetch the first instruction after reset, the tco timer times out twice and cmi asserts pltrst#. if tco reboots are not enabled, then: a. the smlink sends out the first eight bits of the message. after the eighth bit, the logic stalls because there is no integrated lan controller to send the ack. the logic then aborts the transfer. external logic monitors the toggling and use that to drive an led. b. if an external lan controller is connected send the appropriate message to the external lan controller. if tco reboots are enabled, then the cmi attempts to reboot the system. 1. if the no-reboot bit (nr field in table 17-27, ?offset 3410h: gcs - general control and status register? on page 706 ) is set (no reboots are intended) and second_to_sts bit (tco i/o offset 06h, bit 1) is set and doacpu_sts bit (tco i/o offset 06h, bit 2) is set, then the cmi indicates this in the tco message by setting the cpu missing bit in the message. 2. if the no-reboot bit (nr field in table 17-27, ?offset 3410h: gcs - general control and status register? on page 706 ) is not set (reboots intended) and second_to_sts bit tco i/o offset 06h, bit 1) is set, then the cmi attempts to reboot. after the reboot, the second_to_sts bit is still set. if the cpu fails to fetch the first instruction, the doa_cpu_sts bit is set, and when the tco timer times out (actually for the third time, the first two caused the second_to_sts bit to be set), then the cmi sets the cpu missing event bit for the tco message. 18.4.3 handling an operating system lockup under some conditions, the operating system may lock up. to handle this, the tco timer is used with the following algorithm: 1. bios programs the tco timer, via the tco_tmr register with an initial value. 2. an operating system-based software agent periodically writes to the tco_rld register to reload the timer and keep it from generating the smi#. the software agent can read the tco_rld register to see if it is close to timing out, and possibly determine if the time-out should be increased. the operating system can also modify the values in the tco_tmr register. 3. if the timer reaches 0, an smi# can be generated. this should only occur if the operating system was not able to reload the timer. it is assumed that the operating system is not able to reload the timer if it has locked up. 4. upon generating the smi#, the tco timer automatically reloads with the default value of 04h and start counting down.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 725 intel ? ep80579 integrated processor 5. the smi handler can then: a. read the timeout bit in the tco_sts register to check that the smi# was caused by the tco timer. the smi handler must also clear the timeout bit. b. write to the tco_rld register to reload the timer to make sure the tco timer does not reach 0 again. c. attempt to recover. may need to periodically reload the tco timer. the exact recovery algorithm is system-specific. note: if the smi handler was not able to clear the timeout bit and write to the tco_rld register, the timer reaches zero a second time approximately 2.4 s later. at that point, the hardware is assumed to be locked up, and the timer reads zero a second time, which causes the second_to_sts bit to be set. at that point the logic resets the platform if the reboots are enabled. 18.4.4 handling a cpu or other hardware lockup if after the timeout smi is generated, and the tco timer again reaches 0, and reboots are enabled, the system management logic resets (and reboot) the system. this is in the case where the cpu or other system hardware is locked up. during every boot, bios must read the second_to_sts bit in the tco_sts register to see if this is normal boot or a reboot due to the timeout. the bios may also check the os_policy bits to see if it should try another boot or shutdown. 18.4.5 handling an intruder the cmi has an input signal, intruder#, that can be attached to a switch that is activated by the system?s case being open. this input has a two rtc clock debounce. if intruder# goes active (after the debouncer), this sets the intrd_det bit in the tco_sts register. intruder# can go active in any power state. the intrd_sel bits in the tco_cnt register can enable the cmi to cause an smi# or tco interrupt. the software can also directly read the status of the intruder# signal (high or low) by clearing and then reading the intrd_det bit. this allows the signal to be used as a gpi if the intruder function is not required. note: the intrd_det bit resides in the cmi?s rtc well, and is set and cleared synchronously with the rtc clock. thus, when software attempts to clear intrd_det (by writing a one to the bit location) there may be as much as two rtc clocks (about 65 s) delay before the bit is actually cleared. also, the intruder# signal must be asserted for a minimum of 1 ms to guarantee that the intrd_det bit is set. note: if the intruder# signal is still active when software attempts to clear the intrd_det bit, the bit remains set and the smi is generated again immediately. the smi handler can clear the intrd_sel bits to avoid further smis. however, if the intruder# signal goes inactive and then active again, there is not further smis, since the intrd_sel bits would select that no smi# be generated. 18.4.6 handling a potentially failing power supply it may be possible to detect that a power supply may fail in the near future by monitoring its voltages for fluctuations. to support such an application, external a/ds with programmable thresholds could be included via smbus/i 2 c. upon receiving the smbus/i 2 c message, the cmi can generate an smi or interrupt. the smi handler (or operating system-based extension) could then attempt to send a message before the power completely fails.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 726 order number: 320066-003us another option would be to build an a/d into the power supply itself. another signal, other than pwrok, could report that the power supply might soon fail. 18.4.7 handling an ecc error or other memory error the imch provides a message to indicate that it would like to cause an smi#, sci, serr#, or nmi. the software must check the imch as to the exact cause of the error. 18.4.8 smm to operating system and operating system to smm calls there may be interaction between an smi handler and operating system-related code. two 8-bit data registers are provided. 1. the smi handler generates an interrupt to the operating system by writing to the tco_dat_out register. this sets the tco_int_sts bit in the tco_sts register. the interrupt is cleared by writing a one to the tco_int_sts bit. 2. the operating system (or driver) can generate an smi# by writing to the tco_dat_in register. this sets the os_smi_sts bit in the tco_sts register. the smi# is cleared by writing a one to the os_smi_sts bit. reads to the tco_dat_in and tco_dat_out register do not effect the smi# or interrupt. writing a one to the nmi_now bit allows for an immediate nmi. 18.4.9 detecting an improper fwh programming the cmi can detect the case where the fwh is not programmed. this results in the first instruction fetched to have a value of ffh. if this occurs, the cmi sets the bad_bios bit. 18.4.10 irq1 and irq12 for legacy elimination the new irq1 and irq12 sources are each logically anded with the respective irq1 and irq12 that come from the serirq logic. this is necessary because the serirq logic reports irq1 and irq12 to be high (active), since there is no super i/o to drive them low. note: in a system that does have a super i/o, the new bits must be left at one, since it is anded with the super i/os irq. do not attempt to write these bits to 0 in a system that has a keyboard controller (such as in a super i/o). it is not validated, and is highly likely to cause errors. the following algorithm assumes the byte is being sent from the keyboard. the byte being sent from the mouse is equivalent. the setup to the area of interest is left at a high level in this description. the area of interest is then described in more detail. 1. an smi is received and discovered to be a usb interrupt. 2. the interrupt is discovered to be due to a td associated with a keyboard device. 3. the data is analyzed and it is determined that the interrupt is due to a new key press. 4. the usb key-code is translated into the equivalent scan code set 2 (ss2) ps/2 scan code. 5. the result is queued on a queue of data to be sent from the keyboard to the system. 6. other usb interrupts are handled.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 727 intel ? ep80579 integrated processor 7. the keyboard controller emulation code is executed at exit. it determines if the conditions are correct to return a byte to the system (e.g., emulated obf indicates empty, keyboard interface not disabled, etc.). if not, the emulation exits awaiting the next event. 8. the queue of data to be sent from the keyboard to the system is found to contain a byte to be returned. 9. given the typical keyboard controller configuration, it is translated from ss2 to ss1. end of setup . 10. the byte to be returned is stored in the emulated output buffer. 11. the emulation does the out to the port to enable irq 1. 12. the emulation exits. 13. time passes 14. the system code services the interrupt and reads port 60h. 15. the uhci traps the read and causes an smi trap. 16. the trap is determined to be caused by the read from port 60h (tby60r in legsup). 17. the emulation code clears the interrupt register thus turning off irq 1 and / or irq 12. note: the emulation code can validly do this each ti me there is a read from 60h since that is what the keyboard controller would do as well. (there is no time where both irq 1 and irq 12 must be asserted simultaneously by either the kbc or the emulated kbc. this would be a violation of the kbc/system protocol.) 18.5 event reporting via smlink/smbus the cmi has smlink signals to support tco compatible mode. event reporting is accomplished via the smlink signals. 18.5.1 overview 18.5.1.1 tco compatible mode the cmi can function directly with a lan controller to report message to a network management console without the aid of the system cpu. this is crucial in cases where the cpu is malfunctioning or cannot function due to being in a low-power state. the basic scheme is to send specific messages via the smlink interface to the lan. upon receiving the smlink message, the lan has a prepared ethernet message that it can send to a network management console. the prepared message is stored in a non- volatile memory connected directly to the lan. messages are sent by the cmi to the lan either because a specific event has occurred (see table 18-13 ), or they are sent periodically. the event messages have exactly the same form.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 728 order number: 320066-003us whenever an event occurs that causes the cmi to send a new message, it increments the seq[03:00] field. if a triggering event occurs while a message is already being generated and sent, the new event may not appear in the current message. if not, then a second message is generated, the seq[03:00] field increments to report the new event. the following rules/steps apply if the system is in a g0 state and the policy is to reboot the system after a hardware lockup: 1. upon detecting the lockup the second_to_sts bit is set. the cmi may send up to one event message to the lan. the cmi then attempts to reboot the cpu. 2. if the reboot at step 1 is successful then the bios must clear the second_to_sts bit. this prevents any further messages from being sent. the bios may then perform addition recovery/boot steps. warning: it is important the bios clears the second_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts reset part of the lan and would prevent an operating system?s device driver from sending or receiving some messages. 3. if the reboot attempt in step 1 is not successful, then the timer timeouts a third time. at this point the system has locked up and was unsuccessful in rebooting. the cmi does not attempt to automatically reboot again. the cmi starts sending a message every period (30-32 seconds). this continues until some external intervention occurs (reset, power failure, etc.). 4. after step 3 (unsuccessful reboot after third timeout), if the user presses a power button override, the system goes to an s5 state. the cmi continues sending the messages every period. 5. after step 4 (power button override after unsuccessful reboot) if the user presses the power button again, the system must wake to an s0 state and the cpu must start executing the bios. 6. if step 5 (power button press) is successful in waking the system, the cmi continues sending messages every period until the bios clears the second_to_sts bit. warning: it is important the bios clears the second_to_sts bit, as the messages interfere with the lan device driver from working properly. the alerts reset part of the lan and prevents an operating system?s device driver from sending or receiving some lan packets. table 18-13. event transitions that cause messages event assertion deassertion comments intruder# pin yes no prochot# pin yes yes the prochot# pin is isolated when the core power is off, thus preventing this event in s3,s5. watchdog timer expired yes no (na) send_now bit yes na occurs in g0 gpio[11]/smbalert# pin yes yes batlow# yes yes cpu_pwr_flr yes no note: the gpio[11]/smbalert# pin triggers an event message (when enabled by the gpio11_alert_disable bit) regardless of whether it is configured as a gpi or not.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 729 intel ? ep80579 integrated processor 7. if step 5 (power button press) is unsuccessful in waking the system, the cmi continues sending a message every period. the cmi does not attempt to automatically reboot again. the cmi starts sending a message every period (30-32 seconds). this continues until some external intervention occurs (reset, power failure, etc.). note: a system that has locked up and can not be restarted with the power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond the cmi?s recovery mechanisms. 8. after step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave interface), the cmi attempts to reset the system. 9. after step 8 (reset attempt) if the reset is successful, then the bios is run. the cmi continues sending a message every period until the bios clears the second_to_sts bit. warning: it is important the bios clears the second_to_sts bit, as the messages interfere with the lan device driver from working properly. the alerts reset part of the lan and prevent an operating system?s device driver from sending or receiving some lan packets. 10. after step 8 (reset attempt), if the reset is unsuccessful, then the cmi continues sending a message every period. the cmi does not attempt to reboot the system again without external intervention. note: a system that has locked up and can not be restarted with the power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond the cmi?s recovery mechanisms. the following rules/steps apply if the system is in a g0 state and the policy is for the cmi to not reboot the system after a hardware lockup: 1. upon detecting the lockup the second_to_sts bit is set. the cmi sends a message with the watchdog (wd) event status bit set (and any other bits that must also be set). this message is sent as soon as the lockup is detected, and is sent with the next (increment) sequence number. 2. after step 1, the cmi sends a message every period until some external intervention occurs. 3. rules/steps 4-10 apply if no user intervention (resets, power button presses, smbus reset messages) occur after a third timeout of the watchdog timer. if the intervention occurs before the third timeout, then jump to step11. 4. after step 3 (third timeout), if the user does a power button override, the system goes to an s5 state. the cmi continues sending messages at this point. 5. after step 4 (power button override), if the user presses the power button again, the system must wake to an s0 state and the cpu must start executing the bios. 6. if step 5 (power button press) is successful in waking the system, the cmi continues sending messages until the bios clears the second_to_sts bit. warning: it is important the bios clears the second_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts reset part of the lan and would prevent an operating system?s device driver from sending or receiving some messages. 7. if step 5 (power button press) is unsuccessful in waking the system, the cmi continues sending messages. the cmi does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 730 order number: 320066-003us note: a system that has locked up and can not be restarted with power button press is probably very broken (bad power supply, short circuit on some bus, etc.) and beyond the cmi?s recovery mechanisms. 8. after step 3 (third timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave interface), the cmi attempts to reset the system. 9. if step 8 (reset attempt) is successful, then the bios is run. the cmi continues sending messages until the bios clears the second_to_sts bit. warning: it is important the bios clears the second_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts reset part of the lan and would prevent an operating system?s device driver from sending or receiving some messages. 10. if step 8 (reset attempt), is unsuccessful, then the cmi continues sending messages. the cmi does not attempt to reboot the system again without external intervention. note: a system that has locked up and can not be restarted with the power button press is broken (bad power supply, short circuit on some bus, etc.) 11. this and the following rules/steps apply if the user intervention (power button press, reset, smbus message, etc.) occur prior to the third timeout of the watchdog timer. 12. after step 1 (second timeout), if the user does a power button override, the system goes to an s5 state. the cmi continues sending messages at this point. 13. after step 12 (power button override), if the user presses the power button again, the system must wake to an s0 state and the cpu must start executing the bios. 14. if step 13 (power button press) is successful in waking the system, the cmi continues sending messages until the bios clears the second_to_sts bit. warning: it is important the bios clears the second_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts reset part of the lan and would prevent an operating system?s device driver from sending or receiving some messages. 15. if step 13 (power button press) is unsuccessful in waking the system, the cmi continues sending messages. the cmi does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). note: a system that has locked up and can not be restarted with power button press is broken (bad power supply, short circuit on some bus, etc.) and beyond the cmi?s recovery mechanisms. 16. after step 1 (second timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave interface), the cmi attempts to reset the system. 17. if step 16 (reset attempt) is successful, then the bios is run. the cmi continues sending messages until the bios clears the second_to_sts bit. warning: it is important the bios clears the second_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts reset part of the lan and would prevent an operating system?s device driver from sending or receiving some messages. 18. if step 16 (reset attempt), is unsuccessful, then the cmi continues sending messages. the cmi does not attempt to reboot the system again without external intervention. note: a system that has locked up and can not be restarted with power button press is broken (bad power supply, short circuit on some bus, etc.)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 731 intel ? ep80579 integrated processor the following rules apply if the system is in a g1 (s1 - s4) state: ? the cmi sends a message every period (30-32 seconds). ? if an event occurs prior to the system being shut down, the cmi immediately sends another event message with the next (incremented) sequence number. ? after the event, it resumes sending messages. note: there is a boundary condition when a hardware event happens right as the system transitions into a g0 state. in this condition, the hardware sends messages even though the system is in a g0 state (and the status bits could potentially indicate that). normally the iich does not send messages in the g0 state (except in the case of a lockup). note: a spurious alert could occur in the following sequence: a. the cpu has initiated an alert using the send_now bit b. during the alert, the prochot#, intruder# or gpi[11] changes state c. the system then goes to a non-s0 state once the system transitions to the non-s0 state, it may send a single alert with an incremented sequence number. note: an inaccurate alert message can be generated in the following scenario: a. the system successfully boots after a second watchdog timeout occurs. b. pwrok goes low (typically due to a reset button press) or a power button override occurs (before the second_to_sts bit is cleared). c. an alert message indicating that the cpu is missing or locked up is generated with a new sequence number. 18.5.2 message format the event message is an smbus block write sent to the external lan controller?s smbus address, as shown in ta b l e 1 8 - 1 4 . table 18-14. smbus message format s 1 address byte opcode byte length byte address d aopcode a length a 11001000 11 1001000 100001000 1 data byte 1 data byte 2 data byte 3 (see description) a(see description) a sequence pwrst rsvd a c t b t c s w t s e p e f e g 1 b b b l c f 00000 1 b 3 b 2 b 1 b 0 b 1 b 0 00 1 data byte 4 data byte 5 data byte 6 message 1 register a message 2 register awd status register a b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 732 order number: 320066-003us note: for the system power state field: 00 = g0, 01 = g1, 10 = g2, 11=preboot. the preboot state is entered when the slp_s3#, slp_s4# and slp_s5# signals go from low to high. the indication switches to the g0 state when cpureset done ack completion packet sent to the imch. this corresponds to the time when the cpu has been reset. if the cpu is locked up, then the cpu event bit is set. 18.5.3 connecting an external lan controller the cmi?s tco logic sends the message on the smlink signals in tco compatible mode. an external lan controller claims these cycles. when sending the messages to the external lan controller, the cmi?s iich abides by the standard smbus rules associated with collision detection. it delays starting a message until the link is idle, and detects collisions. if a collision is detected, the cmi drops that message. data byte 7 data byte 8 reserved a reserved ap 00000000 100000000 11 table 18-15. message address byte field bit length comment start 1 ?1? to indicate the start of a packet address 7 lan smbus address. is always 1100100. dir 1 ?0? to indicate write cycle ack 1 returned by external lan controller table 18-14. smbus message format
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 733 intel ? ep80579 integrated processor 19.0 lpc interface: bus 0, device 31, function 0 19.1 overview the lpc bridge function iich resides in pci device 31, function 0. this contains many other functional units, such as dma and interrupt controllers, timers, power management, system management, gpio, rtc, and lpc configuration registers. 19.2 lpc interface configuration register details note: address locations that are not listed are considered reserved register locations. reserved registers are read only and return all zeros. for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? . table 19-1. bus 0, device 31, function 0: summary of lpc interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: id: vendor identification register? on page 734 50318086h 04h 05h ?offset 04h: cmd: device command register? on page 735 0007h 06h 07h ?offset 06h: sts: status register? on page 736 0200h 08h 08h ?offset 08h: rid: revision id register? on page 737 variable 09h 0bh ?offset 09h: cc: class code register? on page 737 060100h 0dh 0dh ?offset 0dh: mlt: master latency timer register? on page 737 00h 0eh 0eh ?offset 0eh: htype: header type register? on page 738 80h 2ch 2fh ?offset 2ch: sid: subsystem identifiers register? on page 738 00000000h 40h 43h ?offset 40h: abase: acpi base address register? on page 739 00000001h 44h 47h ?offset 44h: actl: acpi control register? on page 739 00h 48h 48h ?offset 48h: gba: gpio base address register? on page 740 00000001h 4ch 4ch ?offset 4ch: gc: gpio control register? on page 741 00h 60h 60h ?offset 60h: parc: pirqa routing control register? on page 741 80h 61h 61h ?offset 61h: pbrc: pirqb routing control register? on page 742 80h 62h 62h ?offset 62h: pcrc: pirqc routing control register? on page 742 80h 63h 63h ?offset 63h: pdrc: pirqdq routing control register? on page 743 80h 64h 64h ?offset 64h: scnt: serial irq control register? on page 744 10h 68h 68h ?offset 68h: perc: pirqeq routing control register? on page 745 80h 69h 69h ?offset 69h: pfrc: pirqf routing control register? on page 745 80h 6ah 6ah ?offset 6ah: pgrc: pirqg routing control register? on page 746 80h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 734 order number: 320066-003us 19.2.1 pci configuration registers 19.2.1.1 offset 00h: id: vendor identification register 6bh 6bh ?offset 6bh: phrc: pirqh routing control register? on page 747 80h 80h 81h ?offset 80h: iod: i/o decode ranges register? on page 747 0000h 82h 83h ?offset 82h: ioe: i/o enables register? on page 749 0000h 84h 85h ?offset 84h: lg1: lpc generic decode range 1 register? on page 750 0000h 88h 88h ?offset 88h: lg2: lpc generic decode range 2 register? on page 751 0000h d0h d3h ?offset d0h: fs1: fwh id select 1 register? on page 752 00112233h d4h d5h ?offset d4h: fs2: fwh id select 2 register? on page 753 4567h d8h dbh ?offset d8h: fde: fwh decode enable register? on page 754 ffcfh dch dch ?offset dch: bc: bios control register? on page 756 00h f0h f3h ?offset f0h: rcba: root complex base address register? on page 757 00000000h f8h fbh ?offset f8h: manid: manufacturer id register? on page 757 00010f90h table 19-1. bus 0, device 31, function 0: summary of lpc interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 19-2. offset 00h: id: vendor identification register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 00h 03h size: 32 bit default: 50318086h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 did device identification: these 16 bits of this register are hardwired to5031h. 5031h ro 15 :00 vid vendor identification: this 16-bit value is assigned to intel. intel vid = 8086h 8086h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 735 intel ? ep80579 integrated processor 19.2.1.2 offset 04h: cmd: device command register table 19-3. offset 04h: cmd: device command register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 04h 05h size: 16 bit default: 0007h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :10 reserved reserved 00h 09 fbe fast back to back enable: hardwired to ?0? as per pci express specification . 0h ro 08 see serr# enable: 0 = lpc bridge does not generates serr# 1 = lpc bridge generates serr# 0h rw 07 wcc wait cycle control: hardwired to ?0? as per pci express specification . 0h ro 06 pere parity error response enable: 0 = no action is taken when detecting a parity error. 1 = enables the lpc bridge to respond to parity errors detected on iich interface. 0h rw 05 vga_pse vga palette snoop: hardwired to ?0? as per pci express specification . 0h ro 04 mwie memory write and invalidate enable: hardwired to ?0?as per pci express specification . 0h ro 03 sce special cycle enable: hardwired to ?0? as per pci express specification . 0h ro 02 bme bus master enable: bus masters cannot be disabled. 1 ro 01 mse memory space enable: memory space cannot be disabled on lpc. 1ro 00 iose i/o space enable: i/o space cannot be disabled on lpc. 1 ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 736 order number: 320066-003us 19.2.1.3 offset 06h: sts: status register 19.2.1.4 offset 08h: rid - revision id register writing to this register controls what is reported in all of the rid registers in the component. the value written does not get directly loaded in this register. however, the value is checked to determine which value to report. once written, additional writes to this register must not have any affect until a core- well reset occurs. bios must always write to this register in order to guarantee that the functionality is locked. table 19-4. offset 06h: sts: status register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 06h 07h size: 16 bit default: 0200h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: set when the lpc bridge detects an internal parity error. this bit gets set even if cmd.pere is not set. 0 = parity error not detected 1 = parity error detected 0h rwc 14 sse signaled system error: set when the lpc bridge signals a system error to the internal serr# logic. 0h rwc 13 rma received master abort: 0 = unsupported request status not received 1 = the bridge received a completion with unsupported request status from the iich 0h rwc 12 rta received target abort: 0 = completion abort not received 1 = completion with completion abort received from the iich 0h rwc 11 sta signaled target abort: 0 = target abort not generated on the iich 1 = lpc bridge generated a completion packet with target abort status on the iich 0h rwc 10 :09 dts devsel# timing status: 01 = medium timing 01h ro 08 dpd data parity error detected: 1 = 0 = all conditions listed below not met set when all three of the following conditions are met: ? lpc bridge receives a completion packet from the iich from a previous request ? parity error has been detected (d31, f0, 06, bit 15) ? pcicmd.pere bit (d31, f0, 04, bit 6) is set 0h rwc 07:00 reserved reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 737 intel ? ep80579 integrated processor 19.2.1.5 offset 09h: cc: class code register 19.2.1.6 offset 0dh: mlt: master latency timer register table 19-5. offset 08h: rid: revision id register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 rid revision id: indicates the part revision variable rwo table 19-6. offset 09h: cc: class code register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 09h 0bh size: 24 bit default: 060100h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 :16 bcc base class code: indicates the type of device for the lpc bridge. 06h = bridge device. 06h ro 15 :08 scc sub-class code: indicates the category of bridge for the lpc bridge. 01h = pci-to-isa bridge. 01h ro 07 :00 pi programming interface: the lpc bridge has no programming interface. 00h ro table 19-7. offset 0dh: mlt: master latency timer register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :03 mlc master latency count: reserved per pci express specification . 0h ro 02 :00 reserved reserved 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 738 order number: 320066-003us 19.2.1.7 offset 0eh: htype: header type register 19.2.1.8 offset 2ch: sid: subsystem identifiers register this register is initialized to logic 0 by the assertion of pltrst#. this register can be written only once after pltrst# deassertion. 19.2.2 acpi/gpio configuration registers 19.2.2.1 offset 40h: abase: acpi base address register abase sets the base address in i/o space for the acpi and tco i/o registers (see section 27.3.3, ?general power management i/o-mapped registers? on page 1055 ). these registers can be mapped anywhere in the 64 k i/o space on 128-byte boundaries. table 19-8. offset 0eh: htype: header type register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 0eh 0eh size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mfd multi-function device: this bit is hardwired to ?1? to indicate a multi-function device. 1ro 06 :00 htype header type: identifies the header layout of the configuration space, which is a generic device. 00h ro table 19-9. offset 2ch: sid: subsystem identifiers register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 2ch 2fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 ssid subsystem id: this is written by bios. no hardware action taken on this value. 0000h rwo 15 :00 ssvid subsystem vendor id: this is written by bios. no hardware action taken on this value. 0000h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 739 intel ? ep80579 integrated processor 19.2.2.2 offset 44h: act: acpi control register table 19-10. offset 40h: abase: acpi base address register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 40h 43h size: 32bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved. 0000h 15 :07 bsa base address : this field provides the 128 bytes of i/o space for acpi and tco logic. this is placed on a 128 byte boundary. 00h rw 06 :01 reserved reserved. 00h 00 rte resource type indicator : hardwired 1 to indicate i/o space. 1ro table 19-11. offset 44h: actl: acpi control register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 44h 47h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 en acpi enable: 0 = disable. decoding of the i/o range pointed to by the acpi base register is disabled, and the acpi power management function is enabled. 1 = decoding of the i/o range pointed to by the acpi base register is enabled, and the acpi power management function is enabled. note: the apm power management ranges (b2/b3h) are always enabled and are not affected by this bit. 0h rw 06 :03 reserved reserved 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 740 order number: 320066-003us 19.2.2.3 offset 48h: gba: gpio base address register gba sets the base address in i/o space for the gpio i/o registers (see section 22.2, ?general purpose i/o-mapped configur ation register details? on page 806 ). these registers can be mapped anywhere in the 64 k i/o space on 64-byte boundaries. 02 :00 scis sci irq select: specifies on which irq the sci will internally appear. if not using the apic, the sci must be routed to irq9-11, and that interrupt is not sharable with the serirq stream, but is shareable with other pci interrupts. if using the apic, the sci can also be mapped to irq20-23, and can be shared with other interrupts. bits sci map 000 irq9 001 irq10 010 irq11 011 reserved 100 rq20 (only if apic enabled) 101 irq21 (only if apic enabled) 110 irq22 (only if apic enabled) 111 irq23 (only if apic enabled) note: when the interrupt is mapped to apic interrupts 9, 10 or 11, the apic must be programmed for active-high reception. when the interrupt is mapped to apic interrupts 20 through 23, the apic must be programmed for active-low reception. 000h rw table 19-11. offset 44h: actl: acpi control register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 44h 47h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access table 19-12. offset 48h: gba: gpio base address register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 48h 48h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved. 0000h 15 :06 ba base address: provides the 64 bytes of i/o space for gpio. 00h rw 05 :01 reserved reserved. 00h 00 hd hardwired to 1 to indicate i/o space. 1 ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 741 intel ? ep80579 integrated processor 19.2.2.4 offset 4ch: gc: gpio control register 19.2.3 interrupt conf iguration registers 19.2.3.1 offset 60h: parc: pirqa routing control register table 19-13. offset 4ch: gc: gpio control register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 4ch 4ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :05 reserved reserved. 000h 04 en gpio enable: this bit enables/disables decode of the i/o range pointed to by the gpio base address register (d31, f0, 48h) and enables the gpio function. 0 = disable 1 = enable 0h rw 03 :00 reserved reserved. 0000h table 19-14. offset 60h: parc: pirqa routing control register description: parc - routing control register. view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 60h 60h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 1rw 06 :04 reserved reserved 000h 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001 reserved 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 742 order number: 320066-003us 19.2.3.2 offset 61h: pbrc: pirqb routing control register 19.2.3.3 offset 62h: pcrc: pirqc routing control register table 19-15. offset 61h: pbrc: pirqb routing control register description: pbrc - routing control register. view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 61h 61h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 1rw 06 :04 reserved reserved 000h 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001reserved 1001irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101irq5 1101reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw table 19-16. offset 62h: pcrc: pirqc routing control register (sheet 1 of 2) description: pcrc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 62h 62h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 1rw 06 :04 reserved reserved 000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 743 intel ? ep80579 integrated processor 19.2.3.4 offset 63h: pdrc: pirqd routing control register 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001 reserved 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw table 19-17. offset 63h: pdrc: pirqdq routing control register description: pdrc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 63h 63h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 1rw 06 :04 reserved reserved 000h 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001 reserved 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw table 19-16. offset 62h: pcrc: pirqc routing control register (sheet 2 of 2) description: pcrc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 62h 62h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 744 order number: 320066-003us 19.2.3.5 offset 64h: scnt: serial irq control register when exiting s3/s4/s5, the following procedure must be used if the system needs quiet mode. set the serirq logic to continuous mode for at least one frame before switching it back to quiet mode. table 19-18. offset 64h: scnt: serial irq control register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 64h 64h size: 8 bit default: 10h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 en enable: 0 = serial irqs will not be recognized 1 = serial irqs are recognized 0h rw 06 md mode: 0 = the serial irq machine is in quiet mode 1= the serial irq machine is in continuous mode note: for systems using quiet mode, this bit must be set to 1 (continuous mode) for at least one frame after coming out of reset before switching back to quiet mode. failure to do so will result in the iich not recognizing serirq interrupts. 0h rw 05 :02 fs frame size: 100 = hardwired to indicate the size of the serirq frame is 21 frames. 0100b ro 01 :00 sfpw start frame pulse width: this is the number of 33 mhz clocks that the serirq pin is driven low by the serial irq controller to signal a start frame. in continuous mode, the controller will drive the start frame for the number of clocks specified. in quiet mode, the controller will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. bits clocks 00 4 01 6 10 8 11 reserved 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 745 intel ? ep80579 integrated processor 19.2.3.6 offset 68h: perc: pirqe routing control register 19.2.3.7 offset 69h: pfrc: pirqf routing control register table 19-19. offset 68h: perc: pirqeq routing control register description: perc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 68h 68h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: 1rw 06 :04 reserved reserved 000h 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001 reserved 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw table 19-20. offset 69h: pfrc: pirqf routing control register (sheet 1 of 2) description: farc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 69h 69h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: 1rw 06 :04 reserved reserved 000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 746 order number: 320066-003us 19.2.3.8 offset 6ah: pgrc: pirqg routing control register 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001reserved 1001irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101irq5 1101reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw table 19-20. offset 69h: pfrc: pirqf routing control register (sheet 2 of 2) description: farc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 69h 69h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access table 19-21. offset 6ah: pgrc: pirqg routing control register description: pgrc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 6ah 6ah size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: 1rw 06 :04 reserved reserved 000h 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001reserved 1001irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101irq5 1101reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 747 intel ? ep80579 integrated processor 19.2.3.9 offset 6bh: phrc: pirqh routing control register 19.2.4 lpc i/o configuration registers 19.2.4.1 offset 80h: iod: i/o decode ranges register table 19-22. offset 6bh: phrc: pirqh routing control register description: phrc - routing control register view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 6bh 6bh size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ren interrupt routing enable: 0 = the corresponding pirq is routed to one of the legacy interrupts specified in bits[03:00]. 1 = the pirq is not routed to the 8259. note: 1rw 06 :04 reserved reserved 000h 03 :00 ir irq routing: bits mapping bits mapping 0000 reserved 1000 reserved 0001 reserved 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 0h rw table 19-23. offset 80h: iod: i/o decode ranges register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 80h 81h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :13 reserved reserved. 0h ro 12 fdd fdd range: this field determines which range to decode for the fdd port 0 = 3f0 ? 3f5h, 3f7h (primary) 1 = 370 ? 375h, 377h (secondary) 0h 11 :10 reserved reserved 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 748 order number: 320066-003us 9:8 lpt lpt range: this field determines which range to decode for the lpt port: 00 378 ? 37fh and 778 ? 77fh 01 278 ? 27fh (port 279h is read only) and 678 ? 67fh 10 3bc ?3beh and 7bc ? 7beh 11 reserved 0h 07 reserved reserved 0h ro 06 :04 cb comb range: this field determines which range to decode for the comb port. 000 3f8 ? 3ffh (com1) 001 2f8 ? 2ffh (com2) 010 220 ? 227h 011 228 ? 22fh 100 238 ? 23fh 101 2e8 ? 2efh (com4) 110 338 ? 33fh 111 3e8 ? 3efh (com3) 0h 03 reserved reserved 0h ro 02 :00 ca coma range: this field determines which range to decode for the coma port. 000 3f8 ? 3ffh (com1) 001 2f8 ? 2ffh (com2) 010 220 ? 227h 011 228 ? 22fh 100 238 ? 23fh 101 2e8 ? 2efh (com4) 110 338 ? 33fh 111 3e8 ? 3efh (com3) 0h table 19-23. offset 80h: iod: i/o decode ranges register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 80h 81h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 749 intel ? ep80579 integrated processor 19.2.4.2 offset 82h: ioe: i/o enables register table 19-24. offset 82h: ioe: i/o enables register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 82h 83h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :14 reserved reserved 00h 13 me2 micro controller enable 2: 0 = disable 1 = enables the decoding of the i/o locations 4eh and 4fh to the lpc interface. this range is used for a microcontroller. 0h rw 12 se super i/o enable: 0 = disable 1 = enables the decoding of the i/o locations 2eh and 2fh to the lpc interface. this range is used for super i/o devices. 0h rw 11 me1 micro controller enable 1: 0 = disable 1 = enables the decoding of the i/o locations 62h and 66h to the lpc interface. this range is used for a microcontroller. 0h rw 10 ke keyboard enable: 0 = disable 1 = enables the decoding of the i/o locations 60h and 64h to the lpc interface. this range is used for a microcontroller. 0h rw 09 hge high gameport enable: 0 = disable 1 = enables decoding of the i/o locations 208h to 20fh to lpc 0h rw 08 lge low gameport enable: 0 = disable 1 = enables decoding of the i/o locations 200h to 207h to lpc 0h rw 07 :04 reserved reserved 0h 03 fde floppy drive enable: 0 = disable 1 = enables decoding of the fdd range to lpc. range is selected by liod.fde decode range register (d31, f0, 80h, bit 12) 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 750 order number: 320066-003us 19.2.4.3 offset 84h: lg1: lpc generic decode range 1 register lg1 sets the base address in i/o space for the i/o registers. these registers can be mapped anywhere in the 64 k i/o space on 128-byte boundaries. 02 ppe parallel port enable: 0 = disable 1 = enables decoding of the lpt range to lpc. range is selected by liod.lpt decode range register (d31, f0, 80h, bit 09:08) 0h rw 01 cbe com port b enable: 0 = disable 1 = enables decoding of the comb range to lpc. range is selected liod.cb decode range register (d31, f0, 80h, bits 06:04) 0h rw 00 cae com port a enable: 0 = disable 1 = enables decoding of the coma range to lpc. range is selected liod.ca decode range register (d31, f0, 80h, bits 03:20) 0h rw table 19-24. offset 82h: ioe: i/o enables register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 82h 83h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 19-25. offset 84h: lg1: lpc generic decode range 1 register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 84h 85h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :07 ba base address: base address for this generic decode range. this address is aligned on a 128-byte boundary, and being i/o, must have address lines 31:16 as 0. this generic decode is for i/o addresses only, not memory addresses. the size of this range is 128 bytes. 0h rw 06 :01 reserved reserved. 0h 00 en enable: 0 = disable 1 = enables the range specified in ba to be forwarded to lpc interface 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 751 intel ? ep80579 integrated processor 19.2.4.4 offset 88h: lg2: lpc generic decode range 2 register lg2 sets the base address in i/o space for the i/o registers. these registers can be mapped anywhere in the 64 k i/o space on 16-byte boundaries. the size of this region can be either 16b, 32b, or 64b based on the setting of etr3. 19.2.5 power management configuration registers offsets a0h ? cfh are described in the power management section. refer to chapter 27.0, ?power management? . 19.2.6 fwh configuration registers 19.2.6.1 offset d0h: fs1: fwh id select 1 register this register contains the idsel fields the lpc bridge uses for memory cycles going to the fwh. table 19-26. offset 88h: lg2: lpc generic decode range 2 register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: 88h 88h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :04 ba base address: this address is aligned on a 16-byte boundary, and must have address lines 31:16 as 0. note that configuration bits at d31:f0:ach (bits 13 and 12) allow this range to be increased to 32 or 64 bytes by forcing matches on address bits 4 and/or 5. 0h rw 03 :01 reserved reserved. 0h 00 en enable: 0 = disable 1 = enables the range specified in ba to be forwarded to lpc interface 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 752 order number: 320066-003us table 19-27. offset d0h: fs1: fwh id select 1 register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: d0h d3h size: 32 bit default: 00112233h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 if8 f8-ff idsel: is used in fwh cycle for ranges enabled by fde.ef8. used for two 512-kb firmware hub memory ranges and one 128-kb memory range. this field is fixed at 0000. the idsel programmed in this field addresses the following memory ranges: fff8 0000h ? ffff ffffh ffb8 0000h ? ffbf ffffh 000e 0000h ? 000f ffffh 0h ro 27 :24 if0 f0-f7 idsel: is used in fwh cycle for range enabled by fde.ef0. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: fff0 0000h ? fff7 ffffh ffb0 0000h ? ffb7 ffffh 0h rw 23 :20 ie8 e8-ef idsel: is used in fwh cycle for range enabled by fde.ee8. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ffe8 0000h ? ffef ffffh ffa8 0000h ? ffaf ffffh 1h rw 19 :16 ie0 e0-e7 idsel: is used in fwh cycle for range enabled by fde.ee0. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ffe0 0000h ? ffe7 ffffh ffa0 0000h ? ffa7 ffffh 1h rw 15 :12 id8 d8-df idsel: is used in fwh cycle for range enabled by fde.ed8. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ffd8 0000h ? ffdf ffffh ff98 0000h ? ff9f ffffh 2h rw 11 :08 id0 d0-d7 idsel: is used in fwh cycle for range enabled by fde.ed0. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ffd0 0000h ? ffd7 ffffh ff90 0000h ? ff97 ffffh 2h rw 07 :04 ic8 c8-cf idsel: is used in fwh cycle for range enabled by fde.ec8. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ffc8 0000h ? ffcf ffffh ff88 0000h ? ff8f ffffh 3h rw 03 :00 ic0 c0-c7 idsel: is used in fwh cycle for range enabled by fde.ec0. used for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ffc0 0000h ? ffc7 ffffh ff80 0000h ? ff87 ffffh 3h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 753 intel ? ep80579 integrated processor 19.2.6.2 offset d4h: fs2: fwh id select 2 register this register contains the additional idsel fields the lpc bridge uses for memory cycles going to the fwh. table 19-28. offset d4h: fs2: fwh id select 2 register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: d4h d5h size: 16 bit default: 4567h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :12 i70 70-7f idsel: is used in fwh cycle for range enabled by fde.e70. used for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh 4h rw 11 :08 i60 60-6f idsel: is used in fwh cycle for range enabled by fde.e60. used for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 5h rw 07 :04 i50 50-5f idsel: is used in fwh cycle for range enabled by fde.e50. used for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 6h rw 03 :00 i40 40-4f idsel: is used in fwh cycle for range enabled by fde.e40. used for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh 7h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 754 order number: 320066-003us 19.2.6.3 offset d8h: fde: fwh decode enable register table 19-29. offset d8h: fde: fwh decode enable register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: d8h dbh size: 16 bit default: ffcfh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 ef8 f8-ff enable: enables decoding of 512 kbyte firmware hub memory ranges: 0 = 0 = disable 1 = 1 = enable the following ranges for the firmware hub data space:fff80000h ? ffffffffh feature space:ffb80000h ? ffbfffffh 1ro 14 ef0 f0-f8 enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:fff00000h ? fff7ffffh feature space:ffb00000h ? ffb7ffffh 1rw 13 ee8 e8-ef enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:ffe80000h ? ffefffffh feature space:ffa80000h ? ffafffffh 1rw 12 ee0 e0-e8 enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:ffe00000h ? ffe7ffffh feature space:ffa00000h ? ffa7ffffh 1rw 11 ed8 d8-df enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:ffd80000h ? ffdfffffh feature space:ff980000h ? ff9fffffh 1rw 10 ed0 d0-d7 enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:ffd00000h ? ffd7ffffh feature space:ff900000h ? ff97ffffh 1rw 09 ec8 c8-cf enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:ffc80000h ? ffcfffffh feature space:ff880000h ? ff8fffffh 1rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 755 intel ? ep80579 integrated processor 08 ec0 c0-c7 enable: enables decoding of 512k-kbyte firmware hub memory ranges: 0 = disable. 1 = enable the following ranges for the firmware hub: data space:ffc00000h ? ffc7ffffh feature space:ff800000h ? ff87ffffh 1rw 07 lfe legacy f segment enable: this enables the decoding of the legacy 128k range at f0000h ? fffffh 0 = disable. 1 = enable the following legacy ranges for the firmware hub f0000h ? effffh 1rw 06 lee legacy e segment enable: this enables the decoding of the legacy 128k range at e0000h ? effffh 0 = disable. 1 = enable the following legacy ranges for the firmware hub e0000h ? effffh 1rw 05 :04 reserved reserved 00h 03 e70 70-7f enable: enables decoding of 1 mbyte firmware hub memory range: data space:ff700000h ? ff7fffffh feature space:ff300000h ? ff3fffffh 1rw 02 e60 60-6f enable: enables decoding of 1 mbyte firmware hub memory range: data space:ff600000h ? ff6fffffh feature space:ff200000h ? ff2fffffh 1rw 01 e50 50-5f enable: enables decoding of 1 mbyte firmware hub memory range: data space:ff500000h ? ff5fffffh feature space:ff100000h ? ff1fffffh 1rw 00 e40 40-4f enable: enables decoding of 1 mbyte firmware hub memory range: data space:ff400000h ? ff4fffffh feature space:ff000000h ? ff0fffffh 1rw table 19-29. offset d8h: fde: fwh decode enable register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: d8h dbh size: 16 bit default: ffcfh power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 756 order number: 320066-003us 19.2.6.4 offset dch: bc: bios control register 19.2.7 root complex register block configuration register 19.2.7.1 offset f0h: rcba: root complex base address register rcba sets the base address in memory space for the root complex configuration registers (see section 17.1, ?root complex memory-mapped configuration register details? on page 689 ). these registers can be mapped anywhere in the 32-bit memory space on 16kb boundaries. the spi register space resides in this bar. the base address offset is 3020h. refer to chapter 21.0, ?serial peripheral interface? . table 19-30. offset dch: bc: bios control register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: dch dch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :04 reserved reserved 0h 03 02 src spi read configuration: this 2-bit field controls two policies related to bios reads on the spi interface bit 3 - prefetch enable bit 2 - cache disable 00b -> no prefetching, but caching enabled . 64b demand reads load the read buffer cache with ?valid? data, allowing repeated code fetches to the same line to complete quickly 01b -> no prefetching and no caching. one-to-one correspondence of the host bios reads to spi cycles. this value can be used to invalidate the cache. 10b -> prefetching and caching enabled. this mode is used for long sequences of short reads to consecutive addresses (i.e. shadowing) 11b -> reserved . this is an invalid configuration. 00h rw 01 le lock enable: 0 = setting the wp will not cause smis 1 = enables setting the wp bit to cause smis. once set, this bit can only be cleared by a pltrst# 0h rwo 00 wp write protect: 0 = only read cycles result in firmware hub interface cycles 1 = access to the bios space is enabled for both read and write cycles. when this bit is written from a 0 to a 1 and lock enable (le) is also set, an smi# is generated. this ensures that only smi code can update bios. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 757 intel ? ep80579 integrated processor 19.2.8 manufacturing information register 19.2.8.1 offset f8h: manid: manufacturer id register 19.3 interface the lpc bridge function resides in device 31, function 0. in addition to the lpc bridge function, d31, f0 contains other functional units including dma, interrupt controllers, timers, power management, system management, gpio, and rtc. table 19-31. offset f0h: rcba: root complex base address register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: f0h f3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :14 ba base address: base address for the root complex register block decode range. this address is aligned on a 16 kbyte boundary. 0h rw 13 :01 reserved reserved 0h 00 en enable: 0 = disables the range specified in ba to be claimed as the rcrb (root complex register block) 1 = enables the range specified in ba to be claimed as the rcrb 0h rw table 19-32. offset f8h: manid: manufacturer id register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: f8h fbh size: 32 bit default: 00010f90h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 reserved reserved 00h 23 :16 sid stepping identifier: this field increments for each stepping of the part. note: this field can be used by software to differentiate steppings when the revision id may not change. note: 00h for a0 stepping note: 01h for b0 stepping a single stepping id can be implemented that is readable from all functions in the chip because all of them increment in lock-step. 01h ro 15 :08 mid manufacturing identifier: 0fh = intel 0fh ro 07 :00 reserved reserved. 90h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 758 order number: 320066-003us 19.3.1 overview the lpc interface is described in the low pin count (lpc) interface specification, revision 1.1 . the lpc interface to the iich is shown in figure 19-1 . the lpc controller implements all of the signals that are shown as optional, but peripherals are not required to do so. for the lpc controller: ? lsmi# can be connected to any of the smi capable gpio signals. ? the super i/o?s pme# can be connected to the pci pme# signal, however this may cause software problems. a better choice is to connect it to one of the lpc controller?s sci capable gpio signals. ? the lpc controller?s sus_stat# signal is connected directly to the lpcpd# signal. all the other signals have the same name on the lpc controller and on the lpc interface. 19.3.2 cycle types all of the cycle types implemented are described in the lpc interface specification, revision 1.1 . ta b l e 1 9 - 3 3 shows the supported cycle types. figure 19-1. lpc interface diagram b6464-01 cmi super i/o sus_stat# gpi lad[3:0] lframe# ldrq# (optional ) lpcpd# (optional ) lslmi# (optional ) pciclk pcirst# serirq pme# pci bus signal name during reset after reset s3 s5 lad[3:0] see off off lframe# off off ldreq[1:0]# off off
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 759 intel ? ep80579 integrated processor the low pin count (lpc) interface specification, revision 1.1 allows dma cycles to be 4-bytes in length, but the lpc controller will only allow a maximum of 16-bit transfers. additionally, the lpc specification allows for firmware memory cycles to be 1, 2, or 4 bytes, and in the case of firmware reads, 128 bytes. however, the lpc controller will only perform 8-bit transfers. bus master read or write cycles must be naturally aligned. a 1 byte transfer can be to any address. a 2-byte transfer must be word aligned (address bit a0 = 0). a 4-byte transfer must be dword aligned (address bits a[1:0] = 00). 19.3.3 aborting a cycle the usage of lframe# is followed as it is defined in the lpc specification . the lpc controller performs an abort for the following cases (possible failure cases): ? lpc controller starts a memory, i/o, or dma cycle, but no device drives a valid sync after four consecutive clocks. ? lpc controller starts a memory, i/o, or dma cycle, and the peripheral drives an invalid sync pattern. ? a peripheral drives an illegal address when performing bus master cycles. ? a peripheral drives an invalid value. 19.3.4 memory cycle notes for cycles below 16m and not targeting firmware, the lpc controller will perform standard lpc memory cycles. for cycles ta rgeting firmware, firmware memory cycles are used. for cycles targeting the fixed token, the fixed token format is used. only 8-bit transfers are performed. if a larger transfer occurs, the lpc controller will break it into multiple 8-bit transfers until the request is satisfied. table 19-33. lpc cycle types supported cycle type comment memory read single: 1 byte only memory write single: 1 byte only i/o read 1 byte only. breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. see note 1 below. i/o write 1 byte only. breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. see note 1 below. dma read can be 1, or 2 bytes dma write can be 1, or 2 bytes bus master read can be 1, 2, or 4 bytes. (see note 2 below) bus master write can be 1, 2, or 4 bytes. (see note 2 below) notes: 1. for memory cycles below 16 mb that do not target enabled firmware hub ranges, performs standard lpc memory cycles. it only attempts 8-bit transfers. if the cycle appears on pci as a 16-bit transfer, it appears as two consecutive 8-bit transfers on lpc. likewise, if the cycle appears as a 32-bit transfer on pci, it appears as four consecutive 8-bit transfers on lpc. if the cycle is not claimed by any peripheral, it is subsequently aborted, and returns a value of all ones to the processor. this is done to maintain compatibility with legacy memory cycles where pull-up resistors would keep the bus high if no device responds. 2. bus master read or write cycles must be naturally aligned. for example, a 1-byte transfer can be to any address. however, the 2-byte transfer must be word aligned (i.e., with an address where a0=0). a dword transfer must be dword aligned (i.e., with an address where a1 and a0 are both 0).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 760 order number: 320066-003us note: if the cycle is not claimed by any peripheral (and subsequently aborted), a value of all 1s (ffh) is returned to the processor. this is to maintain compatibility with legacy memory cycles where pull-up resistors would keep the bus high if no device responds. 19.3.5 i/o cycle notes for i/o cycles targeting registers specified in the decode ranges, cmi performs i/o cycles as defined in the lpc specification . these are 8-bit transfers. if the processor attempts a 16-bit or 32-bit transfer, cmi breaks the cycle up into multiple 8-bit transfers to consecutive i/o addresses until the request is satisfied. note: if the cycle is not claimed by any peripheral (and subsequently aborted), cmi returns a value of all 1s (ffh) to the processor. this is to maintain compatibility with legacy i/o cycles where pull-up resistors would keep the bus high if no device responds. 19.3.6 dma cycle notes only 8-bit and 16-bit dma transfers are supported. peripherals must not attempt 32-bit transfers. 19.3.7 bus master cycle notes cmi supports bus master cycles and requests (using ldrq#) as defined in the lpc specification . cmi has two ldrq# inputs, and thus supports two separate bus master devices. it uses the associated start fields for bus master 0 (0010b) or bus master 1 (0011b). note: cmi does not support lpc bus masters performing i/o cycles. lpc bus masters must only perform memory read or memory write cycles and must only target main memory. 19.3.8 fwh cycle notes a fwh device is not allowed to assert an e rror sync. if the lpc controller receives any sync returned from the device other than short wait (0101), long wait (0110), or ready more (0000) when running a fwh cycle, indeterminate results will occur. 19.3.9 lpc pd# protocol the lpcpd# pin must follow the same timings as for sus_stat#.upon driving sus_stat# low, lpc peripherals will drive ldrq# low or tri-state it. the lpc controller must shut the ldrq# input buffers. after driving sus_stat# active, the lpc controller drives lframe# low, and tri-states (or drive low) lad[3:0]. note: the lpc controller does not follow one part of the lpc specification that says ?lreset# is always asserted after lpcpd# ?. lreset# is not always asserted after lpcpd#. the low pin count interface specification, revision 1.1 defines the lpcpd# protocol where there is at least 30 s from lpcpd# assertion to lrst# assertion. this specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. cmi asserts both sus_stat# (connects to lpcpd#) and pltrst# (connects to lrst#) at the same time when the core logic is reset (via cf9h, pwrok, or sys_reset#, etc.). this is not inconsistent with the lpc lpcpd# protocol. 19.3.10 cycle posting policies three main policies are assumed.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 761 intel ? ep80579 integrated processor 1. i/o cycles and memory read cycles from the processor are not posted. memory write cycles from the processor are posted. 2. dma cycles can be pipelined. for example, after reading data from memory, the lpc controller can then release phold# while it writes the data to the peripheral on the lpc interface. this is because there are no processor/smi#-based retry capabilities for dma cycles. in the other direction, after reading data from a peripheral, phold# can be released while the dma controller writes data to main memory. 3. when bus masters read from main memory, the lpc controller can treat this much like dma, and release the memory and pci buses while the data is being transferred to the bus master on the lpc interface. when a bus master writes to main memory, the lpc controller can use the lpc interface while the data is being written to main memory. 19.3.11 configuration 19.3.11.1 lpc interface decoders to allow the i/o cycles and memory mapped cycles to go to the lpc interface, cmi includes several decoders. during configuration, cmi must be programmed with the same decode ranges as the peripheral. the decoders are programmed via the device 31, function 0 configuration space at offset 80h?87h. note: cmi cannot accept pci write cycles from pci-to-pci bridges or devices with similar characteristics (specifically those with a ?retry read? feature which is enabled) to an lpc device if there is an outstanding lpc read cycle towards the same pci device or bridge. these cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. 19.3.11.2 bus master device mapping and start fields bus masters must have a unique start field. in the case of the lpc controller, which supports two bus masters, it will drive 0010 for the start field for grants to bus master 0 (requested via ldrq[0]#) and 0011 for grants to bus master 1 (requested via ldrq[1]#.). 19.3.11.3 firmware memory idsel fields the lpc controller uses a unique idsel field for each eprom. the idsel used is determined through the programming of the fs1 and fs2 configuration registers. 19.3.12 serr# generation several internal and external sources of the lpc bridge can cause serr#, and are described below. the first class of errors is parity errors related internally to cmi. the lpc bridge captures generic data parity errors (errors it finds internally), as well as, errors returned on internal cycles where the bridge was the master. if either of these two conditions are met, and the bridge is en abled for parity error response, serr# is captured. additionally, if the bridge receives a target abort or master abort, and the bridge policy is to serr# on these types of aborts, serr# is generated.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 762 order number: 320066-003us cmd.pere - offset 04-05h bit 06 sts.dpe - offset 06-07h bit 15 sts.dpd - offset 06-07h bit 08 sts.rta - offset 06-07h bit 12 sts.rma - offset 06-07h bit 13 figure 19-2. lpc bridge serr# cmd.pere sts.dpe sts.dpd serr# sts.sse cmd.see
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 763 intel ? ep80579 integrated processor 20.0 lpc dma 20.1 overview lpc dma is supported using the iich dma controller. the dma controller has registers that are fixed in the lower 64 kbyte of i/o space. the dma controller is configured using registers in the pci configuration space. these registers allow configuration of the channels for use by lpc dma. the dma circuitry incorporates the functionality of two 8237 dma controllers with seven independently programmable channels; channels 0?3 and channels 5?7. dma channel 4 cascades the two controllers together and is not available for other use. in addition to accepting requests from dma slaves, the dma controller also responds to requests that software initiates. software may initiate a dma service request by setting any bit in the dma channel request register to a one. the dma controller is used for lpc dma. feature set of the iich dma controller: ? channels 0?3 provide 8-bit, count-by-bytes transfers. ? channels 5?7 provide 16-bit, count-by-words transfers. ? 24-bit addressing. each channel includes a 16-bit, legacy-compatible current address register (car), which holds the 16 least-significant bits, and an legacy compatible page register, which contains the eight next most significant bits of address. ? auto-initialization following a dma termination. the dma controller has registers that are fixed in the lower 64 kbyte of i/o space. the dma controller is configured using registers in the pci configuration space. these registers allow configuration of individual channels for use by lpc. the rpr bit effects the register decoding for the reserved page register (addresses 80, 84-86, 88, 8c-8e and their aliases in the 9x range). see section 17.1.6.3, ?offset 3410h: gcs: general control and status register? bit 2. figure 20-1. iich dma controller channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 dma-1 dma-2
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 764 order number: 320066-003us 20.2 lpc dma i/o-mapped register details note: some registers are normally read-only, but are writable in alt-access mode. likewise, there are some registers that are normally write-only, but are readable in alt-access mode. the individual register descriptions may not indicate this. see alt-access mode for more details. table 20-1. summary of lpc dma registers mapped in i/o space offset start offset end register id - description default value 00h at 02h 10h at 02h ?offset 00h: dma_bca[0-3] - dma base and current address registers for channels 0-3? on page 766 xxxx c4h at 04h c5h at 04h ?offset c4h: dma_bca[5-7] - dma base and current address registers for channels 5-7? on page 767 xxxx 01h at 02h 11h at 02h ?offset 01h: dma_bcc[0-3] - dma base and current count registers for channels 0-3? on page 768 xxxx c6h at 04h c7h at 04h ?offset c6h: dma_bcc[5-7] - dma base and current count registers for channels 5-7? on page 769 xxxx 87h, 83h, 81h, 82h 97h, 93h, 91h, 82h ?offset 87h: dma_mpl[0-3] - dma memory low page registers for channels 0-3? on page 771 xxxxxxx 8bh, 89h, 8ah 9bh, 99h, 9ah ?offset 8bh: dma_mpl[5-7]: dma memory low page registers for channels 5-7? on page 771 xxxxxxx table 20-2. 0000h (io) base address registers in the ia f1 view offset start offset end register id - description default value 08h 08h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b 18h 18h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b 08h 08h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh 18h 18h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh 0ah 0ah ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb 1ah 1ah ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb 0bh 0bh ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh 1bh 1bh ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh 0ch 0ch ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh 1ch 1ch ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh 0dh 0dh ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh 1dh 1dh ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh 0eh 0eh ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh 1eh 1eh ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh 0fh 0fh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b 1fh 1fh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 765 intel ? ep80579 integrated processor table 20-3. 0000h (io) base address registers in the ia f2 view offset start offset end register id - description default value d0h d0h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b d1h d1h ?offset 08h: dma_command - dma command register? on page 770 000x0x00b d0h d0h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh d1h d1h ?offset 08h: dma_status - dma status register? on page 772 xxxxxxxh d4h d4h ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb d5h d5h ?offset 0ah: dma_wsm - dma write single mask register? on page 773 000001xxb d6h d6h ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh d7h d7h ?offset 0bh: dma_chm - dma channel mode register? on page 774 000000xxh d8h d8h ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh d9h d9h ?offset 0ch: dma_cbp - dma clear byte pointer register? on page 775 xxxxxxxxh dah dah ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh dbh dbh ?offset 0dh: dma_mc - dma master clear register? on page 775 xxxxxxxxh dch dch ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh ddh ddh ?offset 0eh: dma_cm - dma clear mask register? on page 776 xxxxxxxxh deh deh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b dfh dfh ?offset 0fh: dma_wam - dma write all mask register? on page 777 00001111b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 766 order number: 320066-003us 20.2.1 register descriptions 20.2.1.1 offset 00h: dma_bca[0-3] - dma base and current address registers for channels 0-3 table 20-4. offset 00h: dma_bca[0-3] - dma base and current address registers for channels 0-3 description: ch. 0: 00h - 10h; ch.1: 02h - 12h; ch.2: 04h - 14h; ch.3: 06h - 16h view: ia f base address: 0000h (io) offset start: offset end: 00h at 02h 10h at 02h size: 16 bit a a. this register provides an 8-bit window into a 16-bit quantity. the byte accessed depends on the current byte pointer flip/flo p. default: xxxx power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 bcadd base and current address: this register determines the address for the transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on reads, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. if the channel is in auto-initialize mode, the current address register is reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channels 5-7), the address is shifted left one bit location. bit 15 is shifted into bit 16. the register is accessed in 8-bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing an address register, the byte pointer flip/flop must be cleared to ensure that the low byte is accessed first. xxxx rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 767 intel ? ep80579 integrated processor 20.2.1.2 offset c4h: dma_bca[5-7] - dma base and current address registers for channels 5-7 table 20-5. offset c4h: dma_bca[5-7] - dma base and current address registers for channels 5-7 description: ch. 5: c4h - c5h; ch. 6: c8h - c9h; ch. 7: cch - cdh view: ia f base address: 0000h (io) offset start: offset end: c4h at 04h c5h at 04h size: 16 bit a a. this register provides an 8-bit window into a 16-bit quantity . the byte accessed depends on the current byte pointer flip/flo p. default: xxxx power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 bcadd base and current address: this register determines the address for the transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on reads, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. if the channel is in auto-initialize mode, the current address register is reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channels 5-7), the address is shifted left one bit location. bit 15 is shifted into bit 16. the register is accessed in 8-bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing an address register, the byte pointer flip/flop must be cleared to ensure that the low byte is accessed first. xxxxh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 768 order number: 320066-003us 20.2.1.3 offset 01h: dma_bcc[0-3] - dma base and current count registers for channels 0-3 table 20-6. offset 01h: dma_bcc[0-3] - dma base and current count registers for channels 0-3 description: ch. 0: 01h - 11h; ch. 1: 03h - 13h; ch. 2: 05h - 15h; ch. 3: 07h - 17h, view: ia f base address: 0000h (io) offset start: offset end: 01h at 02h 11h at 02h size: 16 bit a a. this register provides an 8-bit window into a 16-bit quantity. the byte accessed depends on the current byte pointer flip/flo p. default: xxxx power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 bccnt base and current count: this register determines the number of transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (i.e., programming a count of 4h results in 5 transfers). the count is decremented in the current count register after each transfer. when the value in the register rolls from zero to ffffh, a terminal count is generated. if the channel is in auto-initialize mode, the current count register is reloaded from the base count register after a terminal count is generated. for transfers to/from an 8-bit slave (channels 0-3), the count register indicates the number of bytes to be transferred. for transfers to/from a 16-bit slave (channels 5-7), the count register indicates the number of words to be transferred. the register is accessed in 8-bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing a count register, the byte pointer flip/flop must be cleared to ensure that the lowest byte is accessed first. xxxxh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 769 intel ? ep80579 integrated processor 20.2.1.4 offset c6h: dma_bcc[5-7] - dma base and current count registers for channels 5-7 table 20-7. offset c6h: dma_bcc[5-7] - dma base and current count registers for channels 5-7 description: ch. 5: c6h - c7h, ch. 6: cah - cbh,ch. 7: ceh - cfh view: ia f base address: 0000h (io) offset start: offset end: c6h at 04h c7h at 04h size: 16 bit a a. this register provides an 8-bit window into a 16-bit quantity . the byte accessed depends on the current byte pointer flip/flo p. default: xxxx power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 bccnt base and current count: this register determines the number of transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (i.e., programming a count of 4h results in 5 transfers). the count is decremented in the current count register after each transfer. when the value in the register rolls from zero to ffffh, a terminal count is generated. if the channel is in auto-initialize mode, the current count register is reloaded from the base count register after a terminal count is generated. for transfers to/from an 8-bit slave (channels 0-3), the count register indicates the number of bytes to be transferred. for transfers to/from a 16-bit slave (channels 5-7), the count register indicates the number of words to be transferred. the register is accessed in 8-bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing a count register, the byte pointer flip/flop must be cleared to ensure that the lowest byte is accessed first. xxxxh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 770 order number: 320066-003us 20.2.1.5 offset 08h: dma_command - dma command register table 20-8. offset 08h: dma_command - dma command register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 08h 08h view: ia f 1 base address: 0000h (io) offset start: offset end: 18h 18h view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: d0h d0h view: ia f 2 base address: 0000h (io) offset start: offset end: d1h d1h size: 8 bit default: 000x0x00b power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 05 reserved reserved. software must always write 0 to these bits. 0h 04 dmaarb dma group arbitration priority: each channel group is individually assigned either fixed or rotating arbitration priority. at reset, each group is initialized in fixed priority. 0 = assigns fixed priority to the channel group. 1 = assigns rotating priority to the channel group. xh wo 03 reserved reserved. must be 0 0h 02 dmacgen dma channel group enable: both channel groups are enabled following part reset. disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4. 0 = enables the dma channel group 1 = disables the dma channel group xwo 01 : 00 reserved reserved. must be 0. 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 771 intel ? ep80579 integrated processor 20.2.1.6 offset 87h: dma_mpl[0-3] - dma memory low page registers for channels 0-3 20.2.1.7 offset 8bh: dma_mpl[5-7] - dma memory low page registers for channels 5-7 table 20-9. offset 87h: dma_mpl[0-3] - dma memory low page registers for channels 0- 3 description: ch. 0: 87h - 97h, ch. 1: 83h - 93h, ch. 2: 81h - 91h, ch. 3: 82h, view: ia f base address: 0000h (io) offset start: offset end: 87h, 83h, 81h, 82h 97h, 93h, 91h, 82h size: 8 bit default: xxxxxxx power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 dmalp dma low page (isa address bits [23:16]): this register works in conjunction with the dma controller's current address register to define the complete 24-bit address for the dma channel. this register remains static throughout the dma transfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register. xh rw table 20-10. offset 8bh: dma_mpl[5-7]: dma me mory low page registers for channels 5- 7 description: ch. 5: 8bh - 9bh, ch. 6: 89h - 99h, ch. 7: 8ah - 9ah view: ia f base address: 0000h (io) offset start: offset end: 8bh, 89h, 8ah 9bh, 99h, 9ah size: 8 bit default: xxxxxxx power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 dmalp dma low page (isa address bits [23:16]): this register works in conjunction with the dma controller's current address register to define the complete 24-bit address for the dma channel. this register remains static throughout the dma transfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register. xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 772 order number: 320066-003us 20.2.1.8 offset 08h: dma_status - dma status register table 20-11. offset 08h: dma_status - dma status register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 08h 08h view: ia f 1 base address: 0000h (io) offset start: offset end: 18h 18h view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: d0h d0h view: ia f 2 base address: 0000h (io) offset start: offset end: d1h d1h size: 8 bit default: xxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 crs channel request status: when a valid dma request is pending for a channel, the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note: channel 4 is the cascade channel, so the request status of channel 4 is a logical or of the request status for channels 0 through 3. 4 channel 0 5 channel 1 (5) 6 channel 2 (6) 7 channel 3 (7) xxxx ro 03 : 00 ctcs channel terminal count status: when a channel reaches terminal count (tc), its status bit is set to 1. if tc has not been reached, the status bit is set to 0. channel 4 is programmed for cascade, so the tc bit response for channel 4 is irrelevant: 0 channel 0 1 channel 1 (5) 2 channel 2 (6) 3 channel 3 (7) xxxx ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 773 intel ? ep80579 integrated processor 20.2.1.9 offset 0ah: dma_wsm - dma write single mask register table 20-12. offset 0ah: dma_wsm - dma write single mask register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 0ah 0ah view: ia f 1 base address: 0000h (io) offset start: offset end: 1ah 1ah view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: d4h d4h view: ia f 2 base address: 0000h (io) offset start: offset end: d5h d5h size: 8 bit default: 000001xxb power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved. must be 0. 00000b 02 cms channel mask select: 0 = dreq is enabled for the selected channel 1 = dreq is disabled for the selected channel the channel is selected through bits [1:0]. therefore, only one channel can be masked / unmasked at a time. 1wo 01 : 00 dmacs dma channel select: these bits select which dma channel mode register is programmed. 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) xx wo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 774 order number: 320066-003us 20.2.1.10 offset 0bh: dma_chm - dma channel mode register table 20-13. offset 0bh: dma_chm - dma channel mode register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 0bh 0bh view: ia f 1 base address: 0000h (io) offset start: offset end: 1bh 1bh view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: d6h d6h view: ia f 2 base address: 0000h (io) offset start: offset end: d7h d7h size: 8 bit default: 000000xxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 dmatm dma transfer mode: each dma channel can be programmed in one of four different modes: 00 demand mode 01 single mode 10 reserved 11 cascade mode 00h wo 05 addids address increment/decrement select: this bit controls address increment/decrement during dma transfers. 0 = address increment is selected. 1 = address decrement is selected. address increment is the default after part reset or master clear. 0h wo 04 autoen autoinitialize enable: 0 = the autoinitialize feature is disabled and dma transfers terminate on a terminal count. a part reset or master clear disables autoinitialization. 1 = the dma restores the base address and count registers to the current registers following a terminal count (tc). 0h wo 03 : 02 dmatt dma transfer type: these bits represent the direction of the dma transfer. when the channel is programmed for cascade mode, (bits[07:06] = ?11?) the transfer type is irrelevant. 00 verify - no i/o or memory strobes are generated 01 write - data transfers from the i/o devices to memory 10 read - data transfers from memory to the i/o device 11 illegal 00h wo 01 : 00 dmacsel dma channel select: these bits select the dma channel mode register that are written by bits [07:02]. 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) xx wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 775 intel ? ep80579 integrated processor 20.2.1.11 offset 0ch: dma_cbp - dma clear byte pointer register 20.2.1.12 offset 0dh: dma_mc - dma master clear register table 20-14. offset 0ch: dma_cbp - dma clear byte pointer register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 0ch 0ch view: ia f 1 base address: 0000h (io) offset start: offset end: 1ch 1ch view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: d8h d8h view: ia f 2 base address: 0000h (io) offset start: offset end: d9h d9h size: 8 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cbp clear byte pointer: command is enabled with a write to the i/o port address. writing to this register initializes the byte pointer flip/flop to a known state. it clears the internal latch used to address the upper or lower byte of the 16-bit address and word count registers. the latch is also cleared by a part reset and by the master clear command. this command precedes the first access to a 16 bit dma controller register. the first access to a 16-bit register accesses the least significant byte, and the second accesses the most significant byte. xwo table 20-15. offset 0dh: dma_mc - dma master clear register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 0dh 0dh view: ia f 1 base address: 0000h (io) offset start: offset end: 1dh 1dh view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: dah dah view: ia f 2 base address: 0000h (io) offset start: offset end: dbh dbh size: 8 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mstcl master clear: enabled with a write to the port. this has the same effect as the hardware reset; command, status, request, and byte pointer flip/flop registers are cleared and the mask register is set. xwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 776 order number: 320066-003us 20.2.1.13 offset 0eh: dma_cm - dma clear mask register table 20-16. offset 0eh: dma_cm - dma clear mask register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 0eh 0eh view: ia f 1 base address: 0000h (io) offset start: offset end: 1eh 1eh view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: dch dch view: ia f 2 base address: 0000h (io) offset start: offset end: ddh ddh size: 8 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 clmr clear mask register: command enabled with a write to the port. xwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 777 intel ? ep80579 integrated processor 20.2.1.14 offset 0fh: dma_wam - dma write all mask register table 20-17. offset 0fh: dma_wam - dma write all mask register description: view: ia f 1 a a. view 1 describes the control registers for channels 0-3. base address: 0000h (io) offset start: offset end: 0fh 0fh view: ia f 1 base address: 0000h (io) offset start: offset end: 1fh 1fh view: ia f 2 b b. view 2 describes the control registers for channels 4-7. base address: 0000h (io) offset start: offset end: deh deh view: ia f 2 base address: 0000h (io) offset start: offset end: dfh dfh size: 8 bit default: 00001111b power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved. must be 0. 0h ro 03 : 00 cmskb channel mask bits: setting the bit(s) to a 1 disables the corresponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [03:00] are set to 1 upon part reset or master clear. when read, bits [03:00] indicate the dma channel [03:00] ([07:04]) mask status. 0channel 0 (4) 1channel 1 (5) 2channel 2 (6) 3channel 3 (7) this register permits all four channels to be simultaneously enabled/disabled instead of enabling/ disabling each channel individually, as is the case with the mask register - write single mask bit. this register also has a read path to allow the status of the channel mask bits to be read. a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the channel is in auto-initialization mode). disabling channel 4 also disables channels 0?3 due to the cascade of channels 0?3 through channel 4. 1111b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 778 order number: 320066-003us 20.3 dma channel arbitration the iich dma controller consists of two logical channel groups; channels 0 ? 3 and channels 4 ? 7. each group may be in either fixed or rotate mode as described in detail below. the mode of operation for each controller is determined by the dma command register; address 08h for channels 0 ? 3 and address d0h for channels 4 ? 7. since channels 0 ? 3 are cascaded onto channel 4, any request on channel 0 ? 3 appears as a request on channel 4. the dma controller stops rotating when an nmi is pending. in fixed mode, the lowest numbered channel in a channel group receives highest priority. therefore, channel 0 is the highest priority device of channels 0 ? 3, and channel 4 is the highest priority device of channels 4 ? 7. when both channels are programmed in fixed mode, channel 0 has highest priority and channel 7 the lowest. in rotating mode, the lowest numbered channel starts out with highest priority. when it is serviced, the next numbered channel receives highest priority and the previous channel receives lowest priority. for example, if channel 0 has highest priority and is requesting, it wins arbitration, then is the lowest priority channel until channels 1, 2, and 3 have been serviced. due to the nature of channel 0 ? 3 being cascaded onto channel 4, rotating mode adds some peculiarities to the arbitration scheme. table 20-18 lists arbitration winners assuming all channels ares requesting. table 20-18. dma channel priority current both fixed lower fixed, upper rotating lower rotating, upper fixed both rotating 0 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 1 , 2, 3, 0, 5, 6, 7 5, 6, 7, 1, 2, 3, 0 1 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 2 , 3, 0, 1, 5, 6, 7 5, 6, 7, 2, 3, 0, 1 2 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 3 , 0, 1, 2, 5, 6, 7 5, 6, 7, 3, 0, 1, 2 3 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 0 , 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 5 0, 1, 2, 3, 5, 6, 7 6, 7, 0, 1, 2, 3, 5 0 , 1, 2, 3, 5, 6, 7 6, 7, 0, 1, 2, 3, 5 6 0, 1, 2, 3, 5, 6, 7 7, 0, 1, 2, 3, 5, 6 0 , 1, 2, 3, 5, 6, 7 7, 0, 1, 2, 3, 5, 6 7 0, 1, 2, 3, 5, 6, 7 0, 1, 2, 3, 5, 6, 7 0, 1, 2, 3, 5, 6, 7 0, 1, 2, 3, 5, 6, 7
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 779 intel ? ep80579 integrated processor 20.4 special cases in address/count 20.4.1 address overrun/underrun whenever the dma is operating, the addresses do not increment or decrement through the high page and low page registers. therefore, if a 24-bit address is 01ffffh and increments, the next address is 010000h, not 020000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 02ffffh, not 01ffffh. however, when the dma is operating in 16-bit mode, the addresses do not increment or decrement through the high page and low page registers but the page boundary is now 128 kbyte. therefore, if a 24-bit address is 01fffeh and increments, the next address is 000000h, not 010000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 03fffeh, not 02fffeh. 20.4.2 16-bit channels for 16-bit channels, the dma controller addressing is different than for 8-bit channels. the dma controller shifts the lower 16 bits of address left 1 bit and shifts in a ?0?, as shown in ta bl e 2 0 - 1 9 . the count register is also redefined to represent words instead of bytes. 20.4.3 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes autoinitialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simultaneously with the current registers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. following autoinitialize, the channel is ready to perform another dma service, without processor intervention, as soon as a valid dreq is detected. 20.4.4 software commands there are three additional special software commands that the dma controller can execute. the three software commands are: ? clear byte pointer flip-flop ?master clear ? clear mask register they are independent of any specif ic bit pattern on the data bus. table 20-19. address shifting in 16-bit dma transfers register address on 8 bit channels (hex) address on 16 bit channels (hex) page high byte low byte 00 01 01 00.01.01 00.02.02 01 fe 85 01.fe.85 01.fd.0a 01 ff ff 01.ff.ff 01.ff.fe 00 fe 85 00.fe.85 01.fd.0a 00 ff ff 00.ff.ff 01.ff.fe
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 780 order number: 320066-003us 20.5 theory of operation for lpc dma dma on lpc is handled through the use of the ldrq# lines from peripherals and special encodings on lad[3:0] from the host. single, demand, verify, and increment modes are supported on the lpc interface. channel 0 ? 3 are 8 bit channels. channel 5 ? 7 are 16 bit channels. channel 4 is reserved as a generic bus master request (see section 20.5.1 on lpc bus masters). 20.5.1 asserting dma requests peripherals that need dma service encode their requested channel number on the ldrq# signal. to simplify the protocol, each peripheral on the lpc interface has its own dedicated ldrq# signal (they may not be shared between two separate peripherals). the iich has two ldrq# inputs, allowing at least two devices to support dma or bus mastering. ldrq# is synchronous with lclk (pci clock). as shown in figure 20-2 , the peripheral uses the following serial encoding sequence: ? peripheral starts the sequence by asserting ldrq# low (start bit). ldrq# is high during idle conditions. ? the next three bits contain the encoded dma channel number (msb first). ? the next bit (act) indicates whether the request for the indicated dma channel is active or inactive. the act bit is a 1 (high) to indicate if it is active and a 0 (low) if it is inactive. the case where act is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. see section 20.5.2 for reasons for abandoning dma requests. ? after the active/inactive indication, the ldrq# signal must go high for at least one clock. after that one clock, ldrq# signal can be brought low to the next encoding sequence. if another dma channel also needs to request a transfer, another sequence can be sent on ldrq#. for example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. this allows multiple dma agents behind an i/o device to request use of the lpc interface, and the i/o device does not need to self- arbitrate before sending the message. 20.5.2 abandoning dma requests dma requests can be deasserted in two fashions: on error conditions by sending an ldrq# message with the ?act? bit set to ?0?, or normally through a sync field during the dma transfer. this section describes boundary conditions where the dma request needs to be removed prior to a data transfer. see section 20.5.6 to see how dma requests are terminated through a dma transfer. there may be some special cases where the peripheral desires to abandon a dma transfer. the most likely case of this occurring is due to a floppy disk controller which has overrun or enduring its fifo, or software stopping a device prematurely. figure 20-2. dma request assertion through ldrq# start msb lsb act start lclk ldrq#
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 781 intel ? ep80579 integrated processor in these cases, the peripheral wishes to stop further dma activity. it may do so by sending an ldrq# message with the act bit as ?0?. however, since the dma request was seen, there is no guarantee that the cycle hasn?t been granted and runs on lpc. therefore, peripherals must take into account that a dma cycle may still occur. the peripheral can choose not to respond to this cycle, in which case the host aborts it, or it can choose to complete the cycle normally with any random data. this method of dma deassertion must be prevented whenever possible in order to limit boundary conditions both on the iich and the peripheral. the ldreq dma abort scheme should not be used if a transfer is in progress (a cycle has started) and more than one transfer has been completed. in these cases, the peripheral must use the sync field encoding 0000. 20.5.3 general flow of dma transfers arbitration for dma channels is performed through the 8237 within the host. once the host has won arbitration on behalf of a dma channel assigned to lpc, it asserts lframe# on the lpc interface and begins the dma transfer. the general flow for a basic dma transfer is as follows: 1. the iich starts the transfer by asserting ?0000b? on lad[3:0] with lframe# asserted. 2. the iich asserts ?cycle type? of dma. the direction is based on the dma transfer direction. 3. the iich asserts the channel number and, if applicable, terminal count. 4. the iich indicates the size of the transfer; 8 or 16 bits. 5. if a dma reads: a. the iich drives the first 8 bits of data and turns the bus around. b. the peripheral acknowledges the data with a valid sync. c. if a 16 bit transfer, the process is repeated for the next 8 bits. 6. if a dma writes: a. the iich turns the bus around and waits for data. b. the peripheral indicates data ready through sync and transfers the first byte. c. if a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. the peripheral turns around the bus. 20.5.4 terminal count terminal count is communicated through lad[03] on the same clock that dma channel is communicated on lad[02:00]. this field is the channel field. terminal count indicates the last byte of transfer, based upon the size of the transfer. for example, on an 8-bit transfer size (size field is ?00b?), if the tc bit is set, then this is the last byte. on a 16-bit transfer (size field is ?01b?), if the tc bit is set, then the second byte is the last byte. the peripheral, therefore, must internalize the tc bit when the channel field is communicated and only signal tc when the last byte of that transfer size has been transferred.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 782 order number: 320066-003us 20.5.5 verify mode verify mode is supported on the lpc interface. a verify transfer to the peripheral is similar to a dma write, where the peripheral is transferring data to main memory. the indication from the host is the same as a dm a write, so the peripheral is driving data onto the lpc interface. however, the host does not transfer this data into main memory. 20.5.6 dma request deassertion an end of transfer is communicated to the iich through a special sync field transmitted by the peripheral. if a dma transfer is several bytes, such as a transfer from a demand mode device, the iich needs to know when to deassert the dma request based on the data currently being transferred. the dma agent uses a sync encoding on each byte of data being transferred, which indicates to the iich whether this is the last byte of transfer or if more bytes are requested. to indicate the last byte of transfer, the peripheral uses a sync value of ?0000b? (ready with no error), or ?1010b? (ready with error). these encodings tell the iich that this is the last piece of data transferred on a dma read (iich to peripheral), or the byte which follows is the last piece of data transferred on a dma write (peripheral to iich). when the iich sees one of these two encodings, it ends the dma transfer after this byte and deasserts the dma request to the 8237. therefore, if the iich indicated a 16 bit transfer, the peripheral can end the transfer after one byte by indicating a sync value of ?0000b? or ?1010b?. the iich does not attempt to transfer the second byte, and deasserts the dma request internally. this allows the peripheral, therefore, to terminate a dma burst. if the peripheral indicates a ?0000b? or ?1010b? sync pattern on the last byte of the indicated size, then the iich only deasserts the dma request to the 8237 since it does not need to end the transfer. if the peripheral wishes to keep the dma request active, then it uses a sync value of ?1001b? (ready plus more data). this tells the 8237 that more data bytes are requested after the current byte has been transferred, so the iich keeps the dma request active to the 8237. therefore, on an 8 bit transfer size, if the peripheral indicates a sync value of ?1001b?, the data is transferred and the dma request remains active to the 8237. at a later time, the iich starts with another start ? cyctype ? channel ? size etc. combination to initiate another transfer to the peripheral. the peripheral must not assume that the next start indication from the iich is another grant to the peripheral if it had indi cated a sync value of ?1001b?. on a single mode dma device, the 8237 rearbitrates after every transfer. only demand mode dma devices can be guaranteed that they receive the next start indication from the iich. note: indicating a ?0000b? or ?1010b? encoding on the sync field of an odd byte of a 16 bit channel (first byte of a 16 bit transfer) is an error condition. note: the host stops the transfer on the lpc bus as indicated, fill the upper byte with random data on dma writes (peripheral to memory), and indicate to the 8237 that the dma transfer occurred, incrementing the 8237s address and decrementing its byte count.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 783 intel ? ep80579 integrated processor 20.5.7 sync field/ldrq# rules since dma transfers on lpc are requested through an ldrq# assertion message, and end through a sync field during the dma transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a dma channel. the peripheral must not assert another message for eight lclks after a deassertion is indicated through the sync field. this is needed to allow the 8237, which typically runs off a much slower internal clock, to see a message deasserted before it is reasserted so that it can arbitrate to the next agent. under default operation, the host only perf orms 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. in order to enable 16-bit transfers on 8-bit channels, the peripheral must communicate to system bios that larger transfer sizes are allowed. if the host has this capability, the bios programs the host to attempt larger transfer sizes. the iich does not support 32-bit dma transfer. the method by which this communication between host and peripheral through system bios is performed is beyond the scope of this specification. since the host and peripheral are motherboard devices, no ?plug-n-play? registry is required. the peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the dma channel, and be willing to accept a size field that is smaller than what it may currently have buffered. to that end, it is recommended that future devices which may appear on the lpc bus, which require higher bandwidth than 8-bit or 16-bit dma allow, do so with a bus mastering interface and not rely on the 8237.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 784 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 785 intel ? ep80579 integrated processor 21.0 serial peripheral interface 21.1 overview the serial peripheral interface (spi) is a 4-pin interface that provides a potentially lower-cost alternative for system flash versus the firmware hub interface that is available on the lpc pins. 21.1.1 features ? support for multiple spi flash vendors ? simple hardware ? equivalence to lpc-based firmware hubs ? provide the ep80579 write protection scheme ? equivalent performance (boot time, resume time) ? top swap functionality ? support for e & f segments below 1 mb ? 64 kb-granular protection note that the spi does not provide support for very large bios sizes as easily as the fwh interface. the ep80579 spi interface is restricted to one chip select pin. the serial peripheral interface (spi) is a 4-pin interface that provides a potentially lower-cost alternative for system flash versus the firmware hub interface that is available on the lpc pins. 21.2 external interface table 21-1. spi pin interface signal(s) width type io type description spi_sclk 1 o lvttl, 3.3v serial bit-rate clock 17.86 mhz spi_cs# 1 o lvttl, 3.3v cs for slave spi_mosi 1 o lvttl, 3.3v master data out / slave in spi_miso 1 i lvttl, 3.3v master data in/ slave out
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 786 order number: 320066-003us 21.3 spi protocol communication on the spi bus is done with a master ? slave protocol. typical bus topologies call for a single spi master with a single spi slave. the spi interface consists of a four wire interface: clock (clk), master data out (master out slave in (mosi)), master data in (master in slave out (miso)) and an active low chip select (cs#). 21.3.1 spi pin-level protocol spi communicates utilizing a synchronous protocol with the clock being driven by the master. after selecting a slave by asserting the spi_cs# signal, the master generates eight clock pulses per byte on the spi_clk wire, one clock pulse per data bit. 1 data flows from master to slave on the spi_mosi wire and from slave to master on the spi_miso wire 2 . data is setup and sampled on opposite edges of the spi_clk signal. master drives data off of the falling edge of the clock and slave samples on the rising edge of the clock. similarly, slave drives da ta off of the falling edge of the clock. the master has more flexibility on sampling schemes since it controls the clock. note that spi_clk flight times and the device spi_miso max valid times indicate that the rising edge is not feasible for sampling the spi_miso input at the master for a 20 mhz clock period with 50% duty cycle. table 21-2. gpio boot source selection gpio17 gpio33 description 11 default. boot from lpc 01 reserved. 10 reserved. 00 boot from spi 1. spi supports 8 or 16 bit words, however all devices on the supported list only operate on 8 bit words. 2. spi specifies that data can be shifted msb or lsb first, however all devices on the supported list only operate msb first.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 787 intel ? ep80579 integrated processor only mode 0 is supported. commands, addresses and data are shifted most significant bit (msb) first. for the 24- bit address, this means bit 23 is shifted first while bit 0 is shifted last. however, for data bursts, bytes are shifted out from least significant byte to most significant byte , where each byte is shifted (msb to lsb). 21.3.1.1 addressing a slave is targeted for a cycle when it?s spi_cs# pin is asserted. besides slave addressing there is register addressing within the slave itself. the list of ep80579 supported devices? includes only flash devices. see supported devices data sheets for more information. 21.3.1.2 data transaction all transactions on the spi bus must be a multiple of 8 bits. a frame consists of any number of 8-bit data packets. to initiate a data transfer, the spi master asserts (high to low transition) the spi_cs# signal informing the spi slave that it is being targeted for a cycle. the master will then shift out the 8-bit opcode followed by the slave?s internal address. in the case of a read transaction, the slave will interpret the slave address and begin driving data out on the spi_miso pin and ignore any transactions on the spi_mosi pin. the master indicates read complete by deasserting the spi_cs# signal on an 8-bit boundary. in the case of a write transaction, the slave will continue to receive master data on the spi_mosi pin. the write transaction is completed upon deassertion of the spi_cs# signal on an 8-bit boundary. the spi bus does include a mechanism for flow control, however some devices include the support of a hold signal. see slave documentation for more information. if the slave receives an un-recognized or invalid opcode it should ignore the rest of the packet and wait for the deassertion of spi_cs#. figure 21-1. basic spi protocol bit3 bit2 bit1 bit0 bit3 bit 2 bit 1 bit0 clk cs! miso mosi bit3 bit2 bit1 bit0 bit3 bit 2 bit 1 bit0 clk cs! miso mosi
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 788 order number: 320066-003us 21.3.1.3 bus errors if the first 8 bits specify an opcode which is not supported the slave will not respond and wait for the next high to low transition on spi_cs#. spi hardware should automatically discard 8-bit words that were not completely received upon deassertion of the spi_cs# signal. any other error correction or detection mechanisms must be implemented in firmware/ software. 21.3.1.4 instructions notes: 1. fast read protocol is not supported 2. the auto address increment type is not supported. instruction st m25p80 (8 mb) st m45pe80 (8 mb) nexflash nx25p* sst 25v040 (4mb), sst 25vf080 (8 mb) ching is (1 mb) write status 01 - 01 01 01 data program 02 02 02 02 02 read data 03 03 03 03 03 write disable 04 04 04 04 04 read status 05 05 05 05 05 write enable 06 06 06 06 06 page write - 0a - - - fast read (1) 0b 0b 0b - 0b ena write status - - - 50 - 256b erase - db - - - 4kbyte erase - - - 20 d7 64kb erase d8 d8 d8 52 d8 chip erase c7 - c7 60 c7 auto add inc (2) --- af - power down/up b9 / ab b9 / ab b9 - - read id - 9f 90 ab or 90 ab
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 789 intel ? ep80579 integrated processor 21.3.1.5 spi timings the spi interface is designed to fall within the following protocol timing specs. these specs are intended to operate with most spi flash devices. table 21-3. spi cycle timings 21.4 host side interface 21.4.1 spi host interface registers the spi host interface registers are memory-mapped in the rcrb chipset memory space in the range 3020h to 308fh. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. the table below does not include the 3020h offset. 21.4.2 register overview parameter minimum value description spi_cs# setup 30 ns spi_cs# low to spi_clk high spi_cs# hold 30 ns spi_clk low to spi_cs# low clock high 22 ns time that spi_clk is driven high per clock period clock low 22 ns time that spi_clk is driven low per clock period table 21-4. bus 0, device 31, function 0, pci registers mapped through rcba bar offset start offset end register id - description default value 3020h 3021h ?offset 3020h: spis - spi status? on page 790 0001h 3022h 3023h ?offset 3022h: spic - spi control? on page 791 2005h 3024h 3027h ?offset 3024h: spia - spi address? on page 792 00xxxxxh 3028h 302bh ?offset 3028h: spid0 - spi data 0? on page 792 xxxxxxxxh 3030h at 4h 306ch at 4h ?offset 3030h, 3038h, 3040h, 3048h, 3050h, 3058h, 3060h: spi[0-6] - spi data [0-6]? on page 793 00000000h 3070h 3073h ?offset 3070h: bbar - bios base address? on page 793 00000000h 3074h 3075h ?offset 3074h: preop - prefix opcode configuration? on page 794 0004h 3076h 3077h ?offset 3076h: optype - op code type? on page 794 0000h 3078h 307fh ?offset 3078h: opmenu - opcode menu configuration? on page 795 00000005h 3080h at 4h 3083h at 4h ?offset 3080h: pbr0 - protected bios range #0? on page 796 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 790 order number: 320066-003us 21.4.2.1 offset 3020h: spis ? spi status table 21-5. offset 3020h: spis - spi status description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3020h 3021h size: 16 bit default: 0001h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 scl spi configuration lock-down: when set to 1, the spi static configuration information in offsets 50h through 6bh can not be overwritten. once set to 1, this bit can only be cleared by a hardware reset. 0rwl 14 :4 rsvd reserved 0rv 3bas blocked access status: hardware sets this bit to 1 when an access is blocked from running on the spi interface due to one of the protection policies or when any of the programmed cycle registers are written while a programmed access is already in progress. this bit is set for both programmed accesses and direct memory reads that get blocked. this bit remains asserted until cleared by software writing a 1 or hardware reset. 0rwc 2cds cycle done status: the ep80579 sets this bit to 1 when the spi cycle completes (i.e., scip bit is 0) after software sets the go bit. this bit remains asserted until cleared by software writing a 1 or hardware reset. when this bit is set and the spi bit in offset 3022h: spic ? spi control is set, an internal signal is asserted to the smi# generation block. software must make sure this bit is cleared prior to enabling the spi smi# assertion for a new programmed access. this bit gets set after the status register polling sequence completes after reset deasserts. it is cleared before and during that sequence. 0rwc 1rsvd reserved. 0rv 0scip spi cycle in progress (scip): hardware sets this bit when software sets the spi cycle go bit in the offset 3022h: spic ? spi control . this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0. this bit reports 1b during the status register polling sequence after reset deasserts; it is cleared when that sequence completes. 1ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 791 intel ? ep80579 integrated processor 21.4.2.2 offset 3022h: spic ? spi control table 21-6. offset 3022h: spic - spi control description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3022h 3023h size: 16 bit default: 2005h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 ssmie spi smi# enable: when set to 1, the spi asserts an smi# request whenever the cycle done status bit is 1. 00 rw 14 dc data cycle: when set to 1, there is data that corresponds to this transaction. when 0, no data is delivered for this cycle, and the dbc and data fields themselves are don?t cares. 1rw 13 :08 dbc data byte count (dbc): this field specifies the number of bytes to shift in or out during the data portion of the spi cycle. the valid settings (in decimal) are any value from 0 to 63. the number of bytes transferred is the value of this field plus 1. note that when this field is 00_0000b, then there is 1 byte to transfer and that 11_1111b means there are 64 bytes to transfer. 0rw 7 rsvd reserved 0rv 6:4 cop cycle opcode pointer: this field selects one of the programmed opcodes in the offset 3078h: opmenu ? opcode menu configuration to be used as the spi command/opcode. in the case of an atomic cycle sequence, this determines the second command. 0rw 3spop sequence prefix opcode pointer: this field selects one of the two programmed prefix opcodes for use when performing an atomic cycle sequence. a value of 0 points to the opcode in the least significant byte of the offset 3074h: preop ? prefix opcode configuration register. by making this programmable, the ep80579 supports flash devices that have different opcodes for enabling writes to the data space vs. status register. 0rw 2acs atomic cycle sequence (acs): when set to 1 along with the scgo assertion, the ep80579 will execute a sequence of commands on the spi interface. the sequence is composed of: atomic sequence prefix command (8-bit opcode only) primary command specified by software (can include address and data) polling the flash status register (opcode 05h) until bit 0 becomes 0b. the spi cycle in progress bit remains set and the cycle done status bit in offset 3020h: spis ? spi status register remains unset until the busy bit in the flash status register returns 0. 1rw 1scgo spi cycle go (scgo): this bit always returns 0 on reads. however, a write to this register with a ?1? in this bit starts the spi cycle defined by the other bits of this register. the spi cycle in progress (scip) bit in offset 3020h: spis ? spi status register gets set by this action. hardware must ignore writes to this bit while the spi cycle in progress bit is set. hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. this saves an additional memory write. 0rws 0rsvd reserved 1rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 792 order number: 320066-003us 21.4.2.3 offset 3024h: spia ? spi address 21.4.2.4 offset 3028h: spid0 ? spi data 0 table 21-7. offset 3024h: spia - spi address description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3024h 3027h size: 32 bit default: 00xxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rsvd reserved 0rv 23 :00 sca spi cycle address (sca): this field is shifted out as the spi address (msb first). 0rw table 21-8. offset 3028h: spid0 - spi data 0 description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3028h 302bh size: 64 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :00 scd spi cycle data 0 (scd0): this field is shifted out as the spi data on the master-out slave-in data pin (spi_mosi) during the data portion of the spi cycle. this register also shifts in the data from the master-in slave-out pin (spi_miso) into this register during the data portion of the spi cycle. the data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. specifically, the shift order on spi in terms of bits within this register is: 7-6-5-4-3-2-1-0-15- 14-13-?8-23-22-?16-31?24-39..32?etc. bit 56 is the last bit shifted out/in. there are no alignment assumptions; byte 0 always represents the value specified by the cycle address. note that the data in this register may be modified by the hardware during any programmed spi transaction. direct memory reads do not modify the contents of this register. (this last requirement is needed in order to properly handle the collision case described in section 21.4.3.2 .) this register is initialized to 0 by the reset assertion. however, the least significant byte of this register is loaded with the first status register read of the atomic cycle sequence that the hardware automatically runs out of reset. therefore, bit 0 of this register can be read later to determine if the platform encountered the boundary case in which the spi flash was busy with an internal instruction when the platform reset deasserted. see description rw0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 793 intel ? ep80579 integrated processor 21.4.2.5 spid[0-6] ? spi data n 21.4.2.6 offset 3070h: bbar ? bios base address this register is not writable when the spi configuration lock-down bit in offset 3020h: spis ? spi status register is set. table 21-9. offset 3030h, 3038h, 3040h, 3048h, 3050h, 3058h, 3060h: spi[0-6] - spi data [0-6] description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3030h at 4h 306ch at 4h size: 64 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 : 00 scd spi cycle data n (scd[n]): similar definition as spi cycle data 0. however, this register does not begin shifting until spid[n-1] has completely shifted in/out. 0rw table 21-10. offset 3070h: bbar - bios base address description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3070h 3073h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rsvd reserved 0rv 23 :08 bsp bottom of system flash: this field determines the bottom of the system bios. the ep80579 will not run programmed commands nor memory reads whose address field is less than this value. this field corresponds to bits 23:8 of the 3-byte address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential spi address. software must always program 1?s into the upper, don?t care bits of this field based on the flash size. hardware does not know the size of the flash array and relies upon the correct programming by software. the default value of 0000h results in all cycles allowed. note: the spi host controller prevents any programmed cycle using the address register with an address less than the value in this register. some flash devices specify that the read id command must have an address of 0000h or 0001h. if this command must be supported with these devices, it must be performed with the bbar - bios base address programmed to 0h. some of these devices have actually been observed to ignore the upper address bits of the read id command. 0rws 7:00 rsvd reserved 0rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 794 order number: 320066-003us 21.4.2.7 offset 3074h: preop ? prefix opcode configuration this register is not writable when the spi configuration lock-down bit in offset 3020h: spis ? spi status register is set. 21.4.2.8 offset 3076h: optype ? opcode type configuration this register is not writable when the spi configuration lock-down bit in offset 3020h: spis ? spi status register is set. entries in this register correspond to the entries in the offset 3078h: opmenu ? opcode menu configuration register. note that the definition below only provides write protection for opcodes that have addresses associated with them. therefore, any erase or write opcodes that do not use an address should be avoided (for example, ?chip erase? and ?auto-address increment byte program?). table 21-11. offset 3074h: preop - prefix opcode configuration description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3074h 3075h size: 16 bit default: 0004h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :08 po1 prefix opcode 1: software programs an spi opcode into this field that is permitted to run as the first command in an atomic cycle sequence. 0rws 7:00 po0 prefix opcode 0: software programs an spi opcode into this field that is permitted to run as the first command in an atomic cycle sequence. 04h rws table 21-12. offset 3076h: optype - op code type (sheet 1 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3076h 3077h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :14 ot7 opcode type 7: see the description for bits 1:0 0 rws 13 :12 ot6 opcode type 6: see the description for bits 1:0 0 rws 11 :10 ot5 opcode type 5: see the description for bits 1:0 0 rws 9:08 ot4 opcode type 4: see the description for bits 1:0 0 rws 7:06 ot3 opcode type 3: see the description for bits 1:0 0 rws
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 795 intel ? ep80579 integrated processor 21.4.2.9 offset 3078h: opmenu ? opcode menu configuration this register is not writable when the spi configuration lock-down bit in offset 3020h: spis ? spi status register is set. eight entries are available in this register to give bios a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. this keeps the hardware flexible enough to operate with a wide variety of spi devices. it is recommended that bios avoid programming write enable opcodes in this menu. malicious software could then perform writes and erases to the spi flash without using the atomic cycle mechanism. write enable opcodes should only be programmed in the offset 3074h: preop ? prefix opcode configuration . 5:04 ot2 opcode type 2: see the description for bits 1:0 0 rws 3:02 ot1 opcode type 1: see the description for bits 1:0 0 rws 1:00 ot0 opcode type 0: this field specifies information about the corresponding opcode 0. this information allows the hardware to 1) know whether to use the address field and 2) provide bios protection capabilities. the hardware implementation also uses the read vs. write information for modifying the behavior of the spi interface logic. the encoding of the two bits is: 00 = no address associated with this opcode and read cycle type 01 = no address associated with this opcode and write cycle type 10 = address required; read cycle type 11 = address required; write cycle type 0rws table 21-12. offset 3076h: optype - op code type (sheet 2 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3076h 3077h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 21-13. offset 3078h: opmenu - opcode menu configuration (sheet 1 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3078h 307fh size: 64 bit default: 00000005h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :56 ao7 allowable opcode 7: see the description for bits 7:0 0 rws 55 :48 ao6 allowable opcode 6: see the description for bits 7:0 0 rws 470 :40 ao5 allowable opcode 5: see the description for bits 7:0 0 rws 39 :32 ao4 allowable opcode 4: see the description for bits 7:0 0 rws 31 :24 ao3 allowable opcode 3: see the description for bits 7:0 0 rws
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 796 order number: 320066-003us 21.4.2.10 offset 3080h: pbr0 ? protected bios range [0-2] this register can not be written when the spi configuration lock-down bit in offset 3020h: spis ? spi status register is set to 1. 23 :16 ao2 allowable opcode 2: see the description for bits 7:0 0 rws 15 :08 ao1 allowable opcode 1: see the description for bits 7:0 0 rws 7:00 ao0 allowable opcode 0: software programs an spi opcode into this field for use when initiating spi commands through the control register. 05h rws table 21-13. offset 3078h: opmenu - opcode menu configuration (sheet 2 of 2) description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3078h 307fh size: 64 bit default: 00000005h power well: core bit range bit acronym bit description sticky bit reset value bit access table 21-14. offset 3080h: pbr0 - protected bios range #0 description: view: pci bar: rcba bus:device:function: 0:31:0 offset start: offset end: 3080h at 4h 3083h at 4h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 wpe write protection enable: when set, this bit indicates that the base and limit fields in this register are valid and that writes directed to addresses between them (inclusive) must be blocked by hardware. the base and limit fields are ignored when this bit is cleared. 0rw-special 30 :24 reserved reserved 0rv 23 :12 prl protected range limit: this field corresponds to spi address bits 23:12 and specifies the upper limit of the protected range. address bits 11:0 are assumed to be fffh for the limit comparison. any address greater than the value programmed in this field is unaffected by this protected range. 000h rw- special 11 :00 prb protected range base: this field corresponds to spi address bits 23:12 and specifies the lower base of the protected range. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range. 000h rw- special
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 797 intel ? ep80579 integrated processor 21.4.3 running spi cycles from the host 21.4.3.1 memory reads memory reads to the bios range result in a read command (03h) with the lower 3 bytes of the address delivered in the spi cycle. by sending the entire 24 bits of address out to the spi interface unchanged, the ep80579 hardware can support various flash memory sizes without having straps or automatic detection algorithms in hardware. the flash memory device must ignore the upper address bits such that an address of ffffffh simply aliases to the top of the flash memory. this is true for all supported flash devices. when considering additional flash parts, this behavior should be checked. for compatibility with the fwh interface, the spi interface supports decoding the two 64 kb bios ranges at the e0000h and f0000h segments just below 1 mb. these ranges must be re-directed (aliased) to the ranges just below 4 gb by the ep80579. this is done by forcing the upper address bi ts (23:20) to 1s when performing the read on the spi interface. when the spi prefetch enable bit in offset dch: bc: bios control register is set, the ep80579 checks if the starting address for a read is aligned to the start of a 64b block (i.e., address bits 5:0 are 00h). if this is not the case, then the ep80579 only reads the length specified by the current read. if the read is aligned to the start of the 64b block with the spi prefetch enable bit set, then the read burst continues on the spi pins until 64 bytes have been received. note that the ep80579 always performs the entire 64b burst when the conditions are met to perform the prefetch when the memory read request is received. this policy can result in a large penalty if the read addresses are not sequential. software is allowed and encouraged to dynamically turn on prefetching only when the reads are sequential (for example, if shadowing the bios using consecutive dword reads). when prefetching is enabled, the read buffer must be enabled for caching. if the ep80579 detects a read to the range that is currently in (or being fetched for) the read buffer, it will not perform another read cycle on the spi pins. instead, the data is returned from the read buffer. note that the entire read request must be contained in the cache in order to avoid running the read on the spi interface. the following events invalidate the read buffer ?cache?: 1. a programmed access begins. note that if the cycle is blocked from running for protection or other reasons, the cache is not flushed. 2. a memory read to a bios range that does not hit the range in the read buffer. 3. system reset. 4. software setting the cache disable bit (and clearing the prefetch enable) in offset dch: bc: bios control register . this can serve as a way to flush the cache in software. even when prefetching is disabled, the read buffer can act as a cache for direct memory read data. this is a potentially valuable boot-time optimization that leverages the basic caching mechanism that is needed for prefetching anyway. the cache is loaded with the data received on every dire ct memory read that runs on the spi pins. that data remains valid within the cache until any one of the conditions listed above occurs. for the cache to work properly, the direct memory read must be fully contained within a 64-byte aligned range. the following events result in a valid read buffer cache when the caching is enabled: 1. a host read to the spi bios with a length of 64 bytes. this cycle must be aligned to a 64b boundary. 2. a host read to the spi bios of any length with a 64b-aligned address and prefetching is enabled.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 798 order number: 320066-003us note that, although the spi interface may ?burst ahead? for up to 64 bytes, the host interface may still have to wait for prefetched data to arrive from the flash before generating the completion back to the processor. the round trip delay for the platform to complete one dword and run the host read for the next sequential dword can be shorter than the spi time to receive another 32 bits. if a direct memory read targeting the spi flash is received while the host interface is already busy with either another direct memory read or a programmed access, then the spi host hardware will hold the new direct memory read (and the host processor) pending until the preceding spi access completes. note that it is possible for a second direct memory read to be re ceived while the prefetching continues for a first direct memory read. the spi interface provides empty flash detection equivalent to fwh (i.e., all 1?s on the initial boot access.) it is possible that a direct memory read targeting the spi flash can be issued with non- contiguous byte enables. while the cpu cannot create these cycles, peer agents can. the spi interface handles these direct memory read transactions in the following fashion. note that the byte enables in the table are active high, and be[3] is the most significant byte enable of the dword. table 21-15. byte enable handling on direct memory reads when coming out of a platform reset, the spi host controller must hold the initial direct memory read from the processor pend ing until the spi flash is no longer busy with an internal write or erase instruction. in order to achieve this, the host controller reads the status register (opcode = 05h) of the flash device until bit 0 is cleared. this is equivalent to the polling performed following an atomic cycle, during which the direct memory reads are held pending. depending on the type of flash and type of long instruction performed, the delay could be long enough to cause a watchdog timeout in the processor or chipset. although this error condition is deemed acceptable in response to this rare error scenario (reset during flash update), it can be avoided altogether by selecting flash instructions on spi devices that complete in less than ~1 second. note that in the typical boot case, the status read on the spi interface will complete well before the processor boot fetch due to the delay from pltrst# deassertion to cpurst# deassertion. # dwords requested first dword be[3:0] last dword be[3:0] action taken 1 0000 don?t care zero bytes read from spi, no spi transaction started 1 0001, 0010, 0100, 1000, 0011, 0110, 1100, 0111, 1110, 1111 don?t care bytes read from spi = bytes requested starting from lowest requested byte 1 0101, 1001, 1010, 1011, 1101 don?t care full dw (4 bytes) requested from spi >1 0000 don?t care undefined behavior. illegal protocol >1 1000, 1100, 1110, 1111 don?t care bytes read from spi = 4* (num dw -1) + bytes requested in first dw. address starts from lowest requested byte. >1 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1001, 1010, 1011, 1101 don?t care bytes read from spi = 4* num dw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 799 intel ? ep80579 integrated processor 21.4.3.2 generic programmed commands all commands other than the standard (memory) reads must be programmed by the bios in the spi control, address, data, and opcode configuration registers in section 21.4.1 . the opcode type in offset 3076h: optype ? opcode type configuration and data byte count fields in offset 3074h: preop ? prefix opcode configuration determine how many clocks to run before deasserting the chip enable. the flash data is always shifted in for the number of bytes specified and the bios out data is always shifted out for the number of data bytes specified. note that the hardware restricts the burst lengths that are allowed. the status bit in offset 3020h: spis ? spi status indicates when the cycle has completed on the spi port allowing the host to know when read results can be checked and/or when to initiate a new command. the ep80579 also provides the ?atomic cycle sequence? for performing erases and writes to the spi flash in offset 3022h: spic ? spi control . when this bit is 1 (and the spi cycle go bit is written to 1), a sequence of cycles is performed on the spi interface. in this case, the specified cycle is preceded by the prefix command (8-bit programmable opcode) and followed by repeated reads to the status register (opcode 05h) until bit 0 indicates the cycle has completed. the hardware does not attempt to check that the programmed cycle is a write or erase. if a programmed access is initiated (spi cycle go written to 1) while the spi host interface logic is already busy with a direct memory read, then the spi host hardware will hold the new programmed access pending until the preceding spi access completes. it will then begin to request the spi bus for the programmed access. once the spi host hardware has committed to running a programmed access, subsequent writes to the programmed cycle registers that occur before it has completed will not modify the original transaction and will result in the assertion of the blocked access status bit in offset 3020h: spis ? spi status . software should never purposely behave in this way and rely on this behavior. however, the blocked access status bit provides basic error-reporting in this situation. writes to the following registers cause the blocked access status bit assertion in this situation: ? offset 3022h: spic ? spi control ? offset 3024h: spia ? spi address ? offset 3028h: spid0 ? spi data 0
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 800 order number: 320066-003us 21.4.3.3 flash protection there are two types of flash protection mechanisms: 1. bios range write protection 2. smi#-based global write protection the two mechanisms are conceptually ored together such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. ta bl e 2 1 - 1 6 provides a summary of the three mechanisms. the ep80579 provides these protections in hardware. note that it is critical that the hardware must not allow malicious software to modify the address or opcode pointers after determining that a cycle is allowed to run, such that the actual cycle that runs on spi should have been blocked. if the command associated with an atomic cycle sequence is blocked according to the ep80579 configuration, the ep80579 must not run any of the sequence. a blocked command will appear to software to finish, except that the blocked access status bit in offset 3020h: spis ? spi status register is set in this case. 21.4.3.3.1 bios range write protection the ep80579 provides a method for blocking writes to specific ranges in the spi flash when the protected bios ranges are enabled. this is achieved by checking the opcode type information (which can be locked down by the initial boot bios) and the address of the requested command against the base and limit fields of a write protected bios range. only the initial address is checked. since writes wrap within a page, there should be no issue with writes illegally occurring in the next page (assuming the bios has configured the protection limit to align with the edge of a page). note that once bios has locked down the protected bios range registers, this mechanism remains in place until the next system reset. 21.4.3.3.2 smi# based global write protection the ep80579 provides a method for blocking writes to the spi flash when the write protect bit is cleared (i.e., protected) in offset dch: bc: bios control register . this is achieved by checking the opcode type information (which can be locked down by the initial boot bios) of the requested command. the write protect and lock enable bits interact in the same manner for spi bios as they do for the fwh bios. table 21-16. flash protection mechanism summary mechanism accesses blocked range specific reset-override or smi#- override equivalent function on fwh bios range write protection writes yes reset override fwh sector protection smi#-based global write protection writes no smi# override same as write protect in previous chipsets for fwh
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 801 intel ? ep80579 integrated processor 21.4.3.4 decoding memory ranges for spi the boot bios destination straps are sampled on the rising edge of pwrok. if the spi port is selected, then the section 19.2.4, ?lpc i/o configuration registers? on page 747 to determine what ranges of memory read addresses are forwarded to spi. (see section 3.7 for details of the actual pin(s) used for selecting spi.) the feature space ranges are unique to the fwh flash. however, the feature space can be treated just like standard memory from an spi perspective and therefore allow up to 16 mb of contiguous memory decode. the ep80579 forwards both data and feature space ranges to the spi interface (although the bios bar may block the feature space accesses in situations where the flash size is less than 4 mb). since there is only one flash chip enable pin on the ep80579, there is no need to map the various flash ranges to multiple enables. of course, in order to utilize 16 mb, the single flash device would need to support 128 mbits of data. the top swap mechanism works in the same way that it does on lpc. address bit 16 is inverted when top swap is enabled for any accesses to the upper two 64 kb blocks. also like lpc, the top swap functionality does not apply to accesses generated to the holes below 1 mb. the spi interface performs the address bit inversion on only the direct memory read access method; software can control the address directly with the programmed command access method. the prefetching and caching logic consistently comprehends the address inversion to avoid delivering bad data. also, the protection mechanisms described above observe the address after the inversion logic. memory writes to the bios memory range are dropped. this forces all of these potentially harmful cycles to go through the programmed commands interface. note that direct memory reads to the e0000h-fffffh segments are remapped to top of flash as mentioned previously in section section 21.4.3.1 . this range is not remapped when using programmed accesses. 21.5 bios programming considerations 21.5.1 spi initialization this section provides a high level description of the steps that the bios should take upon coming out of reset when using spi flash. 1. boot vector fetch and other initial bios reads using direct memory reads (some of which are 64 byte code reads). caching is enabled in hardware by default to improve performance on consecutive reads to the same line. 2. turn on the spi prefetching policy in the lpc bridge configuration space ( offset dch: bc: bios control register ). this policy bit is in configuration space to avoid requiring protected memory space early in the boot process. 3. copy the various bios modules out of the spi flash using direct memory reads. it is assumed that these reads are shorter than 64 bytes and are targeted to consecutive addresses; hence, the prefetch mechanism improves the performance of this sequence. 4. turn off the spi prefetch policy. 5. program opcode registers in order to discover which flash device is being used. four of the six supported flash devices support the read id instruction. details of the discovery algorithm are outside the scope of this specification. 6. disable future request, offset 3022h: spic ? spi control bit 0. default state is future request enabled. 7. re-program opcode registers to support specific flash vendor?s commands. if not using all of the opcode menu and prefix opcodes, bios should program a ?safe?
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 802 order number: 320066-003us value in the unused opcodes to minimize what malicious software can do. a suggested safe value is to replicate one of the valid entries. a. offset 3074h: preop ? prefix opcode configuration b. offset 3076h: optype ? opcode type configuration c. offset 3078h: opmenu ? opcode menu configuration 8. setup protection registers as needed. a. offset 3070h: bbar ? bios base address b. offset 3080h: pbr0 ? protected bios range [0-2] 9. lock down the spi registers, offset 3020h: spis ? spi status bit 15. 10. set up smi based write protection as needed (same as fwh).
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 803 intel ? ep80579 integrated processor 22.0 general purpose i/o: bus 0, device 31, function 0 22.1 overview ? the following gpio pins are implemented: note: pin direction is related to gpio mode. input only : 22 (00:15, 26, 29:31, 40:41) output only : 8 (16:21, 23, 48) input/output : 6 (24:25, 27:28, 33:34). ? gpio pins [22, 32, 35:39, 42:47, 50:63] do not exist. ? some of the gpio pins can be configured to be used for alternate functions. the alternate function and irq mapping of function multiplexed gpio pins is provided in ta bl e 2 2 - 1 . ? gpio pins [16:21, 23:25, 27:28, 30:31, 33:34, 40] are configured to generate irq interrupt to io-apic if etr3.gpio_irq_strap_sts = 1 [strap pulling siu2_txd to low on the rising edge of pwrok). but bios can still change the function of each of these pins to gpio mode by programming the individual bits in gpio_use_selx register. ? bits in gpio_use_selx register enable gpio[n] (where n is the bit number) to be used as a gpio, rather than for the alternative function. pin is used as gpio when the individual bit in gpio_use_selx register is set, otherwise used as alternative function. example: software sets bit 2 in this register to enable gpio[2] (instead of using that signal for pirq[e]#). ? if gpio[n] does not exist, then the bit in gpio_use_selx register is always read as 0 and writes have no effect. example: bit 22 in gpio_use_sel1 is not supported because there is no corresponding gpio[22]. ? gpio pins [0:1, 6:10, 12:15, 48] do not have an alternative function. ? gpio pins can not generate irq interrupt when etr3.gpio_irq_strap_sts = 0. ? when configured to irq mode, the pin direction of the relevant pins are set to ?input? by gpio logic. ich6 compatibility is expected when the gpios are in gpio mode. ? when configured to gpio mode, the muxing logic presents the inactive state to alternate mode logic that uses the pin as an input. ? after a full reset (rsmrst#), all multiplexed signals in the resume and core wells are configured as gpio rather than their alternative function.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 804 order number: 320066-003us table 22-1. gpio pin?s alternative function gpio pins gpio mode capability default pin direction (gpio mode) default level driven out ( gpio mode) alternative function interrupt capability pin direction when in alternativ e mode smi#/sci irq wake event 1 : 0 input only input n/a none yes no no n/a 2 input only input n/a pirqe# yes yes-pirq no input 3 input only input n/a pirqf# yes yes-pirq no input 4 input only input n/a pirqg# yes yes-pirq no input 5 input only input n/a pirqh# yes yes-pirq no input 7 : 6 input only input n/a none yes no no n/a 11 : 8 input only input n/a none yes no yes n/a 13 : 12 input only input n/a none yes no no n/a 15 : 14 input only input n/a none yes no yes n/a 16 output only output high irq[24] no yes no input 17 output only output high irq[25] no yes no input 18 output only output high irq[36] no yes no input 19 output only output high irq[37] no yes no input 20 output only output high irq[26] no yes no input 21 output only output high irq[27] no yes no input 22 not implemented n/a n/a n/a n/a n/a n/a n/a 23 output only output low irq[28] no yes no input 24 i/o output high irq[29] no yes no input 25 i/o output high irq[38] no yes no input 26 input only input n/a sata no no no input 27 i/o output high irq[39] no yes no input 28 i/o output high irq[30] no yes no input 29 input only input n/a sata no no no input 30 input only input n/a irq[31] no yes no input 31 input only input n/a irq[32] no yes no input 32 not implemented n/a n/a n/a n/a n/a n/a n/a 33 i/o output high irq[33] no yes no input 34 i/o output high irq[34] no yes no input 39 : 35 not implemented n/a n/a n/a n/a n/a n/a n/a 40 input only input n/a irq[35] no yes no input 41 input only input n/a ldreq1 no no no input 47 : 42 not implemented n/a n/a n/a n/a n/a n/a n/a 48 output only output high none no no no n/a 49 not implemented n/a n/a n/a n/a n/a n/a n/a 63 : 50 not implemented n/a n/a n/a n/a n/a n/a n/a
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 805 intel ? ep80579 integrated processor 22.1.1 gpio summary table some gpios exist in the resume power plane. care must be taken to make sure gpio signals are not driven high into powered-down planes. some gpios may be connected to pins on devices that exist in the core well. if these gpios are outputs, there is a danger that a loss of core power (pwrok low) or a power button override event results incmi driving a pin to a logic ?1? to another device that is powered down. the following table summarizes the gpios. table 22-2. gpio summary table (sheet 1 of 2) gpio# powerwell muxed gpio_use_sel gp_io_sel gp_lvl gpo_blink gpi_inv 0 core no always 1 always 1 always 0 always 0 rw ? d=0 1 core no always 1 always 1 always 0 always 0 rw ? d=0 2:5 core yes 1 when gpio, 0 when pirq[e-h]# always 1 always 0 always 0 rw ? d=0 6 core no always 1 always 1 always 0 always 0 rw ? d=0 7 core no always 1 always 1 always 0 always 0 rw ? d=0 8 resume no always 1 always 1 always 0 always 0 rw ? d=0 9 resume no always 1 always 1 always 0 always 0 rw ? d=0 10 resume no always 1 always 1 always 0 always 0 rw ? d=0 11 resume yes rw ? d=0 always 1 always 0 always 0 rw ? d=0 12 core no always 1 always 1 always 0 always 0 rw ? d=0 13 core no always 1 always 1 always 0 always 0 rw ? d=0 14 resume no always 1 always 1 always 0 always 0 rw ? d=0 15 resume no always 1 always 1 always 0 always 0 rw ? d=0 16 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=1 always 0 always 0 17 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=1 always 0 always 0 18 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=1 rw ? d=1 always 0 19 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=1 rw ? d=0 always 0 20 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=1 always 0 always 0 21 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=1 always 0 always 0 22 unimplemented always 0 always 0 reserved 0 always 0 reserved 0 23 core yes 1 when gpio, 0 when irq 0 when gpio, 1 when irq rw ? d=0 always 0 always 0 24 resume yes 1 when gpio, 0 when irq 1 when irq, 0/1 when gpio rw ? d=1 always 0 always 0 25 resume yes 1 when gpio, 0 when irq 1 when irq, 0/1 when gpio rw ? d=1 rw ? d=0 always 0 26 core yes rw ? d=0 always 1 always 1 always 0 always 0
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 806 order number: 320066-003us notes: 1. n/a - not applicable, since the relevant registers bit do not exist for these gpio. 2. reserved - the bit access type may be rw but it is a reserved bit. 3. rw ? d=1: the bit access type is rw; default value is 1. 22.2 general purpose i/o-mapped configuration register details the control for the general purpose i/o signals is handled through separate 64-byte i/ o space. the general purpose i/o configuration registers are mapped into i/o space using register gba in the pci configuration space for device 31, function 0 (see section 19.2.2.3, ?offset 48h: gba: gpio base address register? on page 740 ). note: for the following registers, if a bit is allocated for a gpio that doesn?t exist, unless otherwise indicated, the bit always reads 0 and values written to that bit have no effect. 27:28 resume yes 1 when gpio, 0 when irq 1 when irq, 0/1 when gpio rw ? d=1 rw ? d=0 always 0 29 core yes rw ? d = 0 always 1 always 1 always 0 always 0 30:31 core yes 1 when gpio, 0 when irq always 1 always 1 always 0 always 0 32 unimplemented always 0 reserved 0 reserved 0 n/a n/a 33:34 core yes 1 when gpio, 0 when irq 1 when irq, 0/1 when gpio rw ? d=1 n/a n/a 35:39 unimplemented always 0 always 0 always 0 n/a n/a 40 core yes 1 when gpio, 0 when irq always 1 always 0 n/a n/a 41 core yes rw ? d = 0 always 1 always 1 n/a n/a 42:47 unimplemented always 0 always 0 always 0 n/a n/a 48 core no always 1 always 0 rw ? d=1 n/a n/a 49 unimplemented always 0 always 0 always 0 n/a n/a 50:63 unimplemented always 0 always 0 always 0 n/a n/a table 22-2. gpio summary table (sheet 2 of 2) gpio# powerwell muxed gpio_use_sel gp_io_sel gp_lvl gpo_blink gpi_inv table 22-3. bus 0, device 31, function 0: summary of general purpose i/o configuration registers mapped through gba bar io bar (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: gpio_use_sel1 - gpio use select 1 {31:0} register? on page 807 variable 04h 07h ?offset 04h: gp_io_sel1 - gpio input/output select 1 {31:0} register? on page 808 e400ffffh 0ch 0fh ?offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register? on page 809 ff3f0000h 18h 1bh ?offset 18h: gpo_blink - gpio blink enable register? on page 810 00040000h 2ch 2fh ?offset 2ch: gpi_inv - gpio signal invert register? on page 812 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 807 intel ? ep80579 integrated processor 22.2.1 register descriptions note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). 22.2.1.1 offset 00h: gpio_use_sel1 -gpio use select 1 {31:0} register 30h 33h ?offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register? on page 813 variable 34h 37h ?offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register? on page 813 00000300h 38h 3bh ?offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register? on page 814 00030207h table 22-3. bus 0, device 31, function 0: summary of general purpose i/o configuration registers mapped through gba bar io bar (sheet 2 of 2) offset start offset end register id - description default value table 22-4. offset 00h: gpio_use_sel1 - gpio use select 1 {31:0} register description: this register is used to select between gpio and alternative functions on gpio[31:0] view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 00h 03h size: 32 bit default: variable power well: core a a. core for 0:7, 16:21, 23; resume for 8:15, 24:31. bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gpio_use_sel enables gpio[n] (where n is the bit number) to be used as a gpio, rather than for the alternative function. 1 = signal used as gpio (or unmuxed). 0 = signal used as alternative function. ? bit access is always ro and returns 0 for bit[22] since there is no gpio pin[22]. ? bit access is always ro and returns 1 for bit[0:1, 6:10, 12:15] since there is no alternative function for gpio pins[0:1, 6:10, 12:15]. ? bit reset value is 0000_f7c3h when siu2_txd is strapped low on the rising edge of pwrok, else dbbff7c3h. ?see section 22.1, ?overview? on page 803 for more details. ?see table 22-1 for list of alternate functions. variable rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 808 order number: 320066-003us 22.2.1.2 offset 04h: gp_io_sel1 - gpio input/output select 1 {31:0} register table 22-5. offset 04h: gp_io_sel1 - gpio input/output select 1 {31:0} register description: this register allows setting of input/output direction of the gpio pins 31-0 view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 04h 07h size: 32 bit default: e400ffffh power well: core a a. core for 0:7, 16:21, 23; resume for 8:15, 24:31. bit range bit acronym bit description sticky bit reset value bit access 31 : 29 gpi_31_29 always 1. the gpi pins are always inputs. 111b ro 28 : 27 gp_io_sel_28_ 27 ? input when in irq mode. i/o when in gpio mode. 0 = the gpio signal is programmed as an output. 1 = the corresponding gpio signal (if enabled in table 22-4, ?offset 00h: gpio_use_sel1 - gpio use select 1 {31:0} register? on page 807 ) is programmed as an input. 00b rw 26 gpi_26 always 1. the gpi pins are always inputs. 1b ro 25 : 24 gp_io_sel_25_ 24 ? input when in irq mode. i/o when in gpio mode. 0 = the gpio mode signal is programmed as an output. 1 = the corresponding gpio mode signal (if enabled in table 22-4, ?offset 00h: gpio_use_sel1 - gpio use select 1 {31:0} register? on page 807 ) is programmed as an input. 00b rw 23 gp_io_23 this gpio pin is output, when in gpio mode (reports 0h). input when used as irq (reports 1h) 0h ro 22 reserved reserved. no corresponding gpio. 0h ro 21 : 16 gp_io_21_16 these gpio pins are outputs, when in gpio mode (reports 00h). input when used as irq (reports 3fh) 00h ro 15 : 00 gpi_15_0 always 1. the gpi pins are always inputs. ffffh ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 809 intel ? ep80579 integrated processor 22.2.1.3 offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register table 22-6. offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register (sheet 1 of 2) description: this register allows reading of the current gpio bit valu es for gpio pins 31-0 when input, and writing the value when output. view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 0ch 0fh size: 32 bit default: ff3f0000h power well: core a bit range bit acronym bit description sticky bit reset value bit access 31 : 29 gp_lvl_31_29 these bits correspond to input-only gpio in the core well. the corresponding gp_lvl bit reflects the state of the input signal. writes to these bits have no effect. 0 = low 1 = high these bits correspond to gpio that are in the core well and are reset to their native function by rsmrst#. 111b ro 28 : 27 gp_lvl_27_28 if gpio[n] is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. if gpio[n] is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal. writes have no effect. 0 = low 1 = high these bits correspond to gpio that are in the resume well and are reset to their native function by rsmrst# and by a writing to the cf9h register. 11b rw 26 gp_lvl_26 this bit corresponds to input-only gpi in the core well. the corresponding gp_lvl bit reflects the state of the input signal. writes to this bit have no effect. 0 = low 1 = high this bit corresponds to a gpi that is in the core well and is reset to its native function by rsmrst#. 1b ro 25 : 24 gp_lvl_25_24 if gpio[n] is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. if gpio[n] is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal. writes have no effect. 0 = low 1 = high these bits correspond to gpio that are in the resume well and are reset to their native function by rsmrst# and by a writing to the cf9h register. 11b rw 23 gp_lvl_23 the bit can be updated by software to drive a high or low value on the output pin when used as gpio function. 0 = low 1 = high the corresponding gpio pin is an input when used as irq. this bit correspond to gpio that is in the core well and is reset to its native function by pltrst#. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 810 order number: 320066-003us 22.2.1.4 offset 18h: gpo_blink - gpio blink enable register 22 reserved reserved. no corresponding gpio. 0h rw 21 : 16 gp_lvl_21_16 these bits can be updated by software to drive a high or low value on the output pin when used as gpio functions. 0 = low 1 = high the corresponding gpio pins are input when used as irq. these bits correspond to gpios that are in the core well and are reset to their native function by pltrst#. 3fh rw 15 : 00 reserved reserved. 0000h ro a. core for 0:7, 16:21, 23; resume for 8:15, 24:31. table 22-7. offset 18h: gpo_blink - gpio blink enable register (sheet 1 of 2) description: view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 18h 1bh size: 32 bit default: 00040000h power well: core a bit range bit acronym bit description sticky bit reset value bit access 31 :29 reserved reserved. 0h ro 28 : 27 gpo_blink_28 _27 the setting of this bit has no effect if the corresponding gpio signal is programmed as an input. 0 = the corresponding gpio functions normally. 1 = if the corresponding gpio is programmed as an output, the output signal blinks at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. the usage model for a blinking output is to control an led. this value does not need to have exactly one second granularity, but must be close. the value of the corresponding gp_lvl bit remains unchanged during the blink process, and does not effect the blink in any way. the gp_lvl bit is not altered when programmed to blink. it remains at its previous value. these bits correspond to gpio in the resume well and are reset to their native function by rsmrst# or a write to the cf9h register or any other pltrst# 00b rw 26 reserved reserved. 0h ro table 22-6. offset 0ch: gp_lvl1 - gpio level 1 for input or output {31:0} register (sheet 2 of 2) description: this register allows reading of the current gpio bit valu es for gpio pins 31-0 when input, and writing the value when output. view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 0ch 0fh size: 32 bit default: ff3f0000h power well: core a bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 811 intel ? ep80579 integrated processor 25 gpo_blink_25 the setting of this bit has no effect if the corresponding gpio signal is programmed as an input. 0 = the corresponding gpio functions normally. 1 = if the corresponding gpio is programmed as an output, the output signal blinks at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. the usage model for a blinking output is to control an led. this value does not need to have exactly one second granularity, but must be close. the value of the corresponding gp_lvl bit remains unchanged during the blink process, and does not effect the blink in any way. the gp_lvl bit is not altered when programmed to blink. it remains at its previous value. these bits correspond to gpio in the resume well and are reset to their native function by rsmrst# or a write to the cf9h register or any other pltrst#. 0b rw 24 :20 reserved reserved 0h ro 19 : 18 gpo_blink_19 _18 the setting of this bit has no effect if the corresponding gpio signal is programmed as an input. 0 = the corresponding gpio functions normally. 1 = if the corresponding gpio is programmed as an output, the output signal blinks at a rate of approximately once per second. the high and low times are approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. the usage model for a blinking output is to control an led. this value does not need to have exactly one second granularity, but must be close. the value of the corresponding gp_lvl bit remains unchanged during the blink process, and does not effect the blink in any way. the gp_lvl bit is not altered when programmed to blink. it remains at its previous value. these bits correspond to gpio in the core well and are reset to their native function by pltrst#. 01b rw 17 :00 reserved reserved. 0h ro a. core for 0:7, 16:21, 23; resume for 8:15, 24:31. table 22-7. offset 18h: gpo_blink - gpio blink enable register (sheet 2 of 2) description: view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 18h 1bh size: 32 bit default: 00040000h power well: core a bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 812 order number: 320066-003us 22.2.1.5 offset 2ch: gpi_inv - gpio signal invert register table 22-8. offset 2ch: gpi_inv - gpio signal invert register description: this register allows gpio inputs for gpio pins 31-0 to be inverted. view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 2ch 2fh size: 32 bit default: 00000000h power well: core a a. core for 0:7, 16:21, 23; resume for 8:15, 24:31. bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved 00h ro 15 : 14 gpi_inv_15_14 input inversion: these bits only have effect if the corresponding gpio is used as an input. this is used to allow active-low and active-high inputs to cause smi# or sci. 0 = no bit is inverted. 1 = the corresponding data value in the gp_lvl bit is inverted. these bits correspond to gpi in the resume well and are reset to their native function by rsmrst# or a write to the cf9h register or any other pltrst#. for triggering requirements, see section 22.3.2, ?triggering? on page 815 . the setting of these bits have no effect if the corresponding gpio is programmed as an output. 00b rw 13 : 12 gpi_inv_13_12 input inversion : these bits only has effect if the corresponding gpio is used as an input. this is used to allow active-low and active-high inputs to cause smi# or sci. 0 = no bit is inverted. 1 = the corresponding data value in the gp_lvl bit is inverted. these bits correspond to gpi in the core well and are reset to their native function by rsmrst#. 00b rw 11 : 08 gpi_inv_11_8 input inversion: these bits only have effect if the corresponding gpio is used as an input. this is used to allow active-low and active-high inputs to cause smi# or sci. 0 = no bit is inverted. 1 = the corresponding data value in the gp_lvl bit is inverted. these bits correspond to gpi in the resume well and are reset to their native function by rsmrst# or a write to the cf9h register or any other pltrst#. for triggering requirements, see section 22.3.2, ?triggering? on page 815 . the setting of these bits have no effect if the corresponding gpio is programmed as an output. 0h rw 07 : 00 gpi_inv_7_0 input inversion : this bit only has effect if the corresponding gpio is used as an input. this is used to allow active-low and active-high inputs to cause smi# or sci. 0 = no bit is inverted. 1 = the corresponding data value in the gp_lvl bit is inverted. these bits correspond to gpi in the core well and are reset to their native function by pltrst#. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 813 intel ? ep80579 integrated processor 22.2.1.6 offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register 22.2.1.7 offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register table 22-9. offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register description: this register is used to select between gpio and alternative functions on gpio[63:32] view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 30h 33h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gpio_use_sel enables gpio[n] (where n is the bit number) to be used as a gpio, rather than for the alternative function. 1 = signal used as gpio (or unmuxed). 0 = signal used as alternative function. ? bit access is always ro for bits[03:07, 10:15, 18:31] and returns 0 since gpio pins[35:39, 42:47, 50:63] do not exist. ? bit access is always ro for bit[16] and returns 1 since there is no alternative function for gpio[48]. ? bit reset value is 0001_0000h when siu2_txd is strapped low on the rising edge of pwrok, else 0001_0106h. ?see section 22.1, ?overview? on page 803 for more details. ?see table , ?? on page 804 for list of alternate functions. variable rw table 22-10. offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register (sheet 1 of 2) description: this register allows setting of input/output direction of the gpio pins 49-32 view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 34h 37h size: 32 bit default: 00000300h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 17 gp_io_sel_63_ 49 always 0. these pins are always outputs. 0h ro 16 : 16 gp_io_sel_48 always 0. these pins are always outputs. 0h ro 15 : 10 gp_io_sel_47_ 42 always 0. no corresponding gpio. 0h ro 09 : 08 gp_io_sel_41_ 40 always 1. these pins are always inputs. 11b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 814 order number: 320066-003us 22.2.1.8 offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register 07 : 03 gp_io_sel_39_ 35 always 0. no corresponding gpio. 0h ro 02 : 01 gp_io_sel_34_ 33 ? input when in irq mode. i/o when in gpio mode. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal is programmed as an input (if enabled in table 22-9, ?offset 30h: gpio_use_sel2 - gpio use select 2 {63:32} register? on page 813 ). 00b rw 00 reserved reserved. no corresponding gpio. 0b rw table 22-11. offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register (sheet 1 of 2) description: this register allows reading of the current gpio bit valu es for gpio pins 31-0 when input, and writing the value when output. view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 38h 3bh size: 32 bit default: 00030207h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 17 reserved read-only 0. 0h 16 : 16 gp_lvl_48 the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. 0 = low 1 = high since these bits correspond to gpio that are in the processor i/o and core well, respectively, these bits are reset to their native function by pltrst#. 1b rw 15 : 10 reserved read-only 0. 0h 09 : 08 gp_lvl_41_40 the corresponding gp_lvl[n] bit reflects the state of the input signal. writes have no effect. 0 = low 1 = high since these bits correspond to gpio that are in the core well they are reset to their native function by pltrst#. 10b ro table 22-10. offset 34h: gp_io_sel2 - gpio input/output select 2 {63:32} register (sheet 2 of 2) description: this register allows setting of input/output direction of the gpio pins 49-32 view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 34h 37h size: 32 bit default: 00000300h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 815 intel ? ep80579 integrated processor 22.3 additional gpio theory of operation 22.3.1 smi# and sci routing the routing bits for gpio[0:15] allow an input to be routed to smi# or sci, or neither. see chapter 40, ?power management? for the routing register. a bit can be routed to either an smi# or an sci, but not both. 22.3.2 triggering gpio[0:15] have ?sticky? bits on the input. see chapter 40, ?power management? for the gpe0_sts register and the alt_gpi_smi_sts register. as long as the signal goes active for at least two clocks (pci clock while in s0-s1 state, rtc clock while in s3-s5 state),cmi keeps the sticky status bit active. the active level (high or low) can be selected via the gp_inv register. if the system is in an s0 or s1-d state, the gpi are sampled at 33 mhz, so the signal only needs to be active for about 60 ns to be latched. in s3,-s5 states, the gpi are sampled at 32.768 khz, and thus must be active for at least 61 s to be latched. note: gpis that are in the core well are not capable of waking the system from sleep states where the core well is not powered. if the input signal is still active when the latch is cleared, it is again set (another edge is not required). this makes these signals ?level? triggered inputs. 07 : 03 reserved read-only 0. 0h 02 : 01 gp_lvl_34_33 if gpio[n] is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. if gpio[n] is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low). writes have no effect. 0 = low 1 = high since these bits correspond to gpio that are in the core well and are reset to their native function by pltrst#. 11b rw 00 reserved reserved. no corresponding gpio. 1b rw table 22-11. offset 38h: gp_lvl2 - gpio level for input or output 2 {63:32} register (sheet 2 of 2) description: this register allows reading of the current gpio bit valu es for gpio pins 31-0 when input, and writing the value when output. view: pci bar: gba(io) bus:device:function: 0:31:0 offset start: offset end: 38h 3bh size: 32 bit default: 00030207h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 816 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 817 intel ? ep80579 integrated processor 23.0 sata: bus 0, device 31, function 2 23.1 sata pci configuration registers all of the sata configuration registers are in the core well. all registers not mentioned are reserved. start end functionality described 00 3f pci header 40 5f sff-8038i configuration (legacy bus master ide) 70 7f pci power management capability pointer 80 8f message signaled interrupt capability pointer 90 a7 additional configuration (test modes, etc.) a8 af serial ata capability pointer b0 ff additional configuration (test modes, etc.) table 23-1. bus 0, device 31, function 2: summary of sata controller pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 03h ?offset 00h: id ? identifiers register? on page 819 variable 04h 05h ?offset 04h: cmd - command register? on page 819 0000h 06h 07h ?offset 06h: sts - device status register? on page 820 02b0h 08h 08h ?offset 08h: rid - revision id register? on page 821 variable 0ah 0bh ?offset 0ah: cc - class code register? on page 823 variable 0dh 0dh ?offset 0dh: mlt ? master latency timer register? on page 823 00h 10h 13h ?offset 10h: pcmdba ? primary command block base address register? on page 824 00000001h 14h 17h ?offset 14h: pctlba ? primary control block base address register? on page 824 00000001h 18h 1bh ?offset 18h: scmdba ? secondary command block base address register? on page 825 00000001h 1ch 1fh ?offset 1ch: sctlba ? secondary control block base address register? on page 825 00000001h 20h 23h ?offset 20h: lbar ? legacy bus master base address register when scc is sata with ahci pi? on page 826 00000001h 24h 27h ?offset 24h: abar ? ahci base address register? on page 826 00000000h 2ch 2fh ?offset 2ch: ss - sub system identifiers register? on page 827 00000000h 34h 34h ?offset 34h: cap ? capabilities pointer register? on page 827 80h 3ch 3dh ?offset 3ch: intr - interrupt information register? on page 828 variable
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 818 order number: 320066-003us 40h 41h ?offset 40h: ptim ? primary timing register? on page 829 0000h 44h 44h ?offset 44h: d1tim ? device 1 ide timing register? on page 830 00h 48h 48h ?offset 48h: syncc ? synchronous dma control register? on page 831 00h 4ah 4bh ?offset 4ah: synctim ? synchronous dma timing register? on page 832 0000h 54h 57h ?offset 54h: iioc ? ide i/o configuration register? on page 833 00000000h 70h 71h ?offset 70h: pid ? pci power management capability id register? on page 834 variable 72h 73h ?offset 72h: pc ? pci power management capabilities register? on page 834 4002h 74h 77h ?offset 74h: pmcs ? pci power management control and status register? on page 835 0000h 80h 81h ?offset 80h: mid ? message signaled interrupt identifiers register? on page 836 7005h 82h 83h ?offset 82h: mc ? message signaled interrupt message control register? on page 837 0000h 84h 87h ?offset 84h: ma ? message signaled interrupt message address register? on page 838 00000000h 88h 89h ?offset 88h: md ? message signaled interrupt message data register? on page 838 0000h 90h 90h ?offset 90h: map ? port mapping register? on page 839 00h 92h 92h ?offset 92h: pcs ? port control and status register? on page 840 00h a8h abh ?offset a8h: satacr0 ? serial ata capability register 0? on page 841 00100012h ach afh ?offset ach: satacr1 ? serial ata capability register 1? on page 841 00000048h c0h c0h ?offset c0h: atc ? apm trapping control register? on page 842 00h c4h c4h ?offset c4h: ats ? atm trapping status register? on page 843 00h d0h d3h ?offset d0h: sp ? scratch pad register? on page 844 00000000h e0h e3h ?offset e0h: bfcs ? bist fis control/status register? on page 844 00000000h e4h e7h ?offset e4h: bftd1 ? bist fis transmit data 1 register? on page 846 00000000h e8h ebh ?offset e8h: bftd2 ? bist fis transmit data 2 register? on page 846 0h f8h fbh ?offset f8h: manid ? manufacturing id register? on page 847 variable table 23-1. bus 0, device 31, function 2: summary of sata controller pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 819 intel ? ep80579 integrated processor 23.1.1 pci header the default values are defined with an h for hex, a b for binary, or 00 for zero. if there is not a a letter showing the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero va lues and are read only. writes to reserved locations may cause system failure and unpredictable results. note: reserved bits are read only. 23.1.1.1 offset 00h: id - identifiers register 23.1.1.2 offset 04h: cmd - command register table 23-2. offset 00h: id ? identifiers register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 00h 03h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 did device id (did): the value reported in this field is in the range between 5028-502bh. the specific value is dependent on map.sms, map.mv. variable ro 15 : 00 vid vendor id (vid): 16-bit field which indicates the company vendor as intel. 8086h ro table 23-3. offset 04h: cmd - command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h ro 10 id interrupt disable (id): this disables pin-based intx# interrupts. this bit has no effect on msi operation. when set, internal intx# messages will not be generated. when cleared, internal intx# messages are generated if there is an interrupt and msi is not enabled. 0h rw 09 fbe fast back-to-back enable (fbe): reserved. 0h ro 08 see serr# enable (see): reserved. the sata controller never generates an serr#. 0h ro 07 wcc wait cycle enable (wcc): reserved. 0h ro 06 pee parity error response enable (pee): when set, the sata controller will corrupt th e outbound data fis crc if a forwarded data parity error is indicated. 0h rw 05 vga vga palette snooping enable (vga): reserved 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 820 order number: 320066-003us 23.1.1.3 offset 06h: sts - device status register 04 mwie memory write and invalidate enable (mwie): reserved 0h ro 03 sce special cycle enable (sce): reserved 0h ro 02 bme bus master enable (bme): controls the sata controller?s ability to act as a master for data transfers. this bit does not impact the generation of completions for split transaction commands. 0h rw 01 mse memory space enable (mse): controls access to the sata controller?s target memory space (for ahci).? 0h rw 00 iose i/o space enable (iose): controls access to the sata controller?s target i/o space. 0h rw table 23-4. offset 06h: sts - device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 06h 07h size: 16 bit default: 02b0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error (dpe): set when the sata controller detects a parity error on its interface. 0h rwc 14 sse signaled system error (sse): the sata controller will never generate an serr#. 0h ro 13 rma received master-abort status (rma): set when the sata controller receives a master abort to a cycle it generated. 0h rwc 12 rta received target-abort status (rta): set when the sata controller receives a target abort to a cycle it generated. 0h rwc 11 sta signaled target-abort status (sta): reserved. the sata controller will never generate a target abort. 0h ro 10 : 09 devt devsel# timing status (devt): controls the device select time for the sata controller?s pci interface. 01h ro 08 dpd master data parity error detected (dpd): set when the sata controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. this bit can only be set on read completions received from the backbone where there is a parity error. 0h rwc 07 reserved fast back-to-back capable: reserved 1h ro 06 reserved reserved 0h ro 05 c66 66 mhz capable 1h ro table 23-3. offset 04h: cmd - command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 821 intel ? ep80579 integrated processor 23.1.1.4 offset 08h: rid - revision id register 04 cl capabilities list (cl): indicates the presence of a capabilities list. the minimum requirement for the capabilities list must be pci power management for the sata controller. 1h ro 03 is interrupt status (is): reflects the state of intx# messages. this bit is set when the interrupt is to be asserted. this bit is a 0 after the interrupt is cleared (independent of the state of cmd.id). 0h ro 02 : 00 reserved reserved 0h ro table 23-5. offset 08h: rid - revision id register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision id (rid): indicates stepping of the host controller hardware. this register follows the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 23-4. offset 06h: sts - device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 06h 07h size: 16 bit default: 02b0h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 822 order number: 320066-003us 23.1.1.5 pi - programming interface register 23.1.1.5.1 programming interface when cc.scc = ?01h? table 23-7. programming interface when cc.scc = ?01h? table 23-6. programming interface, did and cc.scc register value definitions input parameters resulting values map.sms: 00 - select ide 01 - select ahci 10 - reserved 11 - reserved map.mv cc.scc pi did 00b 00b 01h (ide) 8ah a (rw) a. pi register bits 2 and 0 are write-able at all times when map.mv=00h (so the value of this field may be 8ah, 8bh, 8dh, or 8fh), although the write only affects the sata controller's operation when cc.scc is 01h. if pi is written while cc.scc is 04h, the value shown will not be 8ah when cc.scc is changed from 04h to 01h, but rather the value of the last write to pi. bios must always check and set pi to the desired mode of operation (legacy or native) when cc.scc is 01h. 5028h 01b 00b 06h (sata) 01h (ro) 5029h 10b 00b illegal b b. "illegal" means that sw must not program this combination otherwise the results are undefined. illegal illegal 11b 00b illegal illegal illegal bit type reset description 7 ro 1 indicates the sata controller supports bus master operation. 6:4 ro 0 reserved 3ro1 secondary mode native capable (snc): indicates that the secondary controller supports both legacy and native modes. 2rw0 secondary mode native enable (sne): determines the mode that the secondary channel is operating in. ?0? corresponds to 'compatibility', ?1? means pci native. if this bit is set by sw, then the pne bit must also be set by sw. while in theory these bits can be programmed separately, such a configuration is not supported by today?s software and is not supported by this hardware. 1ro1 primary mode native capable (pnc): indicates that the primary controller supports both legacy and native modes. 0rw0 primary mode native enable (pne): determines the mode that the primary channel is operating in. ?0? corresponds to 'compatibility', ?1? means pci native. if this bit is set by sw, then the sne bit must also be set by sw. while in theory these bits can be programmed separately, such a configuration is not supported by today?s software and is not supported by this hardware.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 823 intel ? ep80579 integrated processor 23.1.1.5.2 programming interface when cc.scc = ?06h? table 23-8. programming interface when cc.scc = ?06h? 23.1.1.6 offset 0ah: cc - class code register 23.1.1.7 offset 0dh: mlt ? master latency timer register 23.1.1.8 offset 10h: pcmdba ? primary command block base address register this 8-byte i/o space is used in native mode for the primary controller?s command block. bit type reset description 07:00 ro 01h interface (if): indicates the sata controller is ahci 1.0 compliant. internally, under this condition, the sata controller is in native mode and its i/ o spaces are only accessible through the i/o bars. table 23-9. offset 0ah: cc - class code register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 0ah 0bh size: 16 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 bcc base class code (bcc): indicates that this is a mass storage device. 01h ro 07 : 00 scc sub class code (scc): the value reported in this field is dependent on map.sms, map.mv, . see the table in section 48.1.1.5. variable ro table 23-10. offset 0dh: mlt ? master latency timer register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mlt master latency timer (mlt): this register has no meaning as the controller lives on nsi. 00h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 824 order number: 320066-003us 23.1.1.9 offset 14h: pctlba ? primary control block base address register this 4-byte i/o space is used in native mode for the primary controller?s control block. 23.1.1.10 offset 18h: scmdba ? secondary command block base address register this 8-byte i/o space is used in native mode for the secondary controller?s command block. table 23-11. offset 10h: pcmdba ? primary command block base address register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 10h 13h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro 15 : 03 bar base address (bar): base address of the i/o space (8 consecutive i/o locations). 0h rw 02 : 01 reserved reserved 0h ro 00 rte resource type indicator (rte): indicates a request for io space. 1h ro table 23-12. offset 14h: pctlba ? primary control block base address register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 14h 17h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro 15 : 02 bar base address (bar): base address of the i/o space (4 consecutive i/o locations). 0h rw 01 reserved reserved 0h ro 00 rte resource type indicator (rte): indicates a request for io space. 1h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 825 intel ? ep80579 integrated processor 23.1.1.11 offset 1ch: sctlba ? secondary control block base address register this 4-byte i/o space is used in native mode for the secondary controller?s control block. 23.1.1.12 offset 20h: lbar ? legacy bus master base address register this bar is used to allocate i/o space for the sff-8038i mode of operation (aka bus master ide) and ahci index/data pair. table 23-13. offset 18h: scmdba ? secondary command block base address register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 18h 1bh size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro 15 : 03 bar base address (bar): base address of the i/o space (8 consecutive i/o locations). 0h rw 02 : 01 reserved reserved 0h ro 00 rte resource type indicator (rte): indicates a request for io space 1h ro table 23-14. offset 1ch: sctlba ? secondary control block base address register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 1ch 1fh size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro 15 : 02 bar base address (bar): base address of the i/o space (4 consecutive i/o locations). 0h rw 01 reserved reserved 0h ro 00 rte resource type indicator (rte): indicates a request for io space. 1h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 826 order number: 320066-003us 23.1.1.13 offset 24h: abar ? ahci base address register this register allocates space for the memory registers defined in section 1.3. note that hardware only supports non-combined mode. note that this register must be programmed to value of 0001_0000h or greater, otherwise memory cycles targeting the abar range may not accepted. table 23-15. offset 20h: lbar ? legacy bus master base address register when scc is sata with ahci pi description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 20h 23h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro 15 : 04 ba base address (ba): base address of the i/o space. ? note on bit 4: when cc.scc is 01h, bit 4 is rw, resulting in requesting 16b of i/o space. when cc.scc is not 01h, this bit is ro and reports 0, resulting in requesting 32b of i/o space. ? bits 15:5 are always rw with default value of 0. ? 0h rw 03 : 01 reserved reserved 0h ro 00 rte resource type indicator (rte): indicates a request for i/o space. 1h ro table 23-16. offset 24h: abar ? ahci base address register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 24h 27h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 ba base address (ba): base address of register memory space (aligned to 1 kb) 0h rw 09 : 04 reserved reserved 0h ro 03 pf prefetchable (pf): indicates that this range is not pre- fetchable 0h ro 02 : 01 tp type (tp): indicates that this range can be mapped anywhere in 32-bit address space 00h ro 00 rte resource type indicator (rte): indicates a request for register memory space. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 827 intel ? ep80579 integrated processor 23.1.1.14 offset 2ch: ss - sub system identifiers register this register is initialized to logic 0 by the assertion of pltrst#. this register can be written only once after pltrst# de-assertion. 23.1.1.15 offset 34h: cap ? capabilities pointer register table 23-17. offset 2ch: ss - sub system identifiers register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 2ch 2fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 ssid subsystem id (ssid): this is written by bios. no hardware action taken on this value. 0000h rwo 15 : 00 ssvid subsystem vendor id (ssvid): this is written by bios. no hardware action taken on this value. 0000h rwo table 23-18. offset 34h: cap ? capabilities pointer register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 34h 34h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp capability pointer (cp): if cc.scc=01h, then cap is set to offset 70h to indicate that the first capability pointer is the pci power management capability. if cc.scc is not set to 01h, then cap is set to offset 80h to indicate that the first capability pointer is the message signaled interrupt capability. 80h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 828 order number: 320066-003us 23.1.1.16 offset 3ch: intr - interrupt information register 23.1.2 additional sff-8038i configuration registers the following registers are necessary to implement as read/write bits in order to maintain software functionality for the sff-8038i mode of operation (a.k.a. bus master ide). they have no bearing on serial ata operation unless otherwise indicated, but are necessary to be read/write for legacy software capability. the default values are defined with an h for hex, a bi for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 23-19. offset 3ch: intr - interrupt information register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 3ch 3dh size: 16 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 ipin interrupt pin (ipin): this reflects the value of d31ip.sip in chipset configuration space. variable ro 07 : 00 iline interrupt line (iline): software written value to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. 00h rw start end symbol name 40 41 ptim primary ide timing 42 43 stim secondary ide timing 44 44 d1tim slave ide timing 48 48 syncc synchronous dma control register 4a 4b synctim synchronous dma timing register 54 57 iioc ide i/o configuration
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 829 intel ? ep80579 integrated processor 23.1.2.1 offset 40h: ptim ? primary timing register this controls the timings driven on the parallel cable. table 23-20. offset 40h: ptim ? primary timing register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 40h 41h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 de decode enable (de): enables the sata controller to decode the command blocks (1f0-1f7h for primary, 170- 177h for secondary or their native bar equivalents) and control block (3f6h for primary and 376h for secondary or their native bar equivalents). this bit still has functionality in sata ? if this bit is not set, the port that is mapped to this range will not be decoded. 0h rw 14 d1ste device 1 separate timing enable (d1ste): when cleared, both device 0 and device 1 use the same timings, as defined by bits 13:12 and bits 9:8 of this register. when set, device 0 uses these timings, but device 1 uses the timings from the ?slave timing? register at offset 44h. 0h rw 13 : 12 isp iordy sample point (isp): determines the number of 33 mhz clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 00h rw 11 : 10 reserved reserved 00h ro 09 : 08 rct recovery time (rct): the setting of these bits determines the minimum number of 33 mhz clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 00h rw 07 dte1 device 1 dma timing enable (dte1): when this bit is set, the fast timing mode is enabled for dma transfers only for this drive. pio transfers to the data port will run in compatible timing. 0h rw 06 ppe1 device 1 prefetch/posting enable (ppe1): when this bit is set, prefetch and posting to the ide data port is enabled for this drive. 0h rw 05 e1 device 1 iordy sample point enable (ie1): when this bit is set, iordy sampling will be enabled for this drive. when this bit is cleared, iordy sampling is disabled for this drive. 0h rw 04 tim1 device 1 fast timing bank (tim1): when cleared, accesses to the data port will use compatible timings for this drive. when set and bit 14 cleared, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when set and bit 14 set, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. 0h rw 03 dte0 device 0 dma timing enable (dte0): when this bit is set, the fast timing mode is enabled for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 830 order number: 320066-003us 23.1.2.2 stim ? secondary timing register see the above register description for primary ide timing. 23.1.2.3 offset 44h: d1tim ? device 1 ide timing register the values in this register are only valid if the ?separate timing enable? bit is set in the timing registers. bits 7:4 are used by device 1 on secondary if bit 14 of offset 42h is set, and bits 3:0 are used by device 1 on primary if bit 14 of offset 40h is set. 02 ppe0 device 0 prefetch/posting enable (ppe0): when this bit is set, prefetch and posting to the ide data port is enabled for this drive. 0h rw 01 ie0 device 0 iordy sample point enable (ie0): when this bit is set, iordy sampling will be enabled for this drive. when this bit is cleared, iordy sampling is disabled for this drive. 0h rw 00 timo device 0 fast timing bank (tim0): when cleared, accesses to the data port will use compatible timings for this drive. when set, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time 0h rw table 23-20. offset 40h: ptim ? primary timing register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 40h 41h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 23-21. offset 44h: d1tim ? device 1 ide timing register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 44h 44h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 sisp1 secondary device 1 iordy sample point (sisp1): determines the number of 33 mhz clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 831 intel ? ep80579 integrated processor 23.1.2.4 offset 48h: syncc ? synchronous dma control register 05 : 04 srct1 secondary device 1 recovery time (srct1): determines the minimum number of 33 mhz clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 00h rw 03 : 02 pisp1 primary device 1 iordy sample point (pisp1): same as bits 7:6, except for the primary device. 00h rw 01 : 00 prct1 primary device 1 recovery time (prct1): same as bits 5:4, except for the primary device. 00h rw table 23-22. offset 48h: syncc ? synchronous dma control register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 48h 48h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h ro 03 sdae1 secondary device 1 ataxx enable (sdae1): when set, enables ata33/66/100/133 timing modes for the secondary slave device. 0h rw 02 sdae0 secondary device 0 ataxx enable (sdae0): when set, enables ata33/66/100/133 timing modes for the secondary master device. 0h rw 01 pdae1 primary device 1 ataxx enable (pdae1): when set, enables ata33/66/100/133 timing modes for the primary slave device. 0h rw 00 pdae0 primary device 0 ataxx enable (pdae0): when set, enables ata33/66/100/133 timing modes for the primary master device. 0h rw table 23-21. offset 44h: d1tim ? device 1 ide timing register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 44h 44h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 832 order number: 320066-003us 23.1.2.5 offset 4ah: synctim ? synchronous dma timing register the ct and rp values for the ata_fast (100mb/s and 133 mb/s modes) are based on 133 mhz clock. the ct and rp values for the 66 mhz and 33 mhz modes are based on either a 66 mhz or 33 mhz clock. table 23-23. offset 4ah: synctim ? synchronous dma timing register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 4ah 4bh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 14 reserved reserved 0h ro 13 : 12 sct1 secondary device 1 cycle time (sct1): the setting of these bits determines the minimum write strobe cycle time (ct) and dmardy#-to-stop (rp) time. 00h rw 11 : 10 reserved reserved 0h ro 09 : 08 sct0 secondary device 0 cycle time (sct0): same definition as bits 13:12, except for device 0. 00h rw 07 : 06 reserved reserved 0h ro 05 : 04 pct1 primary device 1 cycle time (pct1): same definition as bits 13:12, except for primary device 1. 00h rw 03 : 02 reserved reserved 0h ro 01 : 00 pct0 primary device 0 cycle time (pct0): same definition as bits 13:12, except for primary device 0. 00h rw bits sbc[3] = 0 sbc[3] = 1 fsbce[3] = 1 ct rp ct rp ct rp 00 4 6 reserved reserved 01 3 5 3 8 3 16 10 2 4 2 8 reserved 11 reserved reserved reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 833 intel ? ep80579 integrated processor 23.1.2.6 offset 54h: iioc ? ide i/o configuration register table 23-24. offset 54h: iioc ? ide i/o configuration register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 54h 57h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 0h ro 23 : 20 sp2 scratchpad (sp2): no hardware action taken on these bits. 0h rw 19 : 18 ssm secondary signals mode (ssm): controls the secondary signals for swap bays. 00 = normal 01 = tri-state 10 = drive low 11 = reserved if buc.prs in chipset configuration space is ?1?, then the reset states of these bits will be ?01? (tri-state) instead of ?00? (normal). 00h rw 17 : 16 psm primary signals mode (psm): controls the primary signals for swap bays. 00 = normal 01 = tri-state 10 = drive low 11 = reserved if buc.prs in chipset configuration space is ?1?, then the reset states of these bits will be ?01? (tri-state) instead of ?00? (normal). 00h rw 15 : 12 fsbce fast synchronous base clock enable (fsbce): when set, enables fast ata modes. this overrides the state of the scb[3:0] bits in this register. 0h rw 11 reserved reserved 0h ro 10 reserved reserved 0h ro 09 : 08 reserved reserved ? these were the secondary and primary command posting enable bits. these do not exist when parallel ata is mapped as part of serial ata, because the command posting bar has been removed. 0h ro 07 : 04 sp1 scratchpad (sp1): no hardware action taken on these bits. 0h rw 03 : 00 sbc synchronous base clock (sbc): clock used to determine ct and rp timings for synchronous dma timings. ?0? = 33 mhz clock used, ?1? = 66 mhz clock used. bit 3 controls the secondary slave device, bit 2 controls the secondary master device, bit 1 controls the primary slave device, and bit 0 controls the primary master device. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 834 order number: 320066-003us 23.1.3 pci power management capabilities 23.1.3.1 offset 70h: offset 70h: pid ? pci power management capability id register the default values are defined with an h for hex, a bi for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. 23.1.3.2 offset 72h: pc ? pci power management capabilities register start end symbol name 70 71 pid pci power management capability id 72 73 pc pci power management capabilities 74 77 pmcs pci power management control and status table 23-25. offset 70h: pid ? pci po wer management capability id register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 70h 71h size: 16 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 next next capability (next): when cc.scc is 01h, this field will be 00h indicating this is the last item in the list. when cc.scc is not 01h, this field will be a8h pointing to the serial ata capability structure. variable ro 07 : 00 cid cap id (cid): indicates that this pointer is a pci power management. 01h ro table 23-26. offset 72h: pc ? pci po wer management capabilities register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 72h 73h size: 16 bit default: 4002h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_support indicates pme# can be generated from the d3 hot state in the sata controller. 01000b ro 10 d2_support the d2 state is not supported. 0h ro 09 d1_support the d1 state is not supported. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 835 intel ? ep80579 integrated processor 23.1.3.3 offset 74h: pmcs ? pci power management control and status register 08 : 06 aux_current pme# from d3 cold state is not supported, therefore this field is 000b. 000h ro 05 dsi device specific initialization (dsi): indicates that no device-specific initialization is required. 0h ro 04 reserved reserved 0h ro 03 pmec pme clock (pmec): indicates that pci clock is not required to generate pme#. 0h ro 02 : 00 vs version (vs): indicates support for revision 1.1 of the pci power management specification. 010b ro table 23-27. offset 74h: pmcs ? pci power management control and status register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 74h 77h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pmes pme status (pmes): this bit is set when a pme event is to be requested, and if this bit is set and pmee is set, a pme# will be generated. 0h rwc 14 : 09 reserved reserved ? sata controller does not implement the data register. 0h ro 08 pmee pme enable (pmee): when set, the sata controller generates pme# form d3 hot on a wake event. 0h rw 07 : 02 reserved reserved 0h ro 01 : 00 ps power state (ps): this field is used both to determine the current power state of the sata controller and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. if software attempts to write a ?10? or ?01? to these bits, the write will be ignored. 00h rw table 23-26. offset 72h: pc ? pci power management capabilities register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 72h 73h size: 16 bit default: 4002h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 836 order number: 320066-003us 23.1.4 message signaled interrupt capability the default values are defined with an h for hex, a bi for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. 23.1.4.1 offset 80h: mid ? message signaled interrupt identifiers register start end symbol name 80 81 mid message signaled interrupt capability id 82 83 mc message signaled interrupt message control 84 87 ma message signaled interrupt message address 88 89 md message signaled interrupt message data table 23-28. offset 80h: mid ? message signaled interrupt identifiers register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 80h 81h size: 16 bit default: 7005h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 next next pointer (next): indicates the next item in the list is the pci power management pointer. 70h ro 07 : 00 cid capability id (cid): capabilities id indicates msi. 05h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 837 intel ? ep80579 integrated processor 23.1.4.2 offset 82h: mc ? message signaled interrupt message control register table 23-29. offset 82h: mc ? message signaled interrupt message control register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 82h 83h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 08 reserved reserved 0h ro 07 c64 64 bit address capable (c64): capable of generating a 32-bit message only. 0h ro 06 : 04 mme multiple message enable (mme): when this field is cleared to ?000? (and msie is set), only a single msi message will be generated for all sata ports, and bits [15:0] of the message vector will be driven from md[15:0]. values ?011b? to ?111b? are reserved. if this field is set to one of these reserved values, the results are undefined. 000h rw 03 : 01 mmc multiple message capable (mmc): indicates the number of interrupt message supported by sata controller. 000: 1 msi capable 001: reserved010: reserved 100: reserved 000h rwo 00 msie msi enable (msie): if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. 0h rw mme value driven on msi memory write bits[15:2] bit[1] bit[0] 000 md[15:2] md[1] md[0] 001 reserved reserved reserved 010 reserved reserved reserved 011?111 reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 838 order number: 320066-003us 23.1.4.3 offset 84h: ma ? message signaled interrupt message address register 23.1.4.4 offset 88h: md ? message signaled interrupt message data register 23.1.5 additional conf iguration registers the default values are defined with an h for hex, a bi for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 23-30. offset 84h: ma ? message signaled interrupt message address register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 84h 87h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 02 addr address (addr): lower 32 bits of the system specified message address, always dword aligned. 0h rw 01 : 00 reserved reserved 00h ro table 23-31. offset 88h: md ? message signaled interrupt message data register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 88h 89h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 data data (data): this 16-bit field is programmed by system software if msi is enabled. its content is driven onto the lower word of the data bus of the msi memory write transaction. 0h rw start end symbol name 90 90 map port mapping register 92 92 pcs port control and status a8 ab satacr0 serial ata capability register 0 ac af satacr1 serial ata capability register 1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 839 intel ? ep80579 integrated processor 23.1.5.1 offset 90h: map ? port mapping register 23.1.5.2 offset 92h: pcs ? port control and status register this register is only used in systems that do not support ahci. in ahci enabled systems, bits[3:0] must always be set, and the status of the port is controlled through ahci memory space. c0 c0 atc apm trapping control c4 c4 ats apm trapping status d0 d3 sp scratch pad e0 e3 bfcs bist fis control/status e4 e7 bftd1 bist fis transmit data, dw1 e8 eb bftd2 bist fis transmit data, dw2 f8 fb manid manufacturer?s id table 23-32. offset 90h: map ? port mapping register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 90h 90h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 sms sata mode select (sms): sw programs these bits to control the mode in which the sata hba should operate: 00b = ide mode 01b = ahci mode 10b = reserved 11b = reserved notes: ? ide mode can be selected when ahci is enabled. ? "programming these bits with values that are illegal will result in indeterministic behavior by the hw. ? 00h rw 05 : 02 reserved reserved 0h ro 01 : 00 mv map value (mv): the value in the bits below indicate the address range the sata ports responds to. 00h ro bits mode primary secondary master master 00 non- combined port 0 port 1 01 reserved 10 reserved 11 reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 840 order number: 320066-003us table 23-33. offset 92h: pcs ? port control and status register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: 92h 92h size: 16 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0h rw 14 : 13 reserved reserved 0h ro 12 orm oob retry mode (orm): when cleared, the sata controller will not retry after an oob failure. when set, the sata controller will continue to retry after an oob failure until successful (infinite retry) 0h rw 11 : 08 reserved reserved 0h rwc 07 reserved reserved. 0h ro 06 reserved reserved. 0h ro 05 p1p port 1 present (p1p): same as p0p, except for port 1. 0h ro 04 p0p port 0 present (p0p): when set, the sata controller has detected the presence of a device on port 0. it may change at any time. this bit is cleared when the port is disabled via p0e. this bit is not cleared upon surprise removal of a device. 0h ro 03 reserved reserved. 0h ro 02 reserved reserved. 0h ro 01 p1e port 1 enabled (p1e): when set, the port is enabled. when cleared, the port is disabled. when enabled, the port can transition between the on, partial, and slumber states and can detect devices. when disabled, the port is in the ?off? state and cannot detect any devices.this bit takes precedence over p1cmd.sud. 0h rw 00 poe port 0 enabled (p0e): when set, the port is enabled. when cleared, the port is disabled. when enabled, the port can transition between the on, partial, and slumber states and can detect devices. when disabled, the port is in the ?off? state and cannot detect any devices. this bit takes precedence over p0cmd.sud. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 841 intel ? ep80579 integrated processor 23.1.6 serial ata capability registers 23.1.6.1 offset a8h: satacr0 ? serial ata capability register 0 this register shall be read-only 0 when cc.scc is 01h. 23.1.6.2 offset ach: satacr1 ? serial ata capability register 1 this register shall be read-only 0 when cc.scc is 01h. start end symbol name a8 ab satacr0 serial ata capability register 0 ac af satacr1 serial ata capability register 1 table 23-34. offset a8h: satacr0 ? serial ata capability register 0 description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: a8h abh size: 32 bit default: 00100012h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 00h ro 23 : 20 majrev major revision (majrev): major revision number of the sata capability pointer implemented. 1h ro 19 : 16 minrev minor revision (minrev): minor revision number of the sata capability pointer implemented. 0h ro 15 : 08 next next capability pointer (next): points to the next capability structure. 00h indicates this is the last capability pointer. 00h ro 07 : 00 cap capability id (cap): this value of 12h has been assigned by the pci sig to designate the sata capability structure. 12h ro table 23-35. offset ach: satacr1 ? serial ata capability register 1 description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: ach afh size: 32 bit default: 00000048h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 00h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 842 order number: 320066-003us 23.1.7 additional conf iguration registers 23.1.7.1 offset c0h: atc ? apm trapping control register 15 : 04 barofst bar offset (barofst): indicates the offset into the bar where the index/data pair are located (in dword granularity). the index and data i/o registers are located at offset 10h within the i/o space defined by lbar. a value of 004h indicates offset 10h. 000h = 0h offset 001h = 4h offset 002h = 8h offset 003h = bh offset 004h = 10h offset fffh = 3fffh offset (max 16kb) 004h ro 03 : 00 barloc bar location (barloc): indicates the absolute pci configuration register address of the bar containing the index/data pair (in dword granularity). the index and data i/o registers reside within the space defined by lbar in the sata controller. a value of 8h indicates offset 20h, which is lbar. 0000 ? 0011b = reserved 0100b = 10h => bar0 0101b = 14h => bar1 0110b = 18h => bar2 0111b = 1ch => bar3 1000b = 20h => lbar 1001b = 24h => bar5 1010 ? 1110b = reserved 1111b = reserved 8h ro table 23-36. offset c0h: atc ? apm trapping control register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: c0h c0h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h ro 03 sst secondary slave trap (sst): enables trapping and smi# assertion on legacy i/o accesses to 170h-177h and 376h. the active device on the secondary interface must be device 1 for the trap and/or smi# to occur. 0h rw table 23-35. offset ach: satacr1 ? serial ata capability register 1 description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: ach afh size: 32 bit default: 00000048h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 843 intel ? ep80579 integrated processor 23.1.7.2 offset c4h: ats ? atm trapping status register 02 spt secondary master trap (spt): enables trapping and smi# assertion on legacy i/o accesses to 170h-177h and 376h. the active device on the secondary interface must be device 0 for the trap and/or smi# to occur. 0h rw 01 pst primary slave trap (pst): enables trapping and smi# assertion on legacy i/o accesses to 1f0h-1f7h and 3f6h. the active device on the primary interface must be device 1 for the trap and/or smi# to occur. 0h rw 00 pmt primary master trap (pmt): enables trapping and smi# assertion on legacy i/o accesses to 1f0h-1f7h and 3f6h. the active device on the primary interface must be device 0 for the trap and/or smi# to occur. 0h rw table 23-37. offset c4h: ats ? atm trapping status register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: c4h c4h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h ro 03 sst secondary slave trap (sst): indicates that a trap occurred to the secondary slave device. 0h rwc 02 spt secondary master trap (spt): indicates that a trap occurred to the secondary master device. 0h rwc 01 pst primary slave trap (pst): indicates that a trap occurred to the primary slave device. 0h rwc 00 pmt primary master trap (pmt): indicates that a trap occurred to the primary master device. 0h rwc table 23-36. offset c0h: atc ? apm trapping control register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: c0h c0h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 844 order number: 320066-003us 23.1.7.3 offset d0h: sp ? scratch pad register 23.1.7.4 offset e0h: bfcs ? bist fis control/status register table 23-38. offset d0h: sp ? scratch pad register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: d0h d3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 dt data (dt): this is a read/write register that is available for software to use. no hardware action is taken on this register. 0h rw table 23-39. offset e0h: bfcs ? bist fis control/status register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: e0h e3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 14 reserved reserved 0h ro 13 reserved reserved 0h ro 12 reserved reserved 0h ro 11 bfs bist fis successful (bfs): this bit is set any time a bist fis transmitted by the sata controller receives an r_ok completion status from the device. 0h rwc 10 bff bist fis failed (bff): this bit is set any time that a bist fis transmitted by the sata controller receives an r_err completion status from the device. 0h rwc 09 p1bfi port 1 bist fis initiate (p1bfi): when a rising edge is detected on this bit, the sata controller will initiate a bist fis to the device on port 1, using the parameters specified in this register and bftd1 and bftd2. the bist fis will only be initiated if a device is present and not in the partial or slumber states. after a bist fis is successfully completed, software must disable and re-enable pcs.p1e prior to attempting additional bist fises or to return the sata controller to a normal op erational mode. if the bist fis fails, as indicated by bff in this register, software can clear then set this bit to initiate another bist fis. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 845 intel ? ep80579 integrated processor 08 p0bfi port 0 bist fis initiate (p0bfi): when a rising edge is detected on this bit, the sata controller will initiate a bist fis to the device on port 0, using the parameters specified in this register and bftd1 and bftd2. the bist fis will only be initiated if a device is present and not in the partial or slumber states. after a bist fis is successfully completed, software must disable and re-enable pcs.p0e prior to attempting additional bist fises or to return the sata controller to a normal operational mode. if the bist fis fails, as indicated by bff in this register, software can clear then set this bit to initiate another bist fis. 0h rw 07 : 02 bfp bist fis parameters (bfp): these bits form the contents of the upper 6 bits of the bist fis pattern definition in the bist fis transmitted by the sata controller. this field is not port specific ? its contents will be used for any bist fis initiated on the sata controller. the specific bit definitions are: 00h rw 01 : 00 reserved reserved. 00h ro table 23-39. offset e0h: bfcs ? bist fis control/status register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: e0h e3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access bit symbol description 7 t far end transmit mode 6 a align bypass mode 5 s bypass scrambling 4 l far end retimed loopback 3 f far end analog loopback 2p primitive bit for use with tra n sm i t m od e
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 846 order number: 320066-003us 23.1.7.5 offset e4h: bftd1 ? bist fis transmit data 1 register 23.1.7.6 offset e8h: bftd2 ? bist fis transmit data 2 register table 23-40. offset e4h: bftd1 ? bist fis transmit data 1 register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: e4h e7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 data data (data): the data programmed into this register will form the contents of the second dw of any bist fis initiated by the sata controller. this register is not port specific ? its contents will be used for bist fis initiated on any port. although the 2 nd and 3 rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 2 nd dw regardless of whether or not the t bit is indicated in the bfcs register. 00000000h rw table 23-41. offset e8h: bftd2 ? bist fis transmit data 2 register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: e8h ebh size: 32 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 data data (data): the data programmed into this register will form the contents of the third dw of any bist fis initiated by the sata controller. this register is not port specific ? its contents will be used for bist fis initiated on any port. although the 2 nd and 3 rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 3 rd dw regardless of whether or not the ?t? bit is set in the bfcs register. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 847 intel ? ep80579 integrated processor 23.1.7.7 offset f8h: manid ? manufacturing id register 23.2 sata i/o mapped registers all i/o registers are in the core well. when the index/data pair is enabled these registers use 32 bytes of i/o space, allocated via the lbar register (configuration offset 20h). when the index/data pair is disabled these registers use 16 bytes of i/o space. registers 00-0fh are only used for legacy operation. software must not use these registers when running ahci. the default values are defined with an h for hex, a bi for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 23-42. offset f8h: manid ? manufacturing id register description: view: pci bar: configuration bus:device:function: 0:31:2 offset start: offset end: f8h fbh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 0h ro 23 : 16 sid stepping identifier (sid): this field is incremented for each stepping of the part. note that this field can be used by software to differentiate steppings when the revision id may not change. note: 00h for a0 stepping note: 01h for b0 stepping the value read from this register is the same as that read from device 31, function 0, offset f8h. variable ro 15 : 08 mid manufacturer identifier (mid): 0fh = intel 0fh ro 07 : 00 pid process/dot identifier (pid): indicates the process as 1263h. 90h ro start end symbol name 00 00 pcmd primary command 02 02 psts primary status 04 07 pdtp primary data table pointer 08 08 scmd secondary command 0a 0a ssts secondary status
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 848 order number: 320066-003us 23.2.1 primary devices 23.2.1.1 offset 00h: pcmd ? primary command register 0c 0f sdtp secondary data table pointer 10 13 index ahci register index 14 17 data ahci register data table 23-43. bus 0, device 31, function 2: summary of sata controller configuration registers mapped through lbar i/o bar offset start offset end register id - description default value 00h 00h ?offset 00h: pcmd ? primary command register? on page 848 00h 02h 02h ?offset 02h: psts ? primary status register? on page 849 00h 04h 07h ?offset 04h: pdtp ? primary descriptor table pointer register? on page 849 variable 10h 13h ?offset 10h: index ? ahci index register? on page 850 00000000h 14h 17h ?offset 14h: data ? ahci data register? on page 851 variable table 23-44. offset 00h: pcmd ? primary command register description: view: pci base address: lbar (io) bus:device:function: 0:31:2 offset start: offset end: 00h 00h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h ro 03 rwc read / write control (rwc): sets the direction of the bus master transfer: 0 = memory to device, 1 = device to memory. this bit must not be changed when the bus master function is active. 0h rw 02 : 01 reserved reserved 0h ro 00 start start/stop bus master (start): setting this bit enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit in pci configuration space is also set. clearing it halts bus master operation. all state information is lost when this bit is written to '0'; master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active and the device has not yet finished its data transfer, the bus master command is said to be aborted. if this bit is cleared to ?0? prior to the dma data transfer being initiated by the drive in a device to memory data transfer, then the ich5 will not send dmat to terminate the data transfer. sw intervention (e.g. sending srst) is required to reset the interface in this condition. this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the act bit being cleared in the status register, or the i bit being set in the status register, or both. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 849 intel ? ep80579 integrated processor 23.2.1.2 offset 02h: psts ? primary status register 23.2.1.3 offset 04h: pdtp ? primary descriptor table pointer register table 23-45. offset 02h: psts ? primary status register description: view: pci base address: lbar (io) bus:device:function: 0:31:2 offset start: offset end: 02h 02h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 prdis prd interrupt status (prdis): this bit is set when the host controller completes execution of a prd that has its prd_int bit set. 0h rwc 06 d1dc device 1 dma capable (d1dc): a scratchpad bit set sw to indicate that device 1 of this channel is capable of dma transfers. this bit has no effect on the hardware. 0h rw 05 d0dc device 0 dma capable (d0dc): a scratchpad bit set by sw to indicate that device 0 of this channel is capable of dma transfers. this bit has no effect on the hardware. 0h rw 04 : 03 reserved reserved 0h ro 02 i interrupt (i): this bit is set when a device fis is received with the ?i? bit has been set provided that software has not disabled interrupt via the nien bit of device control register. 0h rwc 01 err error (err): this bit is set when the controller encounters an error during the transfer and must stop the transfer. see section 1.5.2 for the list of errors that set this bit 0h rwc 00 act active (act): set by the host when the start bit is written to the command register, and cleared by the host when the last transfer for a region is performed, where eot for that region is set in the region descriptor, and when the start bit is cleared in the command register and the controller has returned to an idle condition. 0h ro table 23-46. offset 04h: pdtp ? primary descriptor table pointer register description: view: pci base address: lbar (io) bus:device:function: 0:31:2 offset start: offset end: 04h 07h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 02 dba descriptor base address (dba): corresponds to a[31:2]. this table must not cross a 64k boundary in memory. when read, the current value of the pointer is returned xrw 01 : 00 reserved reserved 00h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 850 order number: 320066-003us 23.2.2 secondary devices 23.2.2.1 offset 08h: scmd ? secondary command register same as that of primary device. see the description of ?offset 00h: pcmd ? primary command register? on page 848 . 23.2.2.2 offset 0ah: ssts ? secondary status register same as that of primary device. see the description of ?offset 02h: psts ? primary status register? on page 849 . 23.2.2.3 offset 0ch: sdtp ? secondary descriptor table pointer register same as that of primary device. see the description of ?offset 04h: pdtp ? primary descriptor table pointer register? on page 849 . 23.2.3 ahci index and data registers 23.2.3.1 offset 10h: index ? ahci index register table 23-47. offset 10h: index ? ahci index register description: view: pci bar: lbar (io) bus:device:function: 0:31:2 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 reserved reserved 0h ro 09 : 02 index index (index): this index register is used to select the dword offset of the memory mapped ahci register to be accessed. a dword, word or byte access is specified by the active byte enables of the i/o access to the data register. 0h rw 01 : 00 reserved reserved 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 851 intel ? ep80579 integrated processor 23.2.3.2 offset 14h: data ? ahci data register 23.3 sata memory mapped registers the memory mapped registers within the sata controller exist in non-cacheable memory space. additionally, locked accesses are not supported. if software attempts to perform locked transactions to the registers, indeterminate results may occur. register accesses shall have a maximum size of 64 bits. 64 bit accesses must not cross an 8 byte alignment boundary. the registers are broken into 2 sections ? global control registers and port control registers. all registers that start below address 100h are global and meant to apply to the entire hba. the port control registers are the same for all ports, and there are as many registers banks as there are ports. all registers not defined and all reserved bits within registers return ?0? when read. table 23-48. offset 14h: data ? ahci data register description: view: pci bar: lbar (io) bus:device:function: 0:31:2 offset start: offset end: 14h 17h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 data data (data) ? r/w : this data register is a ?window? through which data is read or written to the ahci memory mapped registers. a read or write to this data register triggers a corresponding read or write to the memory mapped register pointed to by the index register. the index register must be setup prior to the read or write to this data register. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register pointed to by index. variable rw start end description 00 1f generic host control 20 9f reserved a0 ff vendor specific registers 100 17f port 0 port control registers 180 1ff port 1 port control registers 200 27f reserved 280 2ff reserved 300 3ff reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 852 order number: 320066-003us 23.3.1 generic host controller table 23-49. bus 0, device 31, function 2: summary of sata controller configuration registers mapped through abar memory bar offset start offset end register id - description default value 00h 03h ?offset 00h: hcap ? hba capabilities register? on page 853 variable 04h 07h ?offset 04h: ghc ? global hba control register? on page 855 00000000h 08h 0bh ?offset 08h: is ? interrupt status register? on page 856 00000000h 0ch 0fh ?offset 0ch: pi ? ports implemented register? on page 856 00000000h 10h 13h ?offset 10h: vs ? ahci version register? on page 857 00010100h a0h a3h ?offset a0h: sgpo -spgio control register? on page 857 00000000h 100h, 180h 17fh, 1ffh ?offset 100h: pxclb[0-1] ? port [0-1] command list base address register? on page 858 variable 104h, 184h 107h, 187h ?offset 104h: pxclbu[0-1] ? port [0-1] command list base address register? on page 858 variable 108h, 188h 10bh, 18bh ?offset 108h: pxfb[0-1] ? port [0-1] fis base address register? on page 859 variable 10ch, 18ch 10fh, 18fh ?offset 10ch: pxfbu[0-1] ? port [0-1] fis base address upper 32-bits register? on page 859 variable 110h, 190h 113h, 193h ?offset 110h: pxis[0-1] ? port [0-1] interrupt status register? on page 860 00000000h 114h, 194h 117h, 197h ?offset 114h: pxie[0-1] ? port [0-1] interrupt enable register? on page 861 00000000h 118h, 198h 11bh, 19bh ?offset 118h: pxcmd[0-1] ? port [0-1] command register? on page 863 variable 120h, 1a0h 123h, 1a3h ?offset 120h: pxtfd[0-1] ? port [0-1] task file data register? on page 866 0000007fh 124h, 1a4h 127h, 1a7h ?offset 124h: pxsig[0-1] ? port [0-1] signature register? on page 867 ffffffffh 128h, 1a8h 12bh, 1abh ?offset 128h: pxssts[0-1] ? port [0-1] serial ata status register? on page 868 variable 12ch, 1ach 12fh, 1afh ?offset 12ch: pxsctl[0-1] ? port [0-1] serial ata control register? on page 869 00000000h 130h, 1b0h 133h, 1b3h ?offset 130h: pxserr[0-1] ? port [0-1] serial ata error register? on page 870 00000000h 134h, 1b4h 137h, 1b7h ?offset 134h: pxsact[0-1] ? port [0-1] serial ata active register? on page 872 00000000h 138h, 1b8h 13bh, 1bbh ?offset 138h: pxci[0-1] ? port [0-1] command issue register? on page 872 00000000h 13ch, 1bch 13fh, 1bfh ?offset 13ch: pxsntf[0-1] ? port [0-1] snotification register? on page 873 00000000h start end symbol description 00 03 hcap host capabilities 04 07 ghc global host control 08 0b is interrupt status 0c 0f pi ports implemented 10 13 vs version
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 853 intel ? ep80579 integrated processor 23.3.1.1 offset 00h: hcap ? hba capabilities register this register indicates basic capabilities of the hba to driver software. the rwo bits in this register are only cleared upon pltrst#. table 23-50. offset 00h: hcap ? hba capabilities register (sheet 1 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 00h 03h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 s64a supports 64-bit addressing (s64a): indicates the s-ata controller can access 64-bit data structures. the 32-bit upper bits of the port dma descriptor, the prd base, and each prd entry are read/write. 1h ro 30 scqa supports native command queuing acceleration (scqa): indicates the sata controller supports serial-ata native command queuing. the hba will handle dma setup fises natively and will handle the auto-activate optimization through the fis. 1h rwo 29 ssntf supports snotifiation register (ssntf): the sata controller supports the snotification register. 1h rwo 28 sis supports interlock switch (sis): indicates whether the s-ata controller supports interlock switches on its ports for use in hot plug operations. this value is loaded by platform bios prior to os initialization. if this bit is set, bios must also map the satagp pins to the s-ata controller through gpio space. 1h rwo 27 sss supports staggered spin-up (sss): indicates whether the s-ata controller supports staggered spin-up on its ports, for use in balancing power spikes. this value is loaded by platform bios prior to os initialization. 1h rwo 26 salp supports aggressive link power management (salp): indicates the s-ata controller supports auto-generating link requests to the partial or slumber states when there are no commands to process. 1h rwo 25 sal supports activity led (sal): indicates the s-ata controller supports a single output pin (sataled#) which indicates activity. 1h ro 24 sclo supports command list override (sclo): when set to '1', indicates that the hba supports the pxcmd.clo bit and it's associated function. when cleared to '0', the hba is not capable of clearing the bsy and drq bits in the status register in order to issue a software reset if these bits are still set from a previous operation. 1h rwo 23 : 20 iss interface speed support (iss): indicates the maximum speed the s-ata controller can support is 1.5 gbps and 3 gbps on its ports. speed can be limited in each port by programming pxsctl.det to a lower value. 2h rwo 19 snzo supports non-zero dma offsets (snzo): reserved as per ahci 1.0 0h ro 18 reserved reserved 0h ro 17 reserved reserved: bios must clear this bit. 1h rwo 16 reserved reserved 0h ro 15 pmd pio multiple drq block (pmd): the sata controller support pio multiple drq command block. 1h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 854 order number: 320066-003us 14 ssc slumber state capable (ssc): the sata controller supports the slumber state. 1h rwo 13 psc partial state capable (psc): the sata controller supports the partial state. 1h rwo 12 : 08 ncs number of command slots (ncs): this register field is read only = 1fh indicating support for 32 slots. 1fh ro 07 : 06 reserved reserved 0h ro 05 sxs supports external sata (sxs): when set to '1', indicates that the hba has one or more serial ata ports that has a signal only connector that is externally accessible. if this bit is set, software may refer to the pxcmd.esp bit to determine whether a specific port has its signal connector externally accessible as a signal only connector (i.e. power is not part of that connector). when the bit is cleared to '0', indicates that the hba has no serial ata ports that have a signal only connector externally accessible. 0h rwo 04 : 00 nds number of devices (nds): indicates support for 2 devices. 1h ro table 23-50. offset 00h: hcap ? hba ca pabilities register (sheet 2 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 00h 03h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 855 intel ? ep80579 integrated processor 23.3.1.2 offset 04h: ghc ? global hba control register this register controls various global actions of the hba. table 23-51. offset 04h: ghc ? global hba control register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 04h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 ae ahci enable (ae): when set, indicates that an ahci driver is loaded and communication to the hba shall be via ahci mechanisms. this can be used by an hba that supports both legacy mechanisms (such as sff-8038i) and ahci to know when the hba is running under an ahci driver. when set, software shall only talk to the hba using ahci. the hba will not have to allow command processing via both ahci and legacy mechanisms. when cleared, software will only communicate with the hba using legacy mechanisms. software shall set this bit to ?1? before accessing other ahci registers. 0h rw 30 : 02 reserved reserved 0h ro 01 ie interrupt enable (ie): this global bit enables interrupts from the hba. when cleared (reset default), all interrupt sources from all ports are disabled. when set, interrupts are enabled. 0h rw 00 hr hba reset (hr): when set by sw, this bit causes an internal reset of the hba. all state machines that relate to data transfers and queuing will return to an idle condition, and all ports will be re-initialized via comreset. when the hba has performed the reset action, it will reset this bit to ?0?. a software write of ?0? will have no effect. for a description on which bits are reset when this bit is set, see the ahci specification . 0h rws
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 856 order number: 320066-003us 23.3.1.3 offset 08h: is ? interrupt status register this register indicates which of the ports within the controller have an interrupt pending and require service. 23.3.1.4 offset 0ch: pi ? ports implemented register this register indicates which ports are exposed to the hba. it is loaded by platform bios. it indicates which ports that the device supports are available for software to use. any available port may not be implemented. table 23-52. offset 08h: is ? interrupt status register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 08h 0bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 02 reserved reserved 0h ro 01 ips1 interrupt pending status port 1 (ips1): if set, indicates that port 2 has an interrupt pending. software can use this information to determine which ports require service after an interrupt. 0h rwc 00 ips0 interrupt pending status port 0 (ips0): if set, indicates that port 2 has an interrupt pending. software can use this information to determine which ports require service after an interrupt. 0h rwc table 23-53. offset 0ch: pi ? ports implemented register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 0ch 0fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 02 reserved reserved 0h ro 01 pi1 port 1 implemented (pi1): if set, the port is available for use. if cleared, the port is not available for use. 0h rwo 00 pi0 port 0 implemented (pi0): if set, the port is available for use. if cleared, the port is not available for use. 0h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 857 intel ? ep80579 integrated processor 23.3.1.5 offset 10h: vs ? ahci version register this register indicates the major and minor version of the ahci specification . it is bcd encoded. the upper two bytes represent the major version number, and the lower two bytes represent the minor version number. example: version 3.12 would be represented as 00030102h. the current version of the specification is 1.1 (00010100h). 23.3.2 vendor specific registers this register contains the output bits associated with the two sata drives and vendor specific message when operating in the ahci mode. the bits associated with the drives are intended to control leds (e.g., activity, fault, and locate leds). it is the responsibility of software to write data into this register. three data bits are allocated per drive. 23.3.2.1 offset a0h: sgpo - spgio control register table 23-54. offset 10h: vs ? ahci version register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 10h 13h size: 32 bit default: 00010100h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 mjr major version number (mjr): indicates the major version is ?1? 0001h ro 15 : 00 mnr minor version number (mnr): indicates the minor version is ?10?. 0100h ro table 23-55. offset a0h: sgpo -spgio control register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 reserved reserved ? 00000h ro 11 : 10 reserved reserved ?00bro 9:7 d1dat drive 1 data: indicates the data to be driven out for drive 1 on sdataout0. 000b rw 6:4 d0dat drive 0data: indicates the data to be driven out for drive 0 on sdataout0. 000b rw 03 : 00 svsm sload vendor specific message: indicates the vendor specific message to be driven on to spgpio bus on the sload signal . 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 858 order number: 320066-003us 23.3.3 port dma registers 23.3.3.1 offset 100h: pxclb[0-1] ? port [0-1] command list base address register 23.3.3.2 offset 104h: pxclbu[0-1] ? port [0-1] command list base address upper 32-bits register table 23-56. offset 100h: pxclb[0-1] ? port [0-1] command list base address register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 100h, 180h 17fh, 1ffh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 clb command list base address (clb): indicates the 32- bit base for the command list for this port. this base is used when fetching commands to execute. this address must be 1k aligned as indicated by bits 31:10 being read/ write. note that these bits are not reset on a hba reset. variable rw 09 : 00 reserved reserved 000h ro table 23-57. offset 104h: pxclbu[0-1] ? port [0-1] command list base address register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 104h, 184h 107h, 187h size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 clbu command list base address upper (clbu): indicates the upper 32-bits for the command list base address for this port. this base is used when fetching commands to execute. note that these bits are not reset on a hba reset. variable rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 859 intel ? ep80579 integrated processor 23.3.3.3 offset 108h: pxfb[0-1] ? port [0-1] fis base address register 23.3.3.4 offset 10ch: pxfbu[0-1] ? port [0-1] fis base address upper 32-bits register table 23-58. offset 108h: pxfb[0-1] ? port [0-1] fis base address register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 108h, 188h 10bh, 18bh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 08 fb fis base address (fb): indicates the 32-bit base for received fises. this address must be 256-byte aligned as indicated by bits 31:08 being read/write. note that these bits are not reset on a hba reset. xx rw 07 : 00 reserved reserved 00h ro table 23-59. offset 10ch: pxfbu[0-1] ? port [0-1] fis base address upper 32-bits register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 10ch, 18ch 10fh, 18fh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 fbu fis base address upper (fbu): indicates the upper 32-bits for the received fis base for this port. note that these bits are not reset on a hba reset. variable rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 860 order number: 320066-003us 23.3.3.5 offset 110h: pxis[0-1] ? port [0-1] interrupt status register table 23-60. offset 110h: pxis[0-1] ? port [0-1] interrupt status register (sheet 1 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 110h, 190h 113h, 193h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 cpds cold port detect status (cpds): the sata controller does not support cold presence detect. 0h ro 30 tfes task file error status (tfes): this bit is set whenever the status register is updated by the device and the error bit (bit 0) is set. 0h rwc 29 hbfs host bus fatal error status (hbfs): indicates that the hba encountered a host bus error that it cannot recover from, such as a bad software pointer. in pci, such an indication would be a target or master abort. 0h rwc 28 hbds host bus data error status (hbds): indicates that the hba encountered a data error (uncorrectable ecc / parity) when reading from or writing to system memory. 0h rwc 27 ifs interface fatal error status (ifs): indicates that the hba encountered an error on the sata interface which caused the transfer to stop. 0h rwc 26 infs interface non-fatal error status (infs): indicates that the hba encountered an error on the sata interface but was able to continue operation. 0h rwc 25 reserved reserved 0h ro 24 ofs overflow status (ofs): indicates that the hba received more bytes from a device than was specified in the prd table for the command. 0h rwc 23 reserved reserved. 0h rwc 22 prcs phyrdy change status (prcs): when set to one indicates the internal phyrdy signal changed state. this bit reflects the state of pxserr.diag.n. this bit is ro and is only cleared when pxserr.diag.n is cleared. note that the internal phyrdy signal also transitions when the port interface enters partial or slumber power management states. partial and slumber must be disabled when surprise removal notification is desired, otherwise the power management state transitions will appear as false insertion and removal events. 0h ro 21 : 08 reserved reserved 0h ro 07 dis device interlock status (dis): when set, indicates that a platform interlock switch has been opened or closed, which may lead to a change in the connection state of the device. this bit is only valid in systems that support an interlock switch (hcap.sis set). for systems that do not support an interlock switch, this bit will always be ?0?. 0h rwc 06 pcs port connect change status (pcs): 1=change in current connect status . 0=no change in current connect status . this bit reflects the state of pxserr.diag.x. this bit is only cleared when pxserr.diag.x is cleared. 0h ro 05 dps descriptor processed (dps): a prd with the ?i? bit set has transferred all of its data. 0h rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 861 intel ? ep80579 integrated processor 23.3.3.6 offset 114h: pxie[0-1] ? port [0-1] interrupt enable register this register enables and disables the reporting of the corresponding interrupt to system software. when a bit is set (?1?) and the corresponding interrupt condition is active, then an interrupt is generated. interrupt sources that are disabled (?0?) are still reflected in the status registers. this register is symmetrical with the port 0 status register. 04 ufs unknown fis interrupt (ufs): when set to ?1? indicates that an unknown fis was received and has been copied into system memory. this bit is cleared to ?0? by software clearing the pxserr.diag.f bit to ?0?. note that this bit does not directly reflect the pxserr.diag.f bit. pxserr.diag.f is set immediately when an unknown fis is detected, whereas this bit is set when the fis is posted to memory. software should wait to act on an unknown fis until this bit is set to ?1? or the two bits may become out of sync. 0h ro 03 sdbs set device bits interrupt (sdbs): a set device bits fis has been received with the ?i? bit set and has been copied into system memory. 0h rwc 02 dss dma setup fis interrupt (dss): a dma setup fis has been received with the ?i? bit set and has been copied into system memory. 0h rwc 01 pss pio setup fis interrupt (pss): a pio setup fis has been received with the ?i? bit set, it has been copied into system memory, and the data related to that fis has been transferred. this bit shall be set even if the data transfer resulted in an error. 0h rwc 00 dhrs device to host register fis interrupt (dhrs): a d2h register fis has been received with the ?i? bit set, and has been copied into system memory. 0h rwc table 23-60. offset 110h: pxis[0-1] ? port [0-1] interrupt status register (sheet 2 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 110h, 190h 113h, 193h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 23-61. offset 114h: pxie[0-1] ? port [0-1] interrupt enable register (sheet 1 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 114h, 194h 117h, 197h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 cpde cold presence detect enable (cpde): the sata controller does not support cold presence detect. 0h ro 30 tfee task file error enable (tfee): when set, ghc.ie is set, and p0s.tfes is set, the hba shall generate an interrupt. 0h rw 29 hbfe host bus fatal error enable (hbfe): when set, ghc.ie is set, and p0is.hbfs is set, the hba shall generate an interrupt. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 862 order number: 320066-003us 28 hbde host bus data error enable (hbde): when set, ghc.ie is set, and p0is.hbds is set, the hba shall generate an interrupt. 0h rw 27 ife interface fatal error enable (ife): when set, ghc.ie is set, and p0is.ifs is set, the hba shall generate an interrupt. 0h rw 26 infe interface non-fatal error enable (infe): when set, ghc.ie is set, and p0is.infs is set, the hba shall generate an interrupt. 0h rw 25 reserved reserved 0h ro 24 ofe overflow enable (ofe): when set, and ghc.ie and p0is.ofs are set, the hba shall generate an interrupt. 0h rw 23 reserved reserved. 0h rw 22 prce phyrdy change interrupt enable (prce): when set, and ghc.ie is set, and pxis.prcs is set, the hba shall generate an interrupt. 0h rw 21 : 08 reserved reserved 0h ro 07 die device interlock enable (die): when set, and p0is.dis is set, the hba shall generate an interrupt. for systems that do not support an interlock switch, this bit shall be a read-only ?0?. 0h rw 06 pce port change interrupt enable (pce): when set, ghc.ie is set, and p0is.pcs is set, the hba shall generate an interrupt. 0h rw 05 dpe descriptor processed interrupt enable (dpe): when set, ghc.ie is set, and p0is.dps is set, the hba shall generate an interrupt. 0h rw 04 ufe unknown fis interrupt enable (ufe): when set, ghc.ie is set, and pxis.ufs is set to ?1?, the hba shall generate an interrupt. 0h rw 03 sdbe set device bits fis interrupt enable (sdbe): when set, ghc.ie is set, and p0is.sdbs is set, the hba shall generate an interrupt. 0h rw 02 dse dma setup fis interrupt enable (dse): when set, ghc.ie is set, and p0is.dss is set, the hba shall generate an interrupt. 0h rw 01 pse pio setup fis interrupt enable (pse): when set, ghc.ie is set, and p0is.pss is set, the hba shall generate an interrupt. 0h rw 00 dhre device to host register fis interrupt enable (dhre): when set, ghc.ie is set, and p0is.dhrs is set, the hba shall generate an interrupt. 0h rw table 23-61. offset 114h: pxie[0-1] ? port [0-1] interrupt enable register (sheet 2 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 114h, 194h 117h, 197h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 863 intel ? ep80579 integrated processor 23.3.3.7 offset 118h: pxcmd[0-1] ? port [0-1] command register table 23-62. offset 118h: pxcmd[0-1] ? port [0-1] command register (sheet 1 of 3) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 118h, 198h 11bh, 19bh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 28 icc interface communication control (icc): this is a four bit field which can be used to control reset and power states of the interface. if the link layer is currently in the l_idle state, writes to this field shall cause the hba to initiate a transition to the interface power management state requested. if the link layer is not currently in the l_idle state, writes to this field shall have no effect. when system software writes a non-reserved value other than no-op (0h), the hba will perform the action and update this field back to idle (0h). if software writes to this field to change the state to a state the link is already in (i.e. interface is in the active state and a request is made to go to the active state), the hba will take no action and return this field to idle. if the interface is in a low power state and the software wants to transition to a different low power state, software must first bring the link to active and then initiate the transition to the desired low power state. 0h rw 27 asp aggressive slumber / partial (asp): when set, and the alpe bit is set, the hba will aggressively enter the slumber state when it clears the pxci register and the pxsact register is cleared. when cleared, and the alpe bit is set, the hba will aggressively enter the partial state when it clears the pxci register and the pxsact register is cleared. 0h rw 26 alpe aggressive link power management enable (alpe): when set, the hba will aggressively enter a lower link power state (partial or slumber) based upon the setting of the asp bit. 0h rw 25 dlae drive led on atapi enable (dlae): when set, the hba will drive the led pin active for commands regardless of the state of pxcmd.atapi. when cleared, the hba will only drive the led pin active for commands if pxcmd.atapi is set to ?0?. 0h rw value definition fh?7h reserved 6h slumber: this will cause the hba to request a transition of the interface to the slumber state. the sata device may reject the request and the interface will remain in its current state. 5h?3h reserved 2h partial: this will cause the hba to request a transition of the interface to the partial state. the sata device may reject the request and the interface will remain in its current state. 1h active: this will cause the hba to request a transition of the interface into the active state. 0h no-op / idle: when software reads this value, it indicates the hba is ready to accept a new interface control command, although the transition to the previously selected state may not yet have occurred.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 864 order number: 320066-003us 24 atapi device is atapi (atapi): when set, the connected device is an atapi device. this bit is used by the hba to control whether or not to generate the desktop led when commands are active. 0h rw 23 :22 reserved reserved 0h ro 21 esp external sata port (esp): when set to '1', indicates that this port is routed externally and will be used with an external sata device. when set to '1' hcap.sxs must also be set to '1'. when cleared ('0'), indicates that this port is not routed externally and supports internal sata devices only. esp is mutually exclusive with the hpcp bit in this register 0h rwo 20 cpd cold presence detection (cpd): the sata controller does not support cold presence detect. 0h ro 19 isp interlock switch attached to port (isp): when interlock switches are supported in the platform (hcap.sis set), this indicates whether this particular port has an interlock switch attached. this bit can be used by system software to enable such features as aggressive power management, as disconnects can always be detected regardless of phy state with an interlock switch. when this bit is set, it is expected that hpcp in this register is also set. the hba takes no action on the state of this bit ? it is for system software only. for example, if this bit is cleared, and an interlock switch toggles, the hba shall still treat it as a proper interlock switch event. note that this bit is not reset on a hba reset. 0h rwo 18 hpcp hot plug capable port (hpcp): this indicates whether the this port is connected to a device which can be hot plugged. sata by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for example). this bit can be used by system software to indicate a feature such as ?eject device? to the end-user. the hba takes no action on the state of this bit ? it is for system software only. for example, if this bit is cleared, and a hot plug event occurs, the hba shall still treat it as a proper hot plug event. note that this bit is not reset on a hba reset. 0h rwo 17 reserved reserved. 0h ro 16 reserved reserved 0h ro 15 cr command list running (cr): when this bit is set it indicates that the command list dma engine for the port is running. 0h ro 14 fr fis receive running (fr): when this bit is set it indicates that the fis receive dma engine for the port is running. 0h ro 13 iss interlock switch state (iss): for hbas that support interlock switches (hcap.sis=1), this bit indicates the current state of the interlock switch. a ?0? indicates the switch is closed, and a ?1? indicates the switch is opened. for hbas that do not support interlock switches (hcap.sis=0), this bit reports ?0?. software should only use this bit if both hcap.sis and pxcmd.isp are set to ?1?. variable ro table 23-62. offset 118h: pxcmd[0-1] ? port [0-1] command register (sheet 2 of 3) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 118h, 198h 11bh, 19bh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 865 intel ? ep80579 integrated processor 12 : 08 ccs current command slot (ccs): indicates the current command slot the hba is processing. this field is valid when the pxcmd.st bit is set, and is constantly updated by the hba. this field can be updated as soon as the hba recognizes an active command slot, or at some point soon after when it begins processing the command. when pxcmd.st transitions from a ?1? to a ?0?, the hba will reset this field to ?0?. after pxcmd.st transitions from ?0? to ?1?, the highest priority slot to issue from next is command slot 0. after the first command has been issued, the highest priority slot to issue from next is pxcmd.ccs + 1. for example, after the hba has issued its first command, if pxcmd.ccs = 0h and pxci is set to 3h, the next command that will be issued is from command slot 1. 0h ro 07 : 05 reserved reserved 0h ro 04 fre fis receive enable (fre): when set, the hba may post received fises into the fis receive area pointed to by pxfb and pxfbu. when cleared, received fises are not accepted by the hba, except for the first d2h register fis after the initialization sequence. system software must not set this bit until pxfb (pxfbu) have been programmed with a valid pointer to the fis receive area. if software wishes to move the base, this bit must first be cleared, and software must wait for the pxcmd.fr bit to be cleared. software must not clear this bit while pxcmd.st is set to ?1?. 0h rw 03 clo command list override (clo): setting this bit to '1' causes pxtfd.sts.bsy and pxtfd.sts.drq to be cleared to '0'. this allows a software reset to be transmitted to the device regardless of whether the bsy and drq bits are still set in the pxtfd.sts register. the hba sets this bit to '0' when pxtfd.sts.bsy and pxtfd.sts.drq have been cleared to '0'. a write to this register with a value of '0' shall have no effect. this bit shall only be set to '1' immediately prior to setting the pxcmd.st bit to '1' from a previous value of '0'. setting this bit to '1' at any other time is not supported and will result in indeterminate behavior. 0h rw 02 pod power on device (pod): the sata controller does not support cold presence detect. 1h ro 01 sud spin-up device (sud): this bit is read/write and defaults to 0 for hbas that support staggered spin-up via hcap .sss. this bit is read only ?1? for hbas that do not support staggered spin-up. on an edge detect from ?0? to ?1?, the hba shall start a comreset initialization sequence to the device. clearing this bit causes no action on the interface. variable rw/ro 00 st start (st): when set, the hba may process the command list. when cleared, the hba may not process the command list. whenever this bit is changed from a ?0? to a ?1?, the hba starts processing the command list at entry ?0?. whenever this bit is changed from a ?1? to a ?0?, the pxci register is cleared by the hba upon the hba putting the controller into an idle state. see section 10.2.1 of the ahci spec for restrictions on when pxcmd.st can be set to ?1? and cleared to ?0?. 0h rw table 23-62. offset 118h: pxcmd[0-1] ? port [0-1] command register (sheet 3 of 3) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 118h, 198h 11bh, 19bh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 866 order number: 320066-003us 23.3.4 port interface registers (one set per port) these registers implement various functions of the interface with an sata device, including the sata superset registers of the sata specification . 23.3.4.1 offset 120h: pxtfd[0-1] ? port [0-1] task file data register this is a 32-bit register that copies specific fields of the task file when fises are received. the fises that contain this information are: ? d2h register fis ?pio setup fis ? set device bits fis (bsy and drq are not updated with this fis) table 23-63. port interface registers for ports[1:0] start end symbol description 120 123 p0tfd port 0 task file data 124 127 p0sig port 0 signature 128 12b p0ssts port 0 serial ata status 12c 12f p0sctl port 0 serial ata control 130 133 p0serr port 0 serial ata error 134 137 p0sact port 0 device status 138 13b p0ci port 0 command issue 13c 13f p0sntf port 0 serial ata notification 1a0 1a3 p1tfd port 1 task file data 1a4 1a7 p1sig port 1 signature 1a8 1ab p1ssts port 1 serial ata status 1ac 1af p1sctl port 1 serial ata control 1b0 1b3 p1serr port 1 serial ata error 1b4 1b7 p1sact port 1 device status 1b8 1bb p1ci port 1 command issue 1bc 1bf p1sntf port 1 serial ata notification table 23-64. offset 120h: pxtfd[0-1] ? port [0-1] task file data register (sheet 1 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 120h, 1a0h 123h, 1a3h size: 32 bit default: 0000007fh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 867 intel ? ep80579 integrated processor 23.3.4.2 offset 124h: pxsig[0-1] ? port [0-1] signature register this is a 32-bit register which contains the initial signature of an attached device when the first d2h register fis is received from th at device. it is updated once after a reset sequence. 15 : 08 err error (err): contains the latest copy of the task file error register. 0h ro 07 : 00 sts status (sts): contains the latest copy of the task file status register. fields of note in this register that affect ahci: note that the hba updates all 8 bits of this register from the received fis, not just the bits noted above. 7fh ro table 23-64. offset 120h: pxtfd[0-1] ? port [0-1 ] task file data register (sheet 2 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 120h, 1a0h 123h, 1a3h size: 32 bit default: 0000007fh power well: core bit range bit acronym bit description sticky bit reset value bit access bit field definition 7 bsy indicates the interface is busy 6:4 n/a not applicable 3drq indicates a data transfer is requested 2:1 n/a not applicable 0err indicates an error during the transfer. table 23-65. offset 124h: pxsig[0-1] ? port [0-1] signature register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 124h, 1a4h 127h, 1a7h size: 32 bit default: ffffffffh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 sig signature (sig): contains the signature received from a device on the first d2h register fis. the bit order is as follows: ffffffffh ro bit field 31:24 lba high register 23:16 lba mid register 15:08 lba low register 07:00 sector count register
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 868 order number: 320066-003us 23.3.4.3 offset 128h: pxssts[0-1] ? port [0-1] serial ata status register this is a 32-bit register that conveys the current state of the interface and host. the hba updates it continuously and asynchronously. when the hba transmits a comreset to the device, this register is updated to its reset values. table 23-66. offset 128h: pxssts[0-1] ? port [0-1] serial ata status register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 128h, 1a8h 12bh, 1abh size: 32 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 reserved reserved 0h ro 11 : 08 ipm interface power management (ipm): indicates the current interface state: 0h =device not present or communication not established 1h =interface in active state 2h =interface in partial power management state 6h =interface in slumber power management state all other values reserved. this field reflects the interface power management state for both device and host initiated power management. 0h ro 07 : 04 spd current interface speed (spd): indicates the negotiated interface communication speed. 0h =device not present or communication not established 1h =generation 1 communication rate negotiated 2h =generation 2 communication rate negotiated all other values reserved 0h ro 03 : 00 det device detection (det): indicates the interface device detection and phy state. 0h = no device detected and phy communication not established 1h =device presence detected but phy communication not established 3h =device presence detected and phy communication established 4h =phy in offline mode as a result of the interface being disabled or running in a bist loopback mode all other values reserved. note that, while the true reset default value of this register is 0h, the value read from this register depends on drive presence and the point in time within the initialization process when the register is read. variable ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 869 intel ? ep80579 integrated processor 23.3.4.4 offset 12ch: pxsctl[0-1] ? port [0-1] serial ata control register this is a 32-bit read-write register by whic h software controls sata capabilities. writes to this register result in an action being taken by the host adapter or interface. reads from the register return the last value written to it. table 23-67. offset 12ch: pxsctl[0-1] ? port [0-1] serial ata control register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 12ch, 1ach 12fh, 1afh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 reserved reserved 0h ro 19 : 16 reserved reserved. 0h rw 15 : 12 spm select power management (spm): this field is not used by ahci. 0h rw 11 : 08 ipm interface power management transitions allowed (ipm): indicates which power states the hba is allowed to transition to. if an interface power management state is not allowed via this register fi eld, the hba will not initiate that state and the hba will pmnak p any request from the device to enter that state. 0h =no interface restrictions 1h =transitions to the partial state disabled 2h =transitions to the slumber state disabled 3h =transitions to both partial and slumber states disabled all other values reserved 0h rw 07 : 04 spd speed allowed (spd): indicates the highest allowable speed of the interface. this speed is limited by the hcap.iss field. for example, if hcap.iss is limited to gen1 speeds, only gen1 speeds will be negotiated, even if a 0h or 2h is programmed in this register. 0h =no speed negotiation restrictions 1h =limit speed negotiation to generation 1 communication rate 2h =limit speed negotiation to generation 2 communication rate all other values reserved. 0h rw 03 : 00 det device detection initialization (det): controls the hba?s device detection and interface initialization. 0h =no device detection or in itialization action requested 1h =perform interface communication initialization sequence to establish communication. this is functionally equivalent to a hard reset and results in the interface being reset and communications reinitialized. while this field is 1h, comreset is continuously transmitted on the interface. software should leave the det field set to 1h for a minimum of 1 millisecond to ensure that a comreset is sent on the interface. 4h =disable the serial ata interface and put phy in offline mode. all other values reserved. this field may only be changed to 1h or 4h when pxcmd.st is ?0?. changing this field to 1h or 4h while the hba is running results in undefined behavior. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 870 order number: 320066-003us 23.3.4.5 offset 130h: pxserr[0-1] ? port [0-1] serial ata error register table 23-68. offset 130h: pxserr[0-1] ? port [0-1] serial ata error register (sheet 1 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 130h, 1b0h 133h, 1b3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 diag diagnostics (diag) - contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes: 0000h rwc bits description 31:2 7 reserved 26 exchanged (x): when set to ?1? this bit indicates a cominit signal was received. this bit is reflected in the interrupt register pxis. pcs. 25 unrecognized fis type (f): indicates that one or more fiss were received by the transport layer with good crc, but had a type field that was not recognized/known. 24 transport state transition error (t): indicates that an error has occurred in the transition from one state to another within the transport layer since the last time this bit was cleared. 23 link sequence error (s): indicates that one or more link state machine error conditions was encountered. the link layer state machine defines the conditions under which the link layer detects an erroneous transition. 22 handshake error (h): indicates that one or more r_err handshake response was received in response to frame transmission. such errors may be the result of a crc error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c): indicates that one or more crc errors occurred with the link layer. 20 disparity error (d): this field is not used by ahci. 19 10b to 8b decode error (b): indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w): indicates that a comm wake signal was detected by the phy. 17 phy internal error (i): indicates that the phy detected some internal error. 16 phyrdy change (n): when set to 1 this bit indicates that the internal phyrdy signal changed state since the last time this bit was cleared. in the ich6, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in the pxis.prcs interrupt status bit and an interrupt will be generated if enabled. software clears this bit by writing a 1 to it.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 871 intel ? ep80579 integrated processor 15 : 00 err error (err): the err field contains error information for use by host software in determining the appropriate response to the error condition. if one or more of bits 11:8 of this register are set, the controller will stop the current transfer. 0000h rwc table 23-68. offset 130h: pxserr[0-1] ? port [0-1] serial ata error register (sheet 2 of 2) description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 130h, 1b0h 133h, 1b3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access bits description 15:12 reserved 11 internal error (e): the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p): a violation of the serial ata protocol was detected. 9 persistent communication or data integrity error (c): a communication error that was not recovered occurred that is expected to be persistent. persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t): a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m): communications between the device and host was temporarily lost but was re-established. this can arise from a device temporarily being removed, from a temporary loss of phy synchronization, or from other causes and may be derived from the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i): a data integrity error occurred that was recovered by the interface through a retry operation or other recovery action.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 872 order number: 320066-003us 23.3.4.6 offset 134h: pxsact[0-1] ? port [0-1] serial ata active register 23.3.4.7 offset 138h: pxci[0-1] ? port [0-1] command issue register table 23-69. offset 134h: pxsact[0-1] ? port [0-1] serial ata active register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 134h, 1b4h 137h, 1b7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ds device status (ds): system software sets this bit for random queuing operations prior to setting the pxci.ci bit in the same command slot entry. this field is cleared via the set device bits fis. this field is also cleared when pxcmd.st is cleared by software. note that this field is not cleared by comreset or srst. 0h rws table 23-70. offset 138h: pxci[0-1] ? port [0-1] command issue register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 138h, 1b8h 13bh, 1bbh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ci commands issued (ci): this field is set by software to indicate to the hba that a command has been built in system memory for a command slot and may be sent to the device. when the hba receives a fis which clears the bsy, err, and drq bits for the command, it clears the corresponding bit in this register for that command slot. this field is also cleared when pxcmd.st is written from a ?1? to a ?0? by software. 0h rws
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 873 intel ? ep80579 integrated processor 23.3.4.8 offset 13ch: pxsntf[0-1] ? port [0-1] snotification register 23.4 overview the sata host controller contains two modes of operation ? a legacy mode using i/o space, and an ahci mode using memory space. the memory space bit ghc.ae, set by software, indicates to hardware that ahci is being used. software must not implement code which mixes the use of legacy mode and ahci mode. 23.5 legacy operation in this mode of operation, software is performing i/o operations to the controller and sata devices. the sata controller is using the shadow registers as described in the sata specification , and performing master/slave operation on the ports. the ep80579 does not support slave operations. software must program the dev bit in the task file as its first operation before programming the rest of the transfer or setting the bus master registers. 23.5.1 transfer examples 23.5.1.1 register fis only if software only wishes to send a command to the sata device, and does not wish for any atapi or data transfer to occur, it will perform pio operations, setting up the required fields for the command, and either writing to the command register (1f7h for primary, 177h for secondary) or control register (3f6h for primary, 376h for secondary). hardware will send the register fis with the appropriate field set for command or control block, and upon reception of the device-to-host register fis indicating command completion, will update the shadow block. table 23-71. offset 13ch: pxsntf[0-1] ? port [0-1] snotification register description: view: pci bar: abar bus:device:function: 0:31:2 offset start: offset end: 13ch, 1bch 13fh, 1bfh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h ro 15 : 00 pmn_15_0 pm notify (pmn[15:0]): this field indicates whether a particular device with the corresponding pm port number issued a set device bits fis to the host with the notification bit set. pm port 0h sets bit 0 ? pm port fh sets bit 15 individual bits are cleared by software writing 1?s to the corresponding bit positions. note that, while this field is reset to default on a hba reset, it is not reset by comreset or srst. 0000h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 874 order number: 320066-003us 23.5.1.2 non-queued dma data transfers the following sections describe a data transfer to and from a device using dma as the command type. these transfers are all non-queued. 23.5.1.2.1 ata ? data from memory to device part i - software actions ? command start 1. software sets up a prd table in memory, with one or more entries to accomplish the data transfer of the full command. software places the address for this table prd base register. 2. software writes to the task file to set up the command, with the final write being to the command register (1f7h, 177h). 3. software sets the ?start? bit in the sata host controller. this step can be swapped with the previous step, since no action is taken until the data transfer is to begin. part ii - hardware actions ? command start upon seeing the command register written, hardware sends the register fis to the device, and awaits reception of a pio setup fis, device-to-host register fis, dma activate fis, or data fis. part iii - hardware actions ? data transfer 1. since the direction of the transfer is from the host to the device (and the command was a dma command), hardware will receive a dma activate fis. 2. upon reception, if the ?start? bit has been set, hardware begins fetching data from the locations specified in the prd table. (hardware could, and for performance reasons should, have started fetching data prior to seeing the device-to-host register fis described in part ii). 3. hardware formulates a data fis and begins transmitting data to the device. 4. hardware continues fetching prds as they become exhausted and fetching data from prd locations, until the transfer is complete. if the transfer is small enough, this data may fall under a single data fis. the sata host controller will send fises of maximum size to minimize fis overhead on the data transfer. part iv - hardware actions ? command wrap-up 1. after the last piece of data has been accepted by the device, hardware awaits a device-to-host register fis. 2. when the register fis is received, hardware updates its task file shadow block. part v - software actions ? command wrap-up 1. reading device status and bmide status. 2. complete request to os. 3. error handling may occur, including device reset & dma engine re-initialization. 23.5.1.2.2 ata ? data from device to memory the ata device-to-memory command is exactly the same as the ata memory-to- device command, except that in part iii, hardware is receiving data fises and writing data to memory, instead of fetching data from memory and sending data fises. the number of data fises used is device specific. additionally, a dma activate fis will not be received ? the device will simply start sending a data fis.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 875 intel ? ep80579 integrated processor 23.5.1.2.3 atapi atapi dma transfers are a combination of a pio write command for the packet command transfer, followed by a dma command for the data transfer. see those sections for a detailed explanation. pio data transfers are covered below. 23.5.1.2.4 write to device part i - software actions ? command start software writes to the task file to set up the command, with the final write being to the command register (1f7h, 177h). part ii - hardware actions ? command start 1. upon seeing the command register written, hardware sends the register fis to the device, and awaits reception of either a pio setup fis or a device-to-host register fis. 2. upon reception of the pio setup fis (since the command was a pio command), hardware updates the shadow block with the contents of the fis and the current status, and holds the e-status in reserve. if the ?i? bit was set, it generates an interrupt. part iii - hardware / software actions ? data transfer software writes to the data port as 16-bit quantities. hardware assembles these writes into its fifo, and formulates a single data fis to transmit the data. if software falls behind the data transmission rate of the interface (very likely), hardware will insert idle characters. part iv - hardware actions ? command wrap-up after the last piece of data has been accepted by the device, hardware updates the shadow block?s status register with the e-status field. part v - software actions ? command wrap-up 1. reading device status and bmide status 2. complete request to os 3. error handling may occur, including device reset & dma engine re-initialization. 23.5.1.2.5 read from device the read ata command is exactly the same as the write ata command, except that in part iii, hardware is receiving the data fis and writing data to memory, instead of fetching data from memory and sending a data fis. 23.5.1.3 sw assisted queued dma transfer in this mode of operation, sw supports queuing, the sata device supports queuing, but the sata host controller does not. there are two general flows, one for a device that does not support the dma setup fis, and one for a device that does support the dma setup fis: in both cases, sw is doing the work to determine the tag of the transfer. no special hardware action is taken by the sata host controller.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 876 order number: 320066-003us 23.5.2 error handling 23.5.2.1 errors on dmi errors on the memory interface will cause the following behavior: 23.5.2.2 errors on sata interface there are several errors that can occur on the sata interface which may interrupt a data transfer. there are two aspects from the following tables that are important when. ? errors that occur during dma data in transfers (device sending data) that will result in data corruption will set the bus master error status bit (bit 1 of i/o offset 01h for primary, bit 1 of i/o offset 05h for secondary), while it may or may not set the bit during other cases. if the sata device generates r_err on dma data out transfers (host sending data), the bus master error status bit will be set, while it may or may not be set on other transfers. ? errors that occur in pio or dma data in transfers (device generating data) that will result in data corruption will cause the sata host controller to generate r_err on the sata interface. if the bus master error bit does get set for pio transfers or non-data portions, it is acceptable. ta b l e 1 4 4 8 breaks out conditions for the above rules. additionally, other errors that may occur are listed for information purposes. cycle type address/cmd parity error data parity error tabort mabort i/o, config write set dpe bit do not claim cycle set dpe bit claim cycle, data dropped return completion success na na i/o, config read set dpe bit do not claim cycle na na na memory write (to hc) not supported na na na memory read (to hc) na na na na memory write (from hc) na na na mai not supp memory read (from hc) na na na mai not supp i/o, cfg completion (read and write) na na na mai not supp mem. read comp. (from hc) na na na mai not supp mem. read comp. (to hc) ?set dpe, ? do not claim cycle ? set error bit in bus master i/o space, offset 02h, bit 1 ? stop dma engine needs a system reset to recover set dpe & dpd, claim cycle ? during prd data transfer, abort dma operation and set error bit in bus master i/o space; ? during dma data transfer, propagate the error to the device through crc error without setting error status bit. set rta bit. set error bit and abort set rma bit. set error bit and abort
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 877 intel ? ep80579 integrated processor table 23-72. errors during non-data fis reception error type host controller behavior received disparity error / illegal character (k28.3) assume character is correct. reset disparity counter. do not set bus master error bit. do not return r_err (still check for crc errors). received disparity error / illegal character (d) return r_err at end of fis. do not set bus master error bit. (device will retry) calculated different crc than received or malformed fis received 1 return r_err at end of fis. do not set bus master error bit. (device will retry) phyready dropping unexpectedly send aligns and return link fsm to idle. do not set bus master error bit. (device will retry) illegal fis length for corresponding fis type 2 return r_err at end of fis. do not set bus master error bit. (device will retry). table 23-73. errors during pio data fis reception error type host controller behavior received disparity error/ / illegal character (k28.3) assume character is correct. reset disparity counter. do not set bus master error bit. do not return r_err (still check for crc errors). received disparity error / illegal character (d) return r_err at end of fis. do not set bus master error bit. (device will not retry) calculated different crc than received or malformed fis received return r_err at end of fis. do not set bus master error bit. (device will not retry) phyready dropping unexpectedly send aligns and return link fsm to idle. do not set bus master error bit. (device will not retry) length of pio data fis not matching transfer count in pio_setup fis return r_err at end of fis. do not set bus master error bit. (device will not retry). table 23-74. errors during dma data fis reception error type host controller behavior received disparity error / illegal character (k28.3) assume character is correct. reset disparity counter. do not set bus master error bit. do not return r_err (still check for crc errors). received disparity error / illegal character (d) return r_err at end of fis. set the bus master error bit. (device will not retry) calculated different crc than received or malformed fis received or internal buffer overflows (which could be caused by device violating hold-holda latency) return r_err at end of fis. set the bus master error bit. (device will not retry) phyready dropping unexpectedly send aligns and return link fsm to idle. set the bus master error bit. (device will not retry)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 878 order number: 320066-003us 23.5.3 hot plug operation dynamic hot plug (such as surprise removal) is not supported in legacy mode. however, using the pcs register configuration bits, and power management flows, a device can be powered down by software, and the port can then be powered off, allowing removal and insertion of a new device. 23.5.4 48-bit (?large?) lba operation requirements the sata host controller supports 48-bit lba through the host-to-device register fis when accesses are performed via writes to the task file. the sata host controller will ensure that the correct data is put into the correct byte of the host-to-device fis as follows: if only one write is performed, the data goes to the location specified; if a second write is performed, the data from the first write is shifted into the ?upper? location, and the data from the second write goes to the location specified. suppose a sequence of writes occurred to the taskfile as follows: ? 1f2h (sector count)- 21h ? 1f2h (sector count) - 22h ? 1f3h (sector number - 31h ? 1f3h (sector number) - 32h ? 1f4h (cylinder low) - 41h ? 1f4h (cylinder low) - 42h ? 1f5h (cylinder high) - 51h ? 1f5h (cylinder high) - 52h the resulting fis when the command or control register is written will have the following values: table 23-75. errors during unknown fis type 3 reception error type host controller behavior unknown fis type the unknown fis type is itself an error condition, and will result in bus master error bits being set and r_err being returned. table 23-76. errors during fis transmission error type host controller behavior non-data fis: received r_err (includes link protocol errors during transmission), or phyrdy dropping unexpectedly retry the fis. data fis: received r_err (includes link protocol errors during transmission), or phyrdy dropping unexpectedly set the bus master error bit. do not retry the fis. notes: 1. malformed fis = fis not constructed according to link layer protocols 2. illegal length for corresponding fis type; for example the following fis types and their corresponding lengths: d2h dma_activate fis length = 1dw d2h register fis = 5 dw d2h pio_setup fis = 5dw d2h set-device-bits = 2dw d2h bist fis = 3dw 3. zero-length d2h data fis (i.e. data fis header immediately followed by crc), and any d2h data fis following a d2h dma_activate fis are treated as unknown fis types for all purposes.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 879 intel ? ep80579 integrated processor the writes do not have to come in any specific order. all that is necessary is that the writes to these registers act as a fifo ? the second write moves data from the first write into a new location. there are also special considerations when reading from the task file to support 48-bit lba operation. software may need to read all 16-bits. since the registers are only 8- bits wide and act as a fifo, a bit must be set in the device/control register, which is at offset 3f6h for primary and 376h for secondary (or their native counterparts). if software clears bit 7 of the control register before performing a read, the last item written will be returned from the fifo. if software sets bit 7 of the control register before performing a read, the first item written will be returned from the fifo. 23.5.5 power management operation 23.5.5.1 introduction power management of the sata controller and ports will cover operations of the host controller and the sata wire. this specification does not cover any power management that an sata device may do internally that is transparent to the interface. 23.5.5.2 power state mappings the pci specification defines power management states for devices, which will be applied to the sata host controller. they are: ? d0 ? working (required). ? d1 ? light sleep (not supported). ? d2 ? deeper sleep (not supported). ? d3 ? very deep sleep (required). this state is split into two sub-states, d3 hot (can respond to pci configuration accesses) and d3 cold (cannot respond to pci configuration accesses). these two sub-states are considered the same, where d3 hot has v cc , but d3 cold does not. this is the only state allowed for the host controller when the system is in an s1-s5 state. sata devices may also have multiple power states. from parallel ata, three device states are supported through acpi. they are: ? d0 ? device is working and instantly available. ? d1 ? device enters when it receives a standby immediate command. exit latency from this state is in seconds. ? d3 ? from the sata device?s perspective, no different than a d1 state, in that it is entered via the standby immediate command. however, an acpi method is also called which will reset the device and then cut its power through proprietary chipset methods. (in ich, this included setting the tri-state bits of the interface, a gpio which reset the device, and a gpio to cut power to that device. dw 0 features command c 0000000 fis type (27h) 1 dev / head cyl high (52h) cyl low (42h) sector number (32h) 2 features (exp) cyl high exp (51h) cyl low exp (41h) sector num exp (31h) 3 control reserved (0) sector count exp (21h) sector count (22h) 4 reserved (0) reserved (0) reserved (0) reserved (0)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 880 order number: 320066-003us each of these device states are subsets of the host controller?s d0 state. this is partially because host controllers (as integrated in intel components) have not supported host- based power management, and also because the device must be put into one of the lower power states before power could be removed from the host. finally, sata defines three phy layer power states, which have no equivalent mappings to parallel ata. they are: ? phy ready ? phy logic and pll are both on and active. ? partial ? phy logic is powered, but in a reduced state. exit latency is no longer than 10s. ? slumber ? phy logic is powered, but in a reduced state. exit latency can be up to 10ms. since these states have much lower exit latency than the acpi d1 and d3 states, the sata controller defines these states as sub-states of the device d0 state. figure 23-1 is an hierarchical view of sata power states. 23.5.5.3 power state transitions transitioning between various states is initiated by different levels of software and hardware. 23.5.5.3.1 partial and slumber state entry/exit the partial and slumber states are viewed as cheap and easy mechanism to save interface power when the interface is idle. the sata controller defines phy layer power management (as performed via primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. the sata controller will accept device transition types, but will not issue any transitions as a host. all received requests from an sata device will be acked. when an operation is performed to the sata controller such that it needs to use the sata cable, the controller must check whether the link is in the partial or slumber states, and if so, must issue a com_wake to bring the link back online. similarly, the sata device must perform the same action. figure 23-1. legacy mode host controller power state hierarchy host = d0 device = d3 power resume latency host = d3 device = d3 phy = off device = d0 phy = ready device = d1 phy = slumber phy = partial phy = off (port disabled) phy = slumber phy = off (port disabled) phy = slumber phy = off (port disabled)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 881 intel ? ep80579 integrated processor 23.5.5.3.2 device d1, d3 states these states are entered after some period of time when software has determined that no commands will be sent to this device for some time. the mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. the command most likely to be used in ata/atapi is the ?standby immediate? command. 23.5.5.3.3 host controller d3 state after the interface and device have been put into a low power state, the host controller may be put into a low power state. this is performed via the pci power management registers in configuration space. there are two very important aspects to note when using pci power management. 1. when the power state is d3, only accesses to configuration space are allowed. any attempt to access the memory or i/o spaces must result in master abort. 2. when the power state is d3, no interrupts may be generated, even if they are enabled. if an interrupt status bit is pending when the controller transitions to d0, an interrupt may be generated. when the controller is put into d3, it is assumed that software has properly shut down the device and disabled the ports. therefore, there is no need to sustain any values on the port wires. the interface will be treated as if no device is present on the cable, and power will be minimized. when returning from a d3 state, an internal reset will not be performed. when in legacy mode of operation, the sata controller does not generate pme#. this includes attach events (since the port must be disabled), or interlock switch events (via the satagp pins). 23.5.5.4 smi trapping (apm) the atc register in configuration space contains control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges only (1f0h-1f7h, 3f4h-3f6h, 170h-177h, and 374h-376h). trapping will not occur on the native ide ranges defined by pcmdba, pctlba, scmdba, sctlba, or lbar. if the sata controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set will cause the cycle to not be forwarded to the sata controller, and for smi# to be generated. smi trapping is specifically supported in the following configurations: ? sata controller in legacy addressing mode (non-combined). additionally, an ats register bit will get set on an access to these ranges if the corresponding bit in the atc register is set.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 882 order number: 320066-003us 23.5.6 interrupt architecture ta b l e 2 3 - 7 7 summarizes interrupt behavior for msi and wire-modes. in the table ?bits? refers to the 4 possible interrupt bits in i/o space, which are: psts.prdis (offset 02h, bit 7), psts.i (offset 02h, bit 2), ssts.prdis (offset 0ah, bit 7), and ssts.i (offset 0ah, bit 2). 23.5.7 staggered spin-up to support staggered spin-up with legacy software, the ahci memory space register hcap.sss must be cleared, and the configuration register pcs is used to enable/disable the port. 23.5.8 hw/sw operation for detecting an sata device presence 23.5.8.1 introduction in legacy mode, the sata controller does not generate interrupts based on hot plug/ unplug events. however, the sata phy does know when a device is connected (if not in a partial or slumber state), and it is beneficial to communicate this information to host software as this will greatly reduce boot times and resume times. 23.5.8.2 hardware flow the flow for using these bits is shown in ta bl e 2 3 - 2 . the ?pxe? bit refers to pcs.p0e, and pcs.p1e bits, depending on the port being checked, and the ?pxp? bit refers to the pcs.p0p, and pcs.p1p bits, depending on the port being checked. table 23-77. msi vs. pci irq actions interrupt register wire-mode action msi action all bits ?0? wire inactive no action one or more bits set to ?1? wire active send message one or more bits set to ?1?, new bit gets set to ?1? wire active send message one or more bits set to ?1?, software clears some (but not all) bits wire active send message one or more bits set to ?1?, software clears all bits wire inactive no action software clears one or more bits, and one or more bits is set on the same clock. wire active send message
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 883 intel ? ep80579 integrated processor notes: 1. the sata host controller?s comreset length will be 6 data bursts. 23.5.8.3 software flow the software flow will be as follows: ? sometime after power-on reset or resume from suspend, software will set the pcs.pxe bits, depending on which ports it wants to scan. they can both be set together. ?the sata specification indicates that the comreset sequence to device detection is to be 880 us. for best results, software should wait some period longer than this, such as 10 ms. ? software will read the pcs.pxp bits. if the bit is set, a device is present. if the bit is cleared, a device is not present. if a port was disabled, software checks to see if a new device is connected by periodically re-enabling the port, and waiting 2-3ms to see if a device is present. if one is not, it can disable the port and check again later. if a port remains enabled, software can periodically poll pcs.pxp to see if a new device is connected. 23.5.9 smi generation the sata controller can generate smis on behalf of accesses to the task file. these smis are used to support legacy operating systems running apm (advanced power management). these smis are not used when the controller is an acpi or pci power managed device. to support smi generation, trap registers exist in power management space. these registers can be found at the pmbase + 48h region. the register bits are: d0_trp_en: primary ide master (port 0) d1_trp_en: primary ide slave (port 1) figure 23-2. hardware flow for port enable/device present bits pxp bit set by hba device tx (host rx) host tx (device rx) pxe bit set by software host comreset host releases comreset host calibrate host comwake host releases comwake host align host data device cominit device releases cominit device calibrate device comwake device align device data host d10.2
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 884 order number: 320066-003us these bits, when set, affect the legacy ide ranges 1f0h ? 17fh, 3f6h, 170h ? 17fh, 376h, and the range pointed to by the lbar register in configuration space. if native ide is enabled, trapping will not be performed. if ahci is enabled, trapping will not be performed. 23.5.10 led the led must be driven whenever the bsy bit is set in either port. the led output will go directly to sataled#, an active-low open-collector output. when sataled# is low, the led is active. when sataled# is tri-stated, the led is inactive. 23.6 ahci operation 23.6.1 system memory structures the serial ata controller supports 2ports, and each port supports 32 commands. the command list and received fis may live in 64-bit space figure 23-3. port system memory structure generic host control reserved port 0 port 1 reserved memory registers 00h 10h 100h 180h 280h 3ffh configuration registers abar hba registers system memory command list ( port 0 ) command list ( port 1 ) received fis structure ( port 0 ) received fis structure ( port 1 )
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 885 intel ? ep80579 integrated processor 23.6.2 error reporting and recovery error reporting and recovery all errors within an hba occur within ports. there are no errors that apply to the entire host controller. 23.6.2.1 error types 23.6.2.1.1 system memory errors system memory errors such as target abort, master abort, and parity may cause the host to stop processing the currently running command. these are serious errors that cannot be recovered from wi thout software intervention. a master/target abort error occurs when system software has given a pointer to the hba that does not exist in physical memory. when this occurs, the hba aborts the transfer (if necessary). when this is complete, the hba sets pxis.hbfs. if pxie.hbfe and ghc.ie are set, the hba shall also generate an interrupt. a data error (such as crc or parity), may or may not be transient. if the error occurred on a fetch of a cfis, prd entry or command list, the hba shall stop. if the error occurred on a data fis or the acmd field, the hba is allowed to stop, but may also continue. when a data error occurs, the hba aborts the transfer (if necessary). when this is complete, the hba sets pxis.hbds. if pxie.hbde and ghc.ie are set, the hba shall also generate an interrupt. if the hba continue after a data error on a data or acmd field, it shall poison the crc of the data fis it transfers to the device. 23.6.2.1.2 interface errors interface errors are errors that occur due to electrical issues on the interface, or protocol miscommunication between the device and hba. depending on the type of error, different bits in the pxserr register are set. when these bits are set, either pxis.ifs (fatal) or pxis.infs (non-fatal) shall be set, and if enabled, the hba shall generate an interrupt. conditions that cause pxis.ifs/pxis.infs to be set are: ? in the pxserr.err field, the p bit is set to '1' ? in the pxserr.diag field, the c or h bit is set to '1' ? phyrdy drops unexpectedly examples of these types of errors are below, with the corresponding pxserr bit that is set if appropriate. the only difference between pxis.ifs and pxis.infs being set is the type of fis that is being transmitted/received when the error occurs. if the error occurred during a non- data fis, the fis must be retransmitted, so the error is non-fatal and pxis.infs is set. if the error occurred during a data fis, the transfer shall stop, so the error is fatal and pxis.ifs is set. in the case of a non-data fis error, between seeing a non-data fis fail and the attempt to re-transmit, the hba may receive other fises from the device (this will most likely happen when performing native command queuing commands). when this occurs, the hba must accept the fis, perform the correct actions, and then retry the failed fis.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 886 order number: 320066-003us if the hba was transmitting a data fis it does not retry the fis and waits for software to clear the pxcmd.st bit to '0'. the hba shall retransmit a non-data fis continuously after a failure until either the transfer succeeds or system software stops the controller by clearing pxcmd.st to '0'. ? received disparity error / illegal character (k28.3): when a disparity error is encountered, the hba assumes the disparity of this character is correct and resets the running disparity counter in the 8b/10b decoder. no error bits are set. ? received disparity error / illegal character (d): when this occurs, the hba returns r_err at the end of the fis. it sets pxserr.diag.b. note that pxis.ifs/pxis.infs shall not be set; the crc error that is likely to occur due to this event will set the appropriate bit. if there is an illegal character outside the fis boundaries, the hba may ignore the event and is not required to set pxserr.diag.b. ? phyrdy dropping unexpectedly: when this occurs, the hba returns to idle. if the phyrdy signal dropped during the middle of a command, the hba may have to be restarted. if the phyrdy signal dropped outside of a fis, neither the pxis.ifs nor the pxis.infs bits shall be set. ? calculated different crc than received: when this occurs, the hba returns r_err and returns to idle. it sets pxserr.diag.c ? incorrect fis or fis with illegal length for corresponding fis type received: when this occurs, the hba returns r_err at end of the fis, shall not post the fis to memory, and returns to idle. it sets pxserr.err.p. this can only be done for supported fis types. an unknown fis is not considered an illegal fis, unless the length received is more than 64 bytes. if an unknown fis arrives with length <= 64 bytes, it is posted and the hba continues normal operation. ? internal buffer overflow: this occurs when the hba sends a hold, but a holda was not received quickly enough by the hba, and the hba?s internal data fifos overflow. the hba returns r_err at the end of the fis. it sets pxserr.err.p. ? hba receives r_err: if the hba receives an r_err to a fis it was transmitting, it sets pxserr.diag.h. ? fis received from a device, where both bsy and drq are to be updated in the status register and both pxtfd.sts. bsy and pxtfd.sts.drq are cleared: when this occurs, the hba returns r_ok, does not set any error bits, and does not update any registers or the received fis area based on the received fis (i.e. the fis is ignored). ? it is system software's responsibility to check the pxserr register periodically to determine if the interface is operating cleanly, and take appropriate actions (such as going down to generation1 speed if operating at a higher speed or notifying the user) when interface errors occur. 23.6.2.1.3 device errors when a fis arrives that updates the taskfile, the hba checks to see if pxtfd.sts.err is set. if it is, and pxie.tfee is set, the hba shall generate an interrupt and stop processing any more commands. 23.6.2.1.4 command list overflow command list overflow is defined as software building a command table that has fewer total bytes than the transaction given to the device. on device writes, the hba will run out of data, and on reads, there will be no room to put the data.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 887 intel ? ep80579 integrated processor for an overflow on data read, either pio or dma, the hba shall set pxis.ofs, and if enabled via pxie.ofe and ghc.ie, generate an interrupt. when this condition occurs on data reads, the hba shall make a best effort to continue, however the hba may not be able to recover without software intervention. overflow is a serious error, thus software should perform a fatal error recovery procedure to ensure that the hba is brought back to a known condition before continuing. for an overflow on writes, the hba may transmit holds to the device since it does not have any data to satisfy the request size; a comreset is required by software to clean up from this serious error. for an overflow on data writes with dma, the hba does not know there is more data until it receives the next dma activate. when this occurs, it may optionally set pxis.ofs and attempt to terminate the transfer. however, this is a fatal condition, and an hba is allowed to hang on the transfer. for pio writes, the hba receives the pio setup fis and therefore knows the length, and therefore may optionally set pxis.ofs. however, by not satisfying the length, the transfer shall end in an error, and software must recover. therefore setting pxis.ofs is optional for both dma and pio data write conditions. detecting overflow and setting pxis.ofs on native command queuing commands is optional. 23.6.2.1.5 command list underflow command list underflow is defined as softwa re building a command table that has more total bytes than the transaction given to the device. for data writes, both pio and dma, the device shall detect an error and end the transfer. these errors are most likely going to be fatal errors that will cause the port to be restarted. for data reads, the hba shall update its prd byte count with the total number of bytes received from the last fis, and may be able to continue normally, but is not required to. the hba is not required to detect underflow conditions for native command queuing commands. 23.6.2.1.6 native command queuing tag errors the hba does not actively check incoming dma setup fises to ensure that the pxsact register bit for that slot is set. the reason for this is if the device gives an in correct tag, it could just as likely be for a tag that is active. in this case, the hba would see no error, although the data transfer that occurs is incorrect. therefore, there is little benefit in the hba checking for inactive tags. just as in the wrong active tag case, the data transfer that occurs will be incorrect. existing error mechanisms, such as host bus failure, or bad protocol, are used to recover from this case. 23.6.2.1.7 pio data transfer errors in accordance with serial ata 1.0a, data fises prior to the final data fis must be an integral number of dwords. if the hba receives an intermediate data fis transfer request that is not an integral number of dwords, the hba shall set pxserr.err.p to '1', set pxis.ifs to '1' and stop running until software restarts the port. the hba shall ensure that the size of the data fis received during a pio command matches the size in the transfer count field of the preceding pio setup fis. if the data fis size does not match the transfer count field in the preceding pio setup, the hba shall respond with r_err to the data fis, set pxserr.err.p to '1', set pxis.ifs to '1', and then stop running until software restarts the port.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 888 order number: 320066-003us 23.6.2.2 error recovery 23.6.2.2.1 hba aborting a transfer when the hba detects an error that it cannot recover from, it may need to end the transfer on the sata interface. to do this, the hba asserts sync escape to stop the bad fis, and when the device is quiescent, returns to idle. the sata device should send a d2h register fis at this point, with the err bit set to indicate an error in the transfer. when aborting a transfer, the hba does not wait for the d2h register fis before proceeding with error recovery (such as setting interrupt status bits and generating interrupts). this is because a device may be in a hung condition and cannot generate the d2h register fis. 23.6.2.2.2 software error recovery when an interrupt is generated due to an error condition, software will attempt to recover. fatal errors (signified by the setting of pxis.hbfs, pxis.hbds, pxis.ifs, or pxis.tfes) will cause the hba to enter the err:fatal state, and clear pxcmd.cr. in this state, the hba shall not issue any new commands nor acknowledge dma setup fises to process any native command queuing commands. to recover, the port must be restarted; the port is restarted by clearing pxcmd.st to '0' and then setting pxcmd.st to '1'. for non-fatal errors (signified by the setting of pxis.infs or pxis.ofs) the hba continues to operate. if the transfer was aborted, the device is expected to send a d2h register fis with pxtfd.sts.err set to '1' and both pxtfd.sts.bsy and pxtfd.sts.drq cleared to '0'. under this scenario, system software knows that the device is in a stable state and transfers may be restarted without issuing a comreset to the device. no fis will be posted and no register updates will be done based on fises received after a fatal error has occurred. received fises will not be acted on until a comreset or a new command is sent to the device, after the error is recovered from appropriately including clearing the pxcmd.st bit. for fatal errors, software must determin e which commands were not processed and either re-issue them or notify higher level software that the command failed. to detect an error that requires software recovery actions to be performed, software should check whether any of the following status bits are set on an interrupt: pxis.hbfs, pxis.hbds, pxis.ifs, and pxis.tfes. if any of these bits are set, software should perform the appropriate error recovery actions based on whether non-queued commands were being issued or native command queuing commands were being issued. 23.6.3 hot plug operation if hcap.sis is set, the sata controller uses the satagp[3:0] pins as interlock switches. the ep80579 supports hot plug surprise removal notification. however hot plug surprise removal notification (without an interlock switch) is mutually exclusive with the partial and slumber power management states.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 889 intel ? ep80579 integrated processor 23.6.4 power management operation 23.6.4.1 introduction this section covers power management of the hba and the serial ata interface. this specification does not cover any power mana gement that a serial ata device may do internally that is transparent to the interface. 23.6.4.2 power state mappings the pci specification defines power management states for devices, which shall be applied to the hba. they are: ? d0 - working (required). ? d1 - not defined for storage hbas. ? d2 - not defined for storage hbas. ? d3 - very deep sleep (required). this state is split into two sub-states, d3hot (can respond to pci configuration accesses) and d3cold (cannot respond to pci configuration accesses). these two sub-states are considered the same, where d3hot has vcc, but d3cold does not. pxcmd.st must be cleared to '0' before entering the d3 power state. serial ata devices may also have multiple power states. each of these device states are subsets of the hba's d0 state. they are: ? d0 - device is working and instantly available. ? d1 - device enters when it receives a standby immediate command. exit latency from this state is in seconds. ? d2 - not currently defined for serial ata devices. ? d3 - device enters when it receives a sleep command. exit latency from this state is in seconds. finally, serial ata defines three phy layer (or interface) power states. they are: ? phy ready - phy logic and pll are both on and active. ? partial - phy logic is powered, but in a reduced state. exit latency is no longer than 10s. ? slumber - phy logic is powered, but in a reduced state. exit latency can be up to 10ms. since these states have much lower exit latency than the d1 and d3 states, ahci defines these states as sub-states of the device d0 state. the following picture gives a hierarchical view of power states of serial ata.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 890 order number: 320066-003us note: the phy is not required to be in a slumber state when the device is in a d1 or d3 state, nor is it required to be in a slumber state when the hba is in a d3 state. while this may be the likely condition of the interface when the devices connected to the interface are in a low power state, it is not a requirement, and the interface shall break out of these states on a power management event. 23.6.4.3 power state transitions 23.6.4.3.1 interface power management the serial ata 1.0a specification defines two lower power interface power management states, partial and slumber, in order to save power on the serial ata link in power sensitive systems. the partial and slumber interface power management states can be initiated by software, the hba itself, or by the device. the interface power management state is negotiated between the host and the device on the interface using serial ata primitives. any request can be accepted (using the pmack primitive) or rejected (using pmnack primitives) based upon current conditions and settings in the device and hba. the current interface power management state is reflected to software in pxssts.ipm. device initiated by default, a device that supports initiating interface power management states has the capability disabled. to enable this feature, the appropriate set features command may be issued to the device. the hba shall respond to device initiated power management requests as specified by pxsctl .ipm. a request from the device to enter an interface power management state may be rejected by the hba if the hba needs to transmit a fis to the device. system software initiated pxcmd.icc is used by system software to initiate interface power management state transitions. the request to transition to a different interface power management state shall only be acted on by the hba if the link layer is currently in the l_idle state. if the hba's link layer is not in the l_idle state when the pxcmd.icc field is written, the request shall be ignored. the hba shall not perform a transition directly from partial to slumber or from slumber to partial based on a new value being written to pxcmd.icc. if the link is currently in a partial or slumber interface power management state, it is software's responsibility to bring the link to the active state before requesting a figure 23-4. power state hierarchy hba = d3 device = d3 hba = d0 device = d0 phy = ready device = d3 device = d1 phy = slumber (see note) phy = slumber phy = partial phy = slumber (see note) phy = slumber (see note) resume latency power
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 891 intel ? ep80579 integrated processor transition to a different interface power management state. the time from the request written to pxcmd.icc until the link is active is bounded by the maximum recovery times from partial or slumber as outlined in the serial ata 1.0a specification . hba initiated the hba may implement aggressive power management, as indicated in hcap.salp. aggressive power management allows the hba to initiate an interface power management state as soon as there are no commands outstanding to the device. this enables immediate entry into the low power interface state without waiting for software in power sensitive systems. the pxcmd.alpe bit defines whether the feature is enabled and the pxcmd.asp field controls whether partial or slumber is initiated by the hba when enabled. when pxcmd.alpe is set to '1', if the hba recognizes that there are no commands to process, the hba shall initiate a transition to partial or slumber interface power management state based upon the setting of pxcmd.asp. the hba recognizes no commands to transmit as either: ? pxsact is set to 0h, and the hba updates pxci from a non-zero value to 0h. ? pxci is set to 0h, and a set device bits fis is received that updates pxsact from a non-zero value to 0h. if the pxsact and pxci registers are both cleared to 0h, and the interface is in an active state, the hba shall not initiate placing the interface into a lower power state, unless pxcmd.icc is written with an appropriate value. before performing a fis transmission, the hba must ensure the link is in the active state. if the link is in the partial or slumber interface power management state, a comwake must be issued, and the hba must wait until the link is active before proceeding with transmission of the fis. 23.6.4.3.2 software requirements and precedence software must check hcap.ssc (slumber capable) and hcap.psc (partial capable) to determine if the hba supports interface power management transitions as an initiator or a target. if an interface power management state is not supported, then software shall not write the pxcmd.icc field nor set the aggressive power management capability to initiate a transition to that state. software must set the pxsctl.ipm field to disable transition to any unsupported interface power management state. if hcap.ssc or hcap.psc is cleared to '0', software should disable device-initiated power management by issuing the appropriate set features command to the device. hba initiated interface power management requests are higher priority than software initiated requests. thus if the hba and software request transitions to different states at the same time, the hba's request shall take precedence over the software request. 23.6.4.3.3 device d1, d3 states the d1 and d3 device states are entered when system software has determined that no commands will be sent to the device for some time. to enter these states, software may perform two actions. the first is to issue a command to the device to enter the low power state (standy immediate for d1, sleep for d3), and the second step is to put the interface into a slumber power management state (by setting pxcmd.icc to 6h). note: it is recommended that the device initiate a slumber power management state when it receives a command to enter the d1 or d3 state.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 892 order number: 320066-003us 23.6.4.3.4 hba d3 state after the interface and device have been put into a low power state, the hba may be put into a low power state. this is performed via the pci power management registers in configuration space. ahci only supports the d3 state. there are two very important aspects to note when using pci power management. ? when the power state is d3, only accesses to configuration space are allowed. any attempt to access the register memory space must result in master abort. ? when the power state is d3, no interrupts may be generated, even if they are enabled. if an interrupt status bit is pending when the controller transitions to d0, an interrupt may be generated. software must disable interrupts (ghc.ie must be cleared to '0') prior to requesting a transition of the hba to the d3 state. this precaution by software avoids an interrupt storm if an interrupt occurs during the transition to the d3 state. pxcmd.st must be cleared to '0' before entry into the d3 power state. 23.6.4.4 pme when the hba is in the d3 state, it may optionally wake based on a change in the device state. pme must be generated when the hba is in the d3 state under the following conditions: ? pxis.pcs is set to '1' due to a native hot plug insertion. ? pxis.dis set, indicating an interlock switch has been opened or closed. ? pxis.cpds set, indicating cold presence detect state change. ? set device bits fis received on the interface with the t bit set to ?1? and the notification (?n?) bit also set to ?1?. if any of these bits are set, regardless of the setting of the enables in pxie and ghc.ie, the hba shall generate pme#. for the i 2 c approach, the sgpio control register is made visible in the smbus slave register space. sgpio control register is mapped to smbus slave registers at offset 9h, ah and bh. the sm link interface is externally connected to an unused smbus on the bmc. bmc will read the data, encapsulate it in the ipmi format and drive that data through another smbus or i 2 c bus to the gem controller. gem controller then updates the led drivers with the updated status. 23.7 additional information 23.7.1 mode switching software mode could change from one to another by manipulating the map register. there are some specific requirements for the register: ? map.sms and map.mv shall only be programmed to values that would result in legal cc.scc, did and pi values (see section 48.1.5.1). if map.sms and map.mv are not programmed correctly, hardware shall default the mode back to ide. ? map register must survive across d3hot to d0 power state transitions. ? map.sms shall not be manipulated during runtime operation; i.e. the os will not do this. however, the bios may choose to change it during post to switch to other software mode.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 893 intel ? ep80579 integrated processor when switching from one mode to another (via map.sms), the bios should ensure that lbar and abar configuration register at offset 20h and 24h are cleared correctly. the bios should also ensure that the function disable bits are set or cleared correctly. note that when cc.scc is not 01h, software could also 'change mode' from ide to ahci or vice versa by writing to the ae bit of ghc register. this change of software mode during run-time (by using ahci device driver) is not the kind of mode switching described in this section. 23.7.1.1 ahci mode ahci mode has the following requirements/characteristics: for ahci: ? default cc.scc = 06h ? default pi = 01h ? has a unique device id ? bar0 to bar4 (i.e. pcmdba, pctlba, scmdba, sctlba and lbar) are functional. ? bar5 (i.e. abar) is functional as a memory bar. ? msi is supported. ? map.sms is 01b for ahci mode. ? map.sms is not applicable when map.mv is 10b, indicating combined-mode, in mobile skus. ? bios should program map.mv, then only program map.sms to the desired but legal value. 23.7.1.2 ide mode ? ide mode has the following requirements/characteristics: ? d31f2 shall have cc.scc = 01h ? d31f2 shall support both native and legacy i/o access, indicating by a pi register default value of 8ah. ? msi is not supported. ? bar0 to bar4 (i.e. pcmdba, pctlba, scmdba, sctlba and lbar) are functional. ? bar5 is functional as an i/o bar that implements an index/data pair mechanism for accessing scontrol, serror and sstatus registers. ? map.sms must be 00b for ide mode. ? bios should program map.mv, then only program map.sms to the desired but legal value.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 894 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 895 intel ? ep80579 integrated processor 24.0 smbus controller functional description: bus 0, device 31, function 3 24.1 overview cmi?s iich contains an smbus host interface that allows the processor to communicate with smbus slaves. ta bl e 2 4 - 1 lists the smbus signals and the actions taken during various power events unless specified, all of smbus logic and registers in this chapter are reset by either cf9 reset or rsmrst#. 24.1.1 host controller the cmi provides a system management bus (smbus) specification, version 2.0 - compliant host controller. the host controller provides a mechanism for the processor to initiate communications with smb peripherals (slaves). the cmi is also capable of operating in a mode in which it can communicate with i 2 c compatible devices. the cmi can perform smbus messages with either pec enabled or disabled. the actual pec calculation and checking is performed in software. the smbus host controller logic can automatically append the crc byte if configured to do so. the cmi smbus logic exists in device 31, function 3 configuration space, and consists of a transmit data path and host controller. the transmit data path provides the data flow logic needed to implement the seven different smb command protocols and is controlled by the host controller. the logic is clocked by the rtc clock. the smbus address resolution protocol (arp) is supported through software by using the existing host controller commands, except for the new host notify command (which is actually a received message). the programming model of the host controller is combined into two portions: a pci configuration portion and a system i/o mapped portion. all static configuration, such as the i/o base address, is done via the pci configuration space. real-time programming of the host interface is done in system i/o space. table 24-1. smbus signals signal name power plane during reset after reset s3 s5 alt driver smbdata resume see note high-z high-z peripherals smbclk resume high-z high-z peripherals smbalert# resume can be driven high or low. peripherals note: smbdata and smbclk might go active if other devices are using the bus.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 896 order number: 320066-003us the host controller needs to check for parity errors as a target. if it sees an error, it must set the detected parity error bit (bit 15 of status). if bit 6 and bit 8 of the command register are set, it needs to generate serr#, and set the signalled serr# bit in the status register (bit 14). 24.1.2 slave interface the slave interface allows an external master to write or read. the write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. the internal host controller cannot access the internal slave interface. 24.2 smbus controller pci configuration register details address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values and are read-only. writes to reserved locations may cause system failure and unpredictable behavior. reserved bits are read only. table 24-2. bus 0, device 31, function 3: summary of smbus controller pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor id register? on page 897 8086h 02h 03h ?offset 02h: did: device id register? on page 897 5032h 04h 05h ?offset 04h: cmd: command register? on page 897 0000h 06h 07h ?offset 06h: ds ? device status register? on page 898 0280h 08h 08h ?offset 08h: rid: revision id register? on page 899 variable 09h 09h ?offset 09h: pi: programming interface register? on page 900 00h 0ah 0ah ?offset 0ah: scc: sub class code register? on page 900 05h 0bh 0bh ?offset 0bh: bcc: base class code register? on page 900 0ch 20h 23h ?offset 20h: sm_base: smb base address register? on page 901 00000001h 2ch 2dh ?offset 2ch: svid: svid register? on page 901 0000h 2eh 2fh ?offset 2eh: sid: subsystem identification register? on page 902 0000h 3ch 3ch ?offset 3ch: intln: interrupt line register? on page 902 00h 3dh 3dh ?offset 3dh: ntpn: interrupt pin register? on page 903 variable 40h 40h ?offset 40h: hcfg: host configuration register? on page 903 00h f8h fbh ?offset f8h: manid: manufacturer id register? on page 904 00010f90h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 897 intel ? ep80579 integrated processor 24.2.1 smbus controller pci conf iguration register descriptions note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). 24.2.1.1 offset 00h: vid: vendor id register 24.2.1.2 offset 02h: did: device id register 24.2.1.3 offset 04h: cmd: command register table 24-3. offset 00h: vid: vendor id register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor id : this is a 16-bit value assigned to intel 8086h ro table 24-4. offset 02h: did: device id register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 02h 03h size: 16 bit default: 5032h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device id: indicates the device number assigned by the sig. 5032h ro table 24-5. offset 04h: cmd: command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h 10 intd interrupt disable: 0 = enable (default) 1 = disables smbus to assert its pirqb# signal 0b rw 09 fbe fast back to back enable: reserved as ?0?. 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 898 order number: 320066-003us 24.2.1.4 offset 06h: ds ? device status register 08 serr_en serr# enable: 0 = disables serr# generation 1 = enables serr# generation 0b rw 07 wcc wait cycle control: reserved as ?0?. 0b 06 per parity error response: 0 = disable 1 = sets detected parity error bit (d3, f3, 06, bit 15) when a parity error is detected. 0b rw 05 : 01 reserved reserved 00h 00 iose i/o space enable: 0 = disables access to the sm bus i/o space registers as defined by the base address register 1 = enables access to the sm bus i/o space registers as defined by the base address register 0b rw table 24-6. offset 06h: ds ? device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 06h 07h size: 16 bit default: 0280h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: 0 = no parity error detected 1 = parity error detected 0h rwc 14 sse signaled system error: 0 = no system error detected 1 = system error detected 0h rwc 13 rma received master abort: reserved as ?0?. 0h 12 rta received target abort: reserved as ?0?. 0h 11 sta signaled target-abort status: 0 = did not terminate transaction for this function with a target abort 1 = the function is targeted with a transaction that terminates with a target abort 0h ro 10 : 09 devt devsel# timing status: this 2-bit field defines the timing for devsel# assertion. these read-only bits indicate the devsel# timing when performing a positive decode. note: the cmi generates devsel# with medium time. note: it is not clear if a pci master can write to smbus controller. 01h ro table 24-5. offset 04h: cmd: command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 899 intel ? ep80579 integrated processor 24.2.1.5 offset 08h: rid: revision id register the value reported in this register depends on the value written to the revision id in device 31, function 0, offset 08h. see chapter 19.0, ?lpc interface: bus 0, device 31, function 0,? for details. 08 reserved reserved 0h 07 reserved reserved 1h 06 reserved reserved 0h 05 reserved reserved 0h 04 cap_list capabilities list indicator: hardwired to ?0? because there are no capability list structures in this function 0h ro 03 ints interrupt status: this bit indicates that an interrupt is pending. it is independent from the state of the interrupt enable bit in the command register. 0h ro 02 : 00 reserved reserved 00h table 24-6. offset 06h: ds ? device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 06h 07h size: 16 bit default: 0280h power well: resume bit range bit acronym bit description sticky bit reset value bit access table 24-7. offset 08h: rid: revision id register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 08h 08h size: 8 bit default: variable power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid indicates the revision identifier. the value reported in this register depends on the value written to the revision id in device 31, function 0, offset 08h. this register follows the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 900 order number: 320066-003us 24.2.1.6 offset 09h: pi: programming interface register 24.2.1.7 offset 0ah: scc: sub class code register a value of 05h indicates that this device is a sm bus serial controller. 24.2.1.8 offset 0bh: bcc: base class code register a value of 0ch indicates that this device is a serial controller. table 24-8. offset 09h: pi: programming interface register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 09h 09h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pi reserved 00h ro table 24-9. offset 0ah: scc: sub class code register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 0ah 0ah size: 8 bit default: 05h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scc sub class code: 05h = iich sm bus serial controller 05h ro table 24-10. offset 0bh: bcc: base class code register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 0bh 0bh size: 8 bit default: 0ch power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 bcc base class code: 0ch = serial controller. 0ch ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 901 intel ? ep80579 integrated processor 24.2.1.9 offset 20h: sm_base: smb base address register sm_base sets the base address in i/o space for the smbus i/o registers (see section 24.3, ?smbus controller i/o-mapped configuration register details? on page 905 ). these registers can be mapped anywhere in the i/o space on 32-byte boundaries. 24.2.1.10 offset 2ch: svid: svid register bios sets the value in this register to identify the subsystem vendor id. the smbus svid register, in combination with the smbus subsystem id register, enables the operating system to distinguish each subsystem from the others. note: the software can write to this register only once per core well reset. writes must be done as a single 16-bit cycle. table 24-11. offset 20h: sm_base: smb base address register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 20h 23h size: 32 bit default: 00000001h power well: resume bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h 15 : 05 base_ad base address: provides the 32 byte system i/o base address for the smb logic. 0h rw 04 : 01 reserved reserved 0h 00 iosi i/o space indicator: this read-only bit always is 1, indicating that the smb logic is i/o mapped. 1ro table 24-12. offset 2ch: svid: svid register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. note: software can write to this register only once per core well reset. writes must be done as a single 16-bit cycle. 00h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 902 order number: 320066-003us 24.2.1.11 offset 2eh: sid: subsystem identification register bios sets the value in this register to identify the subsystem id. the smbus sid register, in combination with the smbus svid register, enables the operating system to distinguish each subsystem from the others. note: the software can write to this register only once per core well reset. writes must be done as a single 16-bit cycle. 24.2.1.12 offset 3ch: intln: interrupt line register table 24-13. offset 2eh: sid: subsystem identification register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. note: software can write to this register only once per core well reset. writes must be done as a single 16-bit cycle. 00h rwo table 24-14. offset 3ch: intln: interrupt line register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intln interrupt line: this data is not used. it is used to communicate to software the interrupt line that the interrupt pin is connected to pirqb#. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 903 intel ? ep80579 integrated processor 24.2.1.13 offset 3dh: ntpn: interrupt pin register 24.2.1.14 offset 40h: hcfg: host configuration register table 24-15. offset 3dh: ntpn: interrupt pin register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 3dh 3dh size: 8 bit default: variable power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intpn interrupt pin: this reflects the value of d31ip.smip in cmi configuration space. variable ro table 24-16. offset 40h: hcfg: host configuration register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: 40h 40h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 00h 02 i2c_en 0 = smbus behavior 1 = enabled to communicate with i 2 c devices. this changes the formatting of some commands. 0h rw 01 smb_smi_en 0 = smbus interrupts will not generate an smi# 1 = any source of an smb interrupt is instead be routed to generate an smi#. refer to section 24.7 (interrupts / smi#). this bit needs to be set for smbalert# to be enabled. 0h rw 00 hst_en 0 = disable the smbus host controller 1 = enable. the smb host controller interface is enabled to execute commands. the intren bit (offset sm_base + 02h, bit 0) needs to be enabled for the smb host controller to interrupt or smi#. the smb host controller does not respond to any new requests until all interrupt requests have been cleared. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 904 order number: 320066-003us 24.2.1.15 offset f8h: manid: manufacturer id register table 24-17. offset f8h: manid: manufacturer id register description: view: pci bar: configuration bus:device:function: 0:31:3 offset start: offset end: f8h fbh size: 32 bit default: 00010f90h power well: resume bit range bit acronym bit description sticky bit reset value bit access 31 :24 reserved reserved 0h ro 23 :16 sid stepping identifier: this field increments for each stepping of the part. this field can be used by software to differentiate steppings when the revision id may not change. see section 19.2.8.1, ?offset f8h: manid: manufacturer id register? on page 757 for cases in which the revision id may not increment. note: 00h for a0 stepping note: 01h for b0 stepping 01h ro 15 : 08 mid manufacturing identifier: indicates 0fh = intel 0fh ro 07 : 00 reserved reserved 90h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 905 intel ? ep80579 integrated processor 24.3 smbus controller i/o-mapped configuration register details note: warning: address locations that are not listed are considered reserved register locations. reserved registers are read only and return all zeros. note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). table 24-18. bus 0, device 31, function 3: summary of smbus controller configuration registers mapped through sm_base i/o bar offset start offset end register id - description default value 00h 00h ?offset 00h: hsts: host status register? on page 906 00h 02h 02h ?offset 02h: hctl: host control register? on page 908 00h 03h 03h ?offset 03h: hcmd: host command register? on page 912 00h 04h 04h ?offset 04h: tsa: transmit slave address register? on page 912 00h 05h 05h ?offset 05h: hd0: data 0 register? on page 913 00h 06h 06h ?offset 06h: hd1: data 1 register? on page 913 00h 07h 07h ?offset 07h: hbd: host block data register? on page 914 00h 08h 08h ?offset 08h: pec: packet error check data register? on page 915 00h 0ch 0ch ?offset 0ch: auxs: auxiliary status register? on page 915 00h 0dh 0dh ?offset 0dh: auxc: auxiliary control register? on page 916 00h 0eh 0eh ?offset 0eh: smlc: smlink_pin_ctl register? on page 916 07h 0fh 0fh ?offset 0fh: smbc: smbus_pin_ctl register? on page 917 07h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 906 order number: 320066-003us 24.3.1 smbus controller i/o-ma pped configuration register descriptions the smbus controller i/o-mapped configuration registers are mapped into i/o space using register sm_base (see section 24.2.1.9, ?offset 20h: sm_base: smb base address register? on page 901 ). 24.3.1.1 offset 00h: hsts: host status register all status bits are set by hardware and cleared by the software writing a one to the particular bit position. writing a zero to any bit position has no effect. table 24-19. offset 00h: hsts: host status register (sheet 1 of 2) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 00h 00h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 bds byte_done_sts: 0 = software can clear this by writing a 1 1 = host controller received a byte (for block read commands) or if it has completed transmission of a byte (for block write commands) when the 32-byte buffer is not being used. this bit is set, even on the last byte of the transfer. this bit is not set when transmission is due to the lan interface heartbeat. this bit has no meaning for block transfers when the 32- byte buffer is enabled. when the last byte of a block message is received, the host controller sets this bit. however, it does not immediately set the intr bit (bit 1 in this register). when the interrupt handler clears the byte_done_sts bit, the message is considered complete, and the host controller will then set the intr bit (and generate another interrupt). thus, for a block message of n bytes, n+1 interrupts will be generated. the interrupt handler needs to be implemented to handle these cases. 0h rwc 06 ius in use status: 0 = after a full pci reset, a read to this bit returns a 0. 1 = after the first read, subsequent reads return a 1. a write of a 1 to this bit resets the next read value to 0. writing a 0 to this bit has no effect. software can poll this bit until it reads a 0, and then own the usage of the host controller. this bit has no other effect on the hardware, and is only used as semaphore among various independent software threads that may need to use the smbus logic. 0h rw 05 smbalert_ sts system bus alert status: 0 = interrupt or smi# was not generated by smbalert#. software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was the smbalert# signal. this bit is only cleared by software writing a 1 to the bit position or by cf9 reset or rsmrst# going low (but not pltrst#). if the signal is programmed as a gpi, then this bit is never set. 0h rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 907 intel ? ep80579 integrated processor 04 fail failed: 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was a failed bus transaction. this bit is set in response to the kill bit being set to terminate the host transaction. 0h rwc 03 mcerr machine check error: 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt of smi# was a transaction collision. 0h rwc 02 derr device error: 0 = software clears this bit by writing a 1 to it, then deasserts the interrupt or smi#. 1 = the source of the interrupt or smi# was due to one of the following: ? illegal command field ? unclaimed cycle (host initiated) ?host device time-out error ? crc error 0h rwc 01 intr interrupt: when set, this indicates that the source of the interrupt or smi# was the successful completion of its last command. 0h rwc 00 hbsy host busy: 0 = cleared when the current transaction is completed 1 = indicates that the cmi is running a command from the host interface. no smb registers must be accessed while this bit is set, except the block data byte register. the block data byte register can be accessed when this bit is set only when the smb_cmd bits in the host control register are programmed for block command or i 2 c read command. this is necessary in order to check the done_sts bit. 0h rwc table 24-19. offset 00h: hsts: host status register (sheet 2 of 2) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 00h 00h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 908 order number: 320066-003us 24.3.1.2 offset 02h: hctl: host control register note: a read to this register clears the pointer in the 32-byte buffer. table 24-20. offset 02h: hctl: host control register (sheet 1 of 4) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 02h 02h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 pec_en packet error check enable: 0 = smbus host controller does not perform the transaction with the pec phase appended. 1 = causes the host controller to perform the smbus transaction with the packet error checking phase appended. for writes, the value of the pec byte is transferred from the pec register. for reads, the pec byte is loaded in to the pec register. this bit must be written prior to the write in which the start bit is set. 0h rw 06 start 0 = this bit will always return 0 on reads. the host_busy bit in the host status register (offset 00h) can be used to identify when the command is finished. 1 = writing a 1 to this bit initiates the command described in the smb_cmd field. all registers should be setup prior to writing a 1 to this bit position. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 909 intel ? ep80579 integrated processor 05 last_byte used for i 2 c read commands as an indication that the next byte is the last one to be received for that block. the algorithm and usage model for this bit is as follows (assume a message of n bytes): 1. when the software sees the byte_done_sts bit set (bit 7 in the smbus host status register) for each of bytes 1 through n-2 of the message, the software should then read the block data byte register to get the byte that was just received. 2. after reading each of bytes 1 to n-2 of the message, the software will then clear the byte_done_sts bit. 3. after receiving byte n-1 of the message, the software will then set the ?last byte? bit. the software will then clear the byte_done_sts bit. 4. the cmi then receives the last byte of the message (byte n). however, the state machine sees the last byte bit set, and instead of sending an ack after receiving the last byte, it instead sends a nak. 5. after receiving the last byte (byte n), the software still clears the byte_done_sts bit. however, the last_byte bit is irrelevant at that point. notes: 1. this bit may be set when the tco timer causes the second_to_sts bit to be set. see section section 18.2.2.6 , bit 1 for more details on that bit. the smbus device driver should clear the last_byte bit (if it is set) before starting any new command. 2. in addition to i2c read commands, the last_byte bit also causes block read/write cycles to stop prematurely (at the end of the next byte). 0h rw table 24-20. offset 02h: hctl: host control register (sheet 2 of 4) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 02h 02h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 910 order number: 320066-003us 04 : 02 smb_cmd as shown by the bit encoding below, indicates which command is to be performed. if enabled, the cmi generates an interrupt or smi# when the command has completed if the value is for a non-supported or reserved command, the cmi will sets the device error (dev_err) status bit and generates an interrupt when the start bit is set. the cmi performs no command, and does not operate until dev_err is cleared. 000h rw table 24-20. offset 02h: hctl: host control register (sheet 3 of 4) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 02h 02h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access bits name command description 000 quick the slave address and read/write value (bit 0) are stored in the tx slave address register. 001 byte this command uses the transmit slave address and command registers. bit 0 of the slave address register determines if this is a read or write command. 010 byte data this command uses the transmit slave address, command, and data0 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, the data0 register contains the read data. 011 word data this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, after the command completes the data0 and data1 registers contain the read data. 100 proce ss call this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. after the command completes, the data0 and data1 registers will contain the read data. 101 block this command uses the transmit slave address, command, and data0 registers, and the block data byte register. for block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block reads, the count is received and stored in the data0 register. bit 0 of the slave address register selects if this is a read or write command. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. 110 i 2 c read this command uses the transmit slave address, command, data0, data1 registers, and the block data byte register. the read data is stored in the block data byte register. the cmi will continue reading data until the nak is received.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 911 intel ? ep80579 integrated processor 04 : 02 smb_cmd (cont?d) 0h rw 01 kill 0 = normal smbus host controller functionality. 1 = kills the current host transaction taking place, sets the failed status bit, and asserts the interrupt (or smi#). this bit, once set, must be cleared by software to allow the smbus host controller to function normally. 0h rw 00 intren 0 = disable 1 = enable the generation of an interrupt or smi# upon the completion of the command 0h rw table 24-20. offset 02h: hctl: host control register (sheet 4 of 4) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 02h 02h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access bits name command description 111 block- process this command uses the transmit slave address, command, data0 and the block data byte register. for block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block read, the count is received and stored in the data0 register. bit 0 of the slave address register always indicate a write command. for writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. note: e32b bit in the auxiliary control register must be set for this command to work.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 912 order number: 320066-003us 24.3.1.3 offset 03h: hcmd: host command register this eight bit field is transmitted by the host controller in the command field of the smb protocol during the execution of any command. 24.3.1.4 offset 04h: tsa: transmit slave address register this register is transmitted by the host controller in the slave address field of the smb protocol. this is the address of the target. table 24-21. offset 03h: hcmd: host command register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 03h 03h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hst_cmd this 8-bit field is transmitted by the host controller in the command field of the smbus protocol during the execution of any command. 00h rw table 24-22. offset 04h: tsa: transmit slave address register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 04h 04h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 01 address 7-bit address of the targeted slave 0000000h rw 00 rw direction of the host transfer. 0 = write 1 = read 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 913 intel ? ep80579 integrated processor 24.3.1.5 offset 05h: hd0: data 0 register 24.3.1.6 offset 06h: hd1: data 1 register table 24-23. offset 05h: hd0: data 0 register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 05h 05h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 data0_count this field contains the eight bit data sent in the data0 field of the smb protocol. for block write commands, this register reflects the number of bytes to transfer. this register should be programmed to a value between 1 and 32 for block counts. a count of 0 or a count above 32 will result in unpredictable behavior. the host controller does not check or log illegal block counts. 00h rw table 24-24. offset 06h: hd1: data 1 register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 06h 06h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 data1 this eight bit register is transmitted in the data1 field of the smb protocol during the execution of any command. 00h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 914 order number: 320066-003us 24.3.1.7 offset 07h: hbd: host block data register table 24-25. offset 07h: hbd: host block data register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 07h 07h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 bdta block data: this is either a register, or a pointer into a 32-byte block array, depending upon whether the e32b bit is set in the auxiliary control register. when the e32b bit is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read. when the e32b bit is set, reads and writes to this register are used to access the 32-byte block data storage array. an internal index pointer is used to address the array, which is reset to 0 by reading the hctl register (offset 02h). the index pointer then increments automatically upon each access to this register. the transfer of block data into (read) or out of (write) this storage array during an smbus transaction always starts at index address 0. when the e2b bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. after the host controller has sent the address, command, and byte count fields, it will send the bytes in the sram pointed to by this register. when the e2b bit is cleared for writes, software will place a single byte in this register. after the host controller has sent the address, command, and byte count fields, it will send the byte in this register. if there is more data to send, software will write the next series of bytes to the sram pointed to by this register and clear the done_sts bit. the controller will then send the next byte. during the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. when the e2b bit is set for reads, after receiving the byte count into the data0 register, the first series of data bytes go into the sram pointed to by this register. if the byte count has been exhausted or the 32-byte sram has been filled, the controller will generate an smi# or interrupt (depending on configuration) and set the done_sts bit. software will then read the data. during the time between when the last byte is read from the sram to when the done_sts bit is cleared, the controller will insert wait-states on the interface.this eight bit register is transmitted in the data1 field of the smb protocol during the execution of any command. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 915 intel ? ep80579 integrated processor 24.3.1.8 offset 08h: pec: packet error check data register this register contains the 8-bit crc value that is used as the packet error check on smbus. for writes, this register is written by software prior to running the command. for reads, this register is read by software after the re ad command is completed on smbus. 24.3.1.9 offset 0ch: auxs: auxiliary status register table 24-26. offset 08h: pec: packet error check data register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 08h 08h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pec_data this 8-bit register is written with the smbus pec data prior to a write transaction. for read transactions, the pec data is loaded from the smbus into this register and is then read by software. software must ensure that the inuse_sts bit is properly maintained to avoid having this field overwritten by a write transaction following a read transaction. 00h rw table 24-27. offset 0ch: auxs: auxiliary status register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 0ch 0ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 0h 01 stco smbus tco mode: this is the status bit that reflects the setting of legacy tco mode vs. advanced tco mode. 0 = indicates that this bit is always zero, since advanced tco mode is not supported. 0h ro 00 crce crc error: 0 = software clears this bit by writing a 1 to it. 1 = this bit is set if a received message contained a crc error. when this bit is set, the derr bit of the host status register is also set. this bit is set by the controller if a software abort occurs in the middle of the crc portion of the cycle or an abort happens after the cmi has received the final data bit transmitted by an external slave. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 916 order number: 320066-003us 24.3.1.10 offset 0dh: auxc: auxiliary control register 24.3.1.11 offset 0eh: smlc: smlink_pin_ctl register this register is only applicable in the tco compatible mode. this register is in the resume well and is reset by cf9 reset or rsmrst#. table 24-28. offset 0dh: auxc: auxiliary control register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 0h 01 e32b enable 32-byte buffer: 0 = the host block data register is a pointer into a single register. 1 = when set, the host block data register is a pointer into a 32-byte buffer. this enables the block commands to transfer or receive up to 32-bytes before the cmi generates an interrupt. 0h rw 00 aac automatically append crc: 0 = does not automatically append the crc 1 = automatically appends the crc this bit must not be changed during sm bus transactions, or undetermined behavior results. it should be programmed only once during the lifetime of the function. 0h rw table 24-29. offset 0eh: smlc: smlink _pin_ctl register (sheet 1 of 2) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 0eh 0eh size: 8 bit default: 07h power well: resume a bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 0h 02 smlink_clk_c tl this read/write bit has a default of 1. 0 = drives the smlink[0] pin low, independent of what the other smlink logic would otherwise indicate for the smlink[0] pin. 1 = the smlink[0] pin is not overdriven low. the other smlink logic controls the state of the pin. 1b rw 01 smlink1_cur_ sts this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink[1] pin. this allows software to read the current state of the pin. 0 = low 1 = high 1b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 917 intel ? ep80579 integrated processor 24.3.1.12 offset 0fh: smbc: smbus_pin_ctl register this register is in the resume well and is reset by cf9 reset or rsmrst#. 00 smlink0_cur_ sts this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink[0] pin. 0 = low 1 = high this allows software to read the current state of the pin. 0h ro a. reset by cf9 reset or rsmrst# table 24-29. offset 0eh: smlc: smlink_pin_ctl register (sheet 2 of 2) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 0eh 0eh size: 8 bit default: 07h power well: resume a bit range bit acronym bit description sticky bit reset value bit access table 24-30. offset 0fh: smbc: smbus_pin_ctl register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 0fh 0fh size: 8 bit default: 07h power well: resume a a. reset by cf9 reset or rsmrst# bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 00h ro 02 smbclk_ctl this bit has a default of 1. 0 = drives the smbclk pin low, independent of what the other smb logic would otherwise indicate for the smbclk pin. 1 = the smbclk pin is not overdriven low. the other smbus logic controls the state of the pin. 1b rw 01 smbdata_ cur_sts this bit has a default value that is dependent on an external signal level. this pin returns the value on the smbdata pin. this allows software to read the current state of the pin. 0 = low 1 = high 1b ro 00 smbclk_ cur_sts this bit has a default value that is dependent on an external signal level. this pin returns the value on the smbclk pin. this allows software to read the current state of the pin. 0 = low 1 = high 1b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 918 order number: 320066-003us 24.4 host controller 24.4.1 overview the smb host controller is used to send commands to other smb slave devices. software sets up the host controller with an address, command, and for writes, data and optionally pec; and then tells the controller to start. when the controller has finished transmitting data on writes, or receiving data on reads, it generates an smi# or interrupt, if enabled. the host controller supports eight command protocols of the smb interface (see the system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read, block write and block write-block read process call. the smb host controller requires that the various data and command fields be setup for the type of command to be sent. when software sets the start bit, the smb host controller performs the requested transaction and interrupt the processor (or generate an smi#) when its finished. once a start command has been issued, the values of the ?active registers? (host control, host command, transmit slave address, data0, data1) should not be changed or read until the interrupt status bit (intr) has been set (indicating the completion of the command). any register values needed for computation purposes should be saved prior to issuing of a new command, as the smb host controller will update all registers while completing the new command. the cmi supports slave functionality, including the host notify protocol, on the smlink pins when in tco compatible mode. therefore, in order to be fully compliant with the smbus specification (which requires the host notify cycle), the smlink and smbus signals must be tied together externally. using the smb host controller to send commands to the smb slave port is not supported. 24.4.2 command protocols in all of the following commands, the host status register (offset 00h) is used to determine the progress of the command. while the command is in operation, the host_busy bit is set. if the command completes successfully, the intr bit is set in the host status register. if the device does not respond with an acknowledge, and the transaction times out, the dev_err bit is set. if software sets the kill bit in the host control register while the command is running, the transaction stops and the failed bit is set after the cmi forces a timeout. in addition, if the kill bit is set during the crc cycle, both the crce and dev_err bits are also set. when the kill bit is set, the cmi aborts current transaction by asserting smbclk low for greater than the timeout period, asserts a stop condition and then releases smbclk and smbdata. however, setting the kill bit does not affect smlink or tco transactions or causes the cmi to force a timeout if it is not performing a transaction. 24.4.2.1 quick command when programmed for a quick command, the transmit slave address register is sent. ta b l e 2 4 - 3 1 shows the order. the pec byte is never appended to the quick protocol. software must force the pec_en bit to ?0? when performing the quick command for possible future enhancements. also, quick command with i2c_en set produces undefined results. software must force the i2c_en bit to 0 when running this command.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 919 intel ? ep80579 integrated processor 24.4.2.2 send byte/receive byte for the send byte command, the transmit slave address and device command registers are sent. the receive byte is similar to a send byte, the only difference is the direction of data transfer. when programmed for the receive byte command, the transmit slave address register is sent. the data received is stored in the data0 register. the order sent/ received without pec is shown in ta b l e 2 4 - 3 2 . send byte/receive byte command with i2c_en set produces undefined results. software must force the i2c_en bit to 0 when running this command. the order sent/received, with pec, is shown in ta bl e 2 4 - 3 3 . table 24-31. quick protocol bit description 1 start condition 2?8 slave address - 7 bits 9 read / write direction 10 acknowledge from slave 11 stop table 24-32. send/receive byte protocol without pec send byte protocol receive byte protocol bit description bit description 1start 1start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9write 9read 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 data byte from slave 19 acknowledge from slave 19 not acknowledge 20 stop 20 stop table 24-33. pec send/receive order send byte protocol receive byte protocol bit description bit description 1start 1start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9write 9read 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 data byte from slave 19 acknowledge from slave 19 acknowledge 20 ? 27 pec 20 ? 27 pec from slave 28 acknowledge from slave 28 not acknowledge 29 stop 29 stop
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 920 order number: 320066-003us 24.4.2.3 write byte/word the first byte of a write byte/word access is the command code. the next one or two bytes are the data to be written. when programmed for a write byte/word command, the transmit slave address, device command, and data0 registers are sent. in addition, the data1 register is sent on a write word command. the order of bits without pec is shown in table 24-34 . issuing a write byte/word command with i2c_en set produces undefined results. software must force the i2c_en bit to 0 when running this command. the order of bits with pec is shown in table 24-35 . table 24-34. write byte/word protocol without pec write byte protocol write word protocol bit description bit description 1start 1start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 ? 27 data byte - 8 bits 20 ? 27 data byte low - 8 bits 28 acknowledge from slave 28 acknowledge from slave 29 stop 29 ? 36 data byte high - 8 bits 37 acknowledge from slave 38 stop table 24-35. pec bit order write byte protocol write word protocol bit description bit description 1start 1start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 ? 27 data byte - 8 bits 20 ? 27 data byte low - 8 bits 28 acknowledge from slave 28 acknowledge from slave 29 ? 36 pec 29 ? 36 data byte high - 8 bits 37 acknowledge from slave 37 acknowledge from slave 38 stop 38 ? 45 pec 46 acknowledge from slave 47 stop
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 921 intel ? ep80579 integrated processor 24.4.2.4 read byte/word reading data is slightly more complicated than writing data. first a command to the slave device must be written. then it must follow that command with a repeated start condition to denote a read from that device's address. the slave then returns one or two bytes of data. when programmed for the read byte/word command, the transmit slave address and device command registers are sent. data is received into the data0 on the read byte, and the dat0 and data1 registers on the read word. the order sent and received with pec disabled is shown in ta b l e 2 4 - 3 6 . read byte/word command with i2c_en set produces undefined results. software must force the i2c_en bit to 0 when running this command. the order sent and received with pec enabled is shown in ta b l e 2 4 - 3 7 . table 24-36. read byte/word protocol without pec read byte protocol read word protocol bit description bit description 1start 1start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 repeated start 20 repeated start 21 ? 27 slave address - 7 bits 21 ? 27 slave address - 7 bits 28 read 28 read 29 acknowledge from slave 29 acknowledge from slave 30 ? 37 data from slave - 8 bits 30 ? 37 data byte low from slave - 8 bits 38 not acknowledge 38 acknowledge 39 stop 39 ? 46 data byte high from slave - 8 bits 47 not acknowledge 48 stop table 24-37. read byte/word protocol with pec read byte protocol read word protocol bit description bit description 1start 1start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 repeated start 20 repeated start 21 ? 27 slave address - 7 bits 21 ? 27 slave address - 7 bits
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 922 order number: 320066-003us 24.4.2.5 process call the process call is named because a command sends data and waits for the slave to return a value dependent on that data. the protocol is simply a write word followed by a read word, but without a second command or stop condition. when programmed for the process call command, the cmi transmits the transmit address, device command, and data0 and data1 registers. data received from the device is stored in the data0 and data1 registers. the value written into bit 0 of the transmit slave address register (smbus offset 04h) needs to programmed to 0. note: if the i2c_en bit is set, then the command field is not sent. the order sent with pec disabled is shown in ta b l e 2 4 - 3 8 . the process call command with i2c_en set and either the pec_en or aac bit set produces undefined results. software must either force the i2c_en bit or both pec_en and aac bits to 0 when running this command. 28 read 28 read 29 acknowledge from slave 29 acknowledge from slave 30 ? 37 data from slave - 8 bits 30 ? 37 data byte low from slave - 8 bits 38 acknowledge 38 acknowledge 39 ? 46 pec from slave 39 ? 46 data byte high from slave - 8 bits 47 not acknowledge 47 acknowledge 48 stop 48 ? 55 pec from slave 56 not acknowledge 57 stop table 24-37. read byte/word protocol with pec table 24-38. process call protocol without pec bit description 1start 2 ? 8 slave address - 7 bits 9write 10 acknowledge from slave 11 ? 18 command code - 8 bits (skip if i2c_en is set) 19 acknowledge from slave (skip if i2c_en is set) 20 ? 27 data byte low - 8 bits 28 acknowledge from slave 29 ? 36 data byte high - 8 bits 37 acknowledge from slave 38 repeated start 39 ? 45 slave address - 7 bits 46 read 47 acknowledge from slave 48 ? 55 data byte low from slave - 8 bits 56 acknowledge
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 923 intel ? ep80579 integrated processor the order sent with pec enabled is shown in ta b l e 2 4 - 3 9 . 24.4.2.6 block read/write the cmi contains a 32-byte buffer for read and write data which can be enabled by setting bit ?1? of the auxiliary control register at offset 0dh in i/o space, as opposed to a single byte of buffering. this 32-byte buffer is filled with write data before transmission and filled with read data on reception. in the cmi, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. the block write command with i2c_en set and either the pec_en or aac bit set produces undefined results. software must either force the i2c_en bit or both pec_en and aac bits to 0 when running this command. 57 ? 64 data byte high from slave - 8 bits 65 not acknowledge 66 stop table 24-38. process call protocol without pec table 24-39. process call protocol with pec bit description 1start 2 ? 8 slave address - 7 bits 9write 10 acknowledge from slave 11 ? 18 command code - 8 bits 19 acknowledge from slave 20 ? 27 data byte low - 8 bits 28 acknowledge from slave 29 ? 36 data byte high - 8 bits 37 acknowledge from slave 38 repeated start 39 ? 45 slave address - 7 bits 46 read 47 acknowledge from slave 48 ? 55 data byte low from slave - 8 bits 56 acknowledge 57 ? 64 data byte high from slave - 8 bits 65 acknowledge 66 ? 73 pec from slave 74 not acknowledge 75 stop
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 924 order number: 320066-003us 24.4.2.6.1 sm bus mode the block write begins with a slave address and a write condition. after the command code the cmi issues a byte count describing how many more bytes will follow in the message. if a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. the byte count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. when programmed for a block write command, the transmit slave address, device command, and data0 (count) registers are sent. data is then sent from the block data byte register; the total data sent being the value stored in the data0 register. on block read commands, the first byte received is stored in the data0 register, and the remaining bytes are stored in the block data byte register. 24.4.2.6.2 i 2 c mode the format of the command changes slightly for block commands if the i2c_en bit is set. the cmi still sends the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the data0 register. however, it does not send the contents of the data0 register as part of the message. the format of the command changes slightly for a block write if the i2c_en bit is set. the cmi still sends the number of bytes indicated in the data0 register. however, it does not send the contents of the data0 register as part of the message. the protocol for the block write and block read without pec is shown in ta bl e 2 4 - 4 0 . table 24-40. block read/write protocol without pec (sheet 1 of 2) block write protocol block read protocol bit description bit description 1 start 1 start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 ? 27 byte count - 8 bits (skip this step if i2c_en bit set) 20 repeated start 28 acknowledge from slave (skip this step if i2c_en bit set) 21 ? 27 slave address - 7 bits 29 ? 36 data byte 1 - 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38 ? 45 data byte 2 - 8 bits 30 ? 37 byte count from slave - 8 bits 46 acknowledge from slave 38 acknowledge ... data bytes / slave acknowledges... 39 ? 46 data byte 1 from slave - 8 bits ... data byte n - 8 bits 47 acknowledge ... acknowledge from slave 48 ? 55 data byte 2 from slave - 8 bits ... stop 56 acknowledge ... data bytes from slave/acknowledge
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 925 intel ? ep80579 integrated processor the protocol for the block write and block read with pec is shown in table 24-41 . the block write command with i2c_en set and the pec_en bit set produces undefined results. software must force the pec_en bit to 0 when running this command. 24.4.2.7 i 2 c read this command allows the cmi to perform block reads to certain i2c devices, such as serial e2proms. the smbus block read supports the 7-bit addressing mode only. however this doesn?t allow access to devices that need to use the i 2 c ?combined format? that has data bytes after the address. typically these data bytes correspond to an offset (address) within the serial memory chips. the i 2 c read command with either pec_en or aac bit set produces undefined results. software must force both pec_en and aac bits to 0 when running this command. ... data byte n from slave - 8 bits ... not acknowledge ... stop table 24-40. block read/write protocol without pec (sheet 2 of 2) table 24-41. block read/write protocol with pec block write protocol block read protocol bit description bit description 1 start 1 start 2 ? 8 slave address - 7 bits 2 ? 8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11 ? 18 command code - 8 bits 11 ? 18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 ? 27 byte count - 8 bits 20 repeated start 28 acknowledge from slave 21 ? 27 slave address - 7 bits 29 ? 36 data byte 1 - 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38 ? 45 data byte 2 - 8 bits 30 ? 37 byte count from slave - 8 bits 46 acknowledge from slave 38 acknowledge ... data bytes / slave acknowledges... 39 ? 46 data byte 1 from slave - 8 bits ... data byte n - 8 bits 47 acknowledge ... acknowledge from slave 48 ? 55 data byte 2 from slave - 8 bits ... pec ? 8 bits 56 acknowledge ... acknowledge from slave ... data bytes from slave/acknowledge ... stop ... data byte n from slave - 8 bits ... acknowledge ... pec from slave ? 8 bits ... not acknowledge ... stop
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 926 order number: 320066-003us to support these devices, the cmi implements an i 2 c read command with the following format: the cmi continues reading data from the peripheral until the nak is received. note: this new command is supported independent of the setting of the i2c_en bit. note: the value written into bit 0 of the transmit slave address register (smbus offset 04h) must be 0. 24.4.2.8 block write-block read process call the block write-block read process call is a two-part message. the call begins with a slave address and a write condition. after the command code the host issues a write byte count (m) that describes how many more bytes will be written in the first part of the message. if a master has six bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the six bytes of data. the write byte count (m) cannot be zero. the second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a read bit. the next byte is the read byte count (n), which may differ from the write byte count (m). the read byte count (n) cannot be zero. the combined data payload must not exceed 32 bytes. the byte length restrictions of this process call are summarized as follows: ?m 1 byte ?n 1 byte ?m + n 32 bytes the read byte count does not include the pec byte. the pec is computed on the total message beginning with the first slave address and using the normal pec computational rules. it is highly recommended that a pec byte be used with the block write-block read process call. software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. bit description 1start 2 ? 8 slave address - 7 bits 9write 10 acknowledge from slave 11 ? 18 send data1 register 19 acknowledge from slave 20 repeated start 21 ? 27 slave address - 7 bits 28 read 29 acknowledge from slave 30 ? 37 data byte 1 from slave - 8 bits 38 acknowledge 39 ? 46 data byte 2 from slave - 8 bits 47 acknowledge ... data bytes from slave/acknowledge ... data byte n from slave - 8 bits ... not acknowledge ... stop
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 927 intel ? ep80579 integrated processor note: there is no stop condition before the repeated start condition, and that a nack signifies the end of the read transfer. note: e32b in the auxiliary control register must be set when using this protocol. table 24-42. block write-block read process call protocol with/without pec bit description 1start 2 ? 8 slave address - 7 bits 9write 10 acknowledge from slave 11 ? 18 command code - 8 bits 19 acknowledge from slave 20 ? 27 data byte count (m) - 8 bits 28 acknowledge from slave 29 ? 36 data byte (1) - 8 bits 37 acknowledge from slave 38 ? 45 data byte (2) - 8 bits 46 acknowledge from slave ?? data byte (m) - 8 bits acknowledge from slave repeated start slave address - 7 bits read acknowledge from slave data byte count (n) from slave ? 8 bits acknowledge from master data byte (1) from slave ? 8 bits acknowledge from master data byte (2) from slave ? 8 bits acknowledge from master ?? data byte count (n) from slave ? 8 bits acknowledge from master (skip if no pec) pec from slave (skip if no pec) not acknowledge stop
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 928 order number: 320066-003us 24.4.3 i 2 c behavior when the i2c_en bit is set, the cmi smbus logic is set to communicate with i 2 c devices. this forces the following changes: 1. the process call command skips the command code (and its associated acknowledge) 2. the block write command skips sending the byte count (data0) in addition, the cmi supports the i 2 c read command. this is independent of the i2c_en bit. when operating in i 2 c mode, (i2c_en bit set), the cmi never uses the 32- byte buffer for any block commands. 24.4.4 heartbeat for use with external lan this method allows the cmi to send messages to an external lan controller when the processor is otherwise unable to do so. it uses the smlink interface between the cmi and external lan controller in tco compatible mode. the actual heartbeat message is a block write. only eight bytes are sent. see chapter 18.0, ?system management,? for more details on the heartbeat packet format, and the specific bits sent in the packet. 24.5 bus arbitration several masters may attempt to get on the bus at the same time by driving the smbdata line low to signal a start condition. the cmi continuously monitors the smbdata line. when the cmi is attempting to drive the bus to a ?1? by letting go of the smbdata line, and it samples smbdata low, then some other master is driving the bus and the cmi stops transferring data. if the cmi detects loss of arbitration, the condition is called a collision. the cmi sets the bus_err bit in the host status register, and if enabled, generates an interrupt or smi#. the processor is responsible for restarting the transaction. 24.6 bus timings the sm bus runs at between 10 ? 100 khz. most of the timings associated with the sm bus are microseconds in length. the sm bus runs off of a divide by two of the rtc clock internally and employs counters of various length off of the rtc clock to drive the sm bus. when the cmi is a sm bus master, it drives the clock. when the cmi is sending address or command as an sm bus master, or data bytes as a master on writes, it will drive data relative to the clock it is also driving. it does not start toggling the clock until the start or stop condition meets proper setup and hold. the cmi also guarantees minimum time between sm bus transactions as a master. 24.6.1 clock stretching some devices may not be able to handle their clock toggling at the rate that the cmi as an sm bus master would like. they have the capability of stretching the low time of the clock. when the cmi attempts to release the clock (allowing the clock to go high), the clock remains low for an extended period of time.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 929 intel ? ep80579 integrated processor the cmi monitors the sm bus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. while the bus is still low, the high time counter must not be enabled. similarly, the low period of the clock can be stretched by an sm bus master if it is not ready to send or receive data. 24.6.2 bus time out (cmi as smb master) if there is an error in the transaction, such that an smbus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the cmi discards the cycle, and set the dev_err bit. the time out minimum is 25 ms. the time-out counter inside the cmi starts when the first bit of data is transferred by the cmi. the time-out minimum is 25 ms (800 rtc clocks). the 25 ms timeout counter does not count under the following conditions: 1. byte_done_status bit (smbus i/o offset 00h, bit 7) is set, and 2. the second_to_sts bit (tco i/o offset 06h, bit 1) is not set (this indicates that the system has not locked up). 24.7 interrupts/smi# the cmi sm bus controller uses pirqb# as its interrupt pin. however, the system can alternatively be set up to generate smi# instead of an interrupt, by setting the smbus_smi_en bit (device 31, function 0, offset 40h, bit 1). the following tables specify how the various enable bits in the smbus function control the generation of the interrupt, host and slave smi, and wake internal signals. the rows in the tables are additive, which means that if more than one row is true for a particular scenario then the results for all of the activated rows occurs. table 24-43. summary of enables for smbalert# event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31, f3, offset 40h, bit 1) smbalert_dis (slave command i/o register, offset 11h, bit 2) result smbalert# asserted low (always reported in smbalert_sts- host status register, bit 5) xx xwake generated x1 0 slave smi# generated (smbus_smi_sts) 1 0 0 interrupt generated table 24-44. summary of enables for smbus slave write, and smbus host events event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31, f3, offset 40h, bit 1) result slave write to wake/smi# command xx wake generated when asleep slave smi# generated when awake (smbus_smi_sts) slave write to smlink_slave_smi command xx slave smi# generated when in the s0 state (smbus_smi_sts) any combination of host status register [04:01] asserted 0xnone 1 0 interrupt generated 11host smi# generated
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 930 order number: 320066-003us 24.8 crc generation and checking if the aac bit is set in the auxiliary control register, the cmi automatically calculates and drives crc at the end of the transmitted packet for write cycles, and checks the crc for read cycles. it does not transmit the contents of the pec register for crc. the pec bit must not be set in the host control register if this bit is set, or unspecified behavior results. if the read cycle results in a crc error, the dev_err bit and the crce bit in the auxiliary status register at offset 0ch is set. 24.8.1 slave interface i/o space the following registers are used by the smbus slave logic. refer to section 24.3 for the complete list of smb i/o registers. table 24-45. summary of enables for the host notify command host_notify_intren (slave control i/o register, offset 11h, bit 0) smb_smi_en (host configuration register, d31, f3, off40h, bit 1) host_notify_wken (slave control i/o register, offset 11h, bit 1) result 0x0none xx1wake generated 1 0 x interrupt generated 11x slave smi# generated (smbus_smi_sts) table 24-46. bus 0, device 31, function 3, slave pci registers mapped through sm_base (io) offset start offset end register id - description default value 09h 09h ?offset 09h: rsa: receive slave address register? on page 931 44h 0ah 0bh ?offset 0ah: sd: slave data register? on page 931 0000h 10h 10h ?offset 10h: ssts: slave status register? on page 932 00h 11h 11h ?offset 11h: scmd: slave command register? on page 932 00h 14h 14h ?offset 14h: nda: notify device address register? on page 933 00h 16h 16h ?offset 16h: ndlb: notify data low byte register? on page 934 00h 17h 17h ?offset 17h: ndhb: notify data high byte register? on page 934 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 931 intel ? ep80579 integrated processor 24.8.2 register details 24.8.2.1 offset 09h: rsa: receive slave address register 24.8.2.2 offset 0ah: sd: slave data register table 24-47. offset 09h: rsa: receive slave address register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 09h 09h size: 8 bit default: 44h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved 0b 06 : 00 rsa slave_addr[06:00]: this field is the slave address that is decoded for read and write cycles. the default is not 0 so that it can respond even before the processor comes up (or if the processor is dead). this register is reset by cf9 reset or rsmrst#, but not by pltrst#. 1000100b rw table 24-48. offset 0ah: sd: slave data register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 0ah 0bh size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sd slave_data[15:00]: this field is the 16-bit data value written by the external smbus master. the processor can then read the value from this register. this register is reset by cf9 reset or rsmrst#, but not by pltrst#. slave_data[07:00] corresponds to the data message byte 0 (see section 24.8.2.1 ) at slave write register 4 in the table. slave_[15:08] corresponds to the data message byte 1 (see section 24.8.2.1 ) at slave write register 5 in the table. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 932 order number: 320066-003us 24.8.2.3 offset 10h: ssts: slave status register 24.8.2.4 offset 11h: scmd: slave command register table 24-49. offset 10h: ssts: slave status register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 10h 10h size: 8 bit default: 00h power well: resume a a. this register is in the resume well and is reset by cf9 reset or rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll the register until a write takes effect before assuming that a write has completed internally. bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved reserved 0h 00 host_ notify_ sts software reads this bit to determine that the source of the interrupt or smi# was the reception of the host notify command. software clears this bit after reading any information needed from the notify address and data registers by writing a 1 to this bit. the cmi allows the notify address and data registers to be overwritten once this bit has been cleared. when this bit is 1,the cmi will nack the first byte (host address) of any new ?host notify? commands on the smlink. writing a 0 to this bit has no effect 0 = bit is clear, allows the notify address and data registers to be overwritten. 1 = this bit is set when the cmi has completely received a successful host notify command on the smlink pins. 0h rwc table 24-50. offset 11h: scmd: slave command register (sheet 1 of 2) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 11h 11h size: 8 bit default: 00h power well: resume a bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 00h 02 smbalert_dis 0 = allows the generation of interrupt or smi#. 1 = software sets this bit to 1 to block the generation of the interrupt or smi# due to the smbalert# source. this bit is logically inverted and anded with the smbalert_sts bit. the resulting signal is distributed to the smi# and/or interrupt generation logic. this bit does not effect the wake logic. 0h rw 01 host_ notify_ wken software sets this bit to 1 to enable the reception of a host notify command as a wake event. when enabled this event is ored with the other smbus wake events and is reflected in the smb_wak_sts bit of the general purpose event 0 status register. 0 = disable 1 = enable 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 933 intel ? ep80579 integrated processor 24.8.2.5 offset 14h: nda: notify device address register this register is in the resume well and is reset by cf9 reset or rsmrst#. 00 host_ notify_ intren software sets this bit to 1 to enable the generation of interrupt or smi# when host_notify_sts is 1. this enable does not affect the setting of the host_notify_sts bit. when the interrupt is generated, either pirqb or smi# is generated, depending on the value of the smb_smi_en bit (d31, f3, off40h, b1). if the host_notify_sts bit is set when this bit is written to a 1, then the interrupt (or smi#) will be generated. the interrupt (or smi#) is logically generated by anding the sts and intren bits. 0 = disable 1 = enable 0h rw a. this register is in the resume well and is reset by cf9 reset or rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll the register until a write takes effect before assuming that a write has completed internally. table 24-50. offset 11h: scmd: slave command register (sheet 2 of 2) description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 11h 11h size: 8 bit default: 00h power well: resume a bit range bit acronym bit description sticky bit reset value bit access table 24-51. offset 14h: nda: notify device address register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 14h 14h size: 8 bit default: 00h power well: resume a bit range bit acronym bit description sticky bit reset value bit access 07 : 01 device_ address this field contains the 7-bit device address received during the host notify protocol of the smbus specification . software should only consider this field valid when the host_notify_sts bit is set to 1. 0000000h ro 00 reserved reserved 0h a. reset by cf9 reset or rsmrst#.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 934 order number: 320066-003us 24.8.2.6 offset 16h: ndlb: notify data low byte register this register is in the resume well and is reset by cf9 reset or rsmrst#. 24.8.2.7 offset 17h: ndhb: notify data high byte register this register is in the resume well and is reset by cf9 reset or rsmrst#. table 24-52. offset 16h: ndlb: notify data low byte register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 16h 16h size: 8 bit default: 00h power well: resume a a. reset by cf9 reset or rsmrst#. bit range bit acronym bit description sticky bit reset value bit access 07 : 00 data_low_byt e this field contains the first (low) byte of data received during the host notify protocol of the smbus specification . software should only consider this field valid when the host_notify_sts bit is set to 1. 00h ro table 24-53. offset 17h: ndhb: no tify data high byte register description: view: pci bar: sm_base (io) bus:device:function: 0:31:3 offset start: offset end: 17h 17h size: 8 bit default: 00h power well: resume a a. reset by cf9 reset or rsmrst#. bit range bit acronym bit description sticky bit reset value bit access 07 : 00 data_ high_byte this field contains the second (high) byte of data received during the host notify protocol of the smbus specification . software should only consider this field valid when the host_notify_sts bit is set to 1. 00h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 935 intel ? ep80579 integrated processor 24.9 slave interface behavioral description the smbus slave logic does not generate or handle receiving the pec byte. there is no asf support. the slave interface allows the cmi to decode cycles on smlink in tco compatible mode, and allows an external microcontroller to perform specific actions. key features and capabilities: ? supports decode of three types of messages: byte write, byte read, and host notify ? register for the receive slave address. this is the address that the cmi decodes. a default value is provided so that the slave interface can be used without the processor having to program this register. ? receive slave data register in the smbus i/o space that includes the data written by the external microcontroller ? registers that the external microcontroller can read to get the state ? status bits to indicate that the smlink/smbus slave logic caused an interrupt or smi# ? bit 0 of the slave status register for the host notify command ? bit 16 of the smi status register for all others note: the external microcontroller should not attempt to access the smbus slave logic until one second after both: rtest# is high and rsmrst# is high. if a master leaves the clock and data bits of the smlink or smbus interface at '1' for 50 s or more in the middle of a cycle, the slave logic's behavior is undefined. this is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. 24.9.1 format of slave write cycle the external master performs byte write commands to the smbus slave interface. the command field (bits 11 ? 18) indicate which register is being accessed. the data field (bits 20 ? 27) indicate the value that should be written to that register. the write cycle format is shown below in table 24-54 . ta b l e 2 4 - 5 5 has the values associated with the registers. table 24-54. slave write cycle format bit description driven by comment 1 start condition external microcontroller 2 ? 8 slave address - 7 bits external microcontroller must match value in receive slave address register 9 write external microcontroller hardwired to 0 10 ack cmi 11 ? 18 command external microcontroller this field indicates which register will be accessed. see table 24-55 for the register definitions 19 ack cmi 20 ? 27 register data external microcontroller see table 24-55 for the register definitions 28 ack cmi 29 stop external microcontroller
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 936 order number: 320066-003us note: the external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. the cmi overwrites the old value with any new value received. a race condition is possible where the new value is being written to the register just at the time it is being read. the cmi does not attempt to cover this race condition (i.e., unpredictable results in this case). 24.9.2 format of read command the external master performs byte read co mmands to the smbus slave interface. the command field (bits 11-18) indicate which register is being accessed. the data field (bits 30-37) indicate the value that should be read from that register. ta b l e 2 4 - 5 7 shows the read cycle format. table 24-58 shows the register mapping for the data byte. table 24-55. slave write registers register function: 0command register. see ta b l e 2 4 - 5 6 for legal values written to this register. 1 ? 3 reserved 4 data message byte 0 5 data message byte 1 6 ? 7 reserved 8 reserved 9 ? ffh reserved table 24-56. command types command type description 0 reserved 1 wake/smi#: wake system if it is not already awake. if system is already awake, then an smi# is generated. 2 unconditional powerdown: this command should set the pwrbtnor_sts bit, and have the same effect as the power button override occurring. 3 hard reset without power cycling system: the causes a soft reset of the system (does not include cycling of the power supply). this is equivalent to a write to the cf9h register with bits 02:01 set to 1, but bit 03 set to 0. 4 hard reset system: the causes a hard reset of the system (including cycling of the power supply). this is equivalent to a write to the cf9h register with bits 03:01 set to 1. 5 disable the tco messages. this command disables the iich from sending heartbeat and event messages. once this command has been done, there is no method to reenable the heartbeat and event messages, until cf9 reset or rsmrst# goes low and then high. 6 wd reload: reload watchdog timer. 7 reserved 8 smlink_slave_smi: when the cmi detects this command type while in the s0 state, it will set the smlink_slave_smi_sts bit. this co mmand should only be used if the system is in an s0 state. if the message is received during s3 or s5 states, it is acknowledged by the cmi but the smlink_slave_smi_sts bit is not set. note: it is possible that the system transitions out of the s0 state at the same time that the smlink_slave_smi command is received. in this case, the smlink_slave_smi_sts bit may get set but not serviced before the system goes to sleep. once the system returns to s0, the smi associated with this bit would then be generated. software must be able to handle this scenario. 9 ? ffh reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 937 intel ? ep80579 integrated processor table 24-57. slave read cycle format bit description driven by: comment: 1 start external microcontroller 2 ? 8 slave address - 7 bits external microcontroller m ust match value in receive slave address register 9 write external microcontroller hardwired to 0 10 ack cmi 11 ? 18 command code - 8 bits external microcontroller indicates which register is being accessed. see table 24-58 for list of implemented registers. 19 ack cmi 20 repeated start external microcontroller 21 ? 27 slave address - 7 bits external microcontroller m ust match value in receive slave address register 28 read external microcontroller hardwired to 1 29 ack cmi 30 ? 37 data byte cmi value depends on register being accessed. see table 24-58 for list of implemented registers. 38 not ack external microcontroller 39 stop external microcontroller table 24-58. data values for slave read registers (sheet 1 of 2) register bits description 0 07:00 reserved for capabilities indication. should always return 00h. future chips may return another value to indicate different capabilities. 1 02:00 system power state 000 = s0 001 = reserved 010 = reserved 011 = s3 100 = reserved 101 = s5 110 = reserved 111 = reserved 07:03 reserved 2 03:00 reserved 07:04 reserved 3 05:00 watchdog timer current value. watchdog timer has 10 bits, but this field is only 6 bits. if the current value is greater than 3fh, the cmi always reports 3fh in this field. 07:06 reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 938 order number: 320066-003us warning: the external microcontroller is responsible to make sure that it does not read the contents of the various message registers until they have been written by the system processor. the cmi overwrites the old value with any new value received. a race condition is possible where the new value is being written to the register just at the time it is being read. the cmi does not attempt to cover this race condition (i.e., unpredictable results in this case). behavioral notes: the smbus protocol always has either start bit-address-write bit or repeated start bit- address-read bit. the cmi is implemented such that the read/write bit in the repeated start phase is ignored with an assumption that the protocol always followed. in other words, if start-address-read occurs (which is illegal for smbus byte read protocol), the cmi still grabs the cycle. in another case, if a repeated start-address-write sequence occurs, then the cycle continues as a slave read. 24.9.3 format of the host notify command the cmi tracks and responds to the standard host notify command as specified in the smbus specification . the host address for this command is fixed to 0001000b. if the cmi already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the host_notify_sts bit), then it will nack following the host address byte of the protocol. this allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. 4 00 1 = the intruder detect (intrd_det) bit is set. this indicates that the system cover has been opened. 01 1 = bti temperature event occurred. this bit is set if the cmi?s prochot# input signal is active. need to take after polarity control. 02 doa processor status. this bit is 1 to indicate that the processor is dead. 03 1 = second_to_sts bit set. this bit is set after the second timeout (second_to_sts bit) of the watchdog timer occurs. 06:04 reserved. will always be 0, but software should ignore. 07 reflects the value of the gpi[11]/smbalert# pin (and is dependent upon the value of the gpi_inv[11] bit. if the gpi_inv[11] bit is 1, then the value in this bit equals the level of the gpi[11]/smbalert# pin (high = 1, low = 0). if the gpi_inv[11] bit is 0, then the value of this bit equals the inverse of the level of the gpi[11]/smbalert# pin (high = 0, low = 1). 5 00 fwh bad bit. this bit is 1 to indicate that the fwh read returned ffh, which indicates that it is probably blank. 01 battery low status. ?1? if the batlow# pin is a ?0?. 02 cpu power failure status: ?1? if the cpupwr_flr bit in the gen_pmcon_2 register is set. 07:01 reserved 6 07:00 contents of the message 1 register. see section 18.2.2.8 for details. 7 07:00 contents of the message 2 register. see section 18.2.2.8 for details. 8 07:00 contents of the wdstatus register. see section 18.2.2.9 for details. 9 07:00 contents of the sata sgpio control register (bits 07:00). see section 48.3.3.1 for details. a 07:00 contents of the sata sgpio control register (bits 15:08). see section 48.3.3.1 for details. b 07:00 contents of the sata sgpio control register (bits 23:16). see section 48.3.3.1 for details. c ? ffh 07:00 reserved table 24-58. data values for slave read registers (sheet 2 of 2) register bits description
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 939 intel ? ep80579 integrated processor note: host software must always clear the host_notify_sts bit after completing any necessary reads of the address and data registers. table 24-59 shows the host notify protocol. table 24-59. host notify protocol bit description driven by: comment: 1 start external master 2 ? 8 smb host addr - 7 bits external master always 0001_000 9 write external master hardwired to 0 10 ack (or nack) cmi the cmi nacks if host_notify_sts is 1 11 ? 17 device address - 7 bits external master indicates the address of the master; loaded in to the notify device address register 18 unused- hardwired to 0 external master 7-bit-only address; this bit is inserted to complete the byte 19 ack cmi 20 ? 27 data byte low external master loaded in to the notify data low byte register 28 ack cmi 29 ? 36 data byte high external master loaded in to the notify data high byte register 37 ack cmi 38 stop external master
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 940 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 941 intel ? ep80579 integrated processor 25.0 usb (1.1) controller: bus 0, device 29, function 0 25.1 usb (1.1) controller configuration register details note: reserved bits are read only. warning: address locations that are not listed are considered reserved register locations and are read only. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure and unpredictable results. table 25-1. bus 0, device 29, functions 0, summary of usb (1.1) controller pci configuration registers offset start offset end register id - description default value 00h 03h ?id - identifiers register? on page 942 50338086h 04h 05h ?pcicmd - command register? on page 942 0000h 06h 07h ?pcists - device status register? on page 943 0280h 08h 08h ?rid - revision id register? on page 944 variable 0ah 0ah ?subc - sub class code register? on page 945 03h 0bh 0bh ?bcc - base class code register? on page 945 0ch 0dh 0dh ?mlt - master latency timer register? on page 945 00h 0eh 0eh ?hdr - header type register? on page 946 variable 20h 23h ?usbiobar - base address register? on page 946 00000001h 2ch 2dh ?usbx_svid - usb subsystem vendor id register? on page 947 0000h 2eh 2fh ?usbx_sid - usb subsystem id register? on page 947 0000h 3ch 3ch ?intl - interrupt line register? on page 948 00h 3dh 3dh ?intp - interrupt pin register? on page 948 variable 60h 60h ?sbrn - serial bus release number register? on page 948 10h c0h c1h ?usblkmcr - usb legacy keyboard/mouse control register? on page 949 2000h c4h c4h ?usbren - usb resume enable register? on page 951 00h c8h c8h ?usbcwp - usb core well policy register? on page 951 00h f8h fbh ?manid - manufacturer id register? on page 952 00010f90h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 942 order number: 320066-003us 25.1.1 register details 25.1.1.1 id - identifiers register 25.1.1.2 pcicmd - command register table 25-2. id - identifiers register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 00h 03h size: 32 bit default: 50338086h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 did device id: this 16-bit field is defined as follows: function 0 5033h 5033h ro 15 : 00 vid vendor id: 16-bit field which indicates the company vendor as intel. 8086h ro table 25-3. pcicmd - command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h 10 intdis interrupt disable: 0 = enable. the function is able to generate its interrupt to the interrupt controller. 1 = disable. the function is not capable of generating interrupts. the corresponding interrupt status bit is not affected by the interrupt enable. 0h rw 09 fbe fast back to back enable: hardwired to?0?. 0h 08 serren serr# enable: hardwired to?0?. 0h 07 wcc wait cycle control: hardwired to?0?. 0h 06 per parity error response: hardwired to?0?. 0h 05 vgaps vga palette snoop: hardwired to?0?. 0h 04 pmwe postable memory write enable: hardwired to?0?. 0h 03 sce special cycle enable: hardwired to?0?. 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 943 intel ? ep80579 integrated processor 25.1.1.3 pcists - device status register 02 bme bus master enable: 0 = disable. 1 = enable. can generate cycles to main memory as a master for usb transfers. 0h rw 01 mse memory space enable: hardwired to?0?. 0h 00 iose i/o space enable: this bit controls access to the i/o space registers. 0 = disable: accesses to the usb i/o registers is disabled. 1 = accesses to the usb i/o registers is enabled. the base address register for usb must be programmed before this bit is set. 0h rw table 25-4. pcists - device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 06h 07h size: 16 bit default: 0280h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: 0 = no parity error detected. 1 = set when a data parity error is detected on writes to the uhci register space or on read completions returned to the host controller. note: software sets this bit to 0 by writing a 1 to this bit location. 0h rwc 14 sse reserved 0h 13 rma received master-abort status: 0 = no master abort generated by usb. 1 = usb as a master, receives a master abort. note: software sets this bit to 0 by writing a 1 to this bit location. 0h rwc 12 reserved reserved 0h 11 sta signaled target-abort status: 0 = did not terminate a transaction to a usb function with a target abort. 1 = usb function is targeted with a transaction that terminates with a target abort. note: software sets this bit to 0 by writing a 1 to this bit location. 0h rwc table 25-3. pcicmd - command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 944 order number: 320066-003us 25.1.1.4 rid - revision id register the value reported in this register depends on the value written to the revision id in device 31, function 0, offset 08h. 10 : 09 devt devsel# timing status: this 2-bit field defines the timing for devsel# assertion. these read-only bits indicate the devsel# timing when performing a positive decode. since usb is not pci-based, the value in this field is arbitrary. 01h ro 08 reserved hardwired as?0?. 0h 07 reserved hardwired as?1? 1 06 reserved hardwired as?0?. 0h 05 reserved hardwired as?0?. 0h 04 reserved hardwired as?0?. 0h 03 intstat interrupt status: this read-only bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = interrupt is deasserted. 1 = interrupt is asserted. the value reported in this bit is independent of the value in the interrupt enable bit. 0h ro 02 : 00 reserved reserved 000h table 25-4. pcists - device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 06h 07h size: 16 bit default: 0280h power well: core bit range bit acronym bit description sticky bit reset value bit access table 25-5. rid - revision id register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 revid revision id: 8-bit value that indicates the revision number of the usb1.1 interface.the value reported in this register depends on the value written to the revision id in device 31, function 0, offset 08h. this register follows the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 945 intel ? ep80579 integrated processor 25.1.1.5 subc - sub class code register a value of 03h indicates that this is a universal serial bus host controller. 25.1.1.6 bcc - base class code register a value of 0ch indicates that this is a serial bus controller. 25.1.1.7 mlt - master latency timer register because the usb controller is internally implemented with arbitration on the cmi, it does not need a master latency timer. the bits are hardwired to 0. table 25-6. subc - sub class code register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 0ah 0ah size: 8 bit default: 03h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scc sub-class code: indicates the device is a usb1.1 device. 03h ro table 25-7. bcc - base class code register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 0bh 0bh size: 8 bit default: 0ch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 bcc base class code: indicates the device is a usb device. 0ch ro table 25-8. mlt - master latency timer register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mlc master latency count: hardwired to 0. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 946 order number: 320066-003us 25.1.1.8 hdr - header type register for function 0, bit 7 is determined by the values in the usb function disable bits (11:8 of the function disable register in memory-mapped configuration space). 25.1.1.9 usbiobar - base address register usbiobar sets the base address in i/o space for additional usb configuration registers (see section 25.2, ?usb (1.1) controller i/o-mapped register details? on page 953 ). these registers can be mapped anywhere in the 64k i/o space on 32-byte boundaries. table 25-9. hdr - header type register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 0eh 0eh size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 mfb multi-function bit: 0 = single-function device. 1 = multi-function device. since the upper functions in this device can be individually hidden, this bit must be based on the function-disable bits in the function disable register in the memory-mapped configuration space as follows: d29_f7_disable d29_f0_disable (bit 15) (bit 8) multi-function bit 0 0 1 0 1 invalid 10 0 11 usb disabled note: variable ro 06 : 00 configl configuration layout: hardwired to 00h, which indicates the standard pci configuration layout. 00h ro table 25-10. usbiobar - base address register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 20h 23h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 reserved reserved 0h 15 : 05 ba base address: bits [15:5] correspond to i/o address signals ad [15:5], respectively. this gives 32 bytes of relocatable i/o space. 0h rw 04 : 01 reserved reserved 0h 00 rte resource type indicator: this bit is hardwired to 1 indicating that the base address field in this register maps to i/o space 1ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 947 intel ? ep80579 integrated processor 25.1.1.10 usbx_svid - usb subsystem vendor id register note: x indicates the usb controller number. bios sets the value in this register to identify the subsystem vendor id. the usb_svid register, in combination with the usb subsystem id register, enables the operating system to distinguish each subsystem from the others. note: software can write to this register only once per core well reset. writes must be done as a single 16-bit cycle. 25.1.1.11 usbx_sid - usb subsystem id register note: x indicates the usb controller number. bios sets the value in this register to identify the subsystem id. the sid register, in combination with the svid register, enables the operating system to distinguish each subsystem from other(s). note: the software can write to this register only once per core well reset. writes must be done as a single 16-bit cycle. table 25-11. usbx_svid - usb subsystem vendor id register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: bios sets the value in this register to identify the subsystem vendor id. the usb_svid register, in combination with the usb subsystem id register, enables the operating system to distinguish each subsystem from the others. 0000h rwo table 25-12. usbx_sid - usb subsystem id register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 subid subsystem id: bios sets the value in this register to identify the subsystem id. the sid register, in combination with the svid register, enables the operating system to distinguish each subsystem from other(s). indicates the subsystem as identified by the vendor. this field is write once and is locked until a reset occurs. 0000h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 948 order number: 320066-003us 25.1.1.12 intl - interrupt line register 25.1.1.13 intp - interrupt pin register 25.1.1.14 sbrn - serial bus release number register a value of 10h indicates that this is controller follows usb release 1.1. table 25-13. intl - interrupt line register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intl interrupt line: this data is not used. this data is used to communicate to software which interrupt line the interrupt pin is connected to. 00h rw table 25-14. intp - interrupt pin register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 3dh 3dh size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 intpn interrupt pin: this read-only value tells the software which interrupt pin each usb host controller uses. the upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the interrupt pin default values that are programmed in the memory-mapped configuration space as follows: function 0 d29ip.u0p note: this does not determine the mapping to the pirq pins. variable ro table 25-15. sbrn - serial bus release number register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: 60h 60h size: 8 bit default: 10h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 sbn indicates that this controller follows usb release 1.0. 10h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 949 intel ? ep80579 integrated processor 25.1.1.15 usblkmcr - usb legacy keyboard/mouse control register this register is implemented separately in each of the usb1.1 functions. however, the enable and status bits for the trapping logic are ored and shared, respectively, since their functionality is not specific to any one host controller. table 25-16. usblkmcr - usb legacy keyboard/mouse control register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: c0h c1h size: 16 bit default: 2000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 smibyendps smi caused by end of pass-through: indicates if the event occurred. even if the corresponding enable bit is not set in the bit 7, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = no event occurred. 1 = event occurred. note: writing a 1 to this bit (in any of the controllers) will clear the latch. 0h rwc 14 reserved reserved 0h 13 usbpirqen pci interrupt enable: used to prevent the usb controller from generating an interrupt due to transactions on its ports. when disabled, that it will probably be configured to generate an smi using bit 4 of this register. defaults to 1 for compatibility with older usb software. 0 = disable 1 = enable 1rw 12 smibyusb smi caused by usb interrupt: this bit indicates if an interrupt event occurred from this classic controller. the interrupts from the classic usb controller is taken before the enable in bit 13 has any effect to create this read-only bit. even if the corresponding enable bit is not set in the bit 4, then this bit may still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = no event occurred 1 = event occurred. note: writing a 1 to this bit will have no effect. the software must clear the interrupts via the usb controllers. 0h ro 11 trapby64w smi caused by port 64 write: indicates if the event occurred. even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. writing a 1 to this bit (in any of the controllers) will clear the bit. the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = no event occurred. 1 = event occurred. note: software clears this bit by writing a 1 to the bit location in any of the controllers 0h rwc 10 trapby64r smi caused by port 64 read: indicates if the event occurs. even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. writing a 1 to this bit (in any of the controllers) will clear the bit. 0 = no event occurred. 1 = event occurred. note: software clears this bit by writing a 1 to the bit location in any of the controllers 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 950 order number: 320066-003us 09 trapby60w smi caused by port 60 write: indicates if the event occurs. even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. writing a 1 to this bit (in any of the controllers) will clear the latch. the a20gate pass-through logic allows specific port 60h writes to complete without setting this bit. 0h rwc 08 trapby60r smi caused by port 60 read: indicates if the event occurs. even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. writing a 1 to this bit (in any of the controllers) will clear the latch. 0h rwc 07 smiatendps smi at end of pass-through enable: this bit enables smi at the end of a pass-through. this can occur if an smi is generated in the middle of a pass through, and needs to be serviced later. 0 = disable 1 = enable 0h rw 06 pstate pass through state: 0 = if software needs to reset this bit, it must set bit 5 in all of the host controllers to 0. 1 = indicates that the state machine is in the middle of an a20gate pass-through sequence. note: software must set bit 5 in all of the host controllers to 0 to reset this bit. 0h ro 05 a20passen a20gate pass-through enable: 0 = disable. 1 = enable. allows a20gate sequence pass-through function. a specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the smi status bits. smi# will not be generated, even if the various enable bits are set. 0h rw 04 usbsmien smi on usb irq: 0 = disable. the usb interrupt will not cause an smi event. 1 = enable. the usb interrupt will cause an smi event. 0h rw 03 64wen smi on port 64 writes enable: 0 = disable. a 1 in bit 11 will not cause an smi event. 1 = enable. a 1 in bit 11 will cause an smi event. 0h rw 02 64ren smi on port 64 reads enable: 0 = disable. a 1 in bit 10 will not cause an smi event. 1 = enable. a 1 in bit 10 will cause an smi event. 0h rw 01 60wen smi on port 60 writes enable: 0 = disable. a 1 in bit 9 will not cause an smi event. 1 = enable. a 1 in bit 9 will cause an smi event. 0h rw 00 60ren smi on port 60 reads enable: 0 = disable. a 1 in bit 8 will not cause an smi event. 1 = enable. a 1 in bit 8 will cause an smi event. 0h rw table 25-16. usblkmcr - usb legacy keyboard/mouse control register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: c0h c1h size: 16 bit default: 2000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 951 intel ? ep80579 integrated processor 25.1.1.16 usbren - usb resume enable register note: there is no support for wake from usb when in s3/s4/s5. 25.1.1.17 usbcwp - usb core well policy register table 25-17. usbren - usb resume enable register description: size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 0h 01 port1en 0 = the usb controller will not look at this port for a wakeup event. 1 = enables port 1 of the usb controller to look at wakeup events. when set, the usb controller will monitor port 1 for remote wakeup and connect/disconnect events. 0h rw 00 port0en 0 = the usb controller will not look at this port for a wakeup event. 1 = enables port 0 of the usb controller to look at wakeup events. when set, the usb controller will monitor port 0 for remote wakeup and connect/disconnect events. 0h rw table 25-18. usbcwp - usb core well policy register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: c8h c8h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved reserved 0h 00 sbmspen static bus master status policy enable: 0 = the uhci host controller dynamically sets the bus master status bit based on the memory accesses that are scheduled. see section 25.5 for details. 1 = the uhci host controller statically forces the bus master status bit in power management space to 1 whenever the hchalted bit is cleared. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 952 order number: 320066-003us 25.1.1.18 manid - manufacturer id register table 25-19. manid - manufacturer id register description: view: pci bar: configuration bus:device:function: 0:29:0 offset start: offset end: f8h fbh size: 32 bit default: 00010f90h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 00h ro 23 : 16 sid stepping id: this field increments for each stepping of the part. this field can be used by software to differentiate steppings when the revision id may not change. note: 00h for a0 stepping note: 01h for b0 stepping 01h ro 15 : 08 mid manufacturer: 0fh = intel 0fh ro 07 : 00 reserved reserved1263 90h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 953 intel ? ep80579 integrated processor 25.2 usb (1.1) controller i/ o-mapped register details some of the read/write register bits which deal with changing the state of the usb hub ports function such that on read back they reflect the current state of the port and not necessarily the state of the last write to the register. this allows the software to poll the state of the port and wait until it is in the proper state before proceeding. a host controller reset, global reset, or port reset will immediately terminate a transfer on the affected ports and disable the port. this affects the usbcmd register, bit [4] and the portsc registers, bits [12,6,2]. see individual bit descriptions for more detail. base address for these i/o registers is set by the usbiobar register, see section 25.1.1.9, ?usbiobar - base address register? on page 946 . 25.2.1 register details 25.2.1.1 usbcmd: usb command register the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. table 25-22 provides additional information on the operation of the run/stop and debug bits. table 25-20. summary of usb (1.1) controller configuration registers mapped through usbiobar i/o bar offset start offset end register id - description default value 00h 01h ?usbcmd: usb command register? on page 954 0000h 02h 03h ?usbsts: usb status register? on page 957 0020h 04h 05h ?usbintr: usb interrupt enable register? on page 959 0000h 06h 07h ?frnum: frame number register? on page 959 0000h 08h 0bh ?frbaseadd: frame list base address register? on page 960 xxxxx000h 0ch 0ch ?sofmod: start of frame modify register? on page 961 40h 10h 11h ?pscr - port status and control register? on page 962 0080h 12h 13h ?pscr - port status and control register? on page 962 0080h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 954 order number: 320066-003us table 25-21. usbcmd: usb command register (sheet 1 of 2) description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 00h 01h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved. 0h 08 reserved 1 = reserved 0h rw 07 maxp max packet: 0 = 32 bytes. 1 = 64 bytes. this bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. this value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the sof counter. use of reclamation packets larger than the programmed size will cause a babble error if executed during the critical window at frame end. the babble error results in the offending endpoint being stalled. software is responsible for ensuring that any packet which could be executed under bandwidth reclamation be within this size limit. 0h rw 06 cf configure flag: 0 = indicates that software has not completed host controller configuration. 1 = hcd software sets this bit as the last action in its process of configuring the host controller. this bit has no effect on the hardware. it is provided only as a semaphore service for software. 0h rw 05 swdbg software debug: 0 = normal mode. 1 = debug mode. in software debug mode, the host controller clears the run/stop bit after the completion of each usb transaction. the next transaction is executed when software sets the run/stop bit back to 1. the swdbg bit must only be manipulated when the controller is in the stopped state. this can be determined by checking the hchalted bit in the usbsts register. 0h rw 04 fgr force global resume: 0 = software sets this bit to 0 after 20 ms has elapsed to stop sending the global resume signal. at that time all usb devices must be ready for bus activity. 1 = host controller sends the global resume signal on the usb. the host controller sets this bit to 1 when a resume event (connect, disconnect, or k-state) is detected while in global suspend mode. the 1 to 0 transition causes the port to send a low speed eop signal. this bit will remain a 1 until the eop has completed. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 955 intel ? ep80579 integrated processor 03 egsm enter global suspend mode: 0 = software resets this bit to 0 to come out of global suspend mode. software writes this bit to 0 at the same time that force global resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = host controller enters the global suspend mode. no usb transactions occurs during this time. the host controller is able to receive resume signals from usb and interrupt the system. software must ensure that the run/stop bit (bit 0) is cleared prior to setting this bit. 0h rw 02 greset global reset: 0 = this bit is reset by the software after a minimum of 10 ms has elapsed as specified in the universal serial bus (usb) specification, rev. 2.0 . 1 = global reset. the host controller sends the global reset signal on the usb and then resets all its logic. chip hardware reset has the same effect as global reset (bit 2), except that the host controller does not send the global reset on usb. 0h rw 01 hcreset host controller reset: the hcreset effects on hub registers are slightly different from chip hardware reset and global usb reset. the hcreset affects bits [8,3:0] of the port status and control register (portsc) of each port. hcreset resets the state machines of the host controller including the connect/disconnect state machine (one for each port). when the connect/ disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the portsc to get set. the disconnect also causes bit 8 of portsc to reset. about 64 bit times after hcreset goes to 0, the connect and low-speed detect will take place and bits 0 and 8 of the portsc will change accordingly. 0 = reset by the host controller when the reset process is complete. 1 = reset. when this bit is set, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. 0h rw 00 rs run/stop: 0 = stop. completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. the host controller clears this bit when the following fatal errors occur: consistency check failure, memory access errors. 1 = run. proceeds with execution of the schedule and continues execution as long as this bit is set. 0h rw table 25-21. usbcmd: usb command register (sheet 2 of 2) description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 00h 01h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 956 order number: 320066-003us when the usb host controller is in software debug mode (usbcmd register bit 5=1), the single stepping software debug operation is as follows: to enter software debug mode: 1. hcd puts host controller in stop state by setting the run/stop bit to 0. 2. hcd puts host controller in debug mode by setting the swdbg bit to 1. 3. hcd sets up the correct command list and start of frame value for starting point in the frame list single step loop: 4. hcd sets run/stop bit to 1. 5. host controller executes next active td, sets run/stop bit to 0, and stops. 6. hcd reads the usbcmd register to check if the single step execution is completed (hchalted=1). 7. hcd checks results of td execution. go to step 4 to execute next td or step 8 to end software debug mode. 8. hcd ends software debug mode by setting swdbg bit to 0. 9. hcd sets up normal command list and frame list table. 10. hcd sets run/stop bit to 1 to resume normal schedule execution. in software debug mode, when the run/stop bit is set, the host controller starts. when a valid td is found, the run/stop bit is reset. when the td is finished, the hchalted bit in the usbsts register (bit 5) is set. the software debug mode skips over inactive tds and only halts after an active td has been executed. when the last active td in a frame has been executed, the host controller waits until the next sof is sent and then fetches the first td of the next frame before halting. this hchalted bit can also be used outside of software debug mode to indicate when the host controller has detected the run/stop bit and has completed the current transaction. outside of the software debug mode, setting the run/stop bit to 0 always resets the sof counter so that when the run/stop bit is set the host controller starts over again from the frame list location pointed to by the frame list index (see frnum register description) rather than continuing where it stopped. table 25-22. run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation swdbg (bit 5) run/ stop (bit 0) description 00 if executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the frnum register. (while run/stop=0, the frnum register can be reprogrammed). 01 execution of the command list resumes from start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 10 if executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. all status are preserved. the host controller begins execution of the command list from where it left off when the run/stop bit is set. 11 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to 0 by the host controller when a td is being fetched. this causes the host controller to stop again after the execution of the td (single step). when the host controller has completed execution, the hc halted bit in the status register is set.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 957 intel ? ep80579 integrated processor 25.2.1.2 usbsts: usb status register this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software sets a bit to 0 in this register by writing a 1 to it. see section 4, ?interrupts,? of the universal host controller interface (uhci) specification, rev. 1.1 , for additional information concerning usb interrupt conditions. table 25-23. usbsts: usb status register (sheet 1 of 2) description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 02h 03h size: 16 bit default: 0020h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 06 reserved reserved 0h ro 05 hch hchalted: 0 = the host controller is running. 1 = the host controller has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). default. software clears this bit by writing a 1 to it. 1rwc 04 hcpe host controller process error: 0 = no error. 1 = the host controller has detected a fatal error. this indicates that the host controller suffered a consistency check failure while processing a transfer descriptor. an example of a consistency check failure would be finding an illegal pid field while processing the packet header portion of the td. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further schedule execution. a hardware interrupt is generated to the system. software clears this bit by writing a 1 to it. 0h rwc 03 hse host system error: 0 = no error occurred. 1 = a serious error occurs during a host system access involving the host controller module. conditions that set this bit to 1 include parity error, master abort, and target abort. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system. software clears this bit by writing a 1 to it. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 958 order number: 320066-003us 25.2.1.3 usbintr: usb interrupt enable register this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error-bit 4, usbsts register) cannot be disabled by the host controller. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. 02 rsm_det resume detect: 0 = resume not detected. 1 = the host controller received a ?resume? signal from a usb device. this is only valid if the host controller is in a global suspend state (bit 3 of command register = 1). software clears this bit by writing a 1 to it. 0h rwc 01 usbeint usb error interrupt: the host controller sets this bit to 1 when completion of a usb transaction results in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. 0 = no usb error interrupt. 1 = completion of a usb transaction results in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. software clears this bit by writing a 1 to it. 0h rwc 00 usbint usb interrupt: 0 = no usb interrupt. 1 = the host controller sets this bit to 1 when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual length field in td is less than maximum length field in td), and short packet detection is enabled in that td. software clears this bit by writing a 1 to it. 0h rwc table 25-23. usbsts: usb status register (sheet 2 of 2) description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 02h 03h size: 16 bit default: 0020h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 959 intel ? ep80579 integrated processor 25.2.1.4 frnum: frame number register bits [10:0] of this register contain the current frame number which is included in the frame sof packet. this register reflects the count value of the internal frame number counter. bits [9:0] are used to select a particular entry in the frame list during schedule execution. this register is updated at the end of each frame time. this register must be written as a word. byte writes are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (usbsts register). a write to this register while the run/stop bit is set (usbcmd register) is ignored. table 25-24. usbintr: usb interrupt enable register description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 05 reserved reserved 0h 04 scratchpad scratchpad 0h rw 03 spien short packet interrupt enable: 0 = disabled 1 = enabled. 0h rw 02 ioc interrupt on complete: 0 = disabled 1 = enabled. 0h rw 01 rien resume interrupt enable: 0 = disabled 1 = enabled. 0h rw 00 tien timeout/crc interrupt enable: 0 = disabled 1 = enabled. 0h rw table 25-25. frnum: frame number register description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 06h 07h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h ro 10 : 00 flcifn frame list current index/frame number: bits [10:0] provide the frame number in the sof frame. the value in this register increments at the end of each time frame (approximately every 1 ms). in addition, bits [9:0] are used for the frame list current index and correspond to memory address signals [11:2]. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 960 order number: 320066-003us 25.2.1.5 frbaseadd: frame list base address register this 32-bit register contains the beginning address of the frame list in the system memory. hcd loads this register prior to starting the schedule execution by the host controller. when written, only the upper 20 bits are used. the lower 12 bits are written as zero (4 kbyte alignment). the contents of this register are combined with the frame number counter to enable the host controller to step through the frame list in sequence. the two least significant bits are always 00. this requires dword alignment for all list entries. this configuration supports 1024 frame list entries. 25.2.1.6 sofmod: start of frame modify register this 1-byte register is used to modify the value used in the generation of sof timing on the usb. only the 7 least significant bits are used. when a new value is written into the these 7 bits, the sof timing of the next frame will be adjusted. this feature can be used to adjust out any offset from the clock source that generates the clock that drives the sof counter. this register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. using this register, the frame length can be adjusted across the full range required by the usb specification . its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by usb system software at any time. its value will take effect from the beginning of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of its value for reprogramming if necessary. table 25-26. frbaseadd: frame list base address register description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 08h 0bh size: 32 bit default: xxxxx000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 bad base address: these bits correspond to memory address signals [31:12], respectively. xrw 11 : 00 reserved reserved. must be written as 0s. 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 961 intel ? ep80579 integrated processor table 25-27. sofmod: start of frame modify register description: view: pci bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 0ch 0ch size: 8 bit default: 40h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved 0h 06 : 00 softv sof timing value: guidelines for the modification of frame time are contained in chapter 7 of the usb specification . the sof cycle time (number of sof counter clock periods to generate a sof frame length) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof cycle time of 12000. for a 12 mhz sof counter clock input, this produces a 1 ms frame period. the following table indicates what sof timing value to program into this field for a certain frame period. 40h rw frame length (# 12 mhz clocks) (decimal) sof timing value (this register) (decimal) 11936 0 11937 1 ?? 11999 63 12000 64 12001 65 ?? 12062 126 12063 127
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 962 order number: 320066-003us 25.2.1.7 pscr - port status and control register after a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (single- ended zero). table 25-28. pscr - port status and control register (sheet 1 of 2) description: view: pci 1 bar: usbiobar (io) bus:device:function: 0:29:0 offset start: a offset end: 10h 11h view: pci 2 bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 12h 13h size: 16 bit default: 0080h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 13 reserved reserved 0h 12 sus suspend: 0 = port not in suspend state. 1 = port in suspend state. this bit should not be written to a 1 if global suspend is active (bit 3=1 in the usbcmd register). this bit and bit 2 below define the hub states: bits [12,2] hub state x,0 disable 0,1 enable 1,1 suspend when in suspend state, downstream propagation of data is blocked on this port, except for single-ended 0 resets (global reset and port reset). the blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. in the suspend state, the port is sensitive to resume detection. the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the usb. normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. however, in the case of a specific error condition (out transaction with babble), the cmi may issue a start-of-frame, and then suspend the port. 0h rw 11 oci overcurrent indicator: this bit is cleared by software writing a ?1?. 0 = overcurrent pin inactive. 1 = overcurrent pin has gone from inactive to active on this port. software clears this bit by writing a 1 to it. 0h rwc 10 ocs overcurrent status: this bit indicates the current status of the oc# pin for this port. this bit is set and cleared by hardware. 0 = this port does not have an overcurrent condition. 1 = this port currently has an overcurrent condition. 0h ro 09 prst port reset: 0 = port is not disabled. 1 = port is disabled and sends the usb reset signaling. 0h rw 08 ls low speed device attached: 0 = full speed device is attached. 1 = low speed device is attached to this port. writes have no effect. 0h ro 07 reserved reserved: always read as 1. 1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 963 intel ? ep80579 integrated processor 06 rsm_det resume detect: 0 = no resume (k-state) detected/driven on port. 1 = resume detected/driven on port. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected for at least 32 s while the port is in the suspend state. cmi will then reflect the k-state back onto the bus as long as the bit remains a ?1?, and the port is still in the suspend state (bit 12,2 are ?11?) writing a 0 (from 1) causes the port to send a low speed eop. this bit will remain a 1 until the eop has completed. 0h rw 05 : 04 lns line status: these bits reflect the d+ (bit 4) and d- (bit 5) signals lines logical levels. these bits are used for fault detect and recovery as well as for usb diagnostics. this field is updated at eof2 time. 00h ro 03 port_enc port enable/disable change: 0 = no change. 1 = port enabled/disabled status has changed. for the root hub, this bit gets set only when a port is disabled due to disconnect on the that port or due to the appropriate conditions existing at the eof2 point (see the usb specification ). software clears this bit by writing a 1 to it. 0h rwc 02 port_en port enabled/disabled: 0 = disable. 1 = enable. ports can be enabled by host software only. ports can be disabled by either a fault condition (disconnect event, overcurrent, or other fault condition) or by host software. the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the usb. 0h rw 01 csc connect status change: 0 = no change. 1 = change in current connect status. indicates a change has occurred in the port?s current connect status (see bit 0). the hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. if, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ?setting? an already-set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a data transfer to the status change endpoint. system software is responsible for determining state change history in such a case. software sets this bit to 0 by writing a 1 to it. 0h rwc 00 ccs current connect status: 0 = no device is present. 1 = device is present on port. this value reflects the current state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0h ro a. usb #1 port 0: 10-11hport 1: 12-13h table 25-28. pscr - port status and control register (sheet 2 of 2) description: view: pci 1 bar: usbiobar (io) bus:device:function: 0:29:0 offset start: a offset end: 10h 11h view: pci 2 bar: usbiobar (io) bus:device:function: 0:29:0 offset start: offset end: 12h 13h size: 16 bit default: 0080h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 964 order number: 320066-003us 25.3 data transfers to/from main memory the universal host controller interface (uhci) specification, rev. 1.1 describes the details on how hcd and cmi communicate via the schedule data structures. 25.4 data structures in main memory the uhci specification details the data structures used to communicate control, status, and data between software and cmi. 25.5 data transfers to/from main memory the following sections describe the details on how hcd and cmi communicate via the schedule data structures. the discussion is organized in a top-down manner, beginning with the basics of walking the frame list, followed by a description of generic processing steps common to all transfer descriptors, and finally a discussion on transf er que ui ng. during data transfers to and from main memory, the uhci dma engine must provide an indication to the processor power management logic that it is busy. therefore, the memory accesses may actually be ?cache accesses?. the indication to the power management logic will be referred to as ?uhci bus master status?. the uhci controllers offer two different policies for the generation of the uhci bus master status: static and dynamic. the static policy requires that the uhci bus master status signal is asserted when the hchalted bit is 0. this policy prevents c3/c4 entry whenever the dma engine is enabled. the dynamic policy requires that the uhci bus master status signal deasserts after completely traversing the schedule for a particular frame unless the frame bit counter indicates that the next frame begins in less than ~100 usecs. specifically the uhci bus master status signal must deassert in any of the following: 1. after reading the frame list pointer and detecting that the terminate bit is set and the next frame is greater than ~100 usecs in the future. 2. after servicing a queue head in which the terminate bit is set in the queue head link pointer and the next frame is greater than ~100 usecs in the future. 3. the run bit is 0 and the hchalted bit is 1 4. after servicing a transfer descriptor which is not in the context of a queue and it's terminate bit is set and the next frame is greater than ~100 us in the future the uhci bus master status signal must assert in either of the following cases: 1. the run bit transitions from 0 to 1 2. the frame bit counter indicates that the next frame begins in less than ~100 s the value of 100 s is somewhat arbitrary. this is based on the assumption that a ?reasonable worst case? exit time is approximately 100 s. even if the exit latency is greater than this, it does not mean that there will be a usb functional failure. it only means that the usb traffic will begin later in the upcoming frame than it normally would have. in order to specify numbers for checking in validation, the ~100 s time must fall within the range 97 s to 110 s. the uhci bm_sts static policy enable configuration bit (d31.f0.a9h.5) selects between the dynamic and static policies.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 965 intel ? ep80579 integrated processor 25.5.1 executing the schedule software programs the starting address of the frame list and the frame list index, then causes cmi to execute the schedule by setting the run/stop bit in the control register to run. the cmi processes the schedule one entry at a time: the next element in the frame list is not fetched until the current element in the frame list is retired. schedule execution proceeds in the following fashion: ? the cmi first fetches an entry from the frame list. this entry has three fields. bit 0 indicates whether the address pointer field is valid. bit 1 indicates whether the address points to a transfer descriptor or to a queue head. the third field is the pointer itself. ? if the frame list entry indicates that it points to a transfer descriptor, the cmi fetches the entry and begins the operations necessary to initiate a transaction on usb. each td contains a link field that points to the next entry, as well as indicating whether it is a td or a qh. ? if the frame list entry contains a pointer to a qh, the cmi processes the information from the qh to determine the address of the next data object that it must process. ? the td/qh process continues until the millisecond allotted to the current frame expires. at this point, the cmi fetches the next entry from the frame list. if the cmi is not able to process all of the transfer descriptors during a given frame, those descriptors are retired by software without having been executed. 25.5.2 processing transfer descriptors the cmi executes a td using the following, generalized algorithm. these basic steps are common across all modes of tds. subsequent sections present processing steps unique to each td mode. 1. the cmi fetches td or qh from the current link pointer. 2. if a qh, go to 1 to fetch from the queue element link pointer. if inactive, go to 12 3. build token, actual bits are in td token. 4. if (host-to-function) then [ memory access ] issue request for data, (referenced through td.bufferpointer) wait for first chunk data arrival end if 5. [ begin usb transaction ] issue token (from token built in 2, above) and begin data transfer. if (host-to-function) then go to 6 else go to 7 end if 6. fetch data from memory (via td buffer pointer) and transfer over usb until td maximum-length bytes have been read and transferred. [ concurrent system memory and usb accesses ]. go to 8. 7. wait for data to arrive (from usb). write incoming bytes into memory beginning at td bufferpointer. internal hc buffer must signal end of data packet. number of bytes received must be td maximum-length; the length of the memory area referenced by td bufferpointer must be td maximum-length. [ concurrent system memory and usb accesses ]. 8. issue handshake based on status of data received (ack or time-out). go to 10. 9. wait for handshake, if required [ end of usb transaction ]. 10. update status [ memory access ] (td.status and td.actuallength). if the td completed successfully, mark the td inactive. go to 11.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 966 order number: 320066-003us if not successful, and the error count has not been reached, leave the td active. if the error count has been reached, mark the td inactive. go to 12. 11. write the link pointer from the current td into the element pointer field of the qh structure. if the vf bit is set in the link pointer, go to 2. 12. proceed to next entry. 25.5.3 command register, status register, and td status bit interaction note: if a nak or stall response is received from a setup transaction, a time out error will be reported. this will cause the error counter to decrement and the crc/time-out error status bit to be set within the td control and status dword during write back. if the error counter changes from 1 to 0, the active bit will be reset to 0 and stalled bit to 1 as normal. 25.5.4 transfer queuing transfer queues are used to implement a guaranteed data delivery stream to a usb endpoint. transfer queues are composed of two parts: a queue header (qh) and a linked list. the linked list of tds and qhs has an indeterminate length (0 to n). the qh contains two link pointers and is or ganized as two contiguous dwords. the first dword is a horizontal pointer (queue head link pointer), used to link a single transfer queue with either another transfer queue, or a td (target data structure depends on q bit). if the t bit is set, this qh represents the last data structure in the current frame. the t bit informs the cmi that no further processing is required until the beginning of the next frame. the second dword is a vertical pointer (queue element link pointer) to the first data structure (td or qh) being managed by this qh. if the t bit is set, the queue is empty. this pointer may reference a td or another qh. condition usb status register actions td status register actions crc/time out error set usb error int bit 1 , clear hc halted bit clear active bit 1 and set stall bit 1 illegal pid, pid error, maximum length (illegal) clear run/stop bit in command register set hc process error and hc halted bits master/target abort on memory accesses clear run/stop bit in command register set host system error and hc halted bits suspend mode clear run/stop bit in command register 2 set hc halted bit resume received suspend mode = 1 set resume received bit run/stop = 0 clear run/stop bit in command register set hc halted bit configuration flag set set configuration flag in command register hc reset/global reset clear run/stop and configuration flag in command register clear usb int, usb error int, resume received, host system error, hc process error, and hc halted bits ioc = 1 in td status set usb int bit stall set usb error int bit clear active bit 1 and set stall bit bit stuff/data buffer error set usb error int bit 1 clear active bit 1 and set stall bit 1 short packet detect set usb int bit clear active bit notes: 1. only if error counter counted down from 1 to 0. 2. suspend mode can be entered only when run/stop bit is 0.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 967 intel ? ep80579 integrated processor figure 25-1 illustrates four example queue conditions. the first qh (on far left) is an example of an ?empty? queue; the termination bit (t bit), in the vertical link pointer field, is set to 1. the horizontal link pointer references another qh. the next queue is the expected typical configuration. the horizontal link pointer references another qh, and the vertical link pointer references a valid td. typically, the vertical pointer in a qh points to a td. however, as shown in figure 25-1 (third example from left side of figure) the vertical pointer could point to another qh. when this occurs, a new q context is entered and the q context just exited is null (the cmi will not update the vertical pointer field). the far right qh is an example of a frame ?termination? node. since its horizontal link pointer has its termination bit set, the cmi assumes there is no more work to complete for the current frame. transfer queues are based on the following characteristics: ? a qh?s vertical link pointer (queue element link pointer) references the ?top? queue member. a qh?s horizontal link pointer (queue head link pointer) references the ?next? work element in the frame. ? each queue member?s link pointer references the next element within the queue. in the simplest model, the cmi follows vertical link point to a queue element, then executes the element. if the completion status of the td satisfies the advance criteria as shown in ta bl e 2 5 - 2 9 , the cmi advances the queue by writing the just-executed td?s link pointer back into the qh?s queue element link pointer. the next time the queue head is traversed, the next queue element will be the top element. the traversal has two options: breadth first, or depth first. a flag bit in each td (vf - vertical traversal flag) controls whether traversal is breadth or depth first. the default mode of traversal is breadth-first. for breadth-first, the cmi only executes the top element from each queue. the execution path is: figure 25-1. example queue conditions frame list pointer qt 0 1 2 31 link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t indicates 'null' queue head link pointer qt td qh link pointer qt td link pointer qt td indicates 'nil' next pointer indicates 'nil' next pointer qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t link pointer qt td link pointer qt td link pointer (horz z )=queue head link pointer field in qh dword 0 link pointer (vert)=queue element link pointer field in qh dword 1
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 968 order number: 320066-003us qh (queue element link pointer) td write-back to qh (queue element link pointer) qh (queue head link pointer). breadth-first is also performed for every transaction execution that fails the advance criteria. this means that if a queued td fails, the queue does not advance, and the cmi traverses the qh?s queue head link pointer. in a depth-first traversal, the top queue element must complete successfully to satisfy the advance criteria for the queue. if the cmi is currently processing a queue, and the advance criteria are met, and the vf bit is set, the cmi follows the td?s link pointer to the next schedule work item. regardless of traversal model, when the advance criteria are met, the successful td?s link pointer is written back to the qh?s queue element link pointer. when the cmi encounters a qh, it caches the qh internally, and sets internal state to indicate it is in a q-context. it needs this state to update the correct qh (for auto advancement) and also to make the correct decisions on how to traverse the frame list. restricting the advancement of queues to advancement criteria implements a guaranteed data delivery stream. a queue is never advanced on an error completion status (even in the event the error count was exhausted). ta b l e 2 5 - 2 9 lists the general queue advance criteria, which are based on the execution status of the td at the ?top? of a currently ?active? queue. ta b l e 2 5 - 3 0 is a decision table illustrating the valid combinations of link pointer bits and the valid actions taken when advancement criteria for a queued transfer descriptor are met. the column headings for the link pointer fields are encoded, based on the following list: table 25-29. queue advance criteria function-to-host (in) host-to-function (out) non-null null error/nak non-null null error/nak advance q advance q retry q element advance q advance q retry q element legend: qh.lp = queue head link pointer (or horizontal link pointer)qe.q = q bit in qe qe.lp = queue element link pointer (or vertical link pointer)qe.t = t bit in qe td.lp = td link pointertd. vf = vf bit in td qh.q = q bit in qh td.q = q bit in td qh.t = t bit in qh td. vf = vf bit in td
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 969 intel ? ep80579 integrated processor 25.6 usb buffer management the usb controller contains a 64 byte fifo, which operate in a ping/pong fashion. this buffer is not aligned to any memory boundary. upon each new transfer descriptor (td), the buffer resets its pointer to the top. when transmitting to a usb port, if the length field from the td is greater than 32 bytes, meaning the internal fifo boundary will be crossed, the host controller will read both ping and pong together. when ping has been transferred to usb, and the total td length has not been fetched, the usb host controller will fetch another 32 bytes. when receiving from a usb port, it is not known how many bytes will be received. therefore, the cmi will flush each buffer to memory as it becomes full. table 25-30. usb schedule list traversal decision table q context qh.q qh.t qe.q qe.t td.vf td.q td.t description 0----x00 not in queue ? execute td. use td.lp to get next td 0----xx1 not in queue ? execute td. end of frame 0----x10 not in queue - execute td. use td.lp to get next (qh+qe). set q context to 1. 1 00000xx in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use qh.lp to get next td. 1 xx00100 in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use td.lp to get next td. 1 xx00110 in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use td.lp to get next (qh+qe). 1 00x1xxx in queue. empty queue. use qh.lp to get next td 1 x x 1 0 - - - in queue. use qe.lp to get (qh+qe) 1 x1000xx in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. end of frame 1 x1x1xxx in queue. empty queue. end of frame 1 10000xx in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use qh.lp to get next (qh+qe). 1 10x1xxx in queue. empty queue. use qh.lp to get next (qh+qe)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 970 order number: 320066-003us 25.7 data encoding and bit stuffing the cmi usb employs nrzi data encoding (non-return to zero inverted) when transmitting packets. full details on this implementation are given in the usb specification, rev. 2.0 . the usb employs nrzi data encoding when transmitting packets. in nrzi encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. a string of zeros causes the nrzi data to toggle each bit time. a string of ones causes long periods with no transitions in the data. in order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device when sending a packet on the usb. a 0 is inserted after every six consecutive 1s in the data stream before the data is nrzi encoded to force a transition in the nrzi data stream. this gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock. a waveform of the data encoding is shown in figure 25-2 . bit stuffing is enabled beginning with the sync pattern and throughout the entire transmission. the data ?one? that ends the sync pattern is counted as the first one in a sequence. bit stuffing is always enforced, without exception. if required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of- packet (eop) signal. 25.8 bus protocol 25.8.1 bit ordering bits are sent out onto the bus least significant bit (lsb) first, followed by next lsb, the most significant bit (msb) last. 25.8.2 sync field all packets begin with a synchronization (sync) field, which is a coded sequence that generates a maximum edge transition density. the sync field appears on the bus as idle followed by the binary string ?kjkjkjkk,? in its nrzi encoding. it is used by the input circuitry to align incoming data with the local clock and is defined to be eight bits in length. sync serves only as a synchronization mechanism and is not shown in the following packet diagrams in section 25.8.3 . the last two bits in the sync field are a marker that is used to identify the first bit of the pid. all subsequent bits in the packet must be indexed from this point. 25.8.3 packet field formats all packets have distinct start and end of packet delimiters. full details are given in the usb specification . figure 25-2. usb data encoding clock data bit stuffed data nrzi data
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 971 intel ? ep80579 integrated processor 25.8.3.1 packet identifier field a packet identifier (pid) immediately follows the sync field of every usb packet. a pid consists of a four bit packet type field fo llowed by a four-bit check field . the pid indicates the type of packet and, by inference, the format of the packet and the type of error detection applied to the packet. the four-bit check field of the pid insures reliable decoding of the pid so that the remainder of the packet is interpreted correctly. the pid check field is generated by performing a ones complement of the packet type field. any pid received with a failed check field or which decodes to a non-defined value is assumed to be corrupted and it, as well as the remainder of the packet, is ignored by the receiver. pids are divided into four coding groups: token, data, handshake, and special, with the first two transmitted pid bits (pid<1:0>) indicating which group. this accounts for the distribution of pid codes. 25.8.4 address fields function endpoints are addressed using two fields: the function address field and the endpoint field. full details on this are given in the usb specification . 25.8.4.1 address field the function address (addr) field specifies the function, via its address, that is either the source or destination of a data packet, depending on the value of the token pid. a total of 128 addresses are specified as addr[6:0]. the addr field is specified for in, setup, and out tokens. 25.8.4.2 endpoint field an additional four-bit endpoint (endp) field, permits more flexible addressing of functions in which more than one sub-channel is required. endpoint numbers are function specific. the endpoint field is defined for in, setup, and out token pids only. 25.8.5 frame number field the frame number field is an 11-bit field that increments by the host on a per frame basis. the frame number field rolls over upon reaching its maximum value of x7ff, and is sent only for sof tokens at the start of each frame. 25.8.6 data field the data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. table 25-31 lists the format for multiple bytes. data bits within each byte are shifted out lsb first. table 25-31. data field bit data sent x - 1 byte n - 1, d7 x byte n, d0 x + 1 byte n, d1 x + 2 byte n, d2 x + 3 byte n, d3 x + 4 byte n, d4
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 972 order number: 320066-003us 25.8.7 cyclic redundancy check (crc) crc is used to protect the all non-pid fields in token and data packets. in this context, these fields are considered to be protected fields. full details on this are given in the usb specification . 25.9 packet formats the usb protocol calls out several packet types: token, data, and handshake packets. full details on this are given in the usb specification . 25.10 usb interrupts 25.10.1 overview there are two general groups of usb interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from a cmi operation error. all transaction-based sources can be masked by software through the interrupt enable register. additionally, individual transfer descriptors can be marked to generate an interrupt on completion. when the cmi drives an interrupt for usb, it internally drives the pirqa# pin for usb function #0(see chapter 26.0, ?usb 2.0 host controller: bus 0, device 29, function 7? ) until all sources of the interrupt are cleared. in order to accommodate some operating systems, the interrupt pin register must contain a different value for each function of this multi-function device. 25.10.2 transaction-based interrupts these interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. this guarantees that software can safely process through (frame list current index -1) when it is servicing an interrupt. 25.10.2.1 crc error/time-out a crc/time-out error occurs when a packet transmitted from the cmi to a usb device or a packet transmitted from a usb device to the cmi generates a crc error. the cmi is informed of this event by a time out from the usb device or by the cmi?s crc checker generating an error on reception of the packet. additionally, a usb bus time- out occurs when usb devices do not respond to a transaction phase within 19 bit times of an eop. either of these conditions will cause the c_err field of the td to be decremented. when the c_err field decrements to zero, the following occurs: ? the active bit in the td is cleared ? the stalled bit in the td is set ? the crc/time-out bit in the td is set. x + 5 byte n, d5 x + 6 byte n, d6 x + 7 byte n, d7 x + 8 byte n+1, d 0 table 25-31. data field
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 973 intel ? ep80579 integrated processor ? at the end of the frame, the usb error interrupt bit is set in the hc status register. if the crc/time out interrupt is enabled in the interrupt enable register, a hardware interrupt will be signaled to the system. 25.10.2.2 interrupt on completion transfer descriptors contain a bit that can be set to cause an interrupt on their completion. the completion of the transaction associated with that block causes the usb interrupt bit in the hc status register to be set at the end of the frame in which the transfer completed. when a td is encountered with the ioc bit set to 1, the ioc bit in the hc status register is set to 1 at the end of the frame if the active bit in the td is set to 0 (even if it was set to 0 when initially read). if the ioc enable bit of interrupt enable register (bit 2 of i/o offset 04h) is set, a hardware interrupt is signaled to the system. this status bit is set whether the td completes successfully, or because of errors. if the completion is because of errors, the usb error bit in the hc status register is also set. 25.10.2.3 short packet detect a transfer set is a collection of data which requires more than 1 usb transaction to completely move the data across the usb. an example might be a large print file which requires numerous tds in multiple frames to completely transfer the data. reception of a data packet that is less than the endpoint?s maximum packet size during control, bulk or interrupt transfers signals the completion of the transfer set, even if there are active tds remaining for this transfer set. setting the spd bit in a td indicates to the hc to set the usb interrupt bit in the hc status register at the end of the frame in which this event occurs. this feature streamlines the processing of input on these transfer types. if the short packet interrupt enable bit in the interrupt enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. 25.10.2.4 serial bus babble when a device transmits on the usb for a time greater than its assigned maximum length, it is said to be babbling. this error results in the active bit in the td being cleared to 0 and the stalled and babble bits being set to one. the c_err field is not decremented for a babble. the usb error interrupt bit in the hc status register is set to 1 at the end of the frame. a hardware interrupt is signaled to the system. if an eof babble was caused by the cmi (due to incorrect schedule for instance), the cmi will force a bit stuff error followed by an eop and the start of the next frame. 25.10.2.5 stalled this event indicates that a device/endpoint returned a stall handshake during a transaction or that the transaction ended in an error condition. the tds stalled bit is set and the active bit is cleared. reception of a stall does not decrement the error counter. a hardware interrupt is signaled to the system. 25.10.2.6 data buffer error this event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. this would generally be caused by the cmi not being able to access required data buffers in memory within necessary latency requirements. either of these conditions will cause the c_err field of the td to be decremented.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 974 order number: 320066-003us when c_err decrements to zero, the active bit in the td is cleared, the stalled bit is set, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. 25.10.2.7 bit stuff error a bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. this will cause the c_err field of the td to be decremented. when the c_err field decrements to 0, the active bit in the td is cleared to 0, the stalled bit is set to 1, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. 25.10.3 non-transaction based interrupts if a cmi process error or system error occur, the cmi halts and immediately issues a hardware interrupt to the system. 25.10.3.1 resume received this event indicates that the cmi received a resume signal from a device on the usb bus during a global suspend. if this interrupt is enabled in the interrupt enable register, a hardware interrupt will be signaled to the system allowing the usb to be brought out of the suspend state and returned to normal operation. 25.10.3.2 process error the hc monitors certain critical fields during operation to ensure that it does not process corrupted data structures. these include checking for a valid pid and verifying that the maxlength field is less than 1280. if it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the hc process error bit in the hc status register and signals a hardware interrupt to the system. this interrupt cannot be disabled through the interrupt enable register. 25.10.3.3 host system error the cmi sets this bit to 1 when a parity erro r, master abort, or target abort occurs on memory accesses. when this error occurs, the cmi clears the run/stop bit in the command register to prevent further execution of the scheduled tds. this interrupt cannot be disabled through the interrupt enable register. 25.10.3.4 implementation notes 1. if a bad pid is found, but the packet wi ll not be run because there is not enough time left in the frame due to the size of the transfer or the packet time out, an error will not be flagged. 2. ?if a bad pid is found, but the packet will not be run because the td?s active bit is off, the host controller will not halt, and an error will not be flagged.? 25.11 usb power management the host controller can be put into a suspended state and its power can be removed. this requires that certain bits of information are retained in the resume power plane of the cmi so that a device on a port may wake the system. such a device may be a fax- modem, which will wake up the machine to receive a fax or take a voice message.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 975 intel ? ep80579 integrated processor the following bits in i/o space are to be maintained when the cmi enters a low power state: when the cmi detects a resume event on any of its ports, it sets the corresponding usb_sts bit in acpi space. if usb is enabled as a wake/break event, the system will wake up and an sci will be generated. 25.12 usb legacy keyboard operation when a usb keyboard is plugged into the sy stem, and a standard keyboard is not, the system may not boot, and dos legacy software will not run, because the keyboard will not be identified. the cmi implements a series of trapping operations which will snoop accesses that go to the keyboard controller, and put the expected data from the usb keyboard into the keyboard controller. the following table summarizes the implementation of the bits in the usb legacy keyboard/mouse control registers. table 25-32. bits maintained in low power states register offset bit description command 00h 3 enter global suspend mode (egsm) status 02h 2 resume detect port status and control 10h and 12h 2 port enabled/disabled 6resume detect 8 low-speed device attached 12 suspend table 25-33. usb legacy keyboard/mouse control register bit implementation (sheet 1 of 2) bit # bit name summary details 15 smi caused by end of pass- through logically 1 bit for all controllers this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a 1 to this bit in any of the classic usb host controllers. this bit may either be implemented separately for each controller or shared and aliased. 13 pci interrupt enable independent enable each bit provides individual host control 12 smi caused by usb interrupt independent status individual status bits for each controller 11 smi caused by port 64 write logically 1 bit for all controllers this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a 1 to this bit in any of the classic usb host controllers. this bit may either be implemented separately for each controller or shared and aliased. 10 smi caused by port 64 read logically 1 bit for all controllers this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a 1 to this bit in any of the classic usb host controllers. this bit may either be implemented separately for each controller or shared and aliased. 9 smi caused by port 60 write logically 1 bit for all controllers this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a 1 to this bit in any of the classic usb host controllers. this bit may either be implemented separately for each controller or shared and aliased.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 976 order number: 320066-003us note: the scheme described below assumes that the keyboard controller (8042 or equivalent) is on the lpc bus. this legacy operation is performed through smm space. the latched smi source (60r, 60w, 64r, 64w) is available in the status register. because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an smi. it is the software's responsibility to logically and the value with the appropriate enable bits. note: smi is generated before the lpc cycle completes on the imch/iich interface to ensure that the processor doesn't complete the cycle before the smi is observed. the logic will also need to block the accesses to the 8042. if there is an external 8042, then this is accomplished by not activating the 8042 cs. this is done by logically anding the four enables (60r, 60w, 64r, 64w) with the 4 types of accesses to determine if 8042 cs should go active. an additional term is required for the ?pass-through? case. 8 smi caused by port 60 read logically 1 bit for all controllers this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a 1 to this bit in any of the classic usb host controllers. this bit may either be implemented separately for each controller or shared and aliased. 7 smi at end of pass-through enable separate enables ored together this bit enables the generation of the smi based on bit 15 within the same function. if bit 15 is implemented as a shared/ aliased bit across all functions, then the bit 7s from all classic usb controllers are ored together and used to enable the smi based on bit 15. 6 pass through state logically 1 bit for all controllers this bit in all host controllers reflects the state of the pass- through state machine. software can force this bit to 0 by clearing the a20gate pass-through enable (bit 5) in all of the host controllers. 5 a20gate pass-through enable ored together to enable the pass-thru state machine if any of these bits in the classic usb host controllers is set, then the iich will enable the legacy keyboard a20gate pass- through sequence. this prevents the smi status bits (11:8) from asserting in all controllers when the specific sequence of i/o cycles is observed. 4 smi on usb irq independent enable each bit provides individual host control 3 smi on port 64 writes enable separate enables ored together each bit enables smi generation if the corresponding bit 11 is set. if bit 11 is implemented as a shared/aliased bit across all functions, then the bit 3s from all classic usb controllers are ored together and used to enable the smi based on bit 11. 2 smi on port 64 reads enable separate enables ored together each bit enables smi generation if the corresponding bit 10 is set. if bit 10 is implemented as a shared/aliased bit across all functions, then the bit 2s from all classic usb controllers are ored together and used to enable the smi based on bit 10. 1 smi on port 60 writes enable separate enables ored together each bit enables smi generation if the corresponding bit 9 is set. if bit 9 is implemented as a shared/aliased bit across all functions, then the bit 1s from all classic usb controllers are ored together and used to enable the smi based on bit 9. 0 smi on port 60 reads enable separate enables ored together each bit enables smi generation if the corresponding bit 8 is set. if bit 8 is implemented as a shared/aliased bit across all functions, then the bit 0s from all classic usb controllers are ored together and used to enable the smi based on bit 8. table 25-33. usb legacy keyboard/mouse control register bit implementation (sheet 2 of 2) bit # bit name summary details
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 977 intel ? ep80579 integrated processor 26.0 usb 2.0 host controlle r: bus 0, device 29, function 7 26.1 overview this section focuses on cmi-specific implementation details of the universal serial bus (usb) specification, revision 2.0 and enhanced host controller interface (ehci) specification for universal serial bus specifications. register address locations not shown in section 26.2 must be treated as reserved. note: all configuration registers in this section are in the core well and reset by a core well reset and the d3-to-d0 warm reset, except as noted. cmi contains an enhanced host controller interface (ehci) compliant host controller which supports up to two usb rev. 2.0 specification -compliant root ports. usb 2.0 allows data transfers up to 480 mbits/s using the same pins as the two usb1 ports. cmi contains port-routing logic that determines whether a usb port is controlled by one of the uhci controllers or by the ehci controller. a usb 2.0-based debug port is also implemented in cmi. a summary of the key architectural differences between the usb 1.1 uhci host controllers and the usb 2.0 ehci host controller is shown in the table below: table 26-1. usb 1.1 and usb 2.0 comparison usb 1.1 uhci usb 2.0 ehci accessible by i/o space memory space memory data structure single linked list sepa rated in to periodic and asynchronous lists differential signaling voltage 3.3 v 400 mv controllers 1 1 ports per controller 2 2
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 978 order number: 320066-003us 26.2 usb 2.0 pci configuration registers the default values are defined with an h for hex, a b for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved registers locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 26-2. bus 0, device 29, function 7: summary of usb (2.0) controller pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid - vendor id register? on page 979 8086h 02h 03h ?offset 02h: did - device identification register? on page 979 5035h 04h 05h ?offset 04h: cmd - command register? on page 980 0000h 06h 07h ?offset 06h: dsr - device status register? on page 981 0290h 08h 08h ?offset 08h: rid - revision id register? on page 983 variable 09h 09h ?offset 09h: pi - programming interface register? on page 983 20h 0ah 0ah ?offset 0ah: scc - sub class code register? on page 983 03h 0bh 0bh ?offset 0bh: bcc - base class code register? on page 984 0ch 0dh 0dh ?offset 0dh: mlt - master latency timer register? on page 984 00h 10h 13h ?offset 10h: mbar - memory base address register? on page 985 00000000h 2ch 2dh ?offset 2ch: ssvid - usb 2.0 subsystem vendor id register? on page 985 xxxxh 2eh 2fh ?offset 2eh: ssid - usb 2.0 subsystem id register? on page 986 xxxxh 34h 34h ?offset 34h: cap_ptr - capabilities pointer register? on page 986 50h 3ch 3ch ?offset 3ch: iline - interrupt line register? on page 987 00h 3dh 3dh ?offset 3dh: ipin - interrupt pin register? on page 987 variable 50h 50h ?offset 50h: pm_cid - pci power management capability id register? on page 987 01h 51h 51h ?offset 51h: pm_next - next item pointer #1 register? on page 988 58h 52h 53h ?offset 52h: pm_cap - power management capabilities register? on page 989 c9c2h 54h 55h ?offset 54h: pm_cs - power management control/status register? on page 990 0000h 58h 58h ?offset 58h: dp_cid - debug port capability id register? on page 991 0ah 59h 59h ?offset 59h: dp_next - next item pointer #2 register? on page 991 00h 5ah 5bh ?offset 5ah: dp_base - debug port base offset register? on page 991 20a0h 60h 60h ?offset 60h: sbrn - serial bus release number register? on page 992 20h 61h 61h ?offset 61h: fla - frame length adjustment register? on page 992 20h 62h 63h ?offset 62h: pwc - port wake capability register? on page 993 01ffh 64h 65h ?offset 64h: cuo - classic usb override register? on page 994 0000h 68h 6bh ?offset 68h: ulsec - usb 2.0 legacy support extended capability register? on page 994 00000001h 6ch 6fh ?offset 6ch: ulscs - usb 2.0 legacy support control/status register? on page 995 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 979 intel ? ep80579 integrated processor 26.2.1 register details 26.2.1.1 offset 00h: vid - vendor id register 26.2.1.2 offset 02h: did - device identification register 70h 73h ?offset 70h: isu2smi - intel specific usb 2.0 smi register? on page 997 00000000h 80h 80h ?offset 80h: ac - access control register? on page 999 00h f8h fbh ?offset f8h: manid - manufacturer id register? on page 1000 00010f90h table 26-2. bus 0, device 29, function 7: summary of usb (2.0) controller pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 26-3. offset 00h: vid - vendor id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 vid vendor id: this is a 16-bit value assigned to intel. 8086h ro table 26-4. offset 02h: did - device identification register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 02h 03h size: 16 bit default: 5035h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 did device id: this is a 16-bit value assigned to the usb2 host controller. 5035h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 980 order number: 320066-003us 26.2.1.3 offset 04h: cmd - command register table 26-5. offset 04h: cmd - command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :11 reserved reserved 00h ro 10 int_dis interrupt disable: 0 = the function is capable of generating interrupts. 1 = the function can not generate its interrupt to the interrupt controller. the corresponding interrupt status bit is not affected by the interrupt enable. this bit defaults to '0'. this bit is added as part of the conventional pci 2.3 specification . 0h rw 09 fbe fast back to back enable: reserved as '0'. 0h ro 08 serr_n_en serr# enable: 0 = the ehc is disabled from generating (internally) serr# 1 = the ehc is capable of generating (internally) serr# in the following cases: ? reception of status other than ?successful? on a memory read completion (if serr on aborts enable is also set) ? detection of an address or command parity error and the parity error response bit is set ? detection of a data parity error (when the data is going to the ehc) and the parity error response bit is set ? since usb 2.0 logic does not support parity checking, bit 6 is never set. 0h rw 07 wcc wait cycle control: reserved as '0'. 0h 06 per parity error response: reserved as ?0?. 0h 05 vps vga palette snoop: reserved as '0'. 0h 04 pmwe postable memory write enable: reserved as '0'. 0h 03 sce special cycle enable: reserved as '0'. 0h 02 bme bus master enable: 0 = clearing the bme bit shuts down the ehc dma engines in the same manner that clearing the run/ stop does. however, the schedule status bits and the hchalted bit do not change based on the bme value 1 = acts as a master on the pci bus for usb transfers. notes: notes on the ehc implementation: ? writes to change this bit occur immediately. specifically, a write followed by a read will return the updated value. ? when the bme bit is changed from 1 to 0, the ehc will cease accessing main memory within 2 microframes (250 s). during this time, any number of reads and/ or writes to memory may occur. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 981 intel ? ep80579 integrated processor 26.2.1.4 offset 06h: dsr - device status register note: for the writable bits, software must write a one to clear bits that are set. writing a zero to the bit has no effect. 01 mse memory space enable: this bit controls access to the usb 2.0 memory space registers. 0 = accesses to the usb 2.0 registers are disabled 1 = accesses to the usb 2.0 registers are enabled. the base address register for usb 2.0 must be programmed before this bit is set. 0h rw 00 iose i/o space enable: reserved as '0'. 0h table 26-5. offset 04h: cmd - command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 26-6. offset 06h: dsr - device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 06h 07h size: 16 bit default: 0290h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: 0 = no serr# detected . 1 = set when a parity error is detected on the internal interface to the usb host controller, regardless of the setting of bit 6 or bit 8 in the command register or any other conditions. software clears this bit by writing a ?1? to this bit location. 0h rwc 14 sse signaled system error: 0 = no serr# detected . 1 = this bit is set whenever it signals serr# (internally). the serr_en bit (bit 8 in the command register) must be 1 for this bit to be set. the following conditions can cause the generation of serr#: ? a parity error is seen on address, command, or data (if the data was targeting the ehc) on the internal interface to the usbe host controller due to a parity error on the system interface and bit 6 of the command register is set to 1. ? an ehc-initiated memory read results in a completion packet with a status other than successful on the system interface (if serr on aborts enable is also set to 1). software clears this bit by writing a ?1? to this bit location. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 982 order number: 320066-003us 13 rma received master-abort status: 0 = no master abort received by ehc on a memory access. 1 = this bit is set when usb 2.0, as a master, receives a master-abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit and the serr on aborts enable (bit 3, offset 84h). software clears this bit by writing a ?1? to this bit location. 0h rwc 12 rta received target abort status: 0 = no target abort received by ehc on memory access. 1 = this bit is set when usb 2.0, as a master, receives a target abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit and the serr on aborts enable (bit 3, offset 84h). software clears this bit by writing a ?1? to this bit location. 0h rwc 11 sta signaled target-abort status: this bit is used to indicate when the usb 2.0 function responds to a cycle with a target abort. this should never occur, so this bit is hard-wired to ?0?. 0h ro 10 :09 devt devsel# timing status: this 2-bit field defines the timing for devsel# assertion. 01h ro 08 dpd master data parity error detected: 0 = no data parity error detected on usb 2.0 read completion packet. 1 = this bit is set whenever a data parity error is detected on a usbe read completion packet on the internal interface to the usbe host controller and bit 6 of the command register is set to 1. software clears this bit by writing a ?1? to this bit location. 0h rwc 07 fb2bc fast back-to-back capable: reserved as ?1?. 1 06 reserved user definable features: reserved as ?0?. 0h 05 c66 66 mhz capable: reserved as ?0?. 0h 04 clist capabilities list: hardwired to ?1? indicating that offset 34h contains a valid capabilities pointer. 1ro 03 is interrupt status: this read-only bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interrupt is deasserted. 1 = this bit is a 1 when the interrupt is asserted. the value reported in this bit is independent of the value in the interrupt enable bit. this bit is added as part of the pci 2.3 specification . 0h ro 02 :00 reserved reserved. 000h table 26-6. offset 06h: dsr - device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 06h 07h size: 16 bit default: 0290h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 983 intel ? ep80579 integrated processor 26.2.1.5 offset 08h: rid - revision id register 26.2.1.6 offset 09h: pi - programming interface register 26.2.1.7 offset 0ah: scc - sub class code register table 26-7. offset 08h: rid - revision id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 rid the value reported in this register depends on the value written to the revision id in device 31, function 0. this register follows the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 26-8. offset 09h: pi - programming interface register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 09h 09h size: 8 bit default: 20h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 pic program interface conforms: a value of 20h indicates that this usb 2.0 host controller conforms to the ehci specification . 20h ro table 26-9. offset 0ah: scc - sub class code register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 0ah 0ah size: 8 bit default: 03h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 scc a value of 03h indicates that this is a universal serial bus host controller. 03h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 984 order number: 320066-003us 26.2.1.8 offset 0bh: bcc - base class code register 26.2.1.9 offset 0dh: mlt - master latency timer register table 26-10. offset 0bh: bcc - base class code register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 0bh 0bh size: 8 bit default: 0ch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 bcc a value of 0ch indicates that this is a serial bus controller. 0ch ro table 26-11. offset 0dh: mlt - master latency timer register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 mlt because the usb 2.0 controller is internally implemented with arbitration on an internal interface, it does not need a master latency timer. the bits will be fixed at 0. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 985 intel ? ep80579 integrated processor 26.2.1.10 offset 10h: mbar - memory base address register 26.2.1.11 offset 2ch: ssvid - usb 2.0 subsystem vendor id register table 26-12. offset 10h: mbar - memory base address register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :10 ba base address: bits [31:10] correspond to memory address signals [31:10], respectively. this gives 1 kbyte of relocatable memory space aligned to 1 kbyte boundaries. 0h rw 09 :04 reserved reserved 0h 03 pref prefetchable: this bit is hardwired to 0 indicating that this range must not be prefetched. 0h ro 02 :01 tpe type: this field is hardwired to 0 indicating that this range can be mapped anywhere within 32-bit address space. 00h ro 00 rte resource type indicator: this bit is hardwired to 0 indicating that the base address field in this register maps to memory space. 0h ro table 26-13. offset 2ch: ssvid - usb 2.0 subsystem vendor id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 2ch 2dh size: 16 bit default: xxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 ssvid this register, in combination with the usb 2.0 subsystem id register, enables the operating system to distinguish each subsystem from the others. writes to this register are enabled when the wrt_rdonly bit (offset 80h, bit 0) is set to 1. xxxxh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 986 order number: 320066-003us 26.2.1.12 offset 2eh: ssid - usb 2.0 subsystem id register 26.2.1.13 offset 34h: cap_ptr - capabilities pointer register table 26-14. offset 2eh: ssid - usb 2.0 subsystem id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 2eh 2fh size: 16 bit default: xxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 ssid bios sets the value in this register to identify the subsystem id. this register, in combination with the subsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). writes to this register are enabled when the wrt_rdonly bit (offset 80h, bit 0) is set to 1. writes must be done as a single 16-bit cycle. xxxxh rw table 26-15. offset 34h: cap_ptr - capabilities pointer register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 34h 34h size: 8 bit default: 50h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 cap_ptr this register points to the starting offset of the usb 2.0 capabilities ranges. 50h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 987 intel ? ep80579 integrated processor 26.2.1.14 offset 3ch: iline - interrupt line register 26.2.1.15 offset 3dh: ipin - interrupt pin register 26.2.1.16 offset 50h: pm_cid - pci powe r management capability id register table 26-16. offset 3ch: iline - interrupt line register description: lockable: d3-to-d0 view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 iline interrupt line: this data is not used. it is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to. 00h rw table 26-17. offset 3dh: ipin - interrupt pin register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end:3d 3dh 3dh size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 ipin interrupt pin: bits 03:00 reflect the value of d29ip.eip in configuration space. bits 07:04 are hardwired to 0000b. variable ro table 26-18. offset 50h: pm_cid - pci powe r management capability id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 50h 50h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 pm_cid a value of 01h indicates that this is a pci power management capabilities field. 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 988 order number: 320066-003us 26.2.1.17 offset 51h: pm_next - next item pointer #1 register table 26-19. offset 51h: pm_next - next item pointer #1 register description: lockable:not d3-to-do view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 51h 51h size: 8 bit default: 58h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 pm_next this register defaults to 58h, which indicates that the next capability registers begin at configuration offset 58h. this register is writable when the wrt_rdonly bit is set. this allows bios to effectively hide the debug port capability registers, if necessary. this register must only be written during system initialization before the plug-and-play software has enabled any master-initiated traffic. only values of 58h (debug port visible) and 00h (debug port invisible) are expected to be programmed in this register. 58h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 989 intel ? ep80579 integrated processor 26.2.1.18 offset 52h: pm_cap - power management capabilities register normally, this register is read-only to report capabilities to the power management software. in order to report different power management capabilities depending on the system in which cmi is used, bits 15:11 and 08:06 in this register are writable when the wrt_rdonly bit in table 26-32, ?offset 80h: ac - access control register? on page 999 is set. the value written to this register does not affect the hardware other than changing the value returned during a read. reset: core well, but not d3-to-d0. table 26-20. offset 52h: pm_cap - power management capabilities register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 52h 53h size: 16 bit default: c9c2h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :11 pme_support this 5-bit field indicates the power states in which the function may assert pme#. the cmi ehc does not support the d1 or d2 states. for all other states, the cmi ehc is capable of generating pme#. software must never need to modify this field. note: these bits are writable (rw) when d29:f7:80h, bit 0 is 1 11001b rwl 10 d2_support the d2 state is not supported. it is hardwired to ?0?. 0b ro 09 d1_support the d1 state is not supported.it is hardwired to ?0?. 0b ro 08 :06 aux_current ehc reports 375 ma maximum suspend well current required when in the d3 cold state. this value can be written by bios when a more accurate value is known. note: these bits are writable (rw) when d29:f7:80h, bit 0 is 1 111b rwl 05 dsi reports 0, indicating that no device-specific initialization is required. it is hardwired to ?0?. 0b ro 04 reserved reserved. 0b ro 03 pme_clock reports 0, indicating that no pci clock is required to generate pme#. it is hardwired to ?0?. 0b ro 02 :00 version reports 010, indicating that it complies with revision 1.1 of the pci power management specification . it is hardwired to ?010?. 010b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 990 order number: 320066-003us 26.2.1.19 offset 54h: pm_cs - power management control/status register table 26-21. offset 54h: pm_cs - power management control/status register description: reset (bits 15:08):suspend well, not d3-to-d0 nor core well reset. reset (bits 1:0):core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 54h 55h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status 0 = writing a 0 has no effect. 1 = set when ehc would normally assert the pme# signal independent of the state of the pme_en bit. note: writing a 1 to this bit will clear it and cause the internal pme to deassert (if enabled). this bit must be explicitly cleared by the operating system each time the operating system is loaded. 0h rwc 14 :13 data_scale hardwired to ?00? because it does not support the associated data register. 00h ro 12 :09 data_select hardwired to ?0000? because it does not support the associated data register. 0000h ro 08 pme_en a ?1? enables ehc to generate an internal pme signal when pme_status is ?1?. this bit must be explicitly cleared by the operating system each time it is initially loaded. 0h rw 07 :02 reserved reserved 0h 01 :00 powerstate this 2-bit field is used both to determine the current power state of ehc function and to set a new power state. the definition of the field values are: 00b ? d0 state 11b ? d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3hot state, accesses to the ehc memory range must not be accessible, but the configuration space must still be accessible. when not in the d0 state, the generation of the interrupt output is blocked. specifically, the pirq[a] is not asserted by cmi when not in the d0 state. when software changes this value from the d3 hot state to the d0 state, an internal warm (soft) reset is generated, and software must reinitialize the function. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 991 intel ? ep80579 integrated processor 26.2.1.20 offset 58h: dp_cid - debug port capability id register 26.2.1.21 offset 59h: dp_next - next item pointer #2 register 26.2.1.22 offset 5ah: dp_base - debug port base offset register this register is hardwired to 20a0h, which indicates that the debug port registers begin at offset a0h in the usb 2.0 function?s memory space. table 26-22. offset 58h: dp_cid - debug port capability id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 58h 58h size: 8 bit default: 0ah power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 dp_cid this register is hardwired to 0ah which indicates that this is the start of a debug port capability structure. 0ah ro table 26-23. offset 59h: dp_next - next item pointer #2 register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 59h 59h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 dp_next this register is hardwired to 00h, which indicates there are no more capability structures in this function. 0h ro table 26-24. offset 5ah: dp_base - debug port base offset register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 5ah 5bh size: 16 bit default: 20a0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :13 bnbr bar number: this field is hardwired to 001b to indicate the memory bar at offset 10h in the ehci configuration space. 001h ro 12 :00 dpo debug port offset: this field is hardwired to 0a0h to indicate that the debug port registers begin at offset a0h in the ehci memory range. 0a0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 992 order number: 320066-003us 26.2.1.23 offset 60h: sbrn - serial bus release number register 26.2.1.24 offset 61h: fla - frame length adjustment register this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written into these six bits, the length of the frame is adjusted. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register must only be modified when the hchalted bit in the usbsts register is a one. changing value of this register while the host controller is operating yields undefined results. it must not be reprogrammed by usb system software unless the default or bios programmed values are incorrect, or the system is restoring the register while returning from a suspended state. table 26-25. offset 60h: sbrn - serial bus release number register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 60h 60h size: 8 bit default: 20h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 sbrn a value of 20h indicates that this controller follows usb 2.0. 20h ro table 26-26. offset 61h: fla - frame length adjustment register description: reset: suspend well, not d3-to-d0 nor core well reset view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 61h 61h size: 8 bit default: 20h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 07 :06 reserved reserved. 00h 05 :00 fltv frame length timing value: each decimal value change to this register corresponds to 16 high-speed bit times. the sof cycle time (number of sof counter clock periods to generate a sof microframe length) is equal to 59488 + value in this field. the default value is decimal 32 (20h), which gives a sof cycle time of 60000. frame length (# high speed bit times)fladj value (decimal) (decimal) 59488 0 (00h) 59504 1 (01h) 59520 2 (02h) ? 59984 31 (1fh) 60000 32 (20h) ? 60480 62(3eh) 60496 63 (3fh) 100000b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 993 intel ? ep80579 integrated processor 26.2.1.25 offset 62h: pwc - port wake capability register this register is in the suspend power well. the intended use of this register is to establish a policy about which ports are to be used for wake events. bit positions 1-8 in the mask correspond to a physical port implemented on the current ehci controller. a one in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/connect or overcurrent events as wake-up events. this is an information-only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system- specific policy can be established by bios initializing this register to a system-specific value. system software uses the information in this register when enabling devices and ports for remote wake-up. note: there is no support for wake from usb when in s3/s4/s5. 26.2.1.26 offset 64h: cuo - classic usb override register this 16-bit register provides a bit corresponding to each of the ports on the ehci host controller (the ehci specification supports up to 16 ports). when a bit is set to ?1?, the corresponding usb port is routed to the classic (uhci) host controller and will only operate using the classic signaling rates. the feature is implemented with the following requirements: ? the associated port owner bit does not reflect the value in this override register. this guarantees compatibility with ehci drivers. ? bios must only write to this register during initialization (while the configured flag is ?0?). ? the register is implemented in the suspend well to maintain port routing when the core power goes down. table 26-27. offset 62h: pwc - port wake capability register description: reset: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 62h 63h size: 16 bit default: 01ffh power well: suspend bit range bit acronym bit description sticky bit reset value bit access 15 :09 reserved reserved. 0000000b 08 03 reserved reserved 111111b rw 02 :01 pwu port wake up capability mask: bit positions 1 through 2 correspond to a physical port implemented on this host controller. for example, bit position 1 corresponds to port 1, position 2 port 2, etc. 11b rw 00 pwi port wake implemented: 0 = indicates that this register is not supported by software. 1 = indicates that this register is supported by software. 1b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 994 order number: 320066-003us ? when a ?1? is present in the override register, then the classic controller operates the port regardless of the ehci port routing logic. the corresponding ehci port will always appear disconnected in this mode. note: ehci test modes will not work on a port that has been overridden by this register. ? port 0 must never be programmed to the classic usb override mode. this is because the debug port is used on port 0 and the two modes conflict with each other. 26.2.1.27 offset 68h: ulsec - usb 2.0 legacy support extended capability register table 26-28. offset 64h: cuo - classic usb override register description: reset:suspend well, and not d3-to-d0, hcreset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 64h 65h size: 16 bit default: 0000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 15 :08 reserved reserved. these bits are reserved for future use; reads return 0. 00h 07 :02 reserved reserved 000000b rw 01 :1 cusbpo classic usb port owner: a ?1? in a bit position forces the corresponding usb port to the classic host controller. 00b rw 00 reserved reserved 0h table 26-29. offset 68h: ulsec - usb 2.0 lega cy support extended capability register (sheet 1 of 2) description: reset: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00000001h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 31 :25 reserved reserved. hardwired to 00h. 00h 24 hc_os host controller os owned semaphore: system software sets this bit to request ownership of the ehci controller. 0 = ownership of the ehci controller is not obtained. 1 = ownership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. 0h rw 23 :17 reserved reserved. 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 995 intel ? ep80579 integrated processor 26.2.1.28 offset 6ch: ulscs - usb 2.0 legacy support control/status register writing a ?1? to that bit location clears bits that are marked as read/write-clear (rwc). 16 hc_bios host controller bios owned semaphore: the bios sets this bit to establish ownership of the ehci controller. system bios will clear this bit in response to a request for ownership of the ehci controller by system software. 0h rw 15 :08 nehci next ehci capability pointer: a value of 00h indicates that there are no ehci extended capability structures in this device. 00h ro 07 :00 capid capability id: a value of 01h indicates that this ehci extended capability is the legacy support capability. 01h ro table 26-29. offset 68h: ulsec - usb 2.0 legacy support extended capability register (sheet 2 of 2) description: reset: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00000001h power well: suspend bit range bit acronym bit description sticky bit reset value bit access table 26-30. offset 6ch: ulscs - usb 2.0 legacy support control/status register (sheet 1 of 3) description: lockable: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 6ch 6fh size: 32bit default: 00000000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 31 smi_bar smi on bar: 0 = base address register (bar) not written. 1 = this bit is set to 1 when the base address register (bar) is written. 0h rwc 30 smi_pcmd smi on pci command: this bit is set to ?1? whenever the pci command register is written. 0 = pci command (pcicmd) register not written. 1 = this bit is set to 1 when the pci command (pcicmd) register is written. 0h rwc 29 smi_osc smi on os ownership change: 0 = no hc os owned semaphore bit change. 1 = this bit is set to 1 when the hc os owned semaphore bit in the leg_ext_cap register (d29:f7:68h, bit 24) transitions from 1 to 0 or 0 to 1. 0h rwc 28 :22 reserved reserved. hardwired to 0. 00h 21 smi_aa smi on async advance: shadow bit of the interrupt on async advance bit in the usb 2.0sts register. to clear this bit, system software must write a one to the interrupt on async advance bit in the usb 2.0sts register. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 996 order number: 320066-003us 20 smi_hse smi on host system error: shadow bit of host system error bit in the usb 2.0sts. to clear this bit, system software must write a one to the host system error bit in the usb 2.0sts register. 0h ro 19 smi_flr smi on frame list rollover: shadow bit of frame list rollover bit in the usb 2.0sts register. to clear this bit, system software must write a one to the frame list rollover bit in the usb 2.0sts register. 0h ro 18 smi_pcd smi on port change detect: shadow bit of port change detect bit in the usb 2.0sts register. to clear this bit, system software must write a one to the port change detect bit in the usb 2.0sts register. 0h ro 17 smi_usber smi on usb error: shadow bit of usb error interrupt (usberrint) bit in the usb 2.0sts register. to clear this bit, system software must write a one to the usb error interrupt bit in the usb 2.0sts register. 0h ro 16 smi_usbc smi on usb complete: shadow bit of usb interrupt (usbint) bit in the usb 2.0sts register. to clear this bit, system software must write a one to the usb interrupt bit in the usb 2.0sts register. 0h ro 15 smi_baren smi on bar enable: 0 = disable. 1 = enable. when this bit is 1 and smi on bar (d29:f7:6ch, bit 31) is 1, then the host controller will issue an smi. 0h rw 14 smi_pcien smi on pci command enable: 0 = disable. 1 = enable. when this bit is 1 and smi on pci command (d29:f7:6ch, bit 31) is 1, then the host controller will issue an smi. 0h rw 13 smi_osen smi on os ownership enable: 0 = disable. 1 = enable. when this bit is a 1 and the os ownership change bit (d29:f7:6ch, bit 29) is 1, the host controller will issue an smi. 0h rw 12 :06 reserved reserved. hardwired to 0. 00h 05 smi_aaen smi on async advance enable: 0 = disable. 1 = enable. when this bit is a 1, and the smi on async advance bit (d29:f7:6ch, bit 21) is a 1, the host controller will issue an smi immediately. 0h rw 04 smi_hsen smi on host system error enable: 0 = disable. 1 = enable. when this bit is a 1, and the smi on host system error (d29:f7:6ch, bit 20) is a 1, the host controller will issue an smi. 0h rw 03 smi_flren smi on frame list rollover enable: 0 = disable. 1 = enable. when this bit is a 1, and the smi on frame list rollover bit (d29:f7:6ch, bit 19) is a 1, the host controller will issue an smi. 0h rw table 26-30. offset 6ch: ulscs - usb 2.0 legacy support control/status register (sheet 2 of 3) description: lockable: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 6ch 6fh size: 32bit default: 00000000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 997 intel ? ep80579 integrated processor 26.2.1.29 offset 70h: isu2smi - intel specific usb 2.0 smi register this register provides a mechanism for bios to provide usb 2.0 related bug fixes and workarounds. writing a ?1? to that bit location clears bits that are marked as read/ write/clear (rw/c). software must clear all smi status bits prior to setting the global smi enable bit and individual smi enable bit to prevent spurious smi when returning from a power down. 02 smi_pcen smi on port change enable: 0 = disable. 1 = enable. when this bit is a 1, and the smi on port change detect bit (d29:f7:6ch, bit 18) is a 1, the host controller will issue an smi. 0h rw 01 smi_usben smi on usb error enable: 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb error bit (d29:f7:6ch, bit 17) is a 1, the host controller will issue an smi immediately. 0h rw 00 smi_usbce smi on usb complete enable: 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb complete bit (d29:f7:6ch, bit 16) is a 1, the host controller will issue an smi immediately. 0h rw table 26-30. offset 6ch: ulscs - usb 2.0 legacy support control/status register (sheet 3 of 3) description: lockable: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 6ch 6fh size: 32bit default: 00000000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access table 26-31. offset 70h: isu2smi - intel specific usb 2.0 smi register (sheet 1 of 3) description: lockable: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 70h 73h size: 32 bit default: 00000000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 31 :30 reserved reserved. hardwired to 0. 00b 29 :26 reserved reserved 0000b rw 25 :24 reserved reserved 00b rwc 23 :22 smi_po smi on portowner: bits 23:22 correspond to the port owner bits for ports 1 (22) through 02 (23). these bits are set to ?1? whenever the associated port owner bits transition from 0->1 or 1->0. software clears these bits by writing a one. 00b rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 998 order number: 320066-003us 21 smi_ pmcsr smi on pmcsr: 0 = power state bits not modified. 1 = software modified the power state bits in the power management control/status (pmcsr) register (d29:f7:54h). 0b rwc 20 smi_async smi on async: 0 = no async schedule enable bit change 1 = async schedule enable bit transitioned from 1 to 0 or 0 to 1. 0b rwc 19 smi_per smi on periodic: 0 = no periodic schedule enable bit change. 1 = periodic schedule enable bit transitions from 1 to 0 or 0 to 1. 0b rwc 18 smi_cf smi on cf: 0 = no configure flag (cf) change. 1 = configure flag (cf) transitions from 1 to 0 or 0 to 1. 0b rwc 17 smi_hch smi on hchalted: 0 = hchalted did not transition to 1 (as a result of the run/stop bit being cleared). 1 = hchalted transitions to 1 (as a result of the run/stop bit being cleared). 0b rwc 16 smi_hcr smi on hcreset: 0 = hcreset did not transition to 1. 1 = hcreset transitioned to 1. 0h rwc 15 :14 reserved reserved. 00b 13 :08 reserved reserved 000000b rw 07 :06 smi_poen smi on portowner enable: when any of these bits are ?1? and the corresponding smi on portowner bits are ?1?, then the host controller will issue an smi. unused ports must have their corresponding bits cleared. 00b rw 05 smi_pmscren smi on pmscr enable: 0 = disable. 1 = enable. when this bit is 1 and smi on pmscr is 1, then the host controller will issue an smi. 0b rw 04 smi_asyen smi on async enable: 0 = disable. 1 = enable. when this bit is 1 and smi on async is 1, then the host controller will issue an smi. 0b rw 03 smi_peren smi on periodic enable: 0 = disable. 1 = enable. when this bit is 1 and smi on periodic is 1, then the host controller will issue an smi. 0b rw table 26-31. offset 70h: isu2smi - intel spec ific usb 2.0 smi register (sheet 2 of 3) description: lockable: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 70h 73h size: 32 bit default: 00000000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 999 intel ? ep80579 integrated processor 26.2.1.30 offset 80h: ac - access control register 02 smi_cfen smi on cf enable: 0 = disable. 1 = enable. when this bit is 1 and smi on cf is 1, then the host controller will issue an smi. 0b rw 01 smi_hchen smi on hchalted enable: 0 = disable. 1 = enable. when this bit is a 1 and smi on hchalted is 1, then the host controller will issue an smi. 0b rw 00 smi_hcren smi on hcreset enable: 0 = disable. 1 = enable. when this bit is a 1 and smi on hcreset is 1, then host controller will issue an smi. 0b rw table 26-31. offset 70h: isu2smi - intel specific usb 2.0 smi register (sheet 3 of 3) description: lockable: suspend well, and not d3-to-d0 warm reset nor core well. view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 70h 73h size: 32 bit default: 00000000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access table 26-32. offset 80h: ac - access control register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: 80h 80h size: 8 bit default: 00h power well: bit range bit acronym bit description sticky bit reset value bit access 07 :01 reserved reserved 00h 00 wrt_rdonly write read only: 0 = disables a select group of normally read-only registers in the ehc function to be written by software. 1 = enables a select group of normally read-only registers in the ehc function to be written by software. registers that may only be written when this mode is entered are noted in the summary tables and detailed description as ?read/write-special?. the registers fall into two categories: a. system-configured parameters b. status bits 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1000 order number: 320066-003us 26.2.1.31 offset f8h: manid - manufacturer id register table 26-33. offset f8h: manid - manufacturer id register description: view: pci bar: configuration bus:device:function: 0:29:7 offset start: offset end: f8h fbh size: 32 bit default: 00010f90h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 reserved reserved 00h 23 :16 sid stepping id: this field increments for each stepping of the part. this field can be used by software to differentiate steppings when the revision id may not change. implementation note: a single stepping id can be implemented that is readable from all functions in the chip because all of them are incremented in lock-step note: 00h for a0 stepping note: 01h for b0 stepping see device 31, function 0, offset f8h for the reported value. 01h ro 15 :08 mid manufacturing id: indicates 0fh = intel 0fh ro 07 :00 reserved reserved 90h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1001 intel ? ep80579 integrated processor 26.3 usb 2.0 memory-mapped i/o registers the usb 2.0 ehci memory-mapped i/o space is composed of two sets of registers: capability registers and operational registers. the base address of the address space that these registers materialize in is set by the mbar bar in the pci configuration header (see section 26.2.1.10, ?offset 10h: mbar - memory base address register? on page 985 ). the ehci controller does not support as a target memory transactions that are locked transactions. attempting to access the ehci controller memory-mapped i/o space using locked memory transactions will result in undefined behavior. note: when the usb 2.0 function is in the d3 pci power state, accesses to the usb 2.0 memory range are ignored and will result in a master abort. similarly, if the memory space enable (mse) bit is not set in the command register in configuration space, the memory range will not be decoded by the enhanced host controller (ehc). if the mse bit is not set, then cmi must default to allowing any memory accesses for the range specified in the bar to go to lpc. this is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. table 26-34. bus 0, device 29, function 7: summary of usb (2.0) controller configuration registers mapped through mbar memory bar offset start offset end register id - description default value 00h 00h ?offset 00h: caplength - capability length register? on page 1002 20h 02h 03h ?offset 02h: hciversion - host controller interface version number register? on page 1003 0100h 04h 07h ?offset 04h: hcsparams - host controller structural parameters register? on page 1003 01001202h 08h 0bh ?offset 08h: hccparams - host controller capability parameters register? on page 1004 00006871h 20h 23h ?offset 20h: usb2cmd - usb 2.0 command register? on page 1007 00080000h 24h 27h ?offset 24h: usb2sts - usb 2.0 status register? on page 1009 00001000h 28h 2bh ?offset 28h: usb2intr - usb 2.0 interrupt enable register? on page 1012 00000000h 2ch 2fh ?offset 2ch: frindex - frame index register? on page 1013 00000000h 30h 33h ?offset 30h: ctrldssegment - control data structure segment register? on page 1014 00000000h 34h 37h ?offset 34h: periodiclistbase - periodic frame list base address register? on page 1014 00000xxxh 38h 3bh ?offset 38h: asynclistaddr - current asynchronous list address register? on page 1015 00000000h 60h 63h ?offset 60h: configflag - configure flag register? on page 1015 00000000h 64h 67h ?offset 64h: portsc - port n status and control register? on page 1016 00003000h 68h 6bh ?offset 64h: portsc - port n status and control register? on page 1016 00003000h a0h a3h ?offset a0h: cntl_sts - control/status register? on page 1037 00000000h a4h a4h ?offset a4h: usbpid - usb pids register? on page 1039 00000000h a8h afh ?offset a8h: databuf - data buffer bytes 7:0? on page 1039 00000000000 00000h b0h b0h ?offset b0h: config - configuration register? on page 1040 00007f01h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1002 order number: 320066-003us 26.3.1 host controller capability register details these registers specify the limits, restrictions and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. this register is implemented in the suspend well and is only reset by the standard suspend-well hardware reset, not by hcreset or the d3-to-d0 reset. 26.3.1.1 offset 00h: caplength - capability length register this register is used as an offset to add to the memory base register to find the beginning of the operational register space. this is fixed at 20h, indicating that the operation registers begin at offset 20h. table 26-35. offset 00h: caplength - capability length register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 00h 00h size: 8 bit default: 20h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 crlv capability register length value: this register is used as an offset to add to the memory base register (d29:f7:10h) to find the beginning of the operational register space. this field is hardwired to 20h indicating that the operation registers begin at offset 20h. 20h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1003 intel ? ep80579 integrated processor 26.3.1.2 offset 02h: hciversion - host controller interface version number register this is a 2-byte register containing a bcd encoding of the version number of interface to which this host controller interface conforms. 26.3.1.3 offset 04h: hcsparams - host controller structural parameters register this is a set of fields that are structural parameters: number of downstream ports, etc. some fields in this register are writable when the wrt_rdonly bit is set. fields that are described as ?hardwired? are never writable. this register is implemented in the suspend well to avoid having to reload the parameters following a system sleep state in which the core power is removed. table 26-36. offset 02h: hciversion - host controller interface version number register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 02h 03h size: 16 bit default: 0100h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 :00 hciversion host controller interface version number: this is a two-byte register containing a bcd encoding of the version number of interface to which this host controller interface conforms. 0100h ro table 26-37. offset 04h: hcsparams - host controller structural parameters register (sheet 1 of 2) description: reset: suspend well reset, but not d3-to-d0 reset or hcreset. view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 04h 07h size: 32 bit default: 01001202h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 31 :24 reserved reserved. 00h 23 :20 dp_n debug port number: hardwired to 1h, indicating that the debug port is on the lowest numbered port. 0001b ro 19 :17 reserved reserved. 000b 16 p_indicator port indicators: this bit indicates whether the ports support port indicator control. cmi usb 2.0 controller does not support port indicator leds, and this bit is hard wired to ?0?. 0h ro 15 :12 n_cc number of companion controllers: this field indicates the number of companion controllers associated with this usb 2.0 host controller. a zero in this field indicates there are no companion host controllers. port-ownership hand-off is not supported. only high-speed devices are supported on the host controller root ports. a value larger than zero in this field indicates there are companion usb 1.1 host controller(s). port-ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. 0001b rws
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1004 order number: 320066-003us 26.3.1.4 offset 08h: hccparams - host controller capability parameters register this register provides general mode information that affects the generation of the data structure in memory. 11 :08 n_pcc number of ports per companion controller: this field indicates the number of ports supported per companion host controller. it is used to indicate the port routing configuration to system software. hardwired to 2h. 0010b ro 07 :04 reserved reserved. 00h 03 :00 n_ports this field specifies the number of physical downstream ports implemented on this host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to 2h 2h is reported by default. however, software may write a value less than 2 for some platform configurations. a zero in this field is undefined. 0010b rws table 26-37. offset 04h: hcsparams - host co ntroller structural parameters register (sheet 2 of 2) description: reset: suspend well reset, but not d3-to-d0 reset or hcreset. view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 04h 07h size: 32 bit default: 01001202h power well: suspend bit range bit acronym bit description sticky bit reset value bit access table 26-38. offset 08h: hccparams - host controller capability parameters register (sheet 1 of 2) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 08h 0bh size: 32 bit default: 00006871h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved 0000h 15 :08 eecp ehci extended capabilities pointer: this field is hardwired to 68h, indicating that the ehci capabilities list exists and begins at offset 68h in the pci configuration space. 68h ro 07 :04 reserved reserved 7h ro 03 reserved reserved 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1005 intel ? ep80579 integrated processor 26.3.2 host controller operational register details this section defines the enhanced host controller operational registers. these registers are located after the capabilities registers. the operational register base must be dword aligned and is calculated by adding the value in the first capabilities register to the base address of the enhanced host controller register address space. in the following text, the offset is relative to the memory base register. all registers are 32 bits in length. software must read and write these registers using only dword accesses. these registers are divided into two sets. the first set at offsets 20h to 3fh are implemented in the core power well. unless otherwise noted, the core-well registers are reset by the assertion of any of the following: ? core well hardware reset ?hcreset ? d3-to-d0 reset 02 aspc asynchronous schedule park capability: this bit is hardwired to 0 indicating that the host controller does not support this optional feature. 0h ro 01 pflf programmable frame list flag: 0 = if this bit is set to a zero, then system software must use a frame list length of 1024 elements with this host controller. the usbcmd register frame list size field is a read-only register and must be set to zero. 1 = if set to a one, then system software can specify and use a smaller frame list and configure the host controller via the usbcmd register frame list size field. the frame list must always be aligned on a 4k page boundary. this requirement ensures that the frame list is always physically contiguous. different frame list lengths are not supported. this bit is read-only ?0?. 0h ro 00 add_cap 64-bit addressing capability: this field documents the addressing range capability of this implementation. the value of this field determines whether software must use the 32-bit or 64-bit data structures. values for this field have the following interpretation: 0 = data structures using 32-bit address memory pointers 1 = data structures using 64-bit address memory pointers only 64-bit addressing is supported. this bit is read-only ?1?. only 44 bits of addressing is supported. bits 63:44 will always be 0 on cycles generated to memory. 1h ro table 26-38. offset 08h: hccparams - host cont roller capability parameters register (sheet 2 of 2) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 08h 0bh size: 32 bit default: 00006871h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1006 order number: 320066-003us the second set at offsets 60h to the end of the implemented register space are implemented in the suspend power well. unless otherwise noted, the core-well registers are reset by the assertion of either of the following: ? suspend well hardware reset ? hcreset the default values are defined with an h for hex, a b for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved registers locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 26-39. host controller operational register details summary table mem_base + offset symbol register name/function default special notes access start end 20 23h usb 2.0cmd usb 2.0 command register 00080000h rw 24 27h usb 2.0sts usb 2.0 status register 00001000h rwc, ro 28 2bh usb 2.0intr usb 2.0 interrupt enable register 00000000h rw 2c 2fh frindex usb 2.0 frame index register 00000000h rw, ro 30 33h ctrldsseg ment control data structure segment register 00000000h rw 34 37h periodicli stbase period frame list base address register 00000000h rw 38 3bh asynclist addr next asynchronous list address register 00000000h rw, ro 60 63h config flag configure flag register 00000000h suspend rw, ro 64 67h portsc port 1 status and control register 00003000h suspend rw 68 6bh portsc port 2 status and control register 00003000h suspend rw a0 b3h debug port registers (see section 26.13.2, ?debug port register details? ) rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1007 intel ? ep80579 integrated processor 26.3.2.1 offset 20h: usb2cmd - usb 2.0 command register the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. table 26-40. offset 20h: usb2cmd - usb 2.0 command register (sheet 1 of 2) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 20h 23h size: 32 bit default: 00080000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 reserved reserved. 00h 23 :16 itc interrupt threshold control: default 08h. this field is used by system software to select the maximum rate at which the host controller will issue interrupts. the only valid values are defined below. if software writes an invalid value to this register, the results are undefined. value maximum interrupt interval 00h reserved 01h 1 microframe 02h 2 microframes 04h 4 microframes 08h 8 microframes (default, equates to 1 ms) 10h 16 microframes (2 ms) 20h 32 microframes (4 ms) 40h 64 microframes (8 ms) refer to section 4 in the ehci specification for interrupts affected by this field. 08h rw 15 :12 reserved reserved. 0h 11 :08 uapm unimplemented asynchronous park mode bits: this field is hardwired to 000b because the host controller does not support this optional feature. 0h ro 07 lhcr light host controller reset: this optional reset is not supported and is hardwired to 0. 0h ro 06 iaad interrupt on async advance doorbell: this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. software must write a 1 to this bit to ring the doorbell. when the host controller has evicted all appropriate cached schedule state, it sets the interrupt on async advance status bit in the usbsts register. if the interrupt on async advance enable bit in the usbintr register is a one then the host controller will assert an interrupt at the next interrupt threshold. see the ehci specification for operational details. the host controller sets this bit to a zero after it has set the interrupt on async advance status bit in the usbsts register to a one. software must not write a one to this bit when the asynchronous schedule is disabled. doing so will yield undefined results. 0h rw 05 asy_scen asynchronous schedule enable: default 0b. this bit controls whether the host controller skips processing the asynchronous schedule. values mean: 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1008 order number: 320066-003us 04 p_scen periodic schedule enable: default 0b. this bit controls whether the host controller skips processing the periodic schedule. values mean: 0 = do not process the periodic schedule 1 = use the periodiclistbase register to access the periodic schedule. 0h rw 03 :02 fls frame list size: hardwired to 00b because it only supports the 1024-element frame list size. 0h ro 01 hcreset host controller reset: this control bit used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset (i.e., rsmrst# assertion and pwrok deassertion). when software writes a one to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. pci configuration registers and host controller capability registers are not affected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effects described in the ehci specification . software must reinitialize th e host controller in order to return the host controller to an operational state. this bit is set to zero by the host controller when the reset process is complete. software cannot terminate the reset process early by writing a zero to this register. software must not set this bit to a one when the hchalted bit in the usbsts register is a zero. attempting to reset an actively running host controller will result in undefined behavior. 0h rw 00 rs run/stop: default 0b. 1=run. 0=stop. 1 = the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set to a 1. 0 = the host controller completes the current and any actively pipelined transactions on the usb and then halts. the host controller must halt within 16 microframes after software clears the run bit. the hc halted bit in the status register indicates when the host controller has finished its pending pipelined transactions and has entered the stopped state. software must not write a 1 to this field unless the host controller is in the halted state (i.e., hchalted in the usbsts register is a one). the following table explains how the different combinations of run and halted must be interpreted: run/stop halted interpretation 0 0 valid - in the process of halting 0 1 valid - halted 1 0 valid - running 1 1 invalid - the hchalted bit clears immediately memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being cleared (and also affect the host error bit). 0h rw table 26-40. offset 20h: usb2cmd - usb 2.0 command register (sheet 2 of 2) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 20h 23h size: 32 bit default: 00080000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1009 intel ? ep80579 integrated processor 26.3.2.2 offset 24h: usb2sts - usb 2.0 status register this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software sets a bit to 0 in this register by writing a 1 to it. see the interrupts description in section 4 of the ehci specification for additional information concerning usb 2.0 interrupt conditions. table 26-41. offset 24h: usb2sts - usb 2.0 status register (sheet 1 of 3) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 24h 27h size: 32 bit default: 00001000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved. 0h 15 asy_sstat asynchronous schedule status: this bit reports the current real status of the asynchronous schedule. 0 = the status of the asynchronous schedule is disabled. 1 = the status of the asynchronous schedule is enabled. the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit in the usbcmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 0h ro 14 per_sstat periodic schedule status: this bit reports the current real status of the periodic schedule. 0 = the status of the periodic schedule is disabled. 1 = the status of the periodic schedule is enabled. the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit in the usbcmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 0h ro 13 recl reclamation: this is a read-only status bit, which is used to detect an empty asynchronous schedule. the operational model and valid tr ansitions for this bit are described in section 4 of the ehci specification . 0h ro 12 hch hchalted: 0 = this bit is a zero whenever the run/stop bit is a one. 1 = the host controller sets this bit to 1 after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (e.g., internal error). 1h ro 11 :06 reserved reserved. 0h 05 int_asya interrupt on async advance: system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the interrupt on async advance doorbell bit in the usbcmd register. this status bit indicates the assertion of that interrupt source. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1010 order number: 320066-003us 04 hs_err host system error: 0 = no serious error occurred during a host system access involving the host controller module. 1 = the host controller sets this bit to 1 when a serious error occurs during a host system access involving the host controller module. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being set. when this error occurs, the host controller clears the run/ stop bit in the command register to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system (if enabled in the interrupt enable register). 0h rwc 03 flro frame list rollover: 0 = no frame list index rollover from its maximum value to 0. 1 = the host controller sets this bit to a one when the frame list index rolls over from its maximum value to zero. since only 1024-entry frame list size is supported, the frame list index rolls over every time frnum[13] toggles. 0h rwc 02 pcd port change detect: the host controller sets this bit to a one when any port for which the port owner bit is set to zero has a change bit transition from a zero to a one or a force port resume bit transition from a zero to a one as a result of a j-k transition detected on a suspended port. this bit will also be set as a result of the connect status change being set to a one after system software has relinquished ownership of a connected port by writing a zero to a port?s port owner bit. this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that, on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bits (including force port resume, overcurrent change, enable/disable change and connect status change). regardless of the implementation, whenever this bit is readable, i.e., in the d0 state, it must provide a valid view of the port status registers. 0h rwc table 26-41. offset 24h: usb2sts - usb 2.0 status register (sheet 2 of 3) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 24h 27h size: 32 bit default: 00001000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1011 intel ? ep80579 integrated processor 26.3.2.3 offset 28h: usb2intr - usb 2.0 interrupt enable register this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see section 4 of the ehci specification ). 01 usberrint usb error interrupt: 0 = no error condition. 1 = the host controller sets this bit to 1 when completion of a usb transaction result s in an error condition, e.g., error counter underflow. if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. see the ehci specification for a list of the usb errors that will result in this interrupt being asserted. 0h rwc 00 usbint usb interrupt: 0 = no completion of a usb transaction whose transfer descriptor had its ioc bit set. no short packet is detected. 1 = the host controller sets this bit to 1 on the completion of a usb transaction, which results in the retirement of a transfer descriptor that had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). 0h rwc table 26-41. offset 24h: usb2sts - usb 2.0 status register (sheet 3 of 3) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 24h 27h size: 32 bit default: 00001000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1012 order number: 320066-003us table 26-42. offset 28h: usb2intr - usb 2.0 interrupt enable register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 28h 2bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :06 reserved reserved. 0h 05 int_aaen interrupt on async advance enable: 0 = disable. 1 = when this bit is a one, and the interrupt on async advance bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the interrupt on async advance bit. 0h rw 04 hse_en host system error enable: 0 = disable. 1 = when this bit is a one, and the host system error status bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the host system error bit. 0h rw 03 flr_en frame list rollover enable: 0 = disable. 1 = when this bit is a one, and the frame list rollover bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. 0h rw 02 pci_en port change interrupt enable: 0 = disable. 1 = when this bit is a one, and the port change detect bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. 0h rw 01 usbei_en usb error interrupt enable: 0 = disable. 1 = when this bit is a one, and the usberrint bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usberrint bit. 0h rw 00 usbi_en usb interrupt enable: 0 = disable. 1 = when this bit is a one, and the usbint bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usbint bit. 0h rw note: for all enable register bits, 1= enabled, 0= disabled
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1013 intel ? ep80579 integrated processor 26.3.2.4 offset 2ch: frindex - frame index register this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each microframe). bits [12:3] are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the index is fixed at 10 since only 1024-entry frame lists are supported. this register must be written as a dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (usb 2.0sts register). a write to this register while the run/stop bit is set to a one (usb 2.0cmd register) produces undefined results. writes to this register also affect the sof value. see section 4 of the ehci specification for details. the sof frame number value for the bus sof token is derived or alternatively managed from this register. please refer to section 4 of the ehci specification for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be 125 s (1 microframe) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 microframes. (1 ms). an example implementation to achieve this behavior is to increment sofv each time the frindex[2:0] increments from a zero to a one. software must use the value of frindex to derive the current microframe number and to provide the get microframe number function required for client drivers. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software writes to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. in order to keep the update as simple as possible, software must never write a frindex value where the three least significant bits are 111b or 000b. 26.3.2.5 offset 30h: ctrldssegment - control data structure segment register this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. since the 64-bit addressing capability field is hardwired in hccparams to one, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concatenated with the link pointer from either the periodiclistbase, asynclistaddr, or any control data structure link field to construct a 64-bit address. this register allows the host software to locate all control data structures within the same 4 gbyte memory segment. table 26-43. offset 2ch: frindex - frame index register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 2ch 2fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :14 reserved reserved. 0h 13 :00 flci frame list current index/frame number: the value in this register increments at the end of each time frame (e.g., microframe).bits [12:3] are used for the frame list current index. this means that each location of the frame list is accessed eight times (frames or microframes) before moving to the next index. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1014 order number: 320066-003us note: cmihas 44-bit addressing internally for both control and data structures. address bits 63:44 [31:12] are hardwired to zero independent of the setting of this register. the lower 12 address bits 43:32 [11:0] are fully read/write capable for software compatibility and specification compliance. 26.3.2.6 offset 34h: periodiclistbase - periodic frame list base address register this 32-bit register contains the beginning address of the periodic frame list in the system memory. since the host controller operates in 64-bit mode (as indicated by the one in the 64-bit addressing capability field in the hccsparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. system software loads this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memory pointer is assumed to be 4 kbyte aligned. the contents of this register are combined with the frame index register (frindex) to enable the host controller to step through the periodic frame list in sequence. table 26-44. offset 30h: ctrldssegment - control data structure segment register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 30h 33h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :12 hc_up upper address[63:44]: this 20-bit field is hard wired to zero. 0h ro 11 :00 hc_lwr upper address[43:32]: this 12-bit field corresponds to address bits 43:32 when forming a control data structure address. 0h rw table 26-45. offset 34h: periodiclistbase - periodic frame list base address register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 34h 37h size: 32 bit default: 00000xxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :12 hc_low base address (low): these bits correspond to memory address signals [31:12], respectively. 0h rw 11 :00 reserved reserved. must be written as 0s. during runtime, the value of these bits are undefined. xxxh
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1015 intel ? ep80579 integrated processor 26.3.2.7 offset 38h: asynclistaddr - current asynchronous list address register this 32-bit register contains the address of the next asynchronous queue head to be executed. since the host controller operates in 64-bit mode (as indicated by a one in 64-bit addressing capability field in the hccparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. bits [4:0] of this register cannot be modified by system software and will always return zeros when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. 26.3.2.8 offset 60h: configflag - configure flag register this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. this 32-bit register contains the address of the next asynchronous queue head to be executed. since the host controller operates in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register (offset 08h). bits [4:0] of this register cannot be modified by system software and will always return 0?s when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. table 26-46. offset 38h: asynclistaddr - current asynchronous list address register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 38h 3bh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :05 lpl link pointer low: these bits correspond to memory address signals [31:5], respectively. this field may only reference a queue head (qh). 0h rw 04 :00 reserved reserved. 0h table 26-47. offset 60h: configflag - configure flag register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 60h 63h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :01 reserved reserved. reads from this field will always return 0. 0h 00 cf configure flag: host software sets this bit as the last action in its process of configuring the host controller. this bit controls the default port-routing control logic. bit values and side effects are listed below. see section 4 of the ehci specification for operation details. 0 = port routing control logic default-routes each port to the classic host controllers. 1 = port routing control logic default-routes all ports to this host controller. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1016 order number: 320066-003us 26.3.2.9 offset 64h: portsc - port n status and control register a host controller must implement one or more port registers. software uses the n_port information from the structural parameters register to determine how many ports need to be serviced. all ports have the structure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well . it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. the initial conditions of a port are: ?no device connected ? port disabled note: when a device is attached, the port state transitions to the connected state and system software will process this as with any status change notification. refer to section 4 of the ehci specification for operational requirements for how change events interact with port suspend mode. note: if a port is being used as the debug port, then the port may report device connected and enabled when the configured flag is a zero. note: there is no support for wake from usb when in s3/s4/s5. table 26-48. offset 64h: portsc - port n status and control register (sheet 1 of 5) description: port 1 64 - 67h, port 2 68 - 6bh view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 64h 67h view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00003000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access 31 :23 reserved reserved. 000h 22 wkoc _ e wake on overcurrent enable: 0 = disable. (default). 1 = writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. when enabled to do so, the ehc sets the pme status bit in the power management control/status register (offset 54, bit 15) when the overcurrent active bit (bit 4 of this register) is set. note: there is no support for wake from usb when in s3/s4/ s5. 0h rw 21 wkdscnnt _e wake on disconnect enable: 0 = disable. (default). 1 = writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. when enabled to do so, the ehc sets the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0). note: there is no support for wake from usb when in s3/s4/ s5. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1017 intel ? ep80579 integrated processor 20 wkcnnt_e wake on connect enable: 0 = disable. (default). 1 = writing this bit to a one enables the port to be sensitive to device connects as wake-up events. when enabled to do so, the ehc sets the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1). note: there is no support for wake from usb when in s3/s4/ s5. 0h rw 19 :16 pt_ctrl port test control: default = 0000b. when this field is zero, the port is not operating in a test mode. a non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. the encoding of the test mode bits are (0110b - 1111b are reserved): bits test mode 0000b test mode not enabled 0001b test j_state - during this test mode the hardware will force pre-emphasis disabled to the afe 0010b test k_state - during this test mode the hardware will force pre-emphasis disabled to the afe 0011b test se0_nak 0100b test packet 0101b test force_enable refer to usb rev. 2.0 specification , chapter 7 and the ehci specification , chapter 4 for details on each test mode. the ehc does not support the option to run the port tests while the run/stop bit is a one. 0000h rw 15 :14 reserved reserved. 00h 13 po port owner: default = 1b. this bit unconditionally goes to a 0b when the configure flag makes a 0b to 1b transition. this bit unconditionally goes to 1b whenever the configure flag bit is zero. system software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). software writes a one to this bit when the attached device is not a high-speed device. a one in this bit means that a companion host controller owns and controls the port. see section 4 of the ehci specification for operational details. 1h rw 12 pp port power: hard-wired with a value of one. this indicates that the port does have power. 1h ro table 26-48. offset 64h: portsc - port n status and control register (sheet 2 of 5) description: port 1 64 - 67h, port 2 68 - 6bh view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 64h 67h view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00003000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1018 order number: 320066-003us 11 :10 ls line status: these bits reflect the current logical levels of the d+ (bit 11) and d- (bit 10) signal lines. these bits are used for detection of low-speed usb devices prior to the port reset and enable sequence. this field is valid only when the port enable bit is zero and the current connect status bit is set to a one. the encoding of the bits is as follows: 0h ro 09 reserved reserved. 0h 08 pr port reset: 0 = port is not in reset (default). 1 = port is in reset. when software writes a one to this bit (from a zero), the bus reset sequence as defined in the usb rev. 2.0 specification is started. software writes a zero to this bit to terminate the bus reset sequence. software must keep this bit at a one long enough to guarantee the reset sequence, as specified in the usb rev. 2.0 specification , completes. note: when software writes this bit to a one, it must also write a zero to the port enable bit. note: when software writes a zero to this bit, there may be a delay before the bit status changes to a zero. the bit status will not read as a zero until after the reset has completed. if the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g., set the port enable bit to a one). a host controller must terminate the reset and stabilize the state of the port within 2 ms of software transitioning this bit from a one to a zero. for example, if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to a zero. the hchalted bit in the usb2sts register must be a zero before software attempts to use this bit. the host controller may hold port reset asserted to a one when the hchalted bit is a one. the run/stop bit in the command register must be set in order for the port reset bit to be cleared. 0h rw table 26-48. offset 64h: portsc - port n status and control register (sheet 3 of 5) description: port 1 64 - 67h, port 2 68 - 6bh view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 64h 67h view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00003000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access bits[11:10] usb state interpretation 00b se0 not low-speed device, perform ehci reset 10b j-state not low-speed device, perform ehci reset 01b k-state low-speed device, release ownership of port 11b undefined not low-speed device, perform ehci reset
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1019 intel ? ep80579 integrated processor 07 ps suspend: 0 = port not in suspend state (default). 1 = port in suspend state. port enabled bit and suspend bit of this register define the port states as follows: bits [port enabled, suspend]port state 0x disable 10 enable 11 suspend when in suspend state, downstream propagation of data is blocked on this port, except for port reset. the blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to a 1. in the suspend state, the port is sensitive to resume detection. the bit status does not change until the port is suspended and there may be a delay in suspending a port if there is a transaction currently in progress on the usb. a write of zero to this bit is ignored by the host controller. the host controller will unconditionally set this bit to a zero when: ? software sets the force port resume bit to a zero (from a one). ? software sets the port reset bit to a one (from a zero). if host software sets this bit to a one when the port is not enabled (i.e., port enabled bit is a zero) the results are undefined. 0h rw 06 fpr force port resume: 0 = no resume (k-state) detected/driven on port (default). 1 = resume detected/driven on port. this functionality defined for manipulating this bit depends on the value of the suspend bit. for example, if the port is not suspended ( suspend and enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. when this bit transitions to a one because a j-to-k transition is detected, the port change detect bit in the usbsts register is also set to a one. if software sets this bit to a one, the host controller must not set the port change detect bit. when the ehci controller owns the port, the resume sequence follows the defined sequence documented in the usb rev. 2.0 specification . the resume signaling (full-speed 'k') is driven on the port as long as this bit remains a one. software must appropriately time the resume and set this bit to a zero when the appropriate amount of time has elapsed. writing a zero (from one) causes the port to return to high- speed mode (forcing the bus below the port into a high-speed idle). this bit will remain a one until the port has switched to the high-speed idle. the host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. 0h rw 05 occ overcurrent change: 0 = no change (default). 1 = this bit gets set to a one when there is a change to the overcurrent active bit. software clears this bit by writing a one to this bit position. the functionality of this bit is not dependent upon the port owner. 0h rwc table 26-48. offset 64h: portsc - port n status and control register (sheet 4 of 5) description: port 1 64 - 67h, port 2 68 - 6bh view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 64h 67h view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00003000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1020 order number: 320066-003us 04 oca overcurrent active: 0 = this port does not have an overcurrent condition (deafult). 1 = this port currently has an overcurrent condition. this bit will automatically transition from a one to a zero when the overcurrent condition is removed. the functionality of this bit is not dependent upon the port owner. cmi automatically disables the port when the overcurrent active bit is ?1?. 0h ro 03 pedc port enable/disable change: 0 = no change (default). 1 = port enabled/disabled status has changed. for the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the eof2 point (see chapter 11 of the usb specification for the definition of a port error). this bit is not set due to the disabled-to-enabled transition, nor due to a disconnect. software clears this bit by writing a 1 to it. 0h rwc 02 pendis port enabled/disabled: 0 = disable (default). 1 = enable. as described in the ehci specification , ports are enabled by the host controller as a part of the reset and enable. software cannot enable a port by writing a one to this field. the host controller will only set this bit to a one when the reset sequence determines that the attached device is a high- speed device. 0h rw 01 csc connect status change: 0 = no change (default). 1 = change in current connect status. indicates a change has occurred in the port?s current connect status. the host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ?setting? an already-set bit (i.e., the bit will remain set). software sets this bit to 0 by writing a 1 to it. 0h rwc 00 ccs current connect status: 0 = no device is present (default). 1 = device is present on port. this value reflects the current state of the port and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0h ro table 26-48. offset 64h: portsc - port n status and control register (sheet 5 of 5) description: port 1 64 - 67h, port 2 68 - 6bh view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 64h 67h view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: 68h 6bh size: 32 bit default: 00003000h power well: suspend bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1021 intel ? ep80579 integrated processor 26.4 ehc initialization the following describes the expected ehc initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 26.4.1 power on the suspend well is a ?deeper? power plane than the core well, which means that the suspend well is always functional when the core well is functional but the core well may not be functional when the suspend well is. therefore, the suspend well reset pin (rsmrst#) deasserts before the core well reset pin (pwrok) rises. 1. the suspend well reset deasserts, leaving all registers and logic in the suspend well in the default state. however, it is not possible to read any registers until after the core well reset deasserts. 2. the core well reset deasserts, leaving all registers and logic in the core well in the default state. the ehc configuration space is accessible at this point. the core well reset can (and typically does) occur without the suspend well reset asserting. this means that all of the configure flag and port status and control bits (and any other suspend-well logic) may be in any valid state at this time. 26.4.2 driver initialization see chapter 4 of the ehci specification, rev. 1.0 . 26.4.3 ehc resets in addition to the standard hardware rese ts, portions of the ehc are reset by the hcreset bit and the transition from the d3hot device power management state to the d0 state. the effect of each of these resets are: table 26-49. hcreset bit summary if the detailed register descriptions give exceptions to these rules, those exceptions override these rules. this summary is provided to help explain the reasons for the reset policies. reset does reset does not reset comments hcreset bit set memory space registers except structural parameters (which is written by bios) configuration registers the hcreset must only affect registers that the ehci driver controls. pci configuration space and bios-programmed parameters must not be reset. software writes the device power state from d3hot (11b) to d0 (00b) core-well registers (except bios- programmed registers) suspend-well registers; bios- programmed core-well registers the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios- programmed registers because bios may not be invoked following the d3-to- d0 transition.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1022 order number: 320066-003us 26.5 data structures in main memory see section 3 and appendix b of the ehci specification, rev. 1.0 for details. 26.6 usb 2.0 enhanced host controller dma the usb 2.0 enhanced host controller implements three sources of usb packets. they are, in order of priority on usb during each microframe, 1. the usb 2.0 debug port (see section 26.13 ), 2. the periodic dma engine, and 3. the asynchronous dma engine. cmi always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. if there is time left in the microframe, then the ehc performs any pending asynchronous traffic at the end of the microframe (eof1). the debug port traffic is only presented on one port (port #0), while the other ports are idle during this time. the following subsections describe the policies of the periodic and asynchronous dma engines. 26.6.1 periodic list execution the periodic dma engine contains buffering for two control structures (two transactions). by implementing two entries, the ehc is able to pipeline the memory accesses for the next transaction while executing the current transaction on the usb ports. a multiple-packet, high-bandwidth transaction occupies one of these buffer entries, which means that up to six 1 kbyte data packets may be associated with the two buffered control structures. in order to simplify the pipelined implementation that is optimized for normal execution, the ehc does not implement immediate retries on high bandwidth interrupt transactions that encounter transaction errors (for ins and outs) or a data toggle mismatch (for interrupt in). this is an optional implementation, but not recommended, by the usb specification and the usb specification, revision 0.95. the ehc will reattempt the transaction when that qtd is encountered again in the periodic schedule. if successful when reattempted, then the ehc will continue with the multiple packets allowed by the high-bandwidth endpoint during that same microframe. 26.6.1.1 read policies for periodic dma the periodic dma engine performs memory reads for the following structures: table 26-50. periodic dma engine memory reads memory structure size (dwords) comments periodic frame list entry 1 the ehc reads the entry for each microframe. the frame list is not internally cached across microframes. frame span trave r sa l no de 2 itd 23 only the 64-bit addressing format is supported. sitd 9 only the 64-bit addressing format is supported.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1023 intel ? ep80579 integrated processor periodic dma read policies: 1. the ehc periodic dma engine (pde) does not generate accesses to main memory unless all three of the following conditions are met: a. the hchalted bit is 0 (memory space, offset 24h, bit 12). software clears this bit indirectly by setting the run/stop bit to 1. b. the periodic schedule status bit is 1 (memory space, offset 24h, bit 14). software sets this bit indirectly by setting the periodic schedule enable bit to 1. c. the bus master enable bit is 1 (configuration space, offset 04h, bit 2). 2. once the above conditions are met, the pde waits until the frame index counter rolls over from the end of microframe 6 to the beginning of microframe 7 to begin prefetching for microframe 0 of the next frame. this means the initial memory access may be delayed up to 1 ms after the dma-enabled conditions are met. further delays within the arbitration and datapath are also possible before the first read request is presented on the imch/iich link. 3. the periodic frame list entry is always read from memory before any data structures associated with the new microframe are accessed. 4. prefetching is limited to the current and next microframes only. if prefetching is disabled, the periodic dma engine will perform transactions serially (no pipelining) and will read structures for the current microframe only. 5. the pde fetches structures in the periodic list until all information (including data) is available to run one usb transaction before beginning to fetch the structures for a pipelined transaction. for high-bandwidth out transactions, all of the data may not fit into the data fifo; in those cases, the next pipelined control structure fetches will be delayed until some data is delivered to usb. 6. the pde does not refetch the control structure between ?multi? packets of a high bandwidth endpoint. 7. the pde will not generate any control structure reads (including the frame list index) if both of the transaction buffers are occupied. data reads are the only read requests that will be generated by the pde in this case. 8. the pde will not pipeline fetch a control structure (itd, sitd, or qh) if the other transaction slot contains that control structure already. this is to avoid executing based on stale fields in the control structure since a status write (or overlay) is expected to occur following execution of the pending transaction. the pde will traverse the schedule (periodic frame list entry and any inactive control structures for the microframe) before encountering the link pointer to the stale structure. at that point the fetching pauses until the pending transaction is completed . the itd could be refetched since a separate status is maintained for each microframe; the pde will not attempt this optimization . 9. once the pde checks the length of a periodic packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the ehc switches over to run asynchronous traffic. the ehc does not attempt to look for any shorter packets in the remainder of the periodic schedule that might be able to fit in the current microframe. qtd 13 only the 64-bit addressing format is supported. queue head 17 only the 64-bit addressing format is supported. out data up to 257 large read requests are broken down into smaller aligned read requests based on the setting of the read request maximum length field. table 26-50. periodic dma engine memory reads
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1024 order number: 320066-003us 10. the pde implements a ?gross late-start? check which determines whether any more control or data structure reads will be initiated for transactions associated with the current microframe. the threshold for this check is determined by the gross late start cut-off field in configuration register offset 84h. 11. an entry in the 2-deep command fifo becomes available for a new transaction fetch when any of the following events occur: a. the final transaction results are posted in write buffers to memory. b. either of the late-start checks fail for this transaction (or the preceding transaction in the same microframe). c. a high-bandwidth interrupt transaction times out. for high-bandwidth interrupt transactions that time out, the cmi does not immediately retry the transaction as recommended by the usb specification (section 5.9.1). instead, all control and data structures are flushed and the transaction is reattempted the next time that endpoint is scheduled. note: when a host error occurs, the commands are kept in the pde. the ehci software driver must assert the hcreset in order to clear the pending transactions before reenabling the pde. 12. data fetches are not initiated unless there is room in the out data fifo to consume the amount of data requested. 13. read requests are broken up and throttled based on the read request maximum length field and the request rate throttle fields in the configuration register at offset fch. control or data structures that cross a maximum length-aligned boundary in memory are broken into multiple requests. this allows other packets from within the iich to be interleaved on the imch/iich link and through the memory controller to avoid temporary starvation of those functions. when generating the multiple read requests, the ehc will naturally-align the requests (i.e., 64-byte requests will not fetch across 64-byte address boundaries in memory). this guarantees that, as cache-line sizes increase, the back-to-back requests do not cause double-snoops on specific cache lines. unlike control structure read requests, only reads for da ta will be subject to the request rate throttle. 14. asynchronous dma memory accesses may be interleaved at any point with the periodic dma memory accesses on the imch/iich link. 26.6.1.2 write policies for periodic dma the periodic dma engine performs writes to the following data structures: periodic dma write policies: 1. the periodic dma engine (pde) will only generate writes after a transaction is executed on usb. some important notes associated with this rule are: a. if either of the late-start checks fails before the transaction is run on the usb ports, then none of the writes normally associated with that transaction will occur. high-bandwidth exception: if the late-start check fails after the first packet of a high-bandwidth (multi) transaction is executed but before the last packet, then the pde must write the status for any completed transfers to memory. b. the queue head overlay write occurs after the first transaction for a qtd is completed on the usb interface. 2. status writes are always performed after in data writes for the same transaction. 3. when writing the status back to the two sitds associated with a backpointer, the pde first writes to the sitd which was referenced by the backpointer and secondly writes to the sitd which contains the backpointer.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1025 intel ? ep80579 integrated processor 4. asynchronous dma memory accesses may be interleaved at any point with the periodic dma memory accesses on the imch/iich link. 5. when writing back the qtd information after clearing the active bit, the ehci specification does not require that the c_page field is written. however, due to byte-granular write control, the ehc does write to this field, and the value is not necessarily the final or incremented c_page value. 26.6.2 asynchronous list execution the asynchronous dma engine contains buffering for two control structures (two transactions). by implementing two entries, the ehc is able to pipeline the memory accesses for the next transaction while executing the current transaction on the usb ports. 26.6.2.1 read policies for asynchronous dma the asynchronous dma engine performs reads for the following structures: asynchronous dma read policies: 1. the ehc asynchronous dma engine (ade) does not generate accesses to main memory unless all four of the following conditions are met. (the ade may be active when the periodic schedule is actively executed, unlike the description in the ehci specification ; since the ehc contains independent dma engines, the ade may perform memory accesses interleaved with the pde accesses.) a. the hchalted bit is 0 (memory space, offset 24h, bit 12). software clears this bit indirectly by setting the run/stop bit to 1. b. the asynchronous schedule status bit is 1 (memory space, offset 24h, bit 14). software sets this bit indirectly by setting the asynchronous schedule enable bit to 1. c. the bus master enable bit is 1 (configuration space, offset 04h, bit 2). d. the ade is not sleeping due to the detection of an empty schedule. there is not one single bit that indicates this state. however, the sleeping state is entered when the queue head with the h bit set is encountered when the reclamation bit in the usb 2.0 status register is 0. 2. once the above conditions are met, the ade immediately begins reading the queue head to which the current asynchronous list address register points. delays within the arbitration and datapath are po ssible before the first read request is presented on the imch/iich link. 3. if prefetching is disabled, the ade will perform transactions serially (no pipelining). 4. the ade fetches structures in the asynchronous list until all information (including data) is available to run one usb transaction before beginning to fetch the structures for a pipelined transaction. 5. the ade will not generate any control structure reads if both of the transaction buffers are occupied. data reads are the only read requests that will be generated by the ade in this case. table 26-51. asynchronous dma engine reads memory structure size (dwords) comments qtd 13 only the 64-bit addressing format is supported. queue head 17 only the 64-bit addressing format is supported. out data up to 129 large read requests are broken down in to smaller aligned read requests based on the setting of the read request maximum length field.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1026 order number: 320066-003us 6. the ade does not fetch data when a qh is encountered in the ping state. an ack handshake in response to the ping results in the ade writing the qh to the out state, which results in the fetching and delivery of the out data on the next iteration through the asynchronous list. 7. the ade will not pipeline fetch a queue head if the other transaction slot contains that queue head already (i.e., only one active qh). this is to avoid executing based on stale fields in the queue head since a status write (or overlay) is expected to occur following execution of the pending transaction. the ade will traverse the schedule (any inactive queue heads) before encountering the link pointer to the stale structure. at that point the fetching pauses until the pending transaction is completed. 8. once the ade checks the length of an asynchronous packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the ehc stops all activity on the usb ports for the remainder of that microframe. the ehc does not attempt to look for any shorter packets in the remainder of the asynchronous schedule that might be able to fit in the current microframe. unlike the pde, the ade keeps the transaction internally for executing in the next microframe without refetching from memory. 9. an entry in the 2-deep command fifo becomes available for a new transaction fetch when any of the following events occur: a. the final transaction results are posted in write buffers to memory. b. a host error causes an unexpected halt. any unexecuted transactions in the command fifo are flushed. 10. once the ade detects an ?empty? asynchronous schedule as described in the ehci specification , it implements a waking mechanism like the one in the example. the amount of time that the ade ?sleeps? is 10 s +/-30 ns. 11. data fetches are not initiated unless there is room in the out data fifo for the amount of data requested. 12. read requests are broken up and throttled based on the read request maximum length field and the request rate throttle fields in the configuration register at offset fch. control or data structures that cross a maximum length-aligned boundary in memory are broken into multiple requests. this allows other packets from within the iich to be interleaved on the imch/iich link and through the memory controller to avoid temporary starvation of those functions. when generating the multiple read requests, the ehc will naturally-align the requests (i.e., 64-byte requests will not fetch across 64-byte address boundaries in memory). this guarantees that, as cache-line sizes increase, the back-to-back requests do not cause double-snoops on specific cache lines. unlike control structure read requests, only reads for da ta will be subject to the request rate throttle. 13. periodic dma memory accesses may be interleaved at any point with the asynchronous dma memory accesses on imch/iich link.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1027 intel ? ep80579 integrated processor 26.6.2.2 write policies for asynchronous dma the asynchronous dma engine performs writes to the following memory structures: asynchronous dma write policies: 1. the asynchronous dma engine (ade) will only generate writes after a transaction is executed on usb. some important notes associated with this rule are: a. if the late-start check fails before the transaction is run on the usb ports, then the usb transaction and the writes are delayed until the next opportunity to run the asynchronous traffic. b. the queue head overlay write occurs after the first transaction for a qtd is completed on the usb interface. 2. status writes are always performed after in data writes for the same transaction. 3. periodic dma memory accesses may be interleaved at any point with the asynchronous dma memory accesses on imch/iich link. 4. when writing back the qtd information after clearing the active bit, the ehci specification does not require that the c_page field is written. however, due to byte-granular write control, the ehc does write to this field, and the value is not necessarily the final or incremented c_page value. 26.7 data encoding and bit stuffing see the usb rev. 2.0 specification. 26.8 packet formats see the usb rev. 2.0 specification. 26.9 usb 2.0 interrupts and error conditions the ehci specification goes into detail on the ehc interrupts and the error conditions that cause them. all error conditions that the ehc detects can be reported through the ehci interrupt status bits. only cmi-specific interrupt and error-reporting behavior is documented in this section. the ehci interrupts section (in the ehci specification ) must be read first, followed by this section, to fully comprehend the ehc interrupt and error-reporting functionality. ? based on the ehc?s buffer sizes and buffer management policies, the data buffer error can never occur. ? master abort and target abort responses from the system interface on ehc- initiated read packets will be treated as fatal host errors. the ehc halts when these conditions are encountered. table 26-52. asynchronous dma engine writes memory structure size (dwords) comments asynchronous queue head overlay 14 only the 64-bit addressing format is supported. dwords 0ch through 43h are written. asynchronous queue head status write 3 dwords 14h through 1fh are written. asynchronous qtd status write 3 dwords 04h through 0fh are written. pid code, ioc, buffer pointer (page 0), and alt. next qtd pointer are rewritten with the original value. in data up to 129 data writes are broken down into 16 dword-aligned chunks.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1028 order number: 320066-003us ? cmi may assert the interrupts that are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. the requirement in the ehci specification (that the status is written to memory) is met internally, even though the write may not be seen on the imch/iich interface before the interrupt is asserted. ? since cmi only supports the 1024-element frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. ? cmi delivers interrupts using pirq#[a]. ? cmi does not modify the cerr count on an interrupt in when the ?do complete- split? execution criteria are not met. ? for complete-split transactions in the periodic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. if subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back. 26.9.1 aborts on usb 2.0-initiated memory reads if a read initiated by the ehc receives any status other than ?successful? in the completion packet, the ehc treats it as a fatal host error. the following actions are taken when this occurs: ? the host system error status bit is set ? the dma engines are halted, the run/stop bit is cleared, and the hchalted bit is set, after completing up to one more transaction on the usb interface ? if enabled (by the host system error enable), then an interrupt is generated ? if the status is master abort, then the received master abort bit in configuration space is set ? if the status is target abort, then the received target abort bit in configuration space is set ? if enabled (by the serr enable bit and the serr on abort enable bit in the function?s configuration space), then the signaled system error bit in configuration bit is set and the internal serr signal is asserted 26.9.2 host interface parity errors in the event of parity errors on the host-side interface, the ehc is required to respond as shown in the following table. the ehc is accessible as a target after the parity errors are detected (assuming that table 26-53. host interface parity errors (sheet 1 of 2) input scenario resulting behavior event parity error resp serr# en (cmd register, bit 8) dpe (dsr register, bit 15) master dpe (dsr register, bit 8) host system error (usb status) notes downbound request command parity error 0 x 1 0 0 do take the cycle, as normal. 10 1 0 1 do not take the cycle (master abort). no serr# generated 11 1 0 1 do not take the cycle (master abort). serr# generated
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1029 intel ? ep80579 integrated processor the system instability has not caused a deadlock in some way). all of the above description is required behavior. the following text describes the cmi- specific implementation details: there are three general forms of parity errors that the ehc may detect on its system interface: ? command/address (on cycles from the host side) ? c/a parity error on host-initiated cycles, or ? command parity error on completion packets to cmi downbound request address parity error identical to the command parity error rows above downbound request data parity error 0 x 1 0 0 do take the cycle, as normal. 10 1 0 1 cycle is taken. halt the host controller, if currently not halted. drop the write data. no serr# generated. (no perr# on the imch/iich link) software can only determine that the error occurred through the host error interrupt or by polling. 11 1 0 1 cycle is taken. halt the host controller, if currently not halted. drop the write data. serr# generated. (no perr# on the imch/iich link) downbound completion command parity error this must be treated the same as the downbound request command parity error because the error could be on the completion/request bit. downbound completion data parity error 0 x 1 0 0 do take the cycle, as normal. 10 1 1 1 cycle is taken. halt the host controller, if currently not halted. do not forward data to the usb ports. no serr# generated. (no perr# on the imch/iich link) software can only determine that the error occurred through the host error interrupt or by polling. 11 1 1 1 cycle is taken. halt the host controller, if currently not halted. do not forward data to the usb ports. serr# generated. (no perr# on the imch/iich link) table 26-53. host interface parity errors (sheet 2 of 2) input scenario resulting behavior event parity error resp serr# en (cmd register, bit 8) dpe (dsr register, bit 15) master dpe (dsr register, bit 8) host system error (usb status) notes
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1030 order number: 320066-003us ? host-initiated write data ? read completion data to the ehc when any of these three errors are detected and the parity error response bit is set in the usb 2.0 function, the ehc immediately sets the host error bit to ?1? and clears the run/stop bit to ?0?. at most, one more packet completes on the high-speed usb ports after this occurs (this packet will not contain, or be based upon, the data containing the host error). when that packet is completed, the hchalted bit is set to a ?1?. once the host error bit has been set, the run/stop bit can not be set by software until after the hcreset is generated by software and completed by the ehc, which lasts for multiple milliseconds. the ehc will still accept host-initiated cycles as a target after the hchalted bit has been set. it is recommended that software reboot in the event of a parity error because the error could be an indication of other system hardware problems. 26.10 usb 2.0 power management 26.10.1 pause feature this feature allows platforms to dynamically enter low-power states during brief periods when the system is idle (i.e., between keystrokes). this is useful for enabling power management features like enhanced intel speedstep technology (eist). the policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. normally, when the ehc is enabled, it regularly accesses main memory while traversing the dma schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the usb ports that makes this unacceptable for the purpose of dynamic power management. as a result, the ehci software drivers are allowed to pause the ehc?s dma engines when it knows that the traffic patterns of the attached devices can afford the delay. the pause only prevents the ehc from generating memory accesses; the sof packets continue to be generated on the usb ports (unlike the suspended state). the expected sequence of events for the pause feature is: 1. when starting the dma engines for the first time, the enable bits are set at the same time as, or after, the run bit is set. however, the ehc should be capable of handling the run bit set to 0 while one or both of the enable bits are 1; this may happen, for example, when the hardware halts the dma due to an error. the enable bits may be set to 1 by different writes to the command register. the ehc takes the following actions when the enable bits are set by software: a. the corresponding asynch/periodic schedule status bit(s) is (are) immediately set to 1. b. if the asynch enable bit is set, the first queue head in the asynchronous schedule is immediately fetched (if the bus master enable bit in configuration space is set). c. if the periodic enable bit is set, then the periodic frame list entry is fetched (if the bus master enable bit in configuration space is set) on the next internal trigger point, which may be up to 1 ms later. 2. before clearing a schedule enable bit, software reads the usb 2.0 status register to make sure that the corresponding schedule status bit has been set.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1031 intel ? ep80579 integrated processor 3. when system software determines that it should pause the ehc schedule, one or both of the schedule enable bits are written to 0. when this happens, the ehc responds as follows: a. the schedule disables are handled independently. in other words, the asynchronous and periodic disables may take effect in any order and vary greatly in latency. b. if the periodic schedule enable is cleared, up to two more periodic transactions may be seen on the usb ports. reads associated with the periodic schedule cease when the first fetch for a new tran saction would normally be initiated; any reads required to execute an alre ady partially-fetched transaction will continue to be generated. writes associated with the periodic schedule may continue until all pending transactions in the periodic dma engine?s transaction queue are completed. the periodic schedule status bit is cleared when the memory reads have completed and the memory writes have been internally posted. note: multiple high-bandwidth packets are considered one transaction. c. if the asynchronous schedule enable is cleared, up to two more asynchronous transactions may be seen on the usb ports. reads associated with the asynchronous schedule cease when the first fetch for a new transaction would normally be initiated; any reads requ ired to execute an already partially- fetched transaction will continue to be generated. writes associated with the asynchronous schedule will continue until all pending transactions in the asynchronous dma engine?s transaction queue are completed. the asynchronous schedule status bit is cleared when the memory reads have completed and the memory writes have been internally posted. 4. before setting a schedule enable bit, soft ware reads the usb 2.0 status register to make sure that the corresponding schedule status bit is cleared. 5. when system software determines that it should reenable the ehc, one or both of the schedule enable are written to 1. when this happens, the ehc responds as described in the initial start-up case above. the cmi does not implement a similar pause mechanism in the classic host controllers, which conflicts with the recommendation in the ehci specification . 26.10.2 suspend feature the ehci specification describes the details of port suspend and resume. 26.10.3 acpi device states the usb 2.0 function only supports the d0 and d3 pci power management states. notes regarding implementation of the device states: 1. the ehc hardware does not inherently consume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ehc features are enabled. 3. in the d3 state, accesses to the ehc memory-mapped i/o range will master abort. since the debug port uses the same memory range, the debug port is only operational when the ehc is in the d0 state. 4. in the d3 state, the ehc interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device powerstate field is written to d0 from d3, an internal reset is generated. see section 26.4.3 for general rules on the effects of this reset.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1032 order number: 320066-003us 6. attempts to write any other value into the device powerstate field other than 00b (d0 state) and 11b (d3 state) will complete normally without changing the current value in this field. software performs the following sequence to put the ehc in the d3 state: 1. software selectively suspends any enabled ehc ports. 2. software reads back the selectively suspended ports to make sure the ehc has completed the suspend request. 3. software clears the run bit. 4. software reads back the usb 2.0 status register to verify that the ehc is halted. 5. software reads and saves the contents of the pci configuration registers for restoring the context after transitioning back to the d0 state. 6. software writes the device powerstate field to the d3 state. 26.10.4 acpi system states the ehc behavior as it relates to other power management states in the system is summarized in the following list: ? the system is always in the s0 state when the ehc is in the d0 state. however, when the ehc is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (described above) enables dynamic cpu low-power states to be entered. ? the pll in the ehc is disabled when entering the s3-cold/s4/s5 states (core power turns off). ? all core-well logic is reset in the s3/s4/s5 states. 26.11 interaction with classic host controllers the enhanced host controller shares the two usb ports with two uhci classic host controllers (chcs). the chc at device 29: function 0 shares ports 1 and 2 with the ehc. there is very little interaction between the enhanced and classic controllers other than the muxing control that is provided as part of the ehc. figure 26-1 depicts the usb port connections at a conceptual level. the dashed rectangle indicates all of the logic that is part of the enhanced host controller cluster.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1033 intel ? ep80579 integrated processor 26.11.1 port-routing logic integrated into the ehc functionality is ?port-routing logic,? which performs the muxing between the classic and enhanced host controllers. cmi conceptually implements this logic as described in the ehci specification, rev. 1.0. if a device is connected that is not capable of usb 2.0?s high-speed signaling protocol or if the ehci software drivers are not present as indicated by the configured flag, then the chc owns the port. owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. the hc that is not the owner of the port internally sees a disconnected port. note: the port-routing logic is the only block of logic that observes the physical (real) connect/disconnect information. the port status logic inside each of the host controllers observes the electrical (artificial) connect/disconnect information that is generated by the port-routing logic. only the differential signal pairs are muxed/demuxed between the classic and enhanced host controllers. the other usb functional signals are handled as follows: ? the overcurrent inputs (oc#[3:0]) are directly routed to both controllers. an overcurrent event is recorded in both controllers? status registers. ? the port routing logic is implemented in the suspend power well so that reenumeration and remapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. ? cmi also allows the usb debug port traffic to be routed in and out of port #0. when in this mode, the enhanced host controller is the owner of port #0. 26.11.2 device connects the ehci specification, rev. 1.0 describes the details of handling device connects. there are four general scenarios that are summarized below. figure 26-1. usb port connections port 1 port 2 port 3 port 4 chc #2 (d29:f1) chc #1 (d29:f0) enhanced host controller logic debug port
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1034 order number: 320066-003us 1. configure flag = 0 and a classic-only device is connected in this case, the classic host controller is the owner of the port both before and after the connect occurs; the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. 2. configure flag = 0 and an enhanced-capable device is connected in this case, the classic host controller is the owner of the port both before and after the connect occurs; the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. since the classic host controller does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. configure flag = 1 and a classic-only device is connected in this case, the enhanced host controller is the owner of the port before the connect occurs. the ehci driver checks the line status bits to determine if a low- speed device is connected. if so, then the port owner bit is written to a 1 and the uhci driver handles the reset sequence. if a low-speed device is not detected through the line status bits, the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has cleared (not set) the port enable bit in the ehc?s portsc register. the ehci driver then writes a 1 to the port owner bit in the same register, causing the classic host controller to see a connect event and the ehc to see an ?electrical? disconnect event. the uhci driver and hardware handle the connection and initialization process from that point on. the ehci driver and hardware handle the perceived disconnect. 4. configure flag = 1 and an enhanced-capable device is connected in this case, the enhanced host controller is the owner of the port before, and remains the owner after, the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has set the port enable bit in the ehc?s portsc register. the port is functional at this point. the classic host controller continues to see an unconnected port. 26.11.3 device disconnects the ehci specification, rev. 1.0 describes the details of handling device connects. there are three general scenarios that are summarized below. 1. configure flag = 0 and the device is disconnected in this case, the classic host controller is the owner of the port both before and after the disconnect occurs; the ehc (except for the port-routing logic) never sees a device attached. the uhci driver handles disconnection process. 2. configure flag = 1 and a classic device is disconnected in this case, the classic host controller is the owner of the port before the disconnect occurs. the disconnect is reported by the classic host controller and serviced by the associated uhci driver. the port-routing logic in the ehc cluster forces the port owner bit to 0, indicating that the ehc owns the unconnected port. 3. configure flag = 1 and an enhanced device is disconnected in this case, the enhanced host controller is the owner of the port before, and remains the owner after, the disconnect occurs. the ehci hardware and driver handle the disconnection process. the classic host controller never sees a device attached. 26.11.4 effect of resets on port-routing logic as mentioned above, the port routing logic is implemented in the suspend power well so that reenumeration and remapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1035 intel ? ep80579 integrated processor 26.12 usb 2.0 legacy keyboard operation cmi must support the possibility of a keyboard downstream from either a usb1 (low- speed or full-speed) or a usb 2.0 (high-speed) port. see section 25.12, ?usb legacy keyboard operation? for the description of the legacy keyboard support. the ehc provides the basic ability to generate smis on an interrupt event, along with more sophisticated control of the generation of smis, as documented in section 26.2.1.27, ?offset 68h: ulsec - usb 2.0 legacy support extended capability register? . 26.13 usb 2.0 based debug port cmi supports the elimination of the legacy com ports by providing the ability for new debugger software to interact with devices on a usb 2.0 port. high-level restrictions and features: ? must be operational before usb 2.0 drivers are loaded. ? must work even when the port is disabled. ? must work even though non-configured port is default-routed to the classic controller. note: the debug port cannot be used to debug an issue that requires a classic usb device on port #0 using the uhci drivers. ? must allow normal system usb 2.0 traffic in a system that may only have one usb port. ? debug port device (dpd) must be high-speed capable and connect to a high-speed port on cmi systems. ? debug port fifo must always make forward progress (a bad status on usb is simply presented back to software). the debug port fifo is only given one usb access per microframe. 26.13.1 usb 2.0 based debug port overview the debug port facilitates os and device driver debug. it allows the software to communicate with an external console using a usb 2.0 connection. because the interface to this link does not go through the normal usb 2.0 stack, it allows communication with the external console during cases where the os is not loaded, the usb 2.0 software is broken, or where the usb 2.0 software is being debugged. specific features of this impl ementation of a debug port are: ? only works with an external usb 2.0 debug device (console) table 26-54. effect of resets on port-routing logic reset event effect on configure flag effect on port owner bits suspend well reset cleared (0) set (1) core well reset no effect no effect d3-to-d0 reset no effect no effect hcreset cleared (0) set (1)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1036 order number: 320066-003us ? implemented for a specific port on the host controller ? operational anytime the port is not suspended and the host controller is in d0 power state. ? capability is interrupted when port is driving usb reset 26.13.2 debug port register details the debug port?s registers are located in the same memory range as the standard ehci registers, which are defined by the base address register (bar). the base offset for these registers (a0h) is declared in the debu g port base offset capability register at configuration offset 5ah. the specific ehci port that supports this debug capability is indicated by a four-bit field (bits 20-23) in the hcsparams register of an ehci controller. behavioral rules: 1. all of these registers are implemented in the core well and reset by ehc hcreset, ehc d3-to-d0 state transition, and pltrst#. 2. the hardware associated with this register provides no checks to ensure that software programs the interface corre ctly. how the hardware behaves when programmed illegally is undefined. the default values are defined with an h for hex, a b for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. 26.13.2.1 offset a0h: cntl_sts - control/status register software must do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. in order to preserve the usage of reserved bits in the future, software must always write the same value read from the bit until it is defined. reserved bits will always return 0 when read.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1037 intel ? ep80579 integrated processor table 26-55. offset a0h: cntl_sts - control/status register (sheet 1 of 2) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved 0h 30 owner_cnt 0 = ownership of the debug port is not forced to the ehci controller (default) 1 = ownership of the debug port is forced to the ehci controller (i.e., immediately taken away from the companion classic usb host controller). if the port was already owned by the ehci controller, then setting this bit has no effect. this bit overrides all of the ownership-related bits in the standard ehci registers. the value in this bit does not affect the value reported in the portsc port owner bit. 0h rw 29 reserved reserved 0h 28 enabled_cnt 0 = software can clear this by writing a 0 to it. the hardware clears this bit for the same conditions where the port enable/disable change bit (in the portsc register) is set. (default) 1 = debug port is enabled for operation. software can directly set this bit if the port is already enabled in the associated portsc register (this is enforced by the hardware). 0h rw 27 reserved reserved 0h 26 :17 reserved reserved 0h 16 done_sts 0 = request not complete. 1 = set by hardware to indicate that the request is complete. writing a 1 to this bit will clear it if it is set. writing a 0 to this bit has no effect. reset default = 0. 0h rwc 15 :12 link_id_sts this field identifies the link interface. it is hardwired to 0h to indicate that it is a usb debug port. 0h ro 11 reserved reserved. 0h 10 in_use_cnt set by software to indicate that the port is in use. cleared by software to indicate that the port is free and may be used by other software. this bit is cleared after reset. (this bit has no effect on hardware.) 0h rw 09 :07 exception_st s this field indicates the exception when the error_good#_sts bit is set. this field must be ignored if the error_good#_sts bit is 0. 000 no error. note: this must not be seen, since this field must only be checked if there is an error. 001 transaction error: indicates the usb 2.0 transaction had an error (crc, bad pid, timeout, etc.) 010 hardware error. request was attempted (or in progress) when port was suspended or reset. all others are reserved. reset default = 000b 000b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1038 order number: 320066-003us 06 error_good_ n_sts 0 = the hardware clears this bit to 0 upon the proper completion of a read or write. 1 = the hardware sets this bit to indicate that an error has occurred. details on the nature of the error are provided in the exception field. reset default = 0. 0h ro 05 go_cnt software sets this bit to cause the hardware to perform a read or write request. writing a 0 to this bit has no effect. writing a 1 to this bit when it is already set may result in undefined behavior. when set, the hardware clears this bit when the hardware sets the done_sts bit. reset default = 0. 0h rw 04 write_read_n _cnt software sets this bit to indicate that the current request is a write. software clears this bit to indicate that the current request is a read. reset default = 0. 0h rw 03 :00 data_len_cnt this field is used to indicate the size of the data to be transferred. for write operations, this field is set by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the console. a value of 0h indicates that a zero-length packet must be sent. a value of 1-8 indicates 1-8 bytes are to be transferred. values 9-fh are illegal and how hardware behaves if used is undefined. for read operations, this field is set by hardware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero length packet was returned and the state of data buffer is not defined. a value of 1-8 indicates 1-8 bytes were received. hardware is not allowed to return values 9-fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. reset default = 0h. 0h rw table 26-55. offset a0h: cntl_sts - control/status register (sheet 2 of 2) description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: a0h a3h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1039 intel ? ep80579 integrated processor 26.13.2.2 offset a4h: usbpid - usb pids register this dword register is used to communicate pid information between the usb debug driver and the usb debug port. the debug port uses some of these fields to generate usb packets, and uses other fields to return pid information to the usb debug driver. 26.13.2.3 offset a8h: databuf - data buffer bytes 7:0 note: this register can be accessed as eight separate 8-bit registers or two separate 32-bit registers. table 26-56. offset a4h: usbpid - usb pids register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: a4h a4h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 reserved reserved. 0h 23 :16 received_pid_ sts the hardware updates this field with the received pid for transactions in either direction. when the controller is writing data, this field is updated with the handshake pid that is received from the device. when the host controller is reading data, this field is updated with the data packet pid (if the device sent data), or the handshake pid (if the device naks the request). this field is valid when the hardware clears the go_done#_cnt bit. 0h ro 15 :08 send_pid_cnt the hardware sends this pid to begin the data packet when sending data to usb (i.e., write_read#_cnt is asserted). software will typically set this field to either data0 or data1 pid values. 0h rw 07 :00 token_pid_cn t the hardware sends this pid as the token pid for each usb transaction. software will typically set this field to either in, out or setup pid values. 0h rw table 26-57. offset a8h: databuf - data buffer bytes 7:0 description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: a8h afh size: 64 bit default: 0000000000000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :00 databuffer these are the 8 bytes of the data buffer. bits 7:0 correspond to least significant byte (byte 0). bits 63:56 correspond to the most significant byte (byte 7). the bytes in the data buffer must be written with data before software initiates a write request. for a read request, the data buffer contains valid data when done_sts is set by the hardware, error_good#_sts is cleared by the hardware, and the data_length_cnt field indicates the number of bytes that are valid. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1040 order number: 320066-003us 26.13.2.4 offset b0h: config - configuration register 26.13.3 usb 2.0 based debug port theory of operation there are two operational modes for the usb debug port: 1. mode 1 is when the enhanced usb host controller is in a disabled state from the viewpoint of a standard ehci driver (i.e., host controller?s run/stop bit is 0). in mode 1, the debug port controller is required to generate ?keepalive? packets less than 2 milliseconds apart to keep the attached debug device from suspending. the keepalive packet must be a standalone 32-bit sync field. 2. mode 2 is when the host controller is running (i.e., host controller?s run/stop# bit is 1). in mode 2, the normal transmission of sof packets (or sync keepalives if the port is functionally disabled) will ke ep the debug device from suspending. 26.13.3.1 behavioral rules 3. in both modes 1 and 2, the debug port controller must check for software requested debug transactions at least ever y 125 microseconds. if the debug port is enabled by the debug driver, and the standard host controller driver resets the usb port, usb debug transactions are held off for the duration of the reset and until after the first sof is sent. 4. if the standard host controller driver suspends the usb port, then usb debug transactions are held off for the duration of the suspend/resume sequence and until after the first sof is sent. 5. the enabled_cnt bit in the debug register space is independent of the similar port control bit in the associated port status and control register. ta b l e 2 6 - 5 9 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated port status and control register. table 26-58. offset b0h: config - configuration register description: view: pci bar: mbar bus:device:function: 0:29:7 offset start: offset end: b0h b0h size: 32 bit default: 00007f01h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :15 reserved reserved 0h 14 :08 usb_address_ cnf 7-bit field that identifies the usb device address used by the controller for all token pid generation. this is a rw field that is set to 7fh after reset. 7fh rw 07 :04 reserved reserved 0h 03 :00 usb_endpoint _cnf this 4-bit field identifies the endpoint used by the controller for all token pid generation. this is a rw field that is set to 01h after reset. 1h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1041 intel ? ep80579 integrated processor 26.13.3.2 out transactions an out transaction sends data to the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is set the sequence of the transaction is: 1. software sets the appropriate values in the following bits: usb_address_cnf usb_endpoint_cnf data_buffer[63:0] token_pid_cnt[7:0] send_pid_cnt[15:8] data_len_cnt write_read#_cnt(note: this will always be 1 for out transactions) go_cnt (note: this will always be 1 to initiate the transaction) 2. the debug port controller sends a token packet consisting of: a. sync b. token_pid_cnt field c. usb_address_cnt field d. usb_endpoint_cnt field e. 5-bit crc field 3. after sending the token packet, the debug port controller sends a data packet consisting of: f. s y n c table 26-59. debug port behavior debug bits ehci bits debug port behavior owner_cnt enabled_cnt port enable run/ stop# suspend 0xxxx debug port is not being used. normal operation. 10xxx debug port is not being used. normal operation. 1100x debug port in mode 1. sync keepalives sent plus debug traffic 1101x debug port in mode 2. sync keepalives or sof packets may be sent plus debug traffic. cmi generates sync keepalives, not sof packets. no other normal traffic is sent out this port, because the port is not enabled. 11100 illegal. host controller driver must never put the controller into this state (enabled, not running and not suspended). 1 1 1 0 1 port is suspended. no debug traffic sent. 11110 debug port in mode 2. debug traffic is interspersed with normal traffic. 1 1 1 1 1 port is suspended. no debug traffic sent.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1042 order number: 320066-003us g. send_pid_cnt field h. the number of data bytes indicated in data_len_cnt from the data_buffer i. 16-bit crc note: a data_len_cnt value of zero is valid in which case no data bytes would be included in the packet. 4. after sending the data packet, the controller waits for a handshake response from the debug device. ? if a handshake is received, the debug port controller: j. places the received pid in the received_pid_sts field k. resets the error_good#_sts bit l. sets the done_sts bit ? if no handshake pid is received, the debug port controller: j. sets the exception_sts field to 001b k. sets the error_good#_sts bit l. sets the done_sts bit 26.13.3.3 in transactions an in transaction receives data from the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is reset the sequence of the transaction is: 1. software sets the appropriate values in the following bits: usb_address_cnf usb_endpoint_cnf token_pid_cnt[7:0] data_len_cnt write_read#_cnt(note: this will always be 0 for in transactions) go_cnt (note: this will always be 1 to initiate the transaction) the debug port controller sends a token packet consisting of: ?sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field. 2. after sending the token packet, the debug port controller waits for a response from the debug device. if a response is received: the received pid is placed into the received_pid_sts field ? any subsequent bytes are placed into the data_buffer ? the data_len_cnt field is updated to show the number of bytes that were received after the pid. 3. if a valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller:
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1043 intel ? ep80579 integrated processor ? resets the error_good#_sts bit ? sets the done_sts bit 4. if a valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: ? transmits an ack handshake packet ? resets the error_good#_sts bit ? sets the done_sts bit 5. if no valid packet is received, then the debug port controller: ? sets the exception_sts field to 001b ? sets the error_good#_sts bit, ? sets the done_sts bit. 26.13.3.4 debug software 26.13.3.4.1 enabling the debug port there are two mutually exclusive conditions that debug software must address as part of its startup processing: ? the ehci has been initialized by system software. ? the ehci has not been initialized by system software. debug software can determine the current ?initialized? state of the ehci by examining the configure flag in the ehci usb 2.0 command register. if this flag is set, then system software has initialized the ehci. otherwise, the ehci must not be considered initialized. debug software will initialize the debug port registers depending on the state of the ehci. however, before this can be accomplished, debug software must determine which root usb port is designated as the debug port. 26.13.3.4.2 determining the debug port debug software can easily determine which usb root port has been designated as the debug port by examining bits 20:23 of the ehci host controller structural parameters register. this 4-bit field represents the numeric value assigned to the debug port (i.e., 0000 == port 0, 0001 == port 1, 0010 == port 2 ?? 1111 == port 15). this value is 0000 (port 0). 26.13.3.4.3 debug software startup with non-initialized ehci debug software can attempt to use the debug port if, after setting the owner_cnt bit, the current connect status bit in the appropriate (see section 26.13.3.4.2, ?determining the debug port? ) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate, or it may choose to wait until a device is connected. if a device is connected to the port, then debug software must reset/enable the port. debug software does this by setting and then clearing the port reset bit in the portsc register. software must set the run/stop bit in the ehci command register before clearing the port reset bit in order to complete the reset and to enable the port. to guarantee a successful reset, debug software must also keep the port reset bit set for at least 50 ms. due to possible delays, this bit may not change to zero immediately; reset is complete when this bit reads as zero. software must not continue until this bit reads zero.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1044 order number: 320066-003us if a high-speed device is attached, the ehci will automatically set the port enabled/ disabled bit in the portsc register and the debug software can proceed. debug software must set the enabled_cnt bit in the debug port control/status register, and then reset (clear) the port enabled/disabled bit in the portsc register and the run/ stop bit in the ehci command register. the ehci bits are cleared in order to present the proper default idle conditions to the ehci driver as it loads. 26.13.3.4.4 debug software startup with initialized ehci debug software can attempt to use the debug port if the current connect status bit in the appropriate (see section 26.13.3.4.2, ?determining the debug port? ) portsc register is set. if the current connect status bit is not set, then debug software may terminate or it may wait until a device is connected. if a device is connected, then debug software must set the owner_cnt bit and then the enabled_cnt bit in the debug port control/status register. 26.13.3.4.5 determining debug peripheral presence after enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. if all attempts result in an error ( exception bits in the debug port control/status register indicates a transaction error), then the attached device is not a debug peripheral. if the debug port peripheral is not present, then debug software may terminate or it may wait until a debug peripheral is connected.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1045 intel ? ep80579 integrated processor 27.0 power management 27.1 features ? acpi power and thermal management support. ? processor thrmtrip# emergency shutdown. ? acpi 24-bit timer. ? software initiated throttling of processor performance for thermal and power reduction. ? sci and smi# generation. ? pci pme# signal for wake up from low-power states. ? sys_reset# input to eliminate external glue logic. ? system clock control. ? acpi c0 state full on: processor operating. individual devices may be shut to save power. ? acpi c1 state auto-halt: processor has executed a autohalt instruction and is not executing code. the processor snoops the bus and maintains cache coherency. ? acpi c2 state stop-grant state (using stpclk# signal) halts processor?s instruction stream. ? system sleeping state control. ? acpi s0 state ? all power planes active (awake). ? acpi s3 state ? suspend to ram (str). ? supports s3-cold state. ? acpi s4 state ? suspend-to-disk (std). ? acpi s5 state ? soft off (soff). ? power failure detection and recovery. ? streamlined legacy power management support for apm-based systems.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1046 order number: 320066-003us 27.2 imch-iich messages nsi messaging protocol is supported. messages associated with power management and state transitions are summarized in table 27-1 . the legacy protocol messages are shown only for reference. nsi messages that are not associated with power management are not shown. table 27-1. imch - iich messages legacy message new message direction description/comment: --- reset-warn iich imch warning from the iich to the imch that the iich is about to assert the pltrst# signal. the imch is expected to acknowledge this with the reset-warn-ack. however, it the imch fails to do this within the ti meout period, the iich will assert the reset. --- reset-warn- ack imch iich acknowledge from the imch that it has seen the reset-warn message is now ready for the iich to cause the reset. stop- grant stop-grant (req-c2) imch iich if the processor is in c0 - indication that the processor has issued last stop-grant cycle. the imch may receive more than one stop-grant cycle from the processor(s). it is the imch?s responsibility to only send the last stop-grant. go-c0 go-c0 iich imch indication that system is going back to c0 state. -- ack-c0 imch iich acknowledge that imch observed the go-c0 message and is ready to proceed. -- go-c2 iich imch this is an indication that the processor has been put into stop-grant state. when coming from c0, this tells the imch that it is safe to assert slp#. -- ack-c2 imch iich imch indicates it observed the go-c2 message and is now ready to proceed.f going toward c0, the iich is free to deassert stpclk#. go-c3 go-s3 iich imch indication that the iich is getting ready to put the system into s3, s4 or s5 state. ack-c3 ack-s3 imch iich indication that the imch observed the go-s3 message and is ready to proceed. -- req-c0 (break-ind) imch iich this is an indication from the imch to the iich that the imch thinks the processor must be brought to a c0 state. this would be sent for several cases: 1. if the imch had received a ?pending break event? indication from the processor. this is needed when pbe# is not muxed with ferr# and is instead muxed with some pin that goes only to the imch. 2. the imch has some internal device or link to external device that can cause a break event that is not associated with an interrupt. note: the imch is not required to implement this message.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1047 intel ? ep80579 integrated processor 27.3 power management register details this section shows the power management registers. the power management registers are distributed within the pci device 31: function 0 space, as well as a separate i/o range. each register is described below. unless otherwise indicated, bits are in the main (core) power well. bits not explicitly defined in each register are assumed to be reserved. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers my return on-zero va lues are read only. writes to reserved locations may cause system failure and unpredictable behavior. note: reserved bits are read only. 27.3.1 power management pc i configuration registers note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). 27.3.1.1 offset a0h: gen_pmcon_1 - general pm configuration 1 register table 27-2. bus 0, device 31, function 0: summary of lpc interface power management pci configuration registers offset start offset end register id - description default value a0h a0h ?offset a0h: gen_pmcon_1 - general pm configuration 1 register? on page 1048 0200h a2h a2h ?offset a2h: gen_pmcon_2 - general pm configuration 2 register? on page 1049 00h a4h a4h ?offset a4h: gen_pmcon_3 - general pm configuration 3 register? on page 1051 00h b8h bbh ?offset b8h: gpi_rout - gpi routing control register? on page 1053 00000000h table 27-3. offset a0h: gen_pmcon_1 - general pm configuration 1 register (sheet 1 of description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: a0h a0h size: 16 bit default: 0200h power well: core a bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h 10 bios_pci_exp _en this bit acts as a global enable for the sci associated with the pci express* ports. 0 = the various pci express* ports and cannot cause the pci_exp_sts bit to go active. 1 = the various pci express* ports and can cause the pci_exp_sts bit to go active. 0h rw 09 pwrbtn_lvl this bit indicates the current state of the pwrbtn# signal. 0 = low 1 = high 1ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1048 order number: 320066-003us 08 reserved reserved 0h 07 reserved reserved 0h 06 1 = reserved 0h rw 05 cpuslp_en cpu slp# enable. software sets this bit to enable the cpuslp# signal to go active in the s1 state. 0 = disable. 1 = enables the cpuslp# signal to go active when the processor is placed in s1 state. the signal is not asserted when the ep80579 is in the s3, s4 or s5 state. 0h 04 smi_lock when this bit is set, writes to the glb_smi_en bit will have no effect. once the smi_lock bit is set, writes of 0 to smi_lock bit will have no effect (i.e., once set, this bit can only be cleared by pltrst#). 0h rwo 03 rsvd reserved 0h 02 rsvd reserved 0h 01 : 00 per_smi_sel software sets these bits to control the rate at which the periodic smi# is generated: 00 = 64 seconds (default) 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds tolerance for the timer is 1 second. 00h rw a. bits 10, 07:00 ? core; bit 9 ? resume table 27-3. offset a0h: gen_pmcon_1 - general pm configuration 1 register (sheet 2 of description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: a0h a0h size: 16 bit default: 0200h power well: core a bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1049 intel ? ep80579 integrated processor 27.3.1.2 offset a2h: gen_pmcon_2 - general pm configuration 2 register table 27-4. offset a2h: gen_pmcon_2 - general pm configuration 2 register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: a2h a2h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access 07 dib dram initialization bit: this bit does not effect hardware functionality in any way.bios is expected to set this bit prior to starting the dram initialization sequence and to clear this bit after completing the dram initialization sequence. bios can detect that a dram initialization sequence was interrupted by a reset by reading this bit during the boot sequence. if the bit is 1, then the dram initialization was interrupted. see section 27.5.1 for the expected bios response. this bit is reset by the assertion of the rsmrst# pin. 0h rw 06 : 05 rsvd reserved 00h 04 srs system reset status: 0 = sys_reset# button not pressed. 1 = this bit is set when the sys_reset# button is pressed. bios is expected to read this bit and clear it if it is set. note: this bit is also reset by rsmrst# and cf9h resets. 0h rwc 03 cts cpu thermal trip status: 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when pltrst# is inactive and thrmtrip# goes active while the system is in an s0 or s1 state. note: this bit is also reset by rsmrst# and cf9h resets. it is not reset by the shutdown and reboot associated with the cputhrmtrip# event. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1050 order number: 320066-003us 02 mawvs minimum slp_s4# assertion width violation status : 0 = software clears this bit by writing a 1 to it. 1 = hardware sets this bit when the slp_s4# assertion width is less than the time programmed in the slp_s4# minimum assertion width field (d31.f0.a4h.5:4). when exiting g3, the timer begins when the rsmrst# input deasserts. note: this bit is functional regardless of the value in the slp_s4# assertion stretch enable. this bit is reset by the assertion of the rsmrst# pin, but can be set in some cases before the default value is readable. 0h rwc 01 cpupwr_flr cpu power failure: 0 = software (typically) bios clears this bit by writing a 0 to it. 1 = indicates that the vrmpwrgd input signal (/ ) from the processor?s vrm went low. note: vrmpwrgd is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected. 0h rw 00 pwrok_flr power ok failure: 0 = software clears this bit by writing a 1 to it, or when the system goes into a g3 state. 1 = this bit will be set any time pwrok goes low, when the system was in s0, or s1 state. the bit will be cleared only by software by writing a 1 to this bit or when the system goes to a g3 state. see section 27.6.3 for more details about the pwrok pin functionality. note: in the case of true pwrok failure, pwrok will go low first before the vrmpwrgd. 0h rwc table 27-4. offset a2h: gen_pmcon_2 - general pm configuration 2 register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: a2h a2h size: 8 bit default: 00h power well: resume bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1051 intel ? ep80579 integrated processor 27.3.1.3 offset a4h: gen_pmcon_3 - general pm configuration 3 register table 27-5. offset a4h: gen_pmcon_3 - general pm configuration 3 register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: a4h a4h size: 8 bit default: 00h power well: rtc bit range bit acronym bit description sticky bit reset value bit access 07 : 06 swsmi_ rate_sel this 2-bit value indicates when the swsmi timer will time out. valid values are: ? 00 1.5 ms +/- 0.6 ms ? 01 16 ms +/- 4 ms ? 10 32 ms +/- 4 ms ? 11 64 ms +/- 4 ms these bits are not cleared by any type of reset except rtest#. 00h rw 05 : 04 smaw slp_s4# minimum assertion width: this 2-bit value indicates the minimum assertion width of the slp_s4# signal to guarantee that the drams have been safely power-cycled. this value may be modified per platform depending on dram types, power supply capacitance, etc. valid values are: ? 11 1 to 2 seconds ? 10 2 to 3 seconds ? 01 3 to 4 seconds ? 00 4 to 5 seconds this value is used in two ways: 1. if the slp_s4# assertion width is ever shorter than this time, a status bit (d31.f0.a2h.2) is set for bios to read when s0 is entered 2. if enabled by bit 3 in this register, the hardware will prevent the slp_s4# signal from deasserting within this minimum time period after asserting note: the logic that measures this time is in the suspend power well. therefore, when leaving the g3 state, the minimum time is measured from the deassertion of rsmrst#. rtest# forces this field to the conservative default state (00b). 00h 03 sase slp_s4# assertion stretch enable: 0 = the slp_s4# minimum assertion time is 1 to 2 rtcclk. 1 = the slp_s4# signal will minimally assert for the time specified in bits 5:4 of this register. this bit is cleared by rtest#. 0h rw 02 rps rtc power status: 0 = rtest# ok 1 = rtest# indicates a weak or missing battery. the bit remains set until the software clears it by writing a 0 back to this bit position. this bit is not cleared by any type of reset. xrw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1052 order number: 320066-003us 01 pwr_flr pwr_flr: 0 = indicates that the trickle current has not failed since the last time the bit was cleared. 1 = indicates that the trickle current (from the main battery or trickle supply) was removed or failed. software writes a 1 to this bit to clear it. this bit is in the rtc well, and is not cleared by any type of reset except rtest#. notes: 1. rsmrst# is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected. 2. clearing cmos in cmi platforms can be done by using a jumper on rtest# or gpi. implementations must not attempt to clear cmos by using a jumper to pull vccrtc low. 0h rwc 00 ag3e afterg3_en: determines what state to go to when power is reapplied after a power failure (g3 state). 0 = system will return to an s0 state (boot) after power is reapplied. 1 = system will return to the s5 state (except if it was in s4, in which case it will return to s4-like state). in addition to software writes, this bit is set by the following hardware conditions: ? power button override ? smbus unconditional powerdown message ? catastrophic temperature condition from an internal sensor ? assertion of cpu thermal trip input 0h rw table 27-5. offset a4h: gen_pmcon_3 - general pm configuration 3 register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: a4h a4h size: 8 bit default: 00h power well: rtc bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1053 intel ? ep80579 integrated processor 27.3.1.4 offset b8h: gpi_rout - gpi routing control register 27.3.2 apm power management i/o-mapped registers ta bl e 2 7 - 7 shows the i/o registers associated with apm support. this register space is enabled in the pci device 31: function 0 space (apmc_en), and cannot be moved (fixed i/o location). note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). table 27-6. offset b8h: gpi_rout - gpi routing control register description: view: pci bar: configuration bus:device:function: 0:31:0 offset start: offset end: b8h bbh size: 32 bit default: 00000000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 31 : 02 gpi gpi[15] through gpi[1]: see bits 1:0 for description. 0h rw 01 : 00 gpi0_route if the corresponding gpio is implemented and is set to an input, a ?1? in the gp_lvl bit can be routed to cause an smi# or sci. if the gpio is not set to an input, this field has no effect. ? 00 ? no effect (or gpio unimplemented) ? 01 ? smi# (if corresponding alt_gpi_smi_en bit also set) ? 10 ? sci (if corresponding gpe0_en bit also set) ? 11 ? reserved if the system is in an s1,s3,s4 or s5 state and if the gpe0_en bit is also set, then the gpi can cause a wake event, even if the gpi is not routed to cause an smi# or sci. exception: if the system is in s5 state due to a powerbutton override, then the gpis will not cause wake events. note: core well gpis are not capable of waking the system from sleep states where the core well is not powered. 00h rw table 27-7. summary of apm registers mapped in i/o space offset start offset end register id - description default value b2h b2h ?offset b2h: apm_cnt - advanced power management control port register? on page 1054 00h b3h b3h ?offset b3h: apm_sts - advanced power management status port register? on page 1054 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1054 order number: 320066-003us 27.3.2.1 offset b2h: apm_cnt - advanced power management control port register used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc register, but also generates an smi# when the apmc_en bit is set. 27.3.2.2 offset b3h: apm_sts - advanced power management status port register used to pass data between the os and the smi handler. basically, this is a scratchpad register and is not effected by any other register or function (other than a pci reset). table 27-8. offset b2h: apm_cnt - advanced power management control port register description: view: ia f base address: 0000h (io) offset start: offset end: b2h b2h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 apm_cnt used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc register, but also generates an smi# when the apmc_en bit is set. 00h rw table 27-9. offset b3h: apm_sts - advanced power management status port register description: view: ia f base address: 0000h (io) offset start: offset end: b3h b3h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 apm_sts used to pass data between the os and the smi handler. basically, this is a scratchpad register and is not affected by any other register or function (other than a platform reset). 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1055 intel ? ep80579 integrated processor 27.3.3 general power management i/o-mapped registers table 27-10 shows the registers associated with acpi and legacy power management support. these registers are enabled in the pci device 31: function 0 space (acpi enable in section 19.2.2 ), and can be moved to any i/o location (128-byte aligned) determined by abase in section 19.2.2.1 (referenced in this chapter by pmbase). the registers are defined to be compliant with the advanced configuration and power interface (acpi) specification, rev. 2.0 , and generally use the same bit names. all reserved bits and registers will always return 0 when read, and will have no effect when written. note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 ). table 27-10. bus 0, device 31, function 0: summary of lpc interface power management general configuration registers mapped through pmbase i/o bar offset start offset end register id - description default value 00h 00h ?offset 00h: pm1_sts ? power management 1 status register? on page 1056 0000h 02h 02h ?offset 02h: pm1_en - power management 1 enables register? on page 1058 0000h 04h 04h ?offset 04h: pm1_cnt - power management 1 control register? on page 1059 0000h 08h b8h ?offset 08h: pm1_tmr - power management 1 timer register? on page 1060 00000000h 10h 10h ?offset 10h: proc_cnt - processor control register? on page 1060 00000000h 14h 14h ?offset 14h: lv2 - level 2 register? on page 1063 00h 28h 28h ?offset 28h: gpe0_sts - general purpose event 0 status register? on page 1063 00000000h 2ch 2ch ?offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register? on page 1067 00000000h 30h 30h ?offset 30h: smi_en - smi control and enable register? on page 1068 00000000h 34h 34h ?offset 34h: smi_sts - smi status register? on page 1071 00000000h 38h 38h ?offset 38h: alt_gpi_smi_en - alternate gpi smi enable register? on page 1073 0000h 3ah 3ah ?offset 3ah: alt_gpi_smi_sts - alternate gpi smi status register? on page 1074 0000h 44h 44h ?offset 44h: devtrap_sts - devtrap_sts register? on page 1074 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1056 order number: 320066-003us 27.3.3.1 offset 00h: pm1_sts ? power management 1 status register table 27-11. offset 00h: pm1_sts ? power mana gement 1 status register (sheet 1 of 2) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 00h 00h size: 16 bit default: 0000h power well: core a bit range bit acronym bit description sticky bit reset value bit access 15 wak_sts 0 = software clears this bit by writing a 1 to it. 1 = this bit can only be set by hardware when the system is in one of the sleep states (via the slp_en bit) and an enabled wake event occurs. upon setting this bit, cmi will transition the system to the on state. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. if a power failure occurs (such as removed batteries) without the slp_en bit set, the wak_sts bit will not be set when the power returns if the after_g3 bit is 0. if the after_g3 bit is 1, then the wak_sts bit will be set after waking from a power failure. if necessary, the bios can clear the wak_sts bit in this case. 0h rwc 14 reserved reserved. 0h 13 : 12 reserved reserved 00h 11 prbtnor_sts 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a power button override event occurs (i.e., the power button is pressed for at least 4 consecutive seconds), or due to the corresponding bit in the smbus slave message, or due to an internal thermal sensor catastrophic condition. these events cause an unconditional transition to the s5 state, as well as sets the afterg3 bit. the bios or sci handler clears this bit by writing a 1 to it. this bit is not affected by hard resets via cf9h writes, and is not reset by rsmrst#. thus, this bit is preserved through power failures. 0h rwc 10 rtc_sts 0 = software clears this bit by writing a 1 to it. 1 = set when the rtc generates an alarm (assertion of the irq8# signal), and is not affected by any other enable bit. see rtc_en for the effect when rtc_sts goes active. this bit is only set by hardware and can only be reset by writing a one to this bit position. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. additionally if the rtc_en bit (pmbase + 02h, bit 10) is set, the setting of the rtc_sts bit will generate a wake event. 0h rwc 09 reserved reserved 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1057 intel ? ep80579 integrated processor 08 pwrbtn_sts this bit is set when the pwrbtn# signal is asserted (low), independent of any other enable bit. see pwrbtn_en for the effect when pwrbtn_sts goes active. pwrbtn_sts is always a wake event. this bit is only set by hardware and can be cleared by software writing a one to this bit position. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. if the pwrbtn# signal is held low for more than 4 seconds, cmi clears the pwrbtn_sts bit, sets the pwrbtnor_sts bit, the system transitions to the s5 state, and only pwrbtn# is enabled as a wake event. if pwrbtn_sts bit is cleared by software while the pwrbtn# pin is still held low, this will not cause the pwrbtn_sts bit to be set. the pwrbtn# signal must go inactive and active again to set the pwrbtn_sts bit. note: the smbus unconditional power down message, the cpu thermal trip and the internal thermal sensors' catastrophic condition result in behavior matching the powerbutton override, which includes clearing this bit. 0h rwc 07 : 06 reserved reserved 0h 05 gbl_sts 0 = the sci handler must then clear this bit by writing a 1 to the bit location. 1 = set when an sci is generated due to bios wanting the attention of the sci handler. bios has a corresponding bit, bios_rls, which will cause an sci and set this bit. this bit will not cause wake events or smi#. this bit is not effected by sci_en. note: gbl_sts being set will cause an sci, even if the sci_en bit is not set. software must take great care not to set the bios_rls bit (which causes gbl_sts to be set) if the sci handler is not in place. 0h rwc 04 01 reserved reserved 000h 00 tmrof_sts 0 = the sci or smi# handler clears this bit by writing a 1 to the bit location. 1 = this bit gets set any time bit 22 of the 24-bit timer goes low (bits are numbered from 0 to 23). this will occur every 2.3435 seconds. hence, it is highly likely that a read to this register after reset will yield a 1 in this field. when the tmrof_en bit (pmbase + 02h, bit 0) is set, then the setting of the tmrof_sts bit will additionally generate an sci or smi# (depending on the sci_en). 0h rwc a. bits 0-7: core, bits 8-15: resume (except 11 in rtc) table 27-11. offset 00h: pm1_sts ? power manage ment 1 status register (sheet 2 of 2) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 00h 00h size: 16 bit default: 0000h power well: core a bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1058 order number: 320066-003us 27.3.3.2 offset 02h: pm1_en - power management 1 enables register table 27-12. offset 02h: pm1_en - power management 1 enables register description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 02h 02h size: 16 bit default: 0000h power well: core a a. bits 0-7: core, bits 8-15: resume bit range bit acronym bit description sticky bit reset value bit access 15 reserved reserved 0h 14 reserved reserved 0h 13 11 reserved reserved 0h 10 rtc_en this is the rtc alarm enable bit. it works in conjunction with the sci_en bit: rtc_en sci_en effect when rtc_sts is set 0 x no smi# or sci. if system was in s1,s3,s4 or s5, no wake event occurs. 1 0 smi#. if system was in s1,s3,s4 or s5, then a wake event occurs before the smi#. 1 1 sci. if system was in s1, s3, s4 or s5, then a wake event occurs before the smi#. 0h rw 09 reserved reserved 0h 08 pwrbtn_en this bit is the power button enable. it works in conjunction with the sci_en bit: pwrbtn_en sci_en effect when pwrbtn_sts is set 0 x no smi# or sci 1 0 smi# 1 1 sci note: pwrbtn_en has no effect on the pwrbtn_sts bit being set by the assertion of the power button. the power button is always enabled as a wake event. 0h rw 07 : 06 reserved reserved 0h 05 gbl_en the global enable bit. when both the gbl_en and the gbl_sts are set, an sci is generated. 0 = disable. 1 = enable sci on gbl_sts going active. 0h rw 04 : 01 reserved reserved 0h 00 tmrof_en this is the timer overflow interrupt enable bit. it works in conjunction with the sci_en bit: tmrof_en sci_en effect when tmrof_sts is set 0 x no smi# or sci. if system was in s1, s3, s4 or s5, no wake event. 1 0 smi#. if system was in s1,s3, s4,s5, then a wake event occurs before the smi#. 1 1 sci. if system was in s1,s3,s4 or s5, then a wake event occurs before the smi#. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1059 intel ? ep80579 integrated processor 27.3.3.3 offset 04h: pm1_cnt - power management 1 control register table 27-13. offset 04h: pm1_cnt - power management 1 control register description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 04h 04h size: 32 bit default: 0000h power well: core a a. bits 0-7: core, bits 8-12: rtc, bits 13-15: resume bit range bit acronym bit description sticky bit reset value bit access 31 : 14 reserved reserved 0h 13 slp_en this is a write-only bit and reads to it always return a zero. setting this bit causes the system to sequence into the sleep state defined by the slp_typ field. 0h wo 12 : 10 slp_typ this 3-bit field defines the type of sleep the system must enter when the slp_en bit is set to 1. these bits are reset by rtest# only. 0h rw 09 : 03 reserved reserved 0h 02 gbl_rls this bit is used by the acpi software to raise an event to the bios software. bios software has a corresponding enable and status bits to control its ability to receive acpi events. this bit always reads as 0. 0h wo reserved reserved 0h 00 sci_en selects the sci interrupt or the smi# for various events. 0 = these events generate an smi#. 1 = the events generate an sci interrupt. 0h rw bits mode typ i ca l mapping 000 on s0 001 just assert stpclk#. puts processor in stop-grant state. can also assert cpuslp#, to put processor in sleep state. s1 010 reserved 011 reserved 100 reserved 101 suspend-to-ram s3 110 suspend-to-disk s4 111 soft off s5
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1060 order number: 320066-003us 27.3.3.4 offset 08h: pm1_tmr - power management 1 timer register 27.3.3.5 offset 10h: proc_cnt - processor control register table 27-14. offset 08h: pm1_tmr - power management 1 timer register description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 08h b8h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved . will always read as 0. 00h 23 : 00 tmr_val this read-only field returns the running count of the pm timer. this counter runs off a 3.579545 mhz clock (derived from 14.31818 mhz divided by 4). it is reset (to 0) during a pci reset, and then continues counting as long as the system is in the s0 state. hence, it is highly likely that a read to this register after reset will yield a non-zero value. after an s1 state, the counter will not be reset (it will continue counting from the last value in s0 state). anytime bit 22 of the timer goes high to low (bits referenced from 0 to 23), the tmrof_sts bit is set. the high-to-low transition will occur every 2.3435 seconds. writes to this register have no effect. 00h ro table 27-15. offset 10h: proc_cnt - processor control register (sheet 1 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 10h 10h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 18 reserved reserved 00h 17 thtl_sts 0 = no clock throttling is occurring (maximum processor performance). 1 = indicates that the clock state machine is throttling the cpu performance. this could be due to the tht_en bit or the force_thtl bit being set. 0h ro 16 : 09 reserved reserved 00h 08 force_thtl software can set this bit to 1 to force the throttling. 0 = the throttling (at a duty cycle specified in prochot_dty) does not start immediately and does generate an smi#. 1 = the throttling (at a duty cycle specified in prochot_dty) starts immediately and does not generate an smi#. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1061 intel ? ep80579 integrated processor 07 : 05 prochot_dty this write-once 3-bit field determines the duty cycle of the throttling when the force_thtl bit is set. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted while in the thermal throttle mode. the stpclk# throttle period is 1024 pciclks. throttling only occurs if the system is in the c0 state. if in the c2 state, no throttling occurs. once the prochot_dty field is written, subsequent writes have no effect until pltrst# goes active. 000h rw table 27-15. offset 10h: proc_cnt - processor control register (sheet 2 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 10h 10h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access prochot_ dty bits[2:0] throttle mode pci clocks 000 default (will be 50%) 512 001 87.5% 896 010 75.0% 768 011 62.5% 640 100 50% 512 101 37.5% 384 110 25% 256 111 12.5% 128
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1062 order number: 320066-003us 04 tht_en when this bit is set and the system is in a c0 state, it enables a software controlled stpclk# throttling. the duty cycle is selected in the thtl_dty field. 0 = disable 1 = enable 0h rw 03 : 01 thtl_dty this 3 ?bit field determines the duty cycle of the throttling when the tht_en bit is set. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted (low) while in the throttle mode. the stpclk# throttle period is 1024 pciclks. 000h rw 00 reserved reserved 0h table 27-15. offset 10h: proc_cnt - processor control register (sheet 3 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 10h 10h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access prochot_ dty bits[3:0] throttle mode pci clocks (stpclk# low) 000 default (will be 50%) 512 001 87.75% 896 010 75% 768 011 62.5% 640 100 50% 512 101 37.5% 384 110 25% 256 111 12.5% 128
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1063 intel ? ep80579 integrated processor 27.3.3.6 offset 14h: lv2 - level 2 register reads to this register return all zeros, writes to this register have no effect. reads to this register generate a ?enter a level 2 power state? (c2) to the clock control logic. this will cause the stpclk# signal to go active, and stay active until a break event occurs. throttling (due to thtl_en or force_thtl) will be ignored. note: this register must not be used by systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/ processors are ready for the c2 state wh en the read to this register occurs. 27.3.3.7 offset 28h: gpe0_sts - general purpose event 0 status register note: this register is symmetrical to the general purpose event 0 enable register. unless indicated otherwise below, if the corresponding _en bit is set, then when the sts bit is set, a wake event is generated. once back in an s0 state (or if already in an s0 state when the event occurs), cmi will also generate an sci if the scien (pmbase + 04h, bit 0) bit is set, or an smi# if the scien bit is not set. bits 31:16 are reset by a cf9h write; bits 15:0 are not be reset by cf9 write. bits 31:0 are reset by rsmrst#. table 27-16. offset 14h: lv2 - level 2 register description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 14h 14h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 7 :0 lv2reg see description above 00h ro table 27-17. offset 28h: gpe0_sts - general purpose event 0 status register (sheet 1 of 4) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 28h 28h size: 32 bit default: 00000000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 31 : 16 gpin_sts 0 = software clears this bit by writing a 1 to it. 1 = these bits are set any time the corresponding gpio is set up as an input and the corresponding gpio signal is high (or low if the corresponding gp_inv bit is set). if the corresponding enable bit is set in the gpe0_en register, then when the gpi[n]_sts bit is set: ? if the system is in an s1, s3, s4 or s5 state, the event will also wake the system. ? if the system is in an s0 state (or upon waking back to an s0 state), an sci will be caused, depending on the gpi_rout bits for the corresponding gpi. 0h rwc 15 reserved reserved 0h 14 reserved reserved. 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1064 order number: 320066-003us 13 pme_b0_sts note: this bit will be set to 1 when any internal device with pci power management capabilities on bus 0 asserts the equivalent of the pme# signal. additionally, if the pme_b0_en bit is set, and the system is in an s0 state, then the setting of the pme_b0_sts bit will generate an sci (or smi# if sci_en is not set). if the pme_b0_sts bit is set, and the system is in an s1/s3/s4 state (or s5 state due to slp_typ and slp_en), then the setting of the pme_b0_sts bit will generate a wake event, and an sci (or smi# if sci_en is not set) will be generated. if the system is in an s5 state due to power button override, then the pme_b0_sts bit will not cause a wake event or sci. the default for this bit is 0. writing a 1 to this bit position clears this bit 0h rwc 12 reserved reserved 0h 11 pme_sts this bit will be set to 1 by hardware when the pme# signal goes active. [note cmi might be the cause of pme# going active in some cases]. additionally, if the pme_en bit is set, and system is in an s0 state, then the setting of the pme_sts bit will generate an sci (or smi# if sci_en is not set). if the pme_en bit is set, and the system is in an s1/s3/s4 state (or s5 state due to slp_typ and slp_en), then the setting of the pme_sts bit will generate a wake event, and an sci (or smi# if smi_en is not set) will be generated. if the system is in an s5 state due to power button override, then pme_sts will not cause a wake event or sci. this bit is cleared by writing a 1 to this bit position. 0h rwc 10 reserved reserved 0h table 27-17. offset 28h: gpe0_sts - general purpose event 0 status register (sheet 2 of 4) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 28h 28h size: 32 bit default: 00000000h power well: resume bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1065 intel ? ep80579 integrated processor 09 pci_exp_sts 0 = software clears this bit by writing a 1 to it. 1 = set to 1 by hardware to indicate that: ? the pme event message was received on one or more of the pci express* ports ? an assert pmegpe message received from the imch via nsi notes: 1. software attempts to clear this bit by writing a 1 to this bit position. if the pci_exp_sts bit went active due to an assert pmegpe message, then a deassert pmegpe message must be received prior to the software write in order for the bit to be cleared. 2. if the bit is not cleared and the corresponding pci_exp_en bit is set, the level-triggered sci will remain active. 3. a race condition exists where the pci express* device sends another pme message because the pci express* device was not serviced within the time when it must resend the message. this may result in a spurious interrupt, and this is comprehended and approved by the pci express* specification . the window for this race condition is approximately 95-105 ms. 0h rwc 08 ri_sts 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the ri# input signal goes active. the value of this bit is maintained through a g3 state. 0h rwc 07 smb_wak_sts 0 = wake event not caused by the smbus logic. 1 = set by hardware to indicate that the wake event was caused by the smbus logic. note: 1. if smb_wak_sts is set due to smbus slave receiving a message, it will be cleared by internal logic when cputhrmtrip event happens or by a power button override event. however, cputhrmtrip or power button override event will not clear smb_wak_sts if it was set due to smbalert# signal going active. 2. the smbus controller will independently cause an smi# so this bit does not need to do so (unlike the other bits in this register). 3. this bit is set by the smbus slave command 01h (wake/smi#) even when the system is in the s0 state. therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the wake/smi# command or just prior to entering the sleep state. 4. the smbalert_sts bit (d31:f3:i/o offset 00h:bit 5) must be cleared by software before clearing this bit. 0h rwc table 27-17. offset 28h: gpe0_sts - general purpose event 0 status register (sheet 3 of 4) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 28h 28h size: 32 bit default: 00000000h power well: resume bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1066 order number: 320066-003us 27.3.3.8 offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register note: this register is symmetrical to the general purpose event 0 status register. all the bits in this register must be cleared to 0 based on a power button override-cpu thermal trip event, or internal thermal sensor catastrophic condition. unless otherwise noted, all bits are in the resume well. the resume well bits are all cleared by rsmrst# and rtc well bits are cleared by rtest#. 06 tcosci_sts 0 = tco logic did not cause sci. 1 = set by hardware when the tco logic causes an sci. this bit can be reset by writing a one to this bit position. 0h rwc 05 reserved reserved 0h 04 reserved reserved 0h 03 usb1_sts 0 = usb uhci controller 1 does not need to cause a wake. 1 = set by hardware when usb uhci controller 1 needs to cause a wake. wake event will be generated if the corresponding usb1_en bit is set. this bit is only set by hardware and can be reset by writing a one to this bit position or a resume-well reset. note: there is no support for wake from usb when in s3/s4/s5. 0h rwc 02 reserved reserved. 0h 01 reserved reserved 0h 00 prochot_sts 0 = prochot# signal not driven active as defined by the prochot_pol bit 1 = set by hardware anytime the prochot# signal is driven active as defined by the prochot_pol bit. additionally, if the prochot_en bit is set, then the setting of the prochot_sts bit will also generate a power management event (sci or smi#). this bit is cleared by s/w writing a one to this bit position or a resume-well reset. 0h rwc table 27-17. offset 28h: gpe0_sts - general purpose event 0 status register (sheet 4 of 4) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 28h 28h size: 32 bit default: 00000000h power well: resume bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1067 intel ? ep80579 integrated processor table 27-18. offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register (sheet 1 of 2) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 2ch 2ch size: 32 bit default: 00000000h power well: resume a bit range bit acronym bit description sticky bit reset value bit access 31 : 16 gpin_en these bits enable the corresponding gpi[n]_sts bits being set to cause an sci and/or wake event. these bits are cleared by rsmrst#. note: mapping is as follows: bit 31 corresponds to gpi[15]... and bit 16 corresponds to gpi:[0]. 0h rw 15 reserved reserved 0h 14 reserved reserved 0h 13 pme_b0_en 0 = disable 1 = enables the setting of the pme_b0_sts bit to generate a wake event and/or an sci or smi#. pme_b0_sts can be a wake event from the s1/s3/ s4 state, or from s5 (if entered via slp_typ and slp_en) or power failure, but not power button override. this bit defaults to 0. note: it is only cleared by software or rtest#. it is not cleared by cf9h writes. this bit is in the rtc well. 0h rw 12 reserved reserved 0h 11 pme_en 0 = disable. 1 = enables the setting of the pme_sts to generate a wake event and/or an sci. pme# can be a wake event from the s1/s3/s4 state or from s5 (if entered via slp_en, but not power button override). this bit is only cleared by software or rtest#. it is not cleared by cf9h writes. this bit is in the rtc well. 0h rw 10 reserved reserved 0h 09 pci_exp_en 0 = disable sci generation upon pci_exp_sts bit being set. 1 = enables an sci when pci_exp_sts bit is set. this is used to allow the pci express ports, including the link to the imch, to cause an sci due to wake/pme events. 0h rw 08 ri_en when ri_en and ri_sts are both set, a wake event will occur. if ri_en is not set, then when ri_sts is set, no wake event will occur. 0 = disable. 1 = enables the setting of the ri_sts to generate a wake event. this bit is only cleared by software or rtest#. this bit is in the rtc well. 0h rw 07 reserved reserved 0h 06 tcosci_en when tcosci_en and tcosci_sts are both set, an sci will be generated. 0 = disable. 1 = enables the setting of the tcosci_sts to generate an sci. this bit is in the resume well. this bit is only cleared by software or rsmrst#. it is not cleared by cf9h writes. 0h rw 05 reserved reserved 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1068 order number: 320066-003us 27.3.3.9 offset 30h: smi_en - smi control and enable register note: this register is symmetrical to the smi status register. 04 reserved reserved 0h 03 usb1_en 0 = disable. 1 = enables the setting of the usb1_sts to generate a wake event. the usb1_sts bit is set anytime usb controller 1 signals a wake event. break events are handled via the usb interrupt. note: there is no support for wake from usb when in s3/s4/s5. 0h rw 02 prochot_pol this bit controls the polarity of the prochot# pin needed to set the prochot_sts bit. 0 = low value on the prochot# signal will set the prochot_sts bit. 1 = high value on the prochot# signal will set the prochot_sts bit. 0h rw 01 reserved reserved 0h 00 prochot_en 0 = disable. 1 = active assertion of the prochot# signal (as defined by the prochot_pol bit) will set the prochot_sts bit and generate a power management event (sci or smi). 0h rw a. bits 0-7: resume; bits 8, 10-11, 13: rtc; bits 9, 12, 16-31: resume table 27-19. offset 30h: smi_en - smi control and enable register (sheet 1 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 30h 30h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 19 reserved reserved 0h 18 intel_ usb2_en 0 = disables intel-specific usb 2.0 smi logic. 1 = enables intel-specific usb 2.0 smi logic to cause smi#. 0h rw 17 legacy_ usb2_en 0 = disable 1 = enables legacy usb 2.0 logic to cause smi#. 0h rw 16 : 15 reserved reserved 0h table 27-18. offset 2ch: pmbase_gpe0_en - general purpose event 0 enables register (sheet 2 of 2) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 2ch 2ch size: 32 bit default: 00000000h power well: resume a bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1069 intel ? ep80579 integrated processor 14 periodic_ en 0 = disable 1 = enables an smi# to be generated when the periodic_sts bit (pmbase + 34h, bit 14) is set in the smi_sts register (pmbase + 34h). 0h rw 13 tco_en 0 = disables tco logic generating an smi#. 1 = enables the tco logic to generate smi#. see chapter 32.0, ?high precision event timers? for more details on tco functions. if the nmi2smi_en bit is set, then smis that are caused by nmis (i.e., rerouted) will not be gated by the tco_en bit. even if the tco_en bit is 0, the nmis will still be routed to cause the smi#. note: this bit can not be written once the tco_lock bit (at offset 08h of tco i/o space) is set. this prevents unauthorized software from disabling the generation of tco-based smis. 0h rw 12 reserved reserved 0h 11 mcsmi_en 0 = disable. 1 = enables iich to trap accesses to the microcontroller range (62h or 66h) and generate an smi#. note that ?trapped? cycles will be claimed by the iich on pci, but not forwarded to lpc. 0h rw 10 : 08 reserved reserved 0h 07 bios_rls 0 = this bit will always return 0 on reads. writes of 0 to this bit have no effect. 1 = enables the generation of an sci interrupt for acpi software when a one is written to this bit position by bios software. note: gbl_sts being set will cause an sci, even if the sci_en bit is not set. software must take great care not to set the bios_rls bit (which causes gbl_sts to be set) if the sci handler is not in place. 0h wo 06 swsmi_ tmr_en 0 = disable. clearing the swsmi_tmr_en bit before the timer expires will reset the timer and the smi# will not be generated. 1 = starts software smi# timer. when the swsmi timer expires (the timeout period depends upon the swsmi_rate_sel bit setting), swsmi_tmr_sts is set and an smi# is generated. swsmi_tmr_en stays set until cleared by software. 0h rw 05 apmc_en 0 = writes to the apm_cnt register will not cause an smi#. 1 = enables writes to the apm_cnt register to cause an smi# 0h rw table 27-19. offset 30h: smi_en - smi control and enable register (sheet 2 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 30h 30h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1070 order number: 320066-003us 27.3.3.10 offset 34h: smi_sts - smi status register note: if the corresponding _en bit is set when the _sts bit is set, cmi will cause an smi# (except bits 8-10, which do not cause smi#.) 04 smi_on_ slp_en 0 = disables the generation of smi# on slp_en. note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the slp_en bit. 1 = a write of 1 to the slp_en bit (bit 13 in pm1_cnt register) will generate an smi#, and the system will not transition to the sleep state based on that write to the slp_en bit. this allows the smi# handle r work around chip-level bugs. it is expected that the smi# handler will turn off the smi_on_slp_en bit before actually setting the slp_en bit. 0h rw 03 legacy_ usb_en 0 = disables legacy usb circuit 1 = enables legacy usb circuit to cause smi#. 0h rw 02 bios_en 0 = disables the generation of smi# when acpi software writes a 1 to the gbl_rls bit. 1 = enables the generation of smi# when acpi software writes a 1 to the gbl_rls bit. 0h rw 01 eos end of smi. this bit controls the arbitration of the smi signal to the processor. this bit must be set in order to assert smi# low to the processor after smi# has been asserted previously. 0 = once smi# low is asserted, the eos bit is automatically cleared. 1 = in the smi handler, the processor must clear all pending smis (by servicing them and then clearing their respective status bits), set the eos bit, and exit smm. this will allow the smi arbiter to reassert smi upon detection of an smi event and the setting of a smi status bit. the smi# signal will go inactive for 4 pci clocks. 0h rw 00 gbl_smi_en 0 = no smi# will be generated. 1 = enables the generation of smis in the system upon any enabled smi event. this bit is reset by a pci reset event. note: when the smi_lock bit is set, this bit cannot be changed. 0h rw table 27-19. offset 30h: smi_en - smi control and enable register (sheet 3 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 30h 30h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1071 intel ? ep80579 integrated processor table 27-20. offset 34h: smi_sts - smi status register (sheet 1 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 34h 34h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 27 reserved reserved 0h 26 spi_smi_sts this bit will be set when the spi logic is requesting an smi#. 0ro 25 : 21 reserved reserved 0h 20 reserved reserved. 0h 19 reserved reserved 0h 18 intel_ usb2_sts this non-sticky read-only bit is a logical or of each of the smi status bits in the intel-specific usb 2.0 smi status register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. 0h ro 17 legacy_ usb2_sts this non-sticky read-only bit is a logical or of each of the smi status bits in the usb 2.0 legacy support register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. 0h ro 16 smbus_ smi_sts this bit is set to 1 to indicate that the smi# was caused by: a. the smbus slave receiving a message that an smi# must be caused. b. the smbalert# signal goes active and the smb_smi_en bit is set and the smbalert_dis bit is cleared. c. the smbus slave receiving a host_notify message and the host_notify_intren and the smb_smi_en bits are set. d. the smbus slave receiving a ?smi in s0? message. this bit is sticky. it is cleared by writing a 1 to this bit position. note: this bit is set from the 64 khz clock domain used by the smbus. software must wait at least 15.63 s (= 1/64 khz) after the initial assertion of this bit before clearing it. 0h rwc 15 serirq_ smi_sts 0 = smi# not caused by serirq decoder. 1 = indicates the smi# was caused by the serirq decoder. note: this bit is not sticky. writes to this bit will have no effect. 0h ro 14 periodic_sts this bit will be set at the rate determined by the per_smi_sel bits. if the periodic_en bit is also set, an smi# is generated. this bit is cleared by writing a 1 to this bit position. 0h rwc 13 tco_sts 0 = smi not caused by tco logic. 1 = indicates smi was caused by the tco logic. the reset value of this bit may be overwritten soon after reset by the tco counter. hence, it is possible that a read to this register after reset will yield a 1 in this field. note: will not cause wake event. this bit is cleared by writing a 1 to this bit position. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1072 order number: 320066-003us 12 devmon_sts this read-only bit is set when bit 0 in the devtrap_sts register is set. it is not sticky, so writes to this bit will have no effect. see section 27.3.1.3 .] 0h ro 11 mcsmi_sts 0 = indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = set if there has been an access to the power management microcontroller range (62h or 66h) and the microcontroller decode enable #1 bit in the lpc bridge i/o enables configuration register is 1. note that this implementation assumes that the microcontroller is on lpc, if this changes in the future (i.e. pci e-based sio), then the implementation will need to remove the lpc decode enable dependency. if this bit is set, and the mcsmi_en bit is also set, cmi will generate an smi#. this bit is set by hardware and cleared by software writing a 1 to its bit position. 0h rwc 10 gpe1_sts this bit is a logical or of the bits in the alt_gpi_smi_sts register that are also set up to cause an smi# (as indicated by the gpi_rout registers) and have the corresponding bit set in the alt_gpi_smi_en register. 0 = smi# was not generated by a gpi assertion. 1 = smi# was generated by a gpi assertion. bits that are not routed to cause an smi# will have no effect on this bit. this bit is not sticky. writes to this bit will have no effect. 0h ro 09 gpe0_sts this bit is a logical or of bits 13, 11, 8:6, 4:3 and 0 in the gpe0_sts register (pmbase + 28h) that also have the corresponding bit set in the gpe0_en register (pmbase + 2ch). this bit is not sticky. 0 = smi# was not generated by a gpe0 event. 1 = smi# was generated by a gpe0 event. note: writes to this bit will have no effect. the setting of this bit does not cause the smi# note: bits 31:16 of the gpe0_sts register are not capable of generating smis; therefore, they do not set this smi status bit. 0h ro 08 pm1_sts_reg this is an or of the bits (except for bits 5 and 4) in the acpi pm1 status reg. (offset pmbase+00h). not sticky. writes to this bit have no effect. 0 = smi# was not generated by a pm1_sts event. 1 = smi# was generated by a pm1_sts event. this bit gets set when pm1_sts.tmrof_sts gets set. hence, it is highly likely that a read to this register after reset will yield a 1 in this field. note: the setting of this bit does not cause the smi#. 0h ro 07 reserved reserved. 0h 06 swsmi_ tmr_sts 0 = software smi# timer has not expired. 1 = set by the hardware when the software smi# timer expires. this bit will remain 1 until the software writes a 1 to this bit. 0h rwc table 27-20. offset 34h: smi_sts - sm i status register (sheet 2 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 34h 34h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1073 intel ? ep80579 integrated processor 27.3.3.11 offset 38h: alt_gpi_smi_en - alternate gpi smi enable register 05 apm_sts smi# was generated by a write access to the apm control register and if the apmc_en bit is set. 0 = no smi# generated by write access to apm control register with apmch_en bit set. 1 = smi# was generated by a write access to the apm control register with the apmc_en bit set. this bit is cleared by writing a one to its bit position. 0h rwc 04 smi_on_ slp_en_sts this bit will be set when a write access attempts to set the slp_en bit. 0 = no smi# caused by write of 1 to slp_en bit when slp_smi_en bit is also set. 1 = indicates an smi# was caused by a write of 1 to slp_en bit when slp_smi_en bit is also set. this bit is cleared by writing a 1 to this bit position. 0h rwc 03 legacy_ usb_sts this non-sticky read-only bit is a logical or of each of the smi status bits in the usb legacy keybd register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. 0 = smi# was not generated by usb legacy event. 1 = smi# was generated by usb legacy event. 0h ro 02 bios_sts 0 = no smi# generated due to acpi software requesting attention. 1 = smi# was generated due to acpi software requesting attention (writing a 1 to the gbl_rls bit with the bios_en bit set). 0h rwc 01 : 00 reserved reserved 0h table 27-21. offset 38h: alt_gpi_smi_en - alternate gpi smi enable register description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 38h 38h size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 00 alt_gpi_ smi_en these bits are used to enable the corresponding gpio to cause an smi#. in order for these bits to have any effect, the following must be true. 1. the corresponding bit in the alt_gpi_smi_en register is set. 2. the corresponding gpi must be routed in the gpi_rout register to cause an smi. 3. the corresponding gpio must be implemented. all bits are in the resume well. 0000h rw table 27-20. offset 34h: smi_sts - smi status register (sheet 3 of 3) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 34h 34h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1074 order number: 320066-003us 27.3.3.12 offset 3ah: alt_gpi_smi_sts - alternate gpi smi status register 27.3.3.13 offset 44h: devtrap_sts - devtrap_sts register each bit indicates if an access has occurred to the corresponding devices trap range, or for bits 6:9 if the corresponding pci interrupt is active. write 1 to the same bit position to clear it. this register is used by apm power management software to see if there has been system activity. the periodic smi# timer indicates if it is the right time to read the devtrap_sts register (pmbase + 44h). table 27-22. offset 3ah: alt_gpi_smi_sts - alternate gpi smi status register description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 3ah 3ah size: 16 bit default: 0000h power well: resume bit range bit acronym bit description sticky bit reset value bit access 15 : 00 alt_gpi_ smi_sts these bits report the status of the corresponding gpis. 1 = active, -0 = inactive. these bits are sticky. if the following conditions are true, then an smi# will be generated and the alt_gpi_smi_sts bit set: 1. the corresponding bit in the alt_gpi_smi_en register is set 2. the corresponding gpi must be routed in the gpi_rout register to cause an smi. 3. the corresponding gpio must be implemented. all bits are in the resume well. default for these bits are dependent on the state of the gpi pins. 0000h rwc table 27-23. offset 44h: devtrap_sts - devtrap_sts register (sheet 1 of 2) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 44h 44h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 13 reserved reserved 0h 12 d12_trp_sts kbc (60/64h): 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 0h rwc 11 : 10 reserved reserved 0h 09 d9_trp_sts pirq[d or h]: 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 0h rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1075 intel ? ep80579 integrated processor 08 d8_trp_sts pirq[c or g]: 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 0h rwc 07 d7_trp_sts pirq[b or f]: 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 0h rwc 06 d6_trp_sts pirq[a or e]: this bit will be set if pci irq a or pci irq e goes active (by the pin or internal signal). 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 0h rwc 05 : 00 reserved reserved 0h table 27-23. offset 44h: devtrap_sts - devtrap_sts register (sheet 2 of 2) description: view: pci bar: pmbase (io) bus:device:function: 0:31:0 offset start: offset end: 44h 44h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1076 order number: 320066-003us 27.4 smi#/sci generation upon any smi# event taking place, iich will assert smi# to the processor, which will cause it to enter smm space. smi# remains active until the eos bit is set. when the eos bit is set, smi# will go inactive for a minimum of 4 pciclk. if another smi event occurs, smi# will be driven active again. the sci is a level-mode interrupt that is typically handled by an acpi-aware operating system. in non-apic systems (which is the default), the sci irq is routed to one of the 8259 interrupts (irq9, 10, or 11). the 8259 interrupt controller must be programmed to level mode for that interrupt. in systems using the apic, the sci can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. the interrupt polarity changes depending on whether it is on an interrupt shareable with a pirq or not; see section 27.3.1 for details. the interrupt will remain asserted until all sci sources are removed. ta b l e 2 7 - 2 4 shows which events can cause an sci and ta b l e 2 7 - 2 6 shows the causes of an smi#. note: some events can be programmed to cause either an smi# or sci. the usage of the event for sci (instead of smi#) is typically associated with an acpi-based system. note: there are various sources that cause the tco sci, shown in ta b l e 2 7 - 2 5 . table 27-24. causes of sci cause additional enables (see note 1) where reported pme# pme_en = 1 pme_sts internal ehci wake (pme_b0) pme_b0_en = 1 pme_b0_sts power button press pwrbtn_en = 1 pwrbtn_sts rtc alarm rtc_en = 1 rtc_sts ring indicate ri_en = 1 ri_sts usb #1 wakes usb1_en = 1 usb1_sts prochot# pin active acpi timer overflow (2.34 seconds) tmrof_en = 1 tmrof_sts any gpi gpi[x]_route = 10, gpe0[x]_en = 1 gpe0[x]_sts tco sci logic (see table 27-25 ) tcosci_en = 1 tcosci_sts bios_rls written to 1 gbl_en = 1 gbl_sts notes: causes of sci: 1. sci_en must be 1 to enable sci 2. sci can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in apic mode) table 27-25. causes of tco sci cause additional enables where reported message from imch none imchsci_sts
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1077 intel ? ep80579 integrated processor table 27-26. causes of smi# (sheet 1 of 2) cause additional enables where reported synch pme# sci_en = 0, pme_en = 1 pme_sts internal ehci wake (pme_b0) sci_en = 0, pme_b0_en = 1 pme_b0_sts power button press sci_en = 0, pwrbtn_en = 1 pwrbtn_sts rtc alarm sci_en = 0, rtc_en = 1 rtc_sts ring indicate sci_en = 0, ri_en = 1 ri_sts usb #1 wakes sci_en = 0, usb1_en = 1 usb1_sts prochot# pin active sci_en = 0 acpi timer overflow (2.34 seconds) sci_en = 0, tmrof_en = 1 tmrof_sts any gpi gpi[x]_route = 01, alt_gpi_smi[x]_en = 1 gpe1_sts, alt_gpi_smi[x]_sts tco smi logic tco_en = 1 tco_sts nmi i (and nmis mapped to smi) see nmi section for causes. nmi2smi_en = 1 tco_sts, nmi2smi_sts gbl_rls written to 1 bios_en = 1 bios_sts x write to b2h register apmc_en apm_sts x periodic timer expires periodic_en = 1 periodic_sts 64 ms timer expires swsmi_tmr_en = 1 swsmi_tmr_sts internal thermal throttle internal_tt_sts monitor status monitor_sts x enhanced usb legacy support event legacy_usb2_en = 1 legacy_usb2_sts enhanced usb intel-specific event intel_usb2_en = 1 intel_usb2_sts classic usb legacy logic (port 64/ 60 rd/wr, end of pass-through) legacy_usb_en = 1 legacy_usb_sts x classic usb legacy logic (irq) legacy_usb_en = 1 legacy_usb_sts serial irq smi reported none serirq_smi_sts device monitors (d15:d0)matches an address in its range see trap section 18.2.2.1 . devmon_sts, x smbus host controller smb_smi_en, host controller enabled various bits in the smbus host status register smbus slave smi message none smbus_smi_sts smbus smbalert# signal active none smbus_smi_sts smbus host notify message received host_notify_intren smbus_smi_sts, host_notify_sts
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1078 order number: 320066-003us see chapter 32.0, ?high precision event timers? for details on the tco smi# causes. 27.4.0.1 pci express* sci pci express* ports and the imch (via nsi ) have the ability to cause pme using messages. when a pme message is received, the pci_exp_sts bit is set. if the pci_exp_en bit is also set, cmi can cause an sci via the gpe1_sts register. access to microcontroller range (62h/66h) mcsmi_en mcsmi_sts x slp_en bit written to 1 smi_on_slp_en = 1 smi_on_slp_en_sts x notes: causes of smi#: 1. gbl_smi_en must be 1 to enable smi 2. eos must be written to 1 to reenable smi for the next one 3. some smi#s are considered ?synchronous?, in that the processor must recognize the smi# prior to completing the instruction (i/o read, i/o write, me mory read, or memory write) that must cause the smi#. this is accomplished by having the smi# signal go active to the processor prior to the processor observing the rdy# signal that terminates the cycle. smi#s marked with x in the synch column are treated as synchronous. 4. nmi2smi_sts isn?t gated by tco_en. 5. an smi# must be fully enabled when cmi is also enabled to trap cycles. if smi# is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. [note: added as per sun# 47], part 3. table 27-27. causes of tco smi# cause additional enables where reported year 2000 rollover none newcentury_sts tco timerout none timeout os writes to tco_dat_in register none os_tco_smi nmi occurred (and nmis mapped to smi) nmi2smi_en = 1 nmi2smi_sts note: nmi2smi_sts isn?t gated by tco_en. intruder# signal goes active intrd_sel = 10 intrd_det changes of the bioswp bit from 0 to 1 bld = 1 bioswr_sts message from imch imchsmi_sts write attempted to bios bioswp = 1 bioswr_sts table 27-26. causes of smi# (sheet 2 of 2) cause additional enables where reported synch
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1079 intel ? ep80579 integrated processor 27.5 dynamic processor clock control 27.5.1 overview cmi has primary control for dynamically starting and stopping system clocks. the clock control is used for the transitions among the various s0/cx states (i.e., ia 32 core throttling). each dynamic clock control method is described in this section. the various sleep states may also perform types of non-dynamic clock control, and are described in section 27.4 . cmi supports the acpi c0, c1 and c2 states the dynamic clock control is handled using the following signals: ? stpclk# - used to halt the ia 32 core instruction stream the c1 state is entered based on the ia 32 core performing an autohalt instruction. the c2 state is entered based on the ia 32 core reading the level 2 register. the c1, and c2 states end due to a break event. based on the break event, cmi returns the system to a c0 state. ta b l e 2 7 - 2 8 lists the possible break events from the c2, states. the pending break event (pbe) indication from the ia 32 core is supported using the ferr# signal. the following rules apply: 1. when stpclk# is detected active by the ia 32 core, the ferr# signal from the ia 32 core will be redefined to indicate whether an interrupt is pending. the signal is active low (i.e., ferr# will be low to indicate a pending interrupt). 2. when the stpclk# asserts, it will latch the current state of the ferr# signal and continue to present this state to the ferr# state machine (independent of what the ferr# pin does after the latching). 3. when the stop-grant cycle is detected, it will start looking at the ferr# signal as a break event indication. if ferr# is sample d low, a break event is indicated. this will force a transition to the c0 state. 4. when the ia 32 core detects the deassertion of stpclk#, the ia 32 core will start driving the ferr# signal with the natural value (i.e., the value it would do if the pin table 27-28. break events event breaks from comment any unmasked interrupt goes active c2 irq[0:15] when using the 8259s, irq[0:23] for i/o (x) apic. since sci is an interrupt, any sci will also be a break event. any internal event that will cause an nmi or smi# c2 many possible sources any internal event that will cause init# to go active c2 could be indicated by the keyboard controller via the rcin input signal. rtc interrupt pending c2 only available if the rtc interrupt (irq8) is enabled as a break event (see rtc interrupt break enable bit in section 29.3.1.1 ). cpu pending break event indication c2 only available if ferr# is enabled for break event indication (see ferr# mux enable bit in section 29.3.1.1 ) req-c0 message from imch c2 can be sent at any time after the ack-c2 message and before the ack-c0 message (i.e., any time not in c0 state).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1080 order number: 320066-003us was not muxed). the time from stpclk# inactive to the ferr# signal transitioning back to the native function must be less than 120 ns. 5. at least 180 ns passes after deasserting stpclk# and then starts using the ferr# signal for an indication of a floating point error. the maximum time that may pass is bounded such that it must have a chance to look at the ferr# signal before reasserting stpclk#. based on current implementation, that maximum time would be 240 ns (8 pci clocks). since the ia 32 core has 120 ns to revert to the proper ferr# function, there are 60 ns of margin inherent in the timings. the break event associated with this mechanism does not need to set any particular status bit, since the pending interrupt will be serviced by the processor after returning to the c0 state. 27.5.2 transition rules among s0/cx and sx states the following priority rules and assumptions apply among the various s0/cx and throttling states: ? entry to any s0/cx state is mutually exclusive with entry to s1, s3, s4 or s5 state. this is because the processor can only perform one register access at a time and sleep states have higher priority than thermal throttling. ? ..when the slp_en bit is set (system going to a s1, s3, s4 or s5 sleep state), the thtl_en and force_thtl bits can be internally treated as being disabled (no throttling while going to sleep state). ? if the thtl_en or force_thtl bits are se t, and a level 2 read then occurs, the system must immediately go and stay in a c2 state until a break event occurs. a level 2 read has higher priority than the software initiated throttling. ? after an exit from a c2 state (due to a break event), and if the thtl_en or force_thtl bits are still set, the system will continue to throttle stpclk#. the first transition on stpclk# active can be delayed by up to one prochot period (1024 pci clocks = 30.72 s), depending on the time of the break event. ? the imch (or equivalent) must post stop-grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to cmi observing the stop-grant cycle. this ensures that the stpclk# signal stays active for a sufficient period after the processor observes the response phase. ? if in the c1 state and the stpclk# signal goes active, the processor will generate a stop-grant cycle, and the system must go to the c2-like state. when stpclk# goes inactive, it must return to the c1 state.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1081 intel ? ep80579 integrated processor 27.5.3 s0/c0, s0/c2, entry/exit timings and sequences the timings associated with the c0-c2-c0, sequences are shown in the following figures and tables. 27.5.3.1 c0 c2 c0 timings and diagram note: in figure 27-1 , the m-i link must be labeled as ?nsi? and the ?sg? message on nsi must be ?req-c2? figure 27-1. c0 c2 c0 entry/exit timings stpclk# s0/c0 state s0/c2 state cpu fsb s0/c0 state m-i link break event t4a t5 cpu i/f signals unlatched t1 latched unlatched t6 t2a sg t2b sg go- c2 ack- c2 t3a t3b go- c0 ack- c0 t4b stpclk# s0/c0 state s0/c2 state cpu fsb s0/c0 state m-i link break event t4a t5 cpu i/f signals unlatched t1 latched unlatched t6 t2a sg t2b sg go- c2 ack- c2 t3a t3b go- c0 ack- c0 t4b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1082 order number: 320066-003us 27.5.3.2 c0 c2 entry sequence the processor goes from a c0 to a c2 state because all of the threads in the processor are idle and have nothing to do. the decision to go to the c2 state is made by software. the following timings are shown in figure 27-1 . 1. the processor reads the level 2 register. 2. t1 prior to asserting stpclk#, cmi will latch the processor interface signals, except smi# activation due to a synchronous smi event. changed as per dcn #014, part 3. 3. t2a later, in response to observing stpclk# active, the processor(s) performs one or more stop-grant cycles on the front-side bus. 4. t2b later, imch forwards the last stop-grant cycle to cmi via nsi. this will be called ?req-c2.? 5. the processor is now in c2 state. there are some additional steps below that must complete between the iich and imch to keep them in synchronization. 6. t3a after receiving the stop-grant from the imch, the iich sends a go-c2 message to the imch 7. t3b after receiving the go-c2 message, the imch sends an ack-c2 message. at this point, the imch is permitted to send the req-c0 (break-ind) message. table 27-29. c0 c2 c0 timings sym min max units description t1 0 note 1 cpu interface signals latched prior to stpclk# active. note that this does not apply for synchronous smi's. changed as per dcn #014, part 1. t2a 0 note 2 stpclk# active to stop-grant cycle on processor front-side bus (can wait forever) t2b 0 note 3 stop-grant on fsb to stop-grant on nsi. note: this is according to an imch specification. t3a 0 note 1 stop-grant on nsi to go-c2 message. this must be as short as feasible. t3b 128 note 3 bclk go c-2 message to ack-c2 message. note that this is according to an imch specification and is only required if the imch has the cpulslp# signal. it is needed to enforce the stop-grant to cpuslp# timing requirements. if the imch does not have the cpuslp# signal, then this can be 0. t4a 0 8 pci clk break event to when go_c0 message is ready to be sent. the actual message may be delayed if nsi is busy with other traffic. t4b 0 note 3 go-c0 message to ack-c0 message. note that this is an imch specification. this must be as short as feasible. t5 0 note 1 end of ack_c0 message to stpclk# high t6 8 9 pci clk stpclk# high to processor interface signals unlatched. 1. this value must be small (a few pci clocks). for messages, it may be difficult to determine the maximum time, since power management messages may have to wait for other traffic on nsi. 2. this is a processor specification that is unbounded. 3. this is an imch specification. the maximum is presently not specified. cmi should not be dependent on this specific value.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1083 intel ? ep80579 integrated processor 27.5.3.3 c2 c0 break sequence cmi returns the processor to a c0 state in order to execute code. this is due to a break event. see ta b l e 2 7 - 2 8 for the various break event causes. the following timings are shown in figure 27-1 . 1. a break event is detected 2. t4a later, cmi sends go_c0 message to the imch. 3. t4b after receiving the go-c0 message, then imch sends an ack-c0 to the iich. at this point, the imch is not permitted to send the req-c0 (break ind) message. 4. t5 after receiving the ack-c0 message, cmi deasserts stpclk# to the processor (this enables processor instruction stream) 5. the processor is now back in a c0 state 6. t6 after deasserting stpclk#, cmi unlatches the processor interface signals, except smi#, which was not latched for synchronous smi events. changed as per dcn #014, part 4. 27.6 sleep states 27.6.1 sleep state overview cmi directly supports different sleep states (s1, s3, s4 or s5), which are entered by setting the slp_en bit, or due to a power button press. the entry to the sleep states are based on several assumptions: ? entry to a cx state is mutually exclusive with entry to a sleep state. this is because the processor can only perform one register access at a time. a request to sleep always has higher priority than throttling. ? prior to setting the slp_en bit, the software turns off processor-controlled throttling. thermal throttling cannot be disabled, but setting the slp_en bit disables thermal throttling (since s1, s3, s4 or s5 sleep states have higher priority). ? the g3 state cannot be entered via any software mechanism. the g3 state indicates a complete loss of power. table 27-30 shows the differences in the sleeping states with regard to the listed output signals: 27.6.2 initiating sleep states table 27-30. sleep state output conditions state stpclk# cpuslp# slp_s3# slp_s4# slp_s5# s1 active optionally active inactive inactive inactive s3 active plane off active inactive inactive s4 active plane off active active inactive s5 active plane off active active active
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1084 order number: 320066-003us entry to sleep states (s1, s3, s4 or s5) are initiated by any of the following methods: 1. masking interrupts, turning off all bus master enable bits, setting the desired type in the slp_typ field and setting the slp_en bit. the hardware will then put the system into the corresponding sleep state. 2. pressing the pwrbtn# signal for more than four seconds to cause a power button override event. in this case the transition to the s5 state will be less graceful, since there will be no dependencies on observing stop-grant cycles from the processor or on clocks other than the rtc clock. other assumptions: ? entry to a cx state is mutually exclusive wi th entry to a sleep state. this is because the processor can only perform one register access at a time. a request to sleep always has higher priority than throttling. ? setting the slp_en bit will disable all throttling (since s1, s3, s4 or s5 sleep states have higher priority). ? the g3 state cannot be entered via any software mechanism. the g3 state indicates a complete loss of power. ? before entering sleep state, an acpi os will mask all interrupts and will turn off all bus master enable bits. for non-acpi systems, the bios will mask interrupts and turn off all bus master enable bits. interrupts might not be masked at the i/o subsystem. some operating systems have been observed to only mask interrupts inside the processor. 27.6.3 exiting sleep states sleep states (s1, s3, s4 or s5) are exited based on wake events. the wake events will force the system to a full on state (s0), although some non-critical subsystems might still be shut and have to be brought back manually. for example, the hard disk may be shut during a sleep state, and have to be enabled via an i/o pin before it can be used. note: upon exit from cmi-controlled sleep states, the wak_sts bit will be set. to enable wake events, the possible causes of wake events (and their restrictions) are shown in ta b l e 2 7 - 3 2 . there is no support for wake from usb when in s3/s4/s5. table 27-31. sleep types sleep type comment s1 cmi asserts the stpclk# signal. it also has the option to assert cpuslp# signal. this lowers the processor?s power consumption. no snooping is possible in this state. s3 cmi asserts slp_s3#. the slp_s3# signal controls the power to non-critical circuits. power is only retained to devices needed to wake from this sleeping state, as well as to the memory. s4 cmi asserts slp_s3# and slp_s4#. the slp_s4# signal shuts off the power to the memory subsystem. only devices needed to wake from this state should be powered. s5 the slp_s5# signal shuts off the power to the memory subsystem. only devices needed to wake from this state must be powered. cmi asserts slp_s3#, slp_s4# and slp_s5#.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1085 intel ? ep80579 integrated processor the latency to exit the various sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to cmi are insignificant. 27.6.4 sx-g3-sx, handling power failures in systems, power failures can occur if the ac power is cut (a real power failure) or if the system is unplugged. in either case, pwrok and rsmrst# are assumed to go low. depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure.the after_g3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. if the policy is to not boot, the system remains in an s5 state. there are only three possible events that will wake the system after a power failure. 1. pwrbtn#: pwrbtn# is always enabled as a wake event. when rsmrst# is low (g3 state), the pwrbtn_sts bit is reset. when cmi exits g3 after power returns table 27-32. causes of wake events cause states can wake from: how enabled rtc alarm s1,s3,s4,s5 set rtc_en bit in pm1_en register power button s1,s3,s4,s5 always enabled as wake event gpi[0:15] s1,s3,s4,s5 gpe0_en register (after having gone to s5 via slp_en, but not after a power failure.) gpis that are in the core well are not capable of waking the system from sleep states where the core well is not powered. classic usb s1 set usb1_en bits in gpe0_en register ri s1,s3,s4,s5 set ri_en bit in gpe0_en register primary pme# s1,s3,s4,s5 (note 2) pme_b0_en bit in gpe0_en register secondary pme# (pin) s1,s3,s4,s5 (note 2) pme_en bit in gpe0_en register. smbus alert# signal s1,s3,s4,s5 always enabled as a wake event smbus slave message s1,s3,s4,s5, including s5- power button override three smbus commands always enabled as wake events. these commands (see note 1. below) can wake from s5 due to power button. smbus host notify message received s1,s3,s4,s5 host_notify_wken bit smbus slave command register. reported in the smb_wak_sts bit in gpe0_sts register. notes: 1. if in the s5 state due to a powerbutton override or thrmtrip#, the only wake events are power button, wake smbus slave message (01h), and hard reset smbus slave messages (03h, 04h). 2. pme#, rtc, gpi[0:n], and ri# will be wake events from s5 only if it was entered via software setting the slp_en and slp_typ bits, or if there is a power failure. 3. gbe wake-up capability (wake on lan) is described in section 37.5.10, ?wake on lan? on page 1402 4. there is no support for wake from usb when in s3/s4/s5. table 27-33. gpi wake events gpi power well wake from notes gpi[12, 11, 7:0] core s1 acpi compliant gpi[8] resume s1,s3,s4,s5 acpi compliant
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1086 order number: 320066-003us (rsmrst# goes high), the pwrbtn# signal is already high (because v cc -standby goes high before rsmrst# goes high) and the pwrbtn_sts bit is 0. 2. ri#: ri# does not have an internal pull-up. therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. if this signal goes low (active), when power returns the ri_sts bit is set and the system interprets that as a wake event. 3. rtc alarm: the rtc_en bit is in the rtc well and is preserved after a power loss. like pwrbtn_sts the rtc_sts bit is cleared when rsmrst# goes low. cmi monitors both pwrok and rsmrst# to detect for power failures. if pwrok goes low, the pwrok_flr bit is set. if rsmrst# goes low, pwr_flr is set. software can clear pwr_flr by writing a 1 to that bit although pme_en is in the rtc well, this signal cannot wake the system after a power loss. pme_en is cleared by rtest#, and pme_sts is cleared by rsmrst#. the power failure bit (pwr_flr) is set after any power failure. software can clear it by writing a 1 to that bit. the cpupwr_flr bit separately reports power failures that result in vrmpwrgd going inactive. 27.7 processor thermal management cmi has several mechanisms to assist with managing thermal problems in the system. 27.7.1 prochot# signal for smi# or sci the prochot# signal is used as a status input from a thermal sensor. the sensor could be inside the processor or in a separate component near the processor. cmi follows these behaviors with regard to the prochot# signal: 1. based on the prochot# signal going active, cmi generates an smi# or sci (depending on sci_en). 2. if the prochot_pol bit is set low, when prochot# goes low, the prochot_sts bit will be set. this is an indicator that the thermal threshold has been exceeded. if the prochot_en bit is set, then when prochot_sts goes active, either an smi# or sci# will be generated (depending on the sci_en bit being set). the power management software (bios or acpi) can then take measures to start reducing the temperature. examples include shutting unneeded subsystems, or halting the processor. 3. by setting the prochot_pol bit to high, another smi# or sci# can optionally be generated when the prochot# signal goes back high. this allows the software (bios or acpi) to turn off the cooling methods. table 27-34. transitions due to power failure state at power failure afterg3_en bit transition when power returns s0, s1, s3 1 0 s5 s0 s4 1 0 s4 s0 s5 1 0 s5 s0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1087 intel ? ep80579 integrated processor note: prochot# assertion does not cause a tco event message in s3 or s4. the level of the signal is not reported in the heartbeat message. 27.7.2 processor passive cooling the force_thtl bit allows the bios to force passive cooling independent of the acpi software (which uses the thtl_en and thtl_dty bits). it has the following behavior: 1. if this bit is set, cmi will start throttling using the ratio in the prochot_dty field. 2. if this bit is turned off, (cleared) cmi will stop throttling, unless the thtl_en bit is set (indicating that acpi software is attempting throttling). if both the thtl_en and force_thtl bits are both set, then the iich must use the duty cycle defined by the prochot_dty field, not the thtl_dty field. (i.e., prochot_dty has higher priority). 27.7.3 on-demand passive cooling this is a method to cool the system by throttling the processor. the mode is initiated by software setting the thtl_en or thtl_dty bits. behavioral description: 1. software sets the thtl_dty bits to select throttle ratio and the thtl_en bit to enable the throttling. 2. throttling results in stopclk# active for a minimum time of 12.5% and a maximum of 87.5%. the period is 1024 pci clocks. thus, the stopclk# signal can be active for as little as 128 pci clocks or as much as 896 pci clocks. the actual slowdown (and cooling) of the processor will depend on the instruction stream, because the processor is allowed to finish the current instruction. furthermore, cmi waits for the stop-grant cycle before starting the count of the time the stopclk# signal is active. 3. cmi will perform the go-c2/ack-c2 and go-c0/ack-c0 messages for throttling, just as if it were making transitions to/from a c2 state. 27.7.4 active cooling active cooling involves fans. the gpio signals from cmi can be used to turn on/off a fan. 27.8 event input signals, messages and their usage cmi has various input signals that trigger specific events. this section describes those signals and how they should be used. 27.8.1 pwrbtn# ? power button cmi pwrbtn# signal operates as a ?fixed power button? as described in the acpi specification . pwrbtn# signal has a 16 ms debounce on the input. the state transition descriptions are included in table 27-35 . the transitions start as soon as the pwrbtn# is pressed (but after the debounce logic), and does not depend on when the power button is released. a power button override will force a transition to s5, even if pwrok is not active.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1088 order number: 320066-003us 27.8.1.1 power button override function if pwrbtn# is observed active for at least 4 consecutive seconds, then the state machine must unconditionally transition to the g2/s5 state, regardless of present state (s0 -, s4) even if pwrok is not active. in this case, the transition to the g2/s5 state must not depend on any particular response from the processor (such as a stop-grant cycle), nor any similar dependency from any other subsystem. note: the 4-second pwrbtn# assertion must only be used if a system lock-up has occurred. the 4-second timer starts counting when cmi is in a s0 state. if the pwrbtn# signal is asserted and held active when the system is in a suspend state (s1 , s5), the assertion causes a wake event. once the system has resumed to the s0 state, the 4-second timer starts. the pwrbtn# status is readable to check if the button is currently being pressed or has been released. the status is taken after the debounce, and is readable via the pwrbtn_lvl bit. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled by d31:f0:a4h bit 3), the power button is not a wake event. as a result, it is conceivable that the user will press and continue to hold the power button waiting for the system to awake. since a 4-second press of the power button is already defined as an unconditional power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. once the power-cycle timer has expired, the power button awakes the system. once the minimum slp_s4# power cycle expires, the power button must be pressed for another 4 to 5 seconds to create the override condition to s5. 27.8.1.2 sleep button the advanced configuration and power interface (acpi) specification, rev. 2.0b defines an optional sleep button. it differs from the power button in that it only is a request to go from s0 to s1-s4 (not s5). also, in an s5 state, the power button can wake the system, but the sleep button cannot. although cmi does not include a specific signal designated as a sleep button, one of the gpio signals can be used to create a ?control method? sleep button see the acpi specification for implementation details. table 27-35. transitions due to power button present state event transition/action comment s0/cx pwrbtn# goes low smi# or sci generated (depending on sci_en) software will typically initiate a sleep state. s1-s5 pwrbtn# goes low wake event. transitions to s0 state. standard wakeup note: could be impacted by slp_s4# minimum assertion. g3 pwrbtn# pressed none no effect since no power. not latched nor detected. s0 -s4 pwrbtn# held low for at least 4 consecutive seconds unconditional transition to s5 state. no dependence on processor (such as stop-grant cycles) or any other subsystem.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1089 intel ? ep80579 integrated processor 27.8.2 ri# ? ring indicate signal the ring indicator can cause a wake event (if enabled) from the s1, s3, s4 or s5 states. ta b l e 2 7 - 3 6 shows when the wake event is generated or ignored in different states. if in the g0/s0/cx states, cmi generates an interrupt based on ri# active, and the interrupt will be set up as a break event. note: there is no filtering on the ri# signal. any debounce filtering must be done externally. 27.8.3 pme# ? pci power management event the pme# signal comes from a pci device to request that the system be restarted. the pme# signal can generate an smi, sci, or optionally a wake event. the event occurs when the pme# signal goes from high to low. no event is caused when it goes from low to high. 27.8.4 sys_reset# button when the sys_reset# button is detected as active after the debounce logic (100 ms debounce on the input, same as pwrbtn#), cmi will attempt to perform a ?graceful? reset, by waiting up to 25 ms, +/- 2ms for sm bus to go idle. if sm bus is idle when the button is detected active, the reset will occur immediately, otherwise the counter will start. if at any point during the count sm bus goes idle, the counter will be reset and the full system reset will occur. if, however, the counter expires and sm bus is still active, a full system reset will be forced upon the system even though smbus activity is still occurring. once the reset is asserted, it will remain asserted for approximately 1 ms, regardless of whether the sys_reset# input remains asserted or not. it cannot occur again until sys_reset# has been detected inactive after the debounce logic, and the system is back to a full s0 state with pltrst# inactive. note: if bit 3 of the cf9h i/o register is set then sys_reset# will result in a full power cycle reset. 27.8.5 processor thermal trip if thrmtrip# goes active, the processor is indicating an overheat condition, and will immediately transition to an s5 state. however, since the processor has overheated, it will not respond to the stpclk# pin with a stop grant special cycle. therefore, cmi will not wait for one. immediately upon seeing thrmtrip# low, cmi will initiate a transition to the s5 state, drive signals slp_s3#, slp_s4#, slp_s5# low, and set the cts bit. the transition will generally look like a power button override. when a thrmtrip# event occurs, cmi will power down immediately without following the normal s0 -> s5 path. table 27-36. transitions due to ri# signal present state event ri_en event s0 ri# active x ignored s1, s3, s4, s5 ri# active 0 1 ignored wake event
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1090 order number: 320066-003us if the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the iich, are no longer executing cycles properly. therefore, if thrmtrip# goes active, and iich is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. cmi will follow this flow for thrmtrip#. 1. at boot (pltrst# low), thrmtrip# ignored. 2. after power-up (pltrst# high), if thrmtrip# sampled active, slp_s3#, slp_s4#, and slp_s5# fire, and normal sequence of sleep machine starts. 3. until sleep machine enters the s5 state, slp_s3#, slp_s4#, and slp_s5# stay active, even if thrmtrip# is now inactive. this is the equivalent of ?latching? the thermal trip event. 4. when s5 state reached, go to step #1, otherwise stay here. if cmi never gets to s5, cmi does not reboot until power is cycled. during boot, thrmtrip# is ignored until slp_s3#, pwrok, vrmpwrgd, and pltrst# are all ?1?. during entry into a powered-down state (due to s3,s4, s5 entry, power cycle reset, etc.) thrmtrip# is ignored until either slp_s3# = 0, or pwrok = 0, or vrmpwrgd = 0. note: a processor thermal trip event will 1. set the afterg3_en bit 2. clear the pwrbtn_sts bit 3. clear all the gpe0_en register bits 4. clear the smb_wak_sts bit only if smb_wak_sts was set due to smbus slave receiving message and not set due to smbalert. note: the thrmtrip# pin must be glitch free. 27.8.6 sata sci the sata logic can cause an sci, but not an smi or wake event. when the sata logic causes an sci, the sata_sci_sts bit will be set. the sci handler enables the sci and clears the sci via bits in the sata unit. 27.8.7 pci express* pme event message pci express* ports and the imch have the ability to cause pme using messages. when a pme messages is receive, cmi will set the pci-exp-sts bit.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1091 intel ? ep80579 integrated processor 27.9 alternate (alt) access mode before entering a low power state, several registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as registers have read and write paths. however, several of the isa (legacy) compatible registers are either read-only or write-only. to get data out of write-only registers, and to restore data into read-only registers, the iich implements an alternate access mode. if the alt access mode is entered and exited after reading the registers of iich timer (8254), the timer starts counting faster (13.5 ms). the following steps listed below can cause problems: 1. bios enters alt access mode for reading the iich timer related registers. 2. bios exits alt access mode. 3. bios continues through the executio n of other needed steps and passes control to the operating system. after getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. for example dos and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. operating systems (e.g., microsoft windows* 98, windows* 2000, and windows nt*) reprogram the system timer and therefore do not encounter this problem. for some other loss (e.g., microsoft ms-dos*) the bios must restore the timer back to 54.6 ms before passing control to the operating system. if the bios is entering alt access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from alt access mode . 27.9.1 write only registers with read paths in alternate access mode the registers described in ta b l e 2 7 - 3 7 have read paths in alternate access mode. the access number field in the table indicates which register will be returned per access to that port.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1092 order number: 320066-003us table 27-37. write-only registers with read paths in alternate access mode (sheet 1 of 2) restore data restore data i/o addr # of reads access data i/o addr # of reads access data 00h 2 1 dma chan 0 base address low byte 40h 7 1 timer counter 0 status, bits [5:0] 2 dma chan 0 base address high byte 2 timer counter 0 base count low byte 01h 2 1 dma chan 0 base count low byte 3 timer counter 0 base count high byte 2 dma chan 0 base count high byte 4 timer counter 1 base count low byte 02h 2 1 dma chan 1 base address low byte 5 timer counter 1 base count high byte 2 dma chan 1 base address high byte 6 timer counter 2 base count low byte 03h 2 1 dma chan 1 base count low byte 7 timer counter 2 base count high byte 2 dma chan 1 base count high byte 41h 1 timer counter 1 status, bits [5:0] 04h 2 1 dma chan 2 base address low byte 42h 1 timer counter 2 status, bits [5:0] 2 dma chan 2 base address high byte 70h 1 bit 7 = nmi enable, bits [6:0] = rtc address 05h 2 1 dma chan 2 base count low byte c4h 2 1 dma chan 5 base address low byte 2 dma chan 2 base count high byte 2 dma chan 5 base address high byte 06h 2 1 dma chan 3 base address low byte c6h 2 1 dma chan 5 base count low byte 2 dma chan 3 base address high byte 2 dma chan 5 base count high byte 07h 2 1 dma chan 3 base count low byte c8h 2 1 dma chan 6 base address low byte 2 dma chan 3 base count high byte 2 dma chan 6 base address high byte 08h 6 1 dma chan 0-3 command 2 cah 2 1 dma chan 6 base count low byte 2dma chan 0-3 request 2 dma chan 6 base count high byte 3 dma chan 0 mode: bits(1:0) = ?00? cch 2 1 dma chan 7 base address low byte 4 dma chan 1 mode: bits(1:0) = ?01? 2 dma chan 7 base address high byte 5 dma chan 2 mode: bits(1:0) = ?10? ceh 2 1 dma chan 7 base count low byte 6 dma chan 3 mode: bits(1:0) = ?11?. 2 dma chan 7 base count high byte notes: 1. the ocw1 register must be read before entering alternate access mode. 2. bits 5, 3, 1, and 0 return 0. 3. the additional write-only registers are described in their respective sections.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1093 intel ? ep80579 integrated processor 27.9.2 pic reserved bits many bits within the pic are reserved, and must have certain values written in order for the pic to operate properly. therefore, there is no need to return these values in alternate (alt) access mode. when reading pic registers from 20h and a0h, the reserved bits shall return the values listed in table 27-38 . 20h 12 1 pic icw2 of master controller d0h 6 1 dma chan 4-7 command 2 2 pic icw3 of master controller 2 dma chan 4-7 request 3 pic icw4 of master controller 3 dma chan 4 mode: bits(1:0) = ?00? 4 pic ocw1 of master controller 1 4 dma chan 5 mode: bits(1:0) = ?01? 5 pic ocw2 of master controller 5 dma chan 6 mode: bits(1:0) = ?10? 6 pic ocw3 of master controller 6 dma chan 7 mode: bits(1:0) = ?11?. 7 pic icw2 of slave controller 8 pic icw3 of slave controller 9 pic icw4 of slave controller 10 pic ocw1 of slave controller 1 11 pic ocw2 of slave controller 12 pic ocw3 of slave controller table 27-37. write-only registers with read paths in alternate access mode (sheet 2 of 2) restore data restore data i/o addr # of reads access data i/o addr # of reads access data notes: 1. the ocw1 register must be read before entering alternate access mode. 2. bits 5, 3, 1, and 0 return 0. 3. the additional write-only registers are described in their respective sections. table 27-38. pic reserved bits return values pic reserved bits value returned icw2(2:0) 000 icw4(7:5) 000 icw4(3:2) 00 icw4(0) 0 ocw2(4:3) 00 ocw3(7) 0 ocw3(5) reflects bit 6 ocw3(4:3) 01
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1094 order number: 320066-003us 27.9.3 read-only registers with write paths in alt access mode the registers described in table 27-39 have write paths to them in alt access mode. software will restore these values after returning from a powered down state. these registers must be handled special by software. when in normal mode, writing to the base address/count register also writes to the current address/count register. therefore, the base address/count must be written first, then the part is put into alternate access mode and the current address/count register is written. only bits 3:0 of the dma status registers listed below are writable. 27.10 system power supplies, planes, and signals 27.10.1 power plane control with slp_s3#, slp_s4# and slp_s5# the usage of slp_s3# and slp_s4# depend on whether the platform is configured for s3-cold. ? s3-cold ? the slp_s3# output signal can be used to cut power to the system core supply, since it will only go active for the str state (typically mapped to acpi s3). power must be maintained to system memory, cmi resume well, and to any other circuits that need to generate wake signals from the str state. cutting power to the core may be done via the power supply, or by external fets to the motherboard. the slp_s4# and slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done via the power supply, or by external fets to the motherboard. the slp_s4# output signal is used to remove power to additional subsystems that are powered during slp_s3#. slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done via the power supply, or by external fets to the motherboard. 27.10.2 slp_s4# and suspend-to-ram sequencing the system memory suspend voltage regulator is controlled by glue logic. the slp_s4# signal must be used to remove power to system memory rather than the slp_s5# signal. the slp_s4# logic in cmi provides a mech anism to fully cycle the power to the dram and/or detect if the power is not cycled for a minimum time. note: to utilize the hardware-enforced minimum dram power-down feature that is enabled by the slp_s4# assertion stretch enable bit ( section 27.3.1.3, ?offset a4h: gen_pmcon_3 - general pm configuration 3 register? bit 3), the dram power must be controlled by the slp_s4# signal. table 27-39. register write accesses in alternate access mode i/o address register write value 08h dma status register for channels 0-3. d0h dma status register for channels 4-7.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1095 intel ? ep80579 integrated processor 27.10.3 pwrok signal the pwrok input must go active based on the core supply voltages becoming valid. pwrok must not go high until at least 99 ms after vcc3_3 and vcc1_5 have reached their nominal values.this is required to meet the 100 ms delay from valid power to pltrst# deassertion in the pci specification, rev. 2.3 . 1. traditional designs have an active-low reset button electrically anded with the pwrok signal from the power supply and the processors voltage regulator module. if this is done with cmi, the pwrok_flr bit will be set. cmi treats this internally as if the rsmrst# signal had gone active. however, it is not treated as a full power failure. if pwrok goes inactive and then active (but rsmrst# stays high), then cmi will reboot (regardless of the state of the afterg3 bit). if the rsmrst# signal also goes low before pwrok goes high, then this is a full power failure, and the reboot policy is controlled by the afterg3 bit. 2. sysreset# is recommended for implementing the system reset button. this saves the external logic that is needed when the pwrok input is used. additionally it allows for better handling of the sm-bus and processor resets, and avoids improperly reporting or power failures. 3. pwrok and rsmrst# are sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by cmi. 4. in the case of true pwrok failure, pwro k will go low first before the vrmpwrgd. 5. if the pwrok input is used to implement the system reset button, cmi does not provide any mechanism to limit the amount of time that the processor is held in reset. the platform must externally guarantee that maximum reset assertion specs are met. 27.10.4 cpupwrgd signal this signal is connected to the processor and is derived from two inputs: vrmpwrgd signal (from the processor?s vrm) and?d with the pwrok signal that comes from the system power supply. 27.10.5 controlling leakage and po wer consumption du ring low-power states to control leakage in the system, various signals will tri-state or go low during some low-power states. general principles (these are board-level guidelines and are not cmi behavioral rules): ? all signals going to powered down planes (either internal or external) must be either tri-states or driven low. ? signals with pull-up resistors must not be low during low-power states. this is to avoid the power consumed in the pull-up resistor. ? buses must be halted (and held) in a known state to avoid a floating input (perhaps to some other device). floating inputs can cause extra power consumption. based on the above principles, the following measures are taken : ? during s3 (str), all signals attached to powered down planes will be tri-stated or driven low.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1096 order number: 320066-003us 27.10.6 vrmpwrok the vrmpwrok signal is generated by the processor?s vrm. it indicates that the voltage outputs from the vrm are on and within spec. 27.11 legacy power manageme nt theory of operation 27.11.1 overview instead of relying on acpi software, legacy power management uses bios and various hardware mechanisms. the scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting accesses are attempted to idle subsystems. however, the os is assumed to at least be apm enabled. without apm calls, there is no quick way to know when the system is idle between keystrokes. cmi does not support burst modes. 27.11.2 apm power management cmi has a timer, when enabled by the 1min_en bit in the smi control and enable register, generates a periodic smi# once per minute. there is also an option to have it generate the smi# once per 32, 16, or 8 seconds.the smi handler can check for system activity by reading the devtrap_sts register. if none of the system bits are set, the smi handler can increment a software counter. if there is activity, the various bits in the devtrap_sts register will be set. software clears the bits by writing a 1 to the bit position. the devtrap_sts register allows for monitoring of various internal devices or super i/ o devices (sp, pp, fdc) on lpc or pci, keyboard controller accesses, or audio functions on pci or lpc. other pci activity can be monitored by checking the pci interrupts.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1097 intel ? ep80579 integrated processor 28.0 ia-32 core interface 28.1 ia-32 core interface i/o-mapped register details table 28-1. ia-32 core interface signal state signal name s3 hot s3 cold s5 a20m# low off off cpuslp# low off off ignne# low off off init# low off off intr low off off nmi low off off smi# low off off stpclk# low off off ferr# x low low notes: x = don?t care nd = not determined. may be high or low depending on programming. table 28-2. summary of ia-32 core interface registers mapped in i/o space offset start offset end register id - description default value 61h 61h ?offset 61h: nmi_sts_cnt - nmi status and control register? on page 1098 00h 70h 70h ?offset 70h: nmi_en - nmi enable (and real time clock index) register? on page 1099 80h 92h 92h ?offset 92h: port92 - fast a20 and init register? on page 1100 00h f0h f0h ?offset f0h: coproc_err - coprocessor error register? on page 1100 00h cf9h cf9h ?offset cf9h: rst_cnt - reset control register? on page 1101 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1098 order number: 320066-003us 28.1.1 register descriptions for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 . 28.1.1.1 offset 61h: nmi_sc - nmi status and control register table 28-3. offset 61h: nmi_sts_cnt - nmi status and control register description: view: ia f base address: 0000h (io) offset start: offset end: 61h 61h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 serr_n_nmi_s ts serr# nmi source status: 0 = bit is cleared when bit 2 is set to 1. 1 = bit is set by any of the sources of the internal serr on iich; this includes serr assertions forwarded from the secondary pci bus, error from a port, do_serr or standard error message from internal bus 0 functions that generate serr#. bit 2 must be cleared in this register in order for this bit to be set. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 1 and then set it to 0. this bit is read-only. when writing to port 61h, this bit must be 0. 0b ro 06 iochk_ nmi_sts iochk# nmi source status: 0 = bit is cleared when bit 3 is set to 1. 1 = bit is set if a legacy agent (via serirq) asserts isa iochk# and bit 3 is cleared (iochk_nmi_en). this interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 1and then set bit 3 to 0. when writing to port 61h, this bit must be a 0. 0b ro 05 tmr2_ out_sts timer counter 2 out status: this bit reflects the current state of the 8254 counter 2 output. counter 2 must be programmed following any pci reset for this bit to have a determinate value. when writing to port 61h, this bit must be a 0. 0b ro 04 ref_ toggle refresh cycle toggle: this signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. when writing to port 61h, this bit must be a 0. assumed for compatibility, although no legacy refreshes occur. must toggle at legacy refresh rate (every 15 s). 0b ro 03 iochk_ nmi_en iochk# nmi enable: 0 = isa iochk# nmis are enabled. 1 = isa iochk# nmis are disabled and cleared. 0b rw 02 pci_serr_en pci serr# enable: 0 = serr# nmis are enabled. 1 = the serr# nmis are disabled and cleared. 0b rw 01 spkr_dat_en speaker data enable: 0 = the spkr output is a 0. 1 = the spkr output is equivalent to the counter 2 out signal value. 0b rw 00 tim_cnt2_en timer counter 2 enable: 0 = counter 2 counting is disabled. 1 = counting is enabled. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1099 intel ? ep80579 integrated processor 28.1.1.2 offset 70h: nmi_en - nmi enable (and real time clock index) register this register is write-only for normal operation. in alt-access mode, this register can be read to find the nmi enable status and the rtc index value. note: the rtc index field is write-only for normal operation. this field can only be read in alt- access mode. note, however, that this register is aliased to port 74h and all bits are readable at that address. see section 29.2, ?rtc i/o registers? for more information. note: software must preserve the value of bit 7 at i/o addresses 70h. when writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. note that port 70h is not directly readable. the only way to read this register is through alt access mode. although rtc index bits 06:00 are readable from port 74h, bit 7 will always return 0. if the nmi# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. table 28-4. offset 70h: nmi_en - nmi enable (and real time clock index) register description: view: ia f base address: 0000h (io) offset start: offset end: 70h 70h size: 8 bit default: 80h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 nmi_en nmi enable: 0 = nmi sources are enabled. 1 = all nmi sources are disabled. 1b rws 06 : 00 rtc_indx real time clock index (address): this data goes to the rtc to select which register or cmos ram address is being accessed. 0000000b rws
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1100 order number: 320066-003us 28.1.1.3 offset 92h: port92 - fast a20 and init register 28.1.1.4 offset f0h: coproc_err - coprocessor error register table 28-5. offset 92h: port92 - fast a20 and init register description: view: ia f base address: 0000h (io) offset start: offset end: 92h 92h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved. 00h 01 alt_a20_ gate alternate a20 gate: 0 = the a20m# signal can potentially go active. this bit is ored with the a20gate input signal to generate a20m# to the processor. 1 = a20m# signal disabled. 0b rw 00 init_now init# forced active: 0 = init# is not forced to be active 1 = when this bit transitions from a 0 to a 1, it forces init# active for 16 pci clocks. 0b rw table 28-6. offset f0h: coproc_err - coprocessor error register description: view: ia f base address: 0000h (io) offset start: offset end: f0h f0h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 oproc_ err any value written to this register causes ignne# to go active, if ferr# generates an internal irq13. in order for ferr# to generate an internal irq13, the coprocessor error enable bit ( section 17.1.5.5, ?offset 31ffh: oic - other interrupt control register? , bit 1) must be set to 1. 00h wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1101 intel ? ep80579 integrated processor 28.1.1.5 offset cf9h: rst_cnt - reset control register table 28-7. offset cf9h: rst_cnt - reset control register description: view: ia f base address: 0000h (io) offset start: offset end: cf9h cf9h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 00h 03 full_rst full reset: this bit is used to determine the states of slp_s3#slp_s4# and slp_s5# after a hard reset (not soft reset). 0 = slp_s3#, slp_s4# and slp_s5# are kept high. 1 = full reset, driving slp_s3#, slp_s4# and slp_s5# low for 3?5 seconds if the following conditions are met: ? sys_rst = 1 (bit 1 of this register) (hard reset not soft reset). ? rst_cpu is written from 0 to 1(bit 2 of this register). ? after pwrok going low (with rsmrst# high), or after two tco timeouts. when this bit is set, it also causes the full power cycle (slp_s3/4/5# assertion) in response to sysreset#, pwrok#, and watchdog timer reset sources. 0b rw 02 rst_cpu reset cpu: this bit causes either a hard or soft reset to the ia-32 core depending on the state of the sys_rst bit (bit 1 in this same register). software causes the reset by setting this bit from a 0 to a 1. 0b rw 01 sys_rst system reset: this bit determines the type of reset caused via rst_cpu (bit 2 of this register). 0 = and rst_cpu goes from 0 to 1 (soft reset), then it forces init# active for 16 pci clocks. 1 = and rst_cpu goes from 0 to 1 (hard reset), then it forces pltrst# (and pcirst#) and sus_stat# active for 5 to 6 ms. the iich main power well is reset when this bit is 1 (and some suspend well logic may also be reset). 0b rw 00 reserved reserved 0b
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1102 order number: 320066-003us 28.2 ia-32 core interface signals this section provides additional behavioral descriptions of the signals that interface between the iich and the ia-32 core. 28.2.1 a20m# (mask a20) the a20m# signal is active (low) when both of the following conditions are true: 1. the alt_a20_gate bit (bit 1 of port92 register) is a ?0?. and 2. the a20gate input signal is a ?0?. the a20gate input signal is expected to be generated by the external microcontroller (kbc). 28.2.2 init# (initialization) the init# signal is active (driven low) based on any one of several events described in ta b l e 2 8 - 8 . when any of these events occur, init# is driven low for 16 pci clocks, then driven high. the iich supports the coprocessor error function with the ferr#/ignne# pins. the function is enabled via the coproc_err_en bit (device 31, function 0, offset d0, bit 13); refer to ta bl e 2 8 - 6 for details. ferr# is tied directly to the coprocessor error signal of the . if ferr# is driven active by the , irq13 goes active (internally). when it detects a write to the coproc_err register, the iich negates the internal irq13 and drives ignne# active. ignne# remains active until ferr# is driven inactive. ignne# is never driven active unless ferr# is active. table 28-8. init# going active cause of init# going active comment shutdown special cycle from ia-32 core observed on the iich interconnect (from imch). port92 write, where init_now (bit 0) transitions from a 0 to a 1. portcf9 write, where sys_rst (bit 1) was a 0 and rst_cpu (bit 2) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the iich arms init# to be generated again.rcin# signal is expected to be high during s3-hot and low (due to core power being off) during s3-cold, s4, and s5 states. transitions on the rcin# signal in those states (or in the transition to those states) may not necessarily cause the init# signal to be generated to the . cpu bist the processor uses two processor pins, init# and reset, to initiate bist. the processor executes bist when init# is active on reset's falling edge. another way to initiate bist is to enter the runbist command through the tap serial port. by default, cpu bist is disabled. in order to enter cpu bist, software must set the rcba.cbe bit 2 = ?1? and then do a full processor reset using the cf9 register bit 2. note: a3# functions in the same manner that init# does as a strap to run bist.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1103 intel ? ep80579 integrated processor if coproc_err_en is not set, then the assertion of ferr# does not generate an internal irq13, nor writes to f0h generate ignne#. non-maskable interrupts (nmis) can be generated by several sources that are described in ta b l e 2 8 - 9 . 28.2.3 intr# (interrupt signals) the behavior of the intr signal and i/o apic interrupt signals are described in chapter 30.0, ?interrupts? . 28.2.4 stpclk# and cpuslp# (stop clock request and processor sleep signals) these active-low signals are controlled by the power management logic. see chapter 27.0, ?power management? for more details. 28.2.5 enhanced intel speedstep technology (eist) signals enhanced intel speedstep technology (eist) is not supported. 28.2.6 dpslp# (deeper sleep) dpslp# is not supported. figure 28-1. coprocessor error timing diagram ferr# internal irq13 i/o write to f0h ignne# table 28-9. nmi sources cause of nmi comment serr# goes active (either internally, externally via serr# signal, or via message from imch) isa iochk# goes active via serirq# stream (legacy system error) iochk# is a legacy signal. cmi does not have this pin, but it may be on the platform. watch dog timer (lpc bus: logical device 6) first stage 35-bit down counter reaches zero. enabled by wdt_int_type field in the wdt configuration register.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1104 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1105 intel ? ep80579 integrated processor 29.0 real time clock 29.1 overview the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each. the first bank has 114 bytes for general purpose usage. three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. daylight savings compensation is optional. the hour is represented in 12 or 24 hour format, and data can be represented in bcd or binary format. the design is meant to be functionally compatible with the motorola* ms146818b. the time keeping comes from a 32.768 khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block have very specific functions. the first ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. the time and calendar data must match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in register b. the programmer must make sure that data stored in these registers is within the reasonable values ranges and represents a possible date and time. the exception to these ranges is to store a value of c0 - ff in the alarm bytes to indicate a ?don?t care? situation. all alarm conditions must match to trigger an alarm flag, which could trigger an alarm interrupt if enabled. the set bit in register b must be ?1? while programming these locations to avoid clashes with update cycles. access to time and date information is done through the ram locations. if a ram read from the ten time and date bytes is attempted during an update cycle, the value read will not necessarily represent the true contents of those locations. any ram writes under the same conditions are ignored. note: the leap year determination for adding a 29 th day to february does not take into account the end-of-the-century exceptions. the logic simply assumes that all years divisible by four are leap years. according to the royal observatory greenwich, years that are divisible by 100 are typically not le ap years. in every fourth century (years divisible by 400, like 2000), the 100-year-exception is overridden and a leap-year occurs. note that the year 2100 is the first time in which the current rtc implementation would incorrectly calculate the leap-year. 29.2 rtc i/o registers the rtc internal registers and ram are organized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a ? d, that are used for configuration of the rtc. the extended bank contains a full 128 bytes of battery backed sram, and is accessible even when the rtc module is disabled (via the rtc configuration register). registers a ? d do not physically exist in the ram. all data movement between the host cpu and the real-time clock is done through registers mapped to the standard i/o space. the register map appears below in ta bl e 2 9 - 1 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1106 order number: 320066-003us i/o locations 70h and 71h are the standard legacy location for the real-time clock. the map for this bank is shown in ta bl e 2 9 - 2 . locations 72h and 73h are for accessing the extended ram. the extended ram bank is also accessed using an indexed scheme. i/o address 72h is used as the address pointer and i/o address 73h is used as the data register. index addresses above 127h are not valid. if the extended ram is not needed, it may be disabled. note: software must preserve the value of bit 7 at i/o addresses 70h. when writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. note that port 70h is not directly readable. the only way to read this register is through alt access mode. although rtc index bits 06:00 are readable from port 74h, bit 7 will always return 0. if the nmi# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. 29.3 real time clock indexed register details the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in ta b l e 2 9 - 2 . table 29-1. i/o registers i/o locations if u128e bit = 0 function: 70h and 74h also alias to 72h and 76h real-time clock (standard ram) index register note: writes to 72h, 74h, and 76h do not affect nmi enable (bit 7 of 70h) 71h and 75h also alias to 73h and 77h real-time clock (standard ram) target register 72h and 76h extended ram index register (if enabled) 73h and 77h extended ram target register (if enabled) table 29-2. rtc (standard) ram bank index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh ? 7fh 114 bytes of user ram
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1107 intel ? ep80579 integrated processor 29.3.1 real time clock register details warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may return non-zero values and are read-only. writes to reserved locations may cause system failure and unpredictable results. note: reserved bits are read only. note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 . 29.3.1.1 offset 0ah: rtc_rega - register a (general configuration) table 29-3. summary of real time clock indexed registers offset start offset end register id - description default value 0ah 0ah ?offset 0ah: rtc_rega - register a (general configuration)? on page 1107 xxh 0bh 0bh ?offset 0bh: rtc_regb - register b (general configuration)? on page 1109 x0x00xxxb 0ch 0ch ?offset 0ch: rtc_regc - register c (flag register)? on page 1110 00x00000b 0dh 0dh ?offset 0dh: rtc_regd - register d (flag register)? on page 1111 10xxxxxxb table 29-4. offset 0ah: rtc_rega - register a (general configuration) (sheet 1 of 2) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0ah 0ah size: 8 bit default: xxh power well: rtc bit range bit acronym bit description sticky bit reset value bit access 07 uip update in progress: this bit may be monitored as a status flag. 0 = the update cycle will not start for at least 488 s. the time, calendar, and alarm information in ram is always available when the uip bit is 0. 1 = the update is soon to occur or is in progress. xro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1108 order number: 320066-003us 06 : 04 dv division chain select: these three bits control the divider chain for the oscillator, and are not affected by rsmrst# or any other reset signal. dv[2] corresponds to bit 6. dv2 dv1 dv0 function 010normal operation 11xdivider reset 00 1invalid 000invalid xrw 03 : 00 rs rate select: selects one of 13 taps of the 15 stage divider chain. the selected tap can generate a periodic interrupt if the pie bit is set in register b. otherwise this tap sets the pf flag of register c. if the periodic interrupt is not to be used, these bits should all be set to zero. rs3 corresponds to bit 3. rs3 rs2 rs1 rs0 periodic rate 0000interrupt never toggles 00013. 90625 ms 00107. 8125 ms 0011122. 070 ms 0100244. 141 ms 0101488. 281 ms 0110976. 5625ms 01111. 953125 ms 10003. 90625 ms 10017. 8125 ms 101015. 625 ms 101131.25 ms 110062.5 ms 1101125 ms 1110250 ms 1111500 ms xrw table 29-4. offset 0ah: rtc_rega - register a (general configuration) (sheet 2 of 2) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0ah 0ah size: 8 bit default: xxh power well: rtc bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1109 intel ? ep80579 integrated processor 29.3.1.2 offset 0bh: rtc_regb - register b (general configuration) table 29-5. offset 0bh: rtc_regb - register b (general configuration) (sheet 1 of 2) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0bh 0bh size: 8 bit default: x0x00xxxb power well: rtc bit range bit acronym bit description sticky bit reset value bit access 07 set update cycle inhibit: enables/inhibits the update cycles. 0 = update cycle occurs normally once each second. 1 = a current update cycle aborts and subsequent update cycles do not occur until set is returned to zero. the bios may initialize time and calendar bytes safely. note: this bit is not affected by rsmrst# nor any other reset signal. note: software must ensure this bit transitions from '1' to '0' once whenever the rtc coin battery is inserted. this is to ensure that the internal rtc time updates occur properly. xrw 06 pie periodic interrupt enable: 0 = disabled 1 = allows an interrupt to occur with a time base set with the rs bits of register a. note: this bit is cleared by rsmrst#, but not on any other reset. 0h rw 05 aie alarm interrupt enable: 0 = disabled 1 = the alarm interrupt enable (aie) bit allows an interrupt to occur when the af is one as set from an alarm match from the update cycle. an alarm can occur once a second, one an hour, once a day, or once a month. note: this bit is cleared by rtest#, but not on any other reset. xrw 04 uie update-ended interrupt enable: 0 = disabled 1 = allows an interrupt to occur when the update cycle ends. note: this bit is cleared by rsmrst#, but not on any other reset. 0h rw 03 sqwe square wave enable: the square wave enable bit serves no function in this device, but it is in this register bank to provide compatibility with the motorola 146818b. there is not a sqw pin on this device. note: this bit is cleared by rsmrst#, but not on any other reset. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1110 order number: 320066-003us 29.3.1.3 offset 0ch: rtc_regc - register c (flag register) 02 dm data mode: the data mode (dm) bit specifies either binary or bcd data representation. 0 = denotes bcd 1 = denotes binary this bit is not affected by rsmrst# nor any other reset signal. xrw 01 hourform hour format: this bit indicates the hour byte format. 0 = twelve-hour mode is selected. in twelve hour mode, the seventh bit represents am as zero and pm as one. 1 = twenty-four hour mode is selected. this bit is not affected by rsmrst# nor any other reset signal. xrw 00 dse daylight savings enable: 0 = disabled 1 = triggers two special hour updates per year when set to one. one is on the first sunday in april, where time increments from 1:59:59 am to 3:00:00 am. the other is the last sunday in october when the time first reaches 1:59:59 am, it is changed to 1:00:00 am. the time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly. these special update conditions do not occur when the dse bit is set to zero. the days for the hour adjustment are those specified in united states federal law as of 1987, which is different than previous years. note: this bit is not affected by rsmrst# nor any other reset signal. xrw table 29-6. offset 0ch: rtc_regc - register c (flag register) (sheet 1 of 2) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0ch 0ch size: 8 bit default: 00x00000b power well: rtc bit range bit acronym bit description sticky bit reset value bit access 07 irqf interrupt request flag: interrupt request flag = (pf * pie) + (af * aie) + (uf *ufe). this also causes the rtc interrupt to be asserted. note: this bit is cleared upon rsmrst# or a read of register c. 0b ro table 29-5. offset 0bh: rtc_regb - register b (general configuration) (sheet 2 of 2) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0bh 0bh size: 8 bit default: x0x00xxxb power well: rtc bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1111 intel ? ep80579 integrated processor 29.3.1.4 offset 0dh: rtc_regd - register d (flag register) 06 pf periodic interrupt flag: 0 = no taps are specified. 1 = set when the tap as specified by the rs bits of register a is one. note: this bit is cleared upon rsmrst# or a read of register c. 0b ro 05 af alarm flag: 0 = all alarm values do not match the current time 1 = all alarm values match the current time. note: this bit is cleared upon rtest# or a read of register c. xro 04 uf update-ended flag: 0 = update cycle not detected 1 = this bit is set immediately following an update cycle for each second. note: the bit is cleared upon rsmrst# or a read of register c. 0b ro 03 : 00 reserved reserved 000b table 29-7. offset 0dh: rtc_regd - register d (flag register) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0dh 0dh size: 8 bit default: 10xxxxxxb power well: rtc bit range bit acronym bit description sticky bit reset value bit access 07 vrt valid ram and time bit: this bit is hard-wired to ?1? in the rtc power well. this bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1b rw 06 reserved reserved: this bit always returns a 0 and should be set to 0 for write cycles. 0b 05 : 00 da date alarm: these bits store the date of month alarm value. if set to 000000, then a don?t care state is assumed. the host must configure the dates alarm for these bits to do anything, yet they can be written at any time. if the date alarm is not enabled, these bits return zeros to mimic the functionality of the motorola 146818b. these bits are not affected by any reset assertion. xxxxxxb rw table 29-6. offset 0ch: rtc_regc - register c (flag register) (sheet 2 of 2) description: view: ia f base address: rtc standard ram bank offset start: offset end: 0ch 0ch size: 8 bit default: 00x00000b power well: rtc bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1112 order number: 320066-003us 29.4 update cycles an update cycle occurs once a second, if the set bit of register b is not asserted and the divide chain is properly configured. during this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the ram locations. the update cycle will start at least 488 s after the uip bit of register a is asserted, and the entire cycle will not take more than 1984 s to complete. the time and date ram locations (0?9) is disconnected from the external bus during this time. to avoid update and data corruption conditions, external ram access to these locations can safely occur upon the detection of either of two conditions. 1. when an updated-ended interrupt is detect ed, almost 999 ms is available to read and write the valid time and date data. 2. if the uip bit of register a is detected to be low, there is at least 488 s before the update cycle begins. warning: the overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. to ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 29.5 interrupts the real-time clock interrupt is internally routed within the iich both to the i/o apic and the 8259. it is mapped to interrupt vector 8. this interrupt does not leave the iich prior to connection to the interrupt controller, nor is it shared with any other interrupt. irq8# from the serirq stream is ignored. however, the high performance event timers can also be mapped to irq8#; in this case, the rtc interrupt is blocked. 29.6 lockable ram ranges the rtc?s battery-backed ram supports two 8-byte ranges that can be locked via the pci configuration space. if the locking bit is set, the corresponding range in the ram is not readable or writeable. a write cycle to those locations has no effect. a read cycle to those locations does not return the locations actual value (resultant value is undefined). once a range is locked, the range can be unlocked only by a hard reset, which will invoke the bios and allow it to relock the ram range. 29.7 century rollover the iich detects a roll over when the year byte (rtc i/o space, index offset 09h) transitions from 99 to 00 (e.g., a rollover from december 31, 2099, 11:59:59 p.m. to 12:00:00 a.m on january 1 st , 2100). upon detecting the rollover, the iich sets the newcentury_sts bit (tcobase + 04h, bit 7). if the system is in an s0 state, this causes an smi#. the smi# handler can update registers in the rtc ram that are associated with the century value. if the system is in a sleep state (s3 and s5) when the century rollover occurs, the iich also sets the newcentury_sts bit, but no smi# is generated. when the system resumes from the sleep state, bios should check the newcentury_sts bit and update the century value in the rtc ram.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1113 intel ? ep80579 integrated processor 29.8 month and year alarms this function is not supported.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1114 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1115 intel ? ep80579 integrated processor 30.0 interrupts 30.1 overview only level-triggered interrupts can be shared. pci interrupts (pirqs) are inherently shared on the board. these must, therefore, be programmed as level-triggered. ta bl e 3 0 - 1 and ta b l e 3 0 - 2 show the mapping of the various interrupts in non-apic and apic modes. ta b l e 3 0 - 3 lists the interrupt signals action in the associated power state table 30-1. interrupt options - 8259 mode irq serirq pin internal modules 0 no no 8254 counter 0, mmt 0 1yes no 2 no no 8259 2 cascade only 3yes nooption for pirqx 4yes nooption for pirqx 5yes nooption for pirqx 6yes nooption for pirqx 7yes nooption for pirqx 8 no no rtc, mmt 1 9 yes no option for pirqx, sci, tco 10 yes no option for pirqx, sci, tco 11 yes no option for pirqx, sci, tco, mmt 2 12 yes no option for pirqx 13 no no ferr# logic 14 yes yes pirqx, sata primary (legacy mode) 15 yes yes pirqx, sata secondary (legacy mode) notes: 1. if an interrupt is used for pci irq[a:h], sci, or tco, it must not be used for isa (legacy)-style interrupts (via serirq). 2. pirq[a-d] do not come out on the pins any longer. 3. in 8259 mode, pci interrupts are mapped to ir q3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15. 4. if irq11 is used for mmt 2, software must ensure irq11 is not shared with any other devices to guarantee the proper operation of mmt 2. the hardware does not prevent sharing of irq11.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1116 order number: 320066-003us table 30-2. interrupt options - apic mode irq # serirq pin pci message internal modules 0 no no no cascade from 8259 1 1yes no yes 2 no no no 8254 counter 0, mmt 0 (legacy mode) 3yes no yes 4yes no yes 5yes no yes 6yes no yes 7yes no yes 8 no no no rtc, mmt 1 (legacy mode) 9yes no yes option for sci, tco 10 yes no yes option for sci, tco 11 yes no yes option for sci, tco 12 yes no yes 13 no no no ferr# logic 14 yes yes yes sata primary (legacy mode) 15 yes yes yes sata secondary (legacy mode) 16 pirqa no yes see section 30.5 for how internal devices are mapped. 17 pirqb no 18 pirqc no 19 pirqd no 20 n/a pirqe option for sci, tco, and hpet (high precision event timer) for other internal devices, see section 30.5 21 n/a pirqf 22 n/a pirqg 23 n/a pirqh 24 n/a gpio[16] n/a external gpio driven interrupt 25 n/a gpio[17] n/a external gpio driven interrupt 26 n/a gpio[20] n/a external gpio driven interrupt 27 n/a gpio[21] n/a external gpio driven interrupt 28 n/a gpio[23] n/a external gpio driven interrupt 29 n/a gpio[24] n/a external gpio driven interrupt 30 n/a gpio[28] n/a external gpio driven interrupt 31 n/a gpio[30] n/a external gpio driven interrupt 32 n/a gpio[31] n/a external gpio driven interrupt notes: 1. if an interrupt is used for pci irq[a:h], sci, or tco, it must not be used for isa (legacy)-style interrupts (via serirq). 2. pirq[a-d]do not come out on the pins any longer. 3. in apic mode, the pci interrupts a:h are mapped to irq[16:23]. 4. when programming the polarity of internal inte rrupt sources on the apic, interrupts 0 through 15 receive active-high internal interrupt sources; interrupts 16 through 23 receive active-low internal interrupt sources. 5. irq24-39 are externally driven interrupts through gpio pins, enabled if gpio_irq_strap_sts field of extended test mode register3 (etr3) is set to 1 (set by externally pulling strap siu2_txd_ad18 to low on the rising edge of pwrok) and if each of the 16 irq capable gpio pins is configured to work in alternative mode (in gpio_use_sel1/gpio_use_sel2 registers).
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1117 intel ? ep80579 integrated processor 30.2 8259 interrupt controllers (pic) 30.2.1 overview the iich incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the legacy (isa) compatible interrupt controller (pic). these interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and dma channels. in addition, this interrupt controller can support the pci based interrupts by mapping the pci interrupt onto the compatible irq interrupt line. each 8259 core supports eight interrupts, numbered 0 ? 7. ta bl e 3 0 - 4 shows how the cores are connected. 33 n/a gpio[33] n/a external gpio driven interrupt 34 n/a gpio[34] n/a external gpio driven interrupt 35 n/a gpio[40] n/a external gpio driven interrupt 36 n/a gpio[18] n/a external gpio driven interrupt 37 n/a gpio[19] n/a external gpio driven interrupt 38 n/a gpio[25] n/a external gpio driven interrupt 39 n/a gpio[27] n/a external gpio driven interrupt table 30-3. signals associated with interrupt logic signal name s3 s5 serirq off off pirq[a:h]# off off table 30-2. interrupt options - apic mode notes: 1. if an interrupt is used for pci irq[a:h], sci, or tco, it must not be used for isa (legacy)-style interrupts (via serirq). 2. pirq[a-d]do not come out on the pins any longer. 3. in apic mode, the pci interrupts a:h are mapped to irq[16:23]. 4. when programming the polarity of internal interrupt sources on the apic, interrupts 0 through 15 receive active-high internal interrupt sources; interrupts 16 through 23 receive active-low internal interrupt sources. 5. irq24-39 are externally driven interrupts through gpio pins, enabled if gpio_irq_strap_sts field of extended test mode register3 (etr3) is set to 1 (set by externally pulling strap siu2_txd_ad18 to low on the rising edge of pwrok) and if each of the 16 irq capable gpio pins is configured to work in alternative mode (in gpio_use_sel1/gpio_use_sel2 registers). table 30-4. 8259 core connection (sheet 1 of 2) 8259 8259 input typical interrupt source connected pin / function master 0 internal internal timer / counter 0 output or multimedia timer 0 1 keyboard irq1 via serirq 2 internal slave controller intr output 3 serial port a irq3 via serirq, pirqx 4 serial port b irq4 via serirq, pirqx 5 parallel port / generic irq5 via serirq, pirqx 6 floppy disk irq6 via serirq, pirqx 7 parallel port / generic irq7 via serirq, pirqx
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1118 order number: 320066-003us the iich cascades the slave controller onto the master controller through master controller interrupt input 2. this means there are only 15 possible interrupts for the iich pic. interrupts can individually be programmed to be edge or level, except for irq0, irq2, irq8#. note: active-low interrupt sources, such as the pirq#s, are internally inverted in the iich. in the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. therefore, the term ?high? indicates ?active?, which means ?low? on an originating pirq#. 30.2.2 i/o registers the interrupt controller registers are locate d at 20h and 21h for the master controller (irq0 ? 7), and at a0h and a1h for the slave controller (irq8 ? 13). these registers have multiple functions depending upon the data written to them. ta b l e 3 0 - 5 lists the different register possibilities for each address. slave 0real time clock inverted irq8# from internal rtc or multimedia timer 1 1 generic irq9 via serirq, sci, or tco, pirqx 2 generic irq10 via serirq, sci, or tco, pirqx 3 generic irq11 via serirq, sci, or tco, pirqx 4 ps/2 mouse irq12 via serirq, sci, or tco, pirqx 5internal state machine output based on processor ferr# assertion. can optionally be used for sci or tco interrupts if ferr# is not needed. 6 sata sata primary (legacy mode), serirq, pirqx 7 sata sata secondary (legacy mode), sata secondary (legacy mode), serirq, pirqx table 30-4. 8259 core connection (sheet 2 of 2) 8259 8259 input typical interrupt source connected pin / function table 30-5. summary of 8259 interrupt controller (pic) registers mapped in i/o space offset start offset end register id - description default value 020h, 0a0h 020h, 0a0h ?icw1[0-1] - initialization command word 1 register? on page 1119 0001x0xxb 021h, 0a1h 021h, 0a1h ?icw2[0-1] - initialization command word 2 register? on page 1120 xxh 21h 21h ?micw3 - master initialization command word 3 register? on page 1121 04h a1h a1h ?sicw3 - slave initialization command word 3 register? on page 1121 00h 21h, 0a1h 21h, 0a1h ?icw4[0-1] - initialization command word 4 register? on page 1122 01h 021h, 0a1h 021h, 0a1h ?ocw1[0-1]- operational control word 1 (interrupt mask) register? on page 1122 00h 020h, 0a0h 020h, 0a0h ?ocw2[0-1] - operational control word 2 register? on page 1123 001xxxxxb 020h, 0a0h 020h, 0a0h ?ocw3[0-1] - operational control word 3 register? on page 1124 001xx10b 4d0h 4d0h ?elcr1 - master edge/level control register? on page 1125 00h 4d1h 4d1h ?elcr2 - slave edge/level control register? on page 1126 00
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1119 intel ? ep80579 integrated processor 30.2.2.1 icw1[0-1] - initialization command word 1 register a write to initialization command word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. table 30-6. icw1[0-1] - initialization command word 1 register description: view: ia f base address: 0000h (io) offset start: offset end: 020h, 0a0h 020h, 0a0h size: 8 bit default: 0001x0xxb power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 05 reserved reserved. must be programmed to zero. 000h 04 reserved reserved. must be programmed to one. 1 03 ltim edge/level bank select: disabled. replaced by the edge/level triggered control registers (elcr, d31, f0, 4d0h and d31, f0, 4d1h). xwo 02 reserved reserved. must be programmed to zero. 0h 01 sngl single or cascade: this bit must be programmed to a 0 to indicate that two controllers are operating in cascade mode. xwo 00 ic4 icw4 write required: this bit must be programmed to a 1 to indicate that icw4 needs to be programmed. xwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1120 order number: 320066-003us 30.2.2.2 icw2[0-1] - initialization command word 2 register icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. the value programmed for bits[07:03] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa (legacy) icw2 values are 08h for the master controller and 70h for the slave controller. table 30-7. icw2[0-1] - initialization command word 2 register description: view: ia f base address: 0000h (io) offset start: offset end: 021h, 0a1h 021h, 0a1h size: 8 bit default: xxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 ivba interrupt vector base address: these bits define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. xh wo 02 : 00 irl interrupt request level: when writing icw2, these bits must all be 0. during an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. this is combined with bits [07:03] to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a three bit binary code: code master interrupt slave interrupt 000 irq0 irq8 001 irq1 irq9 010 irq2 irq10 011i rq3 irq11 100 irq4 irq12 101 irq5 irq13 110 irq6 irq14 111 irq7 irq15 xh wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1121 intel ? ep80579 integrated processor 30.2.2.3 micw3 - master initialization command word 3 register 30.2.2.4 sicw3 - slave initialization command word 3 register table 30-8. micw3 - master initialization command word 3 register description: view: ia f base address: 0000h (io) offset start: offset end: 21h 21h size: 8 bit default: 04h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved. must be programmed to zero. 0h 02 ccc cascaded controller connection: this bit must always be programmed to a 1. this bit indicates that the slave controller is cascaded on irq2. when irq8#?irq15 is asserted, it goes through the slave controller?s priority resolver. the slave controller?s intr output onto irq2. irq2 then goes through the master controller?s priority solver. if it wins, the intr signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1wo 01 : 00 reserved reserved. must be programmed to zero. 0h table 30-9. sicw3 - slave initialization command word 3 register description: view: ia f base address: 0000h (io) offset start: offset end: a1h a1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved. must be programmed to zero. 0h 02 : 00 sic slave identification code: these bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal inta# pulse to the trailing edge of the second internal inta# pulse. these bits must be programmed to 02h to match the code broadcast by the master controller. when 02h is broadcast by the master controller during the inta# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. 0h wo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1122 order number: 320066-003us 30.2.2.5 icw4[0-1] - initialization command word 4 register 30.2.2.6 ocw1[0-1] - operational contro l word 1 (interrupt mask) register table 30-10. icw4[0-1] - initialization command word 4 register description: view: ia f base address: 0000h (io) offset start: offset end: 21h, 0a1h 21h, 0a1h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 05 reserved must be programmed to zero. 0h 04 sfnm special fully nested mode: 0 = disabled by writing a 0 to this bit. 1 = special fully nested mode is programmed. 0h wo 03 buf buffered mode: this bit must be programmed to 0 which is non-buffered mode. note: writing ?1? will result in undefined behavior. 0h wo 02 msbm master/slave in buffered mode: must be programmed to 0. 0h wo 01 aeoi automatic end of interrupt: 0 = this bit must normally be programmed to 0. this is the normal end of interrupt. 1 = automatic end of interrupt (aeoi) mode is programmed. aeoi is discussed in section 30.2.7.2 . 0h wo 00 mm microprocessor mode: must be programmed to 1 to indicate that the controller is operating in an intel architecture-based system. note: writing ?0? will result in undefined behavior. 1wo table 30-11. ocw1[0-1]- operational control word 1 (interrupt mask) register description: view: ia f base address: 0000h (io) offset start: offset end: 021h, 0a1h 021h, 0a1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irm interrupt request mask: 0 = the corresponding irq mask bit is cleared and interrupt requests are again accepted by the controller. 1 = the corresponding irq line is masked. masking irq2 on the master controller also masks the interrupt requests from the slave controller. 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1123 intel ? ep80579 integrated processor 30.2.2.7 ocw2[0-1] - operational control word 2 register following a device reset or icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initialization. table 30-12. ocw2[0-1] - operational control word 2 register description: view: ia f base address: 0000h (io) offset start: offset end: 020h, 0a0h 020h, 0a0h size: 8 bit default: 001xxxxxb power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 05 reoi rotate and eoi codes (r, sl, eo): these three bits control the rotate and end of interrupt modes and combinations of the two. 000 rotate in auto eoi mode (clear) 001 non-specific eoi command 010 no operation 011 *specific eoi command 100 rotate in auto eoi mode (set) 101 rotate on non-specific eoi command 110 *set priority command 111 *rotate on specific eoi command *l0 - l2 are used 001h wo 04 : 03 ocw2_sel ocw2 select: when selecting ocw2, bits 04:03 = ?00? x wo 02 : 00 int_ls interrupt level select: l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined above, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. code interrupt level codeinterrupt level 000i rq0/8 100irq4/12 001 irq1/9 101irq5/13 010 irq2/10 110irq6/14 011 irq3/11 111irq7/15 xwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1124 order number: 320066-003us 30.2.2.8 ocw3[0-1] - operational control word 3 register table 30-13. ocw3[0-1] - operational control word 3 register description: view: ia f base address: 0000h (io) offset start: offset end: 020h, 0a0h 020h, 0a0h size: 8 bit default: 001xx10b power well: core bit range bit acronym bit description sticky bit reset value bit access 07 reserved reserved. 0h 06 smm special mask mode: 0 = the special mask mode will not be used by an interrupt service routine. 1 = the special mask mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. bit 5, the esmm bit, must be set for this bit to have any meaning. 0h wo 05 esmm enable special mask mode: 0 = disable. the smm bit becomes a ?don't care?. 1 = enable the smm bit to set or reset the special mask mode. 1wo 04 : 03 o3s ocw3 select: when selecting ocw3, bits04:03 = ?01?. x wo 02 pmc poll mode command: 0 = disable. poll command is not issued. 1 = enable. the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle. an encoded byte is driven onto the data bus, representing the highest priority level requesting service. xwo 01 : 00 rrc register read command: these bits provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 does not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr is read. if bit 0=1, the isr is read. following icw initialization, the default ocw3 port address read is ?read irr?. to retain the current selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the selected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. 00 no action 01 no action 10 read irq register 11 read is register 10b wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1125 intel ? ep80579 integrated processor 30.2.2.9 elcr1 - master edge/level control register in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the cascade channel, irq2, the heart beat timer (irq0), and the keyboard controller (irq1), cannot be put into level mode. table 30-14. elcr1 - master edge/level control register description: view: ia f base address: 0000h (io) offset start: offset end: 4d0h 4d0h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ecl7 edge level control irq7: 0 = edge mode. the interrupt is recognized by a low to high transition. 1 = level mode. the interrupt is recognized by a high level. 0h rw 06 ecl6 edge level control irq6: 0 = edge mode. the interrupt is recognized by a low to high transition. 1 = level mode. the interrupt is recognized by a high level. 0h rw 05 ecl5 edge level control irq5: 0 = edge mode. the interrupt is recognized by a low to high transition. 1 = level mode. the interrupt is recognized by a high level. 0h rw 04 ecl4 edge level control irq4: 0 = edge mode. the interrupt is recognized by a low to high transition. 1 = level mode. the interrupt is recognized by a high level. 0h rw 03 ecl3 edge level control irq3: 0 = edge mode. the interrupt is recognized by a low to high transition. 1 = level mode. the interrupt is recognized by a high level. 0h rw 02 : 00 reserved reserved. 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1126 order number: 320066-003us 30.2.2.10 elcr2 - slave edge/level control register in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the real time clock, irq8#, and the floating point error interrupt, irq13, cannot be programmed for level mode. table 30-15. elcr2 - slave edge/level control register description: view: ia f base address: 0000h (io) offset start: offset end: 4d1h 4d1h size: 8 bit default: 00 power well: core bit range bit acronym bit description sticky bit reset value bit access 07 ecl15 edge level control irq15: 0 = edge 1 = level 0h rw 06 ecl14 edge level control irq14: 0 = edge 1 = level 0h rw 05 reserved reserved. 0h 04 ecl12 edge level control irq12: 0 = edge 1 = level 0h rw 03 ecl11 edge level control irq11 : 0 = edge 1 = level 0h rw 02 ecl10 edge level control irq10: 0 = edge 1 = level 0h rw 01 ecl9 edge level control irq9 : 0 = edge 1 = level 0h rw 00 reserved reserved. must be zero. 0h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1127 intel ? ep80579 integrated processor 30.2.3 interrupt handling 30.2.3.1 generating interrupts the pic interrupt sequence involves three bits, from the irr, isr, and imr, for each interrupt level. these bits are used to determine the interrupt vector returned and status of any other pending interrupts. these bits are defined in ta bl e 3 0 - 1 6 . 30.2.3.2 acknowledging interrupts the processor generates an interrupt acknowledge cycle that is translated into an interrupt acknowledge special cycle to the iich. the pic translates this cycle into two internal inta# pulses expected by the 8259 cores. the pic uses the first internal inta# pulse to freeze the state of the interrupts for priority resolution. on the second inta# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. this code is based upon bits [07:03] of the corresponding icw2 register, combined with three bits representing the interrupt within that controller. 30.2.3.3 hardware/software interrupt sequence 1. one or more of the interrupt request lines (irq) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the pic sends intr active (high) to the processor if an asserted interrupt is not masked. 3. the processor acknowledges the intr and responds with an interrupt acknowledge cycle. table 30-16. interrupt handling bits name description irr interrupt request register this bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. this bit is set whether or not the interrupt is masked. however, a masked interrupt will not generate intr. isr interrupt service register this bit is set, and the corresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. imr interrupt mask register determines whether an interrupt is masked. masked interrupts do not generate intr. table 30-17. content of interrupt vector byte master, slave interrupt bits [07:03] bits [02:00] irq7,15 icw2[07:03] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1128 order number: 320066-003us 4. upon observing the acknowledge cycle, it is converted into two cycles that the internal 8259 pair can respond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally generated inta# pulse, the highest priority isr bit is set and the corresponding irr bit is reset. on the trailing edge of the first pulse, a slave identification code is broadcast internally by the master pic to the slave pic. the slave controller determines if it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second internally generated inta# pulse, the pic returns the interrupt vector. if no interrupt request is present, the pic will return vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. 30.2.4 initialization command words (icw) before operation can begin, each 8259 must be initialized. in the iich, this is a four byte sequence. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each 8259 initialization command word is a fixed location in the i/ o memory space: 20h for the master controller, and a0h for the slave controller. 30.2.4.1 icw1 an i/o write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensing this write, the iich pic expects three more byte writes to 21h for the master controller or a1h for the slave controller to complete the icw sequence. a write to icw1 starts the initialization sequence during which the following automatically occur: 1. following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7. 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr. 30.2.4.2 icw2 the second write in the sequence, icw2, is programmed to provide bits [07:03] of the interrupt vector that are released during an interrupt acknowledge. a different base is selected for each interrupt controller. 30.2.4.3 icw3 the third write in the sequence, icw3, has a different meaning for each controller. ? for the master controller, icw3 is used to indicate which irq input line is used to cascade the slave controller. within the iich, irq2 is used. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0's. ? for the slave controller, icw3 is the slave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cycles, the master
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1129 intel ? ep80579 integrated processor controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. the slave controller compares this identification code to the value stored in its icw3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 30.2.4.4 icw4 the final write in the sequence, icw4, must be programmed by both controllers. at the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an intel architecture-based system. 30.2.5 operation command words (ocw) these command words reprogram the interrupt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines. ? ocw2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the eoi function. ? ocw3 sets up isr/irr reads, enables/disables the special mask mode smm, and enables/disables polled interrupt mode. 30.2.6 modes of operation 30.2.6.1 fully nested mode in this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. when an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. additionally, the isr for the interrupt is set. this isr bit remains set until: ? the processor issues an eoi command immediately before returning from the service routine; or ? if in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. interrupt priorities can be changed in the rotating priority mode. 30.2.6.2 special fully nested mode this mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully-nested mode is programmed to the master controller. this mode is similar to the fully-nested mode with the following exceptions: ? when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave is recognized by the master and initiates interrupts to the processor. in normal nested mode, a slave is masked out when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non- specific eoi command to the slave and then reading its isr. if it is 0, a non- specific eoi can also be sent to the master.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1130 order number: 320066-003us 30.2.6.3 automatic rotation mode (equal priority devices) in some applications, there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential eight-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 30.2.6.4 specific rotation mode (specific priority) software can change interrupt priorities by programming the bottom priority. for example, if irq5 is programmed as the bottom priority device, then irq6 is the highest priority device. the set priority command is issued in ocw2 to accomplish this, where: r=1, sl=1, and lo-l2 is the binary priority level code of the bottom priority device. in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo-l2=irq level to receive bottom priority. 30.2.6.5 poll mode poll mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. polled mode can also be used to expand the number of interrupts. the polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in ocw3. the pic treats its next i/o read as an interrupt acknowledge, sets the appropriate isr bit if there is a request, and reads the priority level. interrupts are frozen from the ocw3 write to the i/o read. the byte returned during the i/o read will contain a ?1? in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. 30.2.6.6 edge and level triggered mode in isa (legacy) systems this mode is programmed using bit 3 in icw1, which sets level or edge for the entire controller. in the iich, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. if an elcr bit is ?0?, an interrupt request is recognized by a low to high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is ?1?, an interrupt request is recognized by a high level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal inta#. if the irq input goes inactive before this time, a default irq7 vector is returned.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1131 intel ? ep80579 integrated processor 30.2.7 end of interrupt (eoi) operations an eoi can occur in one of two fashions: by a command word write issued to the pic before returning from a service routine, the eoi command; or automatically when aeoi bit in icw4 is set to 1. 30.2.7.1 normal eoi in normal eoi, software writes an eoi command before leaving the interrupt service routine to mark the interrupt as completed. there are two forms of eoi commands: specific and non-specific. when a non-specific eoi command is issued, the pic clears the highest isr bit of those that are set to 1. non-specific eoi is the normal mode of operation of the pic within the iich, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. when the pic is operated in modes which preserve the fully nested structure, software can determine which isr bit to clear by issuing a specific eoi. an isr bit that is masked will not be cleared by a non-specific eoi if the pic is in the special mask mode. an eoi command must be issued for both the master and slave controller. 30.2.7.2 automatic eoi mode in this mode, the pic automatically performs a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse. from a system standpoint, this mode must be used only when a nested multi-level interrupt structure is not required within a single pic. the aeoi mode can only be used in the master controller. 30.2.8 masking interrupts 30.2.8.1 masking on an individual interrupt request each interrupt request can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the master controller masks all requests for service from the slave controller. 30.2.8.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt service routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. the special mask mode is set by ocw3.ssmm and ocw3.smm set, and cleared when ocw3.ssmm and ocw3.smm are cleared. 30.2.9 steering of pci interrupts the iich can be programmed to allow pirqa#-pirqh# to be internally routed to interrupts 3-7, 9-12, 14 or 15, through the parc, pbrc, pcrc, pdrc, perc, pfrc, pgrc, and phrc registers in section 19.2.3.1, ?offset 60h: parc: pirqa routing control register? on page 741 . the assignment is programmable through the pirqx
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1132 order number: 320066-003us route control registers, located at 60?63h and 68?6bh in device 31, function 0. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a platform to share a single line across the connector. when pirqx# is routed to specified irq line, software must change the corresponding elcr1 or elcr2 register to level sensitive mode. the iich internally inverts the pirqx# line to send an active high level to the pic. when a pci interrupt is routed onto the pic, the selected irq can no longer be used by an isa (legacy) device. internal sources of the pirqs, including sci and tco interrupts, cause the external pirq to be asserted. the iich receives the pirq input, like all of the other external sources, and routes it accordingly. 30.3 advanced interrupt controller: apic in addition to the standard isa (legacy )-compatible pic described in the previous chapter, the iich also incorporates the apic. 30.3.1 interrupt handling the i/o apic handles interrupts very differently than the 8259. briefly, these differences are: ? method of interrupt transmission. the i/o apic transmits interrupts through memory writes on the normal data path to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. ? interrupt priority. the priority of interrupts in the i/o apic is independent of the interrupt number. for example, interrupt 10 can be given a higher priority than interrupt 3. ? more interrupts. the i/o apic in the iich supports a total of 40 interrupts (24 interrupts only, when etr3.gpio_irq_strap_sts is 0). ? when gpio_irq_strap_sts field of extended test mode register3(etr3) is 0, mre field in the apic_vs register reports 17h (indicating 24 supported irqs). ? when etr3.gpio_irq_strap_sts is 1 (strap pulling ?siu2_txd_ad18? to low on the rising edge of pwrok), io-apic can support additional 16, dedicated, gpio driven irqs (irq24-39). the function of irq capable gpio pins are set to irq mode by default if etr3.gpio_irq_strap_sts is 1, but can be changed to gpio mode for any or all of those pins by programming the gpio_use_sel registers. if the gpio_use_sel register bits are configured to gpio mode then those gpio pins can not generate irq interrupt to io-apic. ? note: gpio pins can not generate interrupt when etr3.gpio_irq_strap_sts is 0. ? multiple interrupt controllers. the i/o apic architecture allows for multiple i/o apic devices in the system with their own interrupt vectors. 30.3.2 pci/pci express* message-based interrupts when external devices through pci/pci express* wish to generate an interrupt, they send the message defined in the pci express* specification for generating inta# - intd#. these are translated internal assertions/deassertions of inta# - intd#.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1133 intel ? ep80579 integrated processor 30.3.2.1 front side bus interrupt delivery the iich requires that the i/o apic deliver interrupt messages to the processor in a parallel manner, rather than using the i/o apic serial scheme. delivery of interrupts is completed by the iich writing to a memory location that is snooped by the processor. the processors snoops the cycle to know which interrupt goes active. the following sequence is used: 1. when the iich detects an interrupt event (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal irr bit associated with that interrupt. 2. internally, the iich requests to use the bus in a way that automatically flushes upstream buffers. this can be internally implemented similar to a dma device request. 3. the iich delivers the message by performing a write cycle to the appropriate address with the appropriate data. the address and data formats are described in section 30.3.2.6, ?interrupt message format? on page 1133 . 30.3.2.2 edge-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. 30.3.2.3 level-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. if after the eoi the interrupt is still active, then another ?assert message? is sent to indicate that the interrupt is still active. 30.3.2.4 registers associated with front-side bus interrupt delivery capabilities indication is the capability to support front-side bus interrupt delivery indicated via acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. 30.3.2.5 eoi the mechanism by which the processor may generate an eoi is pci express* eoi message. the pci express* eoi message is used by ia-32 core. it is broadcast to the internal ioxapic. the data of the eoi message is the vector. this value is compared with all the vectors inside the ioxapic, and any match causes rte[x].rirr to be cleared. see section 17.1.6.1 for a description of the eoi vendor-specific message. 30.3.2.6 interrupt message format cmi writes the interrupt message internally as a 32-bit memory write cycle. it uses the following formats shown in ta b l e 3 0 - 1 8 and ta b l e 3 0 - 1 9 for the address and data.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1134 order number: 320066-003us table 30-18. interrupt delivery address format bits description 31:20 is always feeh 19:12 destination id (did): this is the same as bits 63:56 of the i/o redirection table entry for the interrupt associated with this message. 11:04 extended destination id ( edid): this is the same as bits 55:48 of the i/o redirection table entry for the interrupt associated with this message. 03 redirection hint (dlm): this bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = the message is delivered to the agent (processor) listed in bits 19:12. 1 = the message is delivered to an agent with a lower interrupt priority this can be derived from bits 10:8 in the data field (see below). the redirection hint bit is a 1 if bits 10:8 in th e delivery mode field associated with corresponding interrupt are encoded as 001 (lowest priority). otherwise, the redirection hint bit is 0 02 destination mode (dsm): this bit is used only when the redirection hint bit is set to 1. if the redirection hint bit and the destination mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical id. 01:00 will always be 00b table 30-19. interrupt delivery data format bits description 31:16 will always be 0000h 15 trigger mode: 1 = level,0 = edge. same as the corresponding bit in the i/o redirection table for that interrupt. 14 delivery status: 0 = deassert 1 = assert if using edge-triggered interrupts, then the bit will always be 1, since only the assertion is sent. if using level-triggered interrupts, then this bit indicates the state of the interrupt input. 13:12 will always be 0h 11 destination mode: 1= logical. 0 = physical. same as the corresponding bit in the i/o redirection table 10:08 delivery mode: this is the same as the corresponding bits in the i/o redirection table for that interrupt. 000 = fixed 100 = nmi 001 = lowest priority 101 = init 010 = smi/pmi 110 = reserved 011 = reserved 111 = extint 07:00 vector: this is the same as the corresponding bits in the i/o redirection table for that interrupt.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1135 intel ? ep80579 integrated processor 30.3.3 apic memory-mapped register details the apic is accessed via an indirect addressing scheme. two registers are visible by software for manipulation of most of the apic registers. these registers are mapped into memory space. the registers are shown in table 30-20 . 30.3.3.1 apic_idx - index register the index register selects which apic indirect register to be manipulated by software. the selector values for the indirect registers are listed in table 30-21 . software programs this register to select the desired apic internal register. table 30-20. summary of apic registers mapped in memory space? offset start offset end register id - description default value 0000h (4b) 0000h (4b) ?apic_idx - index register? on page 1135 00h 0010h (4b) 0010h (4b) ?apic_dat ? data register? on page 1136 00h 0040h (4b) 0040h (4b) ?apic_eoi - eoi register? on page 1136 00h table 30-21. apic_idx - index register description: view: ia f base address: fec00000h offset start: offset end: 0000h (4b) 0000h (4b) size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 apic_index this is an 8-bit pointer into the i/o apic indirect register table listed in section 30-20, ?summary of apic registers mapped in memory space?? . 00h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1136 order number: 320066-003us 30.3.3.2 apic_dat ? data register this register specifies the data to be read or written to the register pointed to by the index register. this register can be accessed only in dword quantities. the register is described in section 30.3.4 . 30.3.3.3 apic_eoi - eoi register when a write is issued to this register, the ioxapic checks the lower 8 bits written to this register, and compares it with the vector field for each entry in the i/o redirection table. when a match is found, rte.rirr for that entry is cleared. if multiple entries have the same vector, each of those entries has rte.rirr cleared. only bits 07:00 are used and bits 31:08 are ignored. table 30-22. apic_dat ? data register description: view: ia f base address: fec00000h offset start: offset end: 0010h (4b) 0010h (4b) size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 wdw this is a register for the data to be read or written to the apic indirect register pointed to by the index register ( table 30-21 ). 00h rw table 30-23. apic_eoi - eoi register description: view: ia f base address: fec00000h offset start: offset end: 0040h (4b) 0040h (4b) size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 08 reserved reserved. software must always write a value of 0 to these bits. 00h 07 : 00 rec redirection entry clear: when a write is issued to this register, the i/o apic checks this field, and compares it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry is cleared. 00h wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1137 intel ? ep80579 integrated processor 30.3.4 index registers table 30-24 lists the registers which can be accessed within the apic via the index (idx) register. when accessing these registers, accesses must be done a dword at a time, otherwise unspecified behavior results. software should not attempt to write to reserved registers. some reserved registers may return non-zero values when read. for example, software must never access byte 2 from the data register before accessing bytes 0 and 1. the hardware does not attempt to recover from a bad programming model in this case. note: the supported message delivery type is parallel, i.e., interrupt message from the ioxapic is delivered on the (parallel) fsb bus only. serial apic bus is not supported. table 30-24. apic index register space offset symbol register 00 apic_id identification 01 apic_vs version 02 - 0f - reserved 10 - 11h apic_rte[0] redirection table 0 12 - 13h apic_rte[1] redirection table 1 ... ... ... 5e - 5fh apic_rte[39] redirection table 39 60 - ffh - reserved table 30-25. summary of apic indexed registers offset start offset end register id - description default value 00h (4b) 00h (4b) ?apic_id ? identification register? on page 1138 0000h 01h (4b) 01h (4b) ?apic_vs - version register? on page 1138 00170020h 10h at 02h (4b) 11h at 02h (4b) ?apic_rte[0-39] - redirection table entry? on page 1139 xxxx0000000 1xxxxh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1138 order number: 320066-003us 30.3.4.1 apic_id ? identification register the apic id serves as a physical name of the apic. the apic bus arbitration id for the apic is derived from its i/o apic id. this register is reset to 0 on power-up reset. 30.3.4.2 apic_vs - version register each i/o apic contains a hardwired version register that identifies different implementation of apic and their versions. the maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this apic. table 30-26. apic_id ? identification register description: view: ia i win:idx: apic_wdw:apic_idx offset start: offset end: 00h (4b) 00h (4b) size: 32 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 28 reserved reserved 0h 27 : 24 aid apic identification: software must program this value before using the apic. 0h rw 23 : 16 reserved reserved 0h 15 scratchpad scratchpad 0h rw 14 reserved reserved. 0h 13 : 00 reserved reserved 0h table 30-27. apic_vs - version register (sheet 1 of 2) description: view: ia i win:idx: apic_wdw:apic_idx offset start: offset end: 01h (4b) 01h (4b) size: 32 bit default: 00170020h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 reserved reserved 0h 23 :16 mre maximum redirection entries: this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. this field reports either 17h or 27h depends on the value of gpio_irq_strap_sts field of extended test mode register3 register. ? 17h (to indicate 24 interrupts), when etr3.gpio_irq_strap_sts = 0 ? 27h (to indicate 40 interrupts), when etr3.gpio_irq_strap_sts = 1 (siu2_txd_ad18 strap configuration) 17h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1139 intel ? ep80579 integrated processor 30.3.4.3 apic_rte[0-39] - redirection table entry the redirection table has a dedicated entry for each interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. the apic responds to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is detected, a delivery status bit internally to the i/o apic is set. the state machine steps ahead and wait for an acknowledgment from the apic unit that the interrupt message was sent. only then will the i/o apic be able to recognize a new edge on that interrupt pin. that new edge only results in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt was not already pending at the destination.) all bits are undefined except for bits 47:17 = 0 and bit 16 = 1. 15 prq pin assertion register supported: indicate that the ioxapic does not implement the pin assertion register. 0h ro 14 : 08 reserved reserved 0h 07 : 00 vs version: identifies the implementation version as ioxapic. this field reports 20h in all io-apic modes (independent of number of enabled irq vectors). 20h ro table 30-27. apic_vs - version register (sheet 2 of 2) description: view: ia i win:idx: apic_wdw:apic_idx offset start: offset end: 01h (4b) 01h (4b) size: 32 bit default: 00170020h power well: core bit range bit acronym bit description sticky bit reset value bit access table 30-28. apic_rte[0-39] - redirection table entry (sheet 1 of 3) description: offset: vector 0: 10h-11h, vector 1: 12h-13h, vector 23: 3eh-3fh, vector 39: 5eh-5fh; vector n: (10h+ (n*2 in hex)) -(11h + (n*2 in hex)) view: ia i win:idx: apic_wdw:apic_idx vector 0 offset start: offset end: 10h at 02h (4b) 11h at 02h (4b) size: 64 bit a default: xxxx00000001xxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 63 : 56 did destination id: destination id of the local apic. x rw 55 : 48 edid extended destination id: extended destination id of the local apic. xrw 47 : 17 reserved reserved 0h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1140 order number: 320066-003us 16 msk mask: 0 = not masked; an edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = masked; interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the device withdrawing the interrupt before it is posted to the processor. it is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. 1rw 15 tm trigger mode: this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered 1 = level triggered xrw 14 rirr remote irr: this bit is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = reset when an eoi message matches the vct field. 1 = set when ioxapic sends the level interrupt message to the processor. xrw 13 pol polarity: this bit specifies the polarity of each interrupt input. 0 = active high 1 = active low xrw 12 ds delivery status: this field contains the current status of the delivery of this interrupt. writes to this bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been injected but delivery is not complete. for edge triggered interrupts , this bit indicates that an event has occurred but an interrupt message has yet to be delivered to its targeted destination. once the interrupt message is delivered, this bit will be cleared. for level triggered interrupts , this bit is set when the input event has occurred. this bit is cleared when the interrupt input event is removed. note that as long as the interrupt input event is active, this bit remains active regardless of whether this interrupt has been delivered or not. xro table 30-28. apic_rte[0-39] - redirection table entry (sheet 2 of 3) description: offset: vector 0: 10h-11h, vector 1: 12h-13h, vector 23: 3eh-3fh, vector 39: 5eh-5fh; vector n: (10h+ (n*2 in hex)) -(11h + (n*2 in hex)) view: ia i win:idx: apic_wdw:apic_idx vector 0 offset start: offset end: 10h at 02h (4b) 11h at 02h (4b) size: 64 bit a default: xxxx00000001xxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1141 intel ? ep80579 integrated processor 11 dsm destination mode: this field determines the interpretation of the destination field. 0 = physical. destination apic id is identified by bits 59:56. 1 = logical. destinations are identified by matching bit 63:56 with the logical destination in the destination format register and logical destination register in each local apic. xrw 10 : 08 dlm delivery mode: this field specifies how the apics listed in the destination field must act upon reception of this signal. delivery modes will only operate as intended when used in conjunction with a specific trigger mode. the encodings are: 000 fixed: deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode can be edge or level. 001 lowest priority: deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode can be edge or level. 010 smi: not supported. requires the interrupt to be programmed as edge triggered. 011 rreserved 100 nmi: not supported. 101 init: not supported. 110 reserved 111 extint: deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259a compatible interrupt controller. the inta cycle that corresponds to this extint delivery is routed to the external controller that is expected to supply the vector. requires the interrupt to be programmed as edge triggered. xrw 07 : 00 vct vector: this field contains the interrupt vector for this interrupt. values range between 10h and feh. xrw a. 64 bit each, accessed as two 32 bit quantities table 30-28. apic_rte[0-39] - redirection table entry (sheet 3 of 3) description: offset: vector 0: 10h-11h, vector 1: 12h-13h, vector 23: 3eh-3fh, vector 39: 5eh-5fh; vector n: (10h+ (n*2 in hex)) -(11h + (n*2 in hex)) view: ia i win:idx: apic_wdw:apic_idx vector 0 offset start: offset end: 10h at 02h (4b) 11h at 02h (4b) size: 64 bit a default: xxxx00000001xxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1142 order number: 320066-003us 30.4 pci interrupts via /pci express* when external devices through pci express* wish to generate an interrupt, they send the message defined in the pci express* specification for generating inta# - intd#. these are translated into internal assertions/deassertions of inta# - intd#. see section 17.1.5, ?interrupt configuration registers? on page 701 30.5 serial interrupt 30.5.1 overview the iich interrupt controller supports a serial irq scheme. this allows a single signal to be used to report interrupt requests. the signal used to transmit this information is shared between the interrupt controller and all peripherals that support serial interrupts. the signal line, serirq, is synchronous to the pci clock, and follows the sustained tri-state protocol that is used by legacy pci signals. this means that if a device has driven serirq low, it first drives it high synchronous to the pci clock and releases it after the following pci clock. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s - sample phase: signal driven low. ? r - recovery phase: signal driven high. ? t - turn-around phase: signal released. the iich supports a message for 21 serial interrupts. these represent the 15 isa (legacy) interrupts (irq0-1, 3-15), the four pci interrupts, and the control signals smi# and isa (legacy) iochk#. the serial irq protocol does not support the additional apic interrupts (20?39). the serial interrupt information is transferred using three types of frames: ? start frame: serirq line driven low by the interrupt controller to indicate the start of irq transmission. ? data frames: irq information transmitted by peripherals. the interrupt controller supports 21 data frames. ? stop frame: serirq line driven low by the interrupt controller to indicate end of transmission and next mode of operation. 30.5.2 start frame the serial irq protocol has two modes of operation which affect the start frame: ? continuous mode: the interrupt controller is solely responsible for generating the start frame. ? quiet mode: peripheral initiates the start frame, and the interrupt controller completes it. the mode that must first be entered when enabling the serial irq protocol is continuous mode. in this mode, the iich asserts the start frame. this start frame is four, six, or eight pci clocks wide based upon the serial irq control register(scnt.sfpw) field, bits 01:00 at 64h in device 31, function 0 configuration space. this is a polling mode. when the serial irq stream enters quiet mode (signaled in the stop frame), the serirq line remains inactive and pulled up between the stop and start frame until a peripheral drives the serirq signal low. the iich senses the line low and continues to drive it low for the remainder of the start frame. since the first pci clock of the start
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1143 intel ? ep80579 integrated processor frame was driven by the peripheral in this mode, the iich drives the serirq line low for one pci clock less than in continuous mode. this mode of operation allows for a quiet, and therefore lower power, operation. 30.5.3 data frames once the start frame has been initiated, the serirq peripherals start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly three phases of one clock each. the three phases are: ? sample phase: during this phase, the serirq device drives serirq low if the corresponding interrupt signal is low. if the corresponding interrupt is high, then the serirq devices tri-state the serirq signal. the serirq line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). a low level during the irq0 ? 1 and irq2 ? 15 frames indicates that an active-high isa (legacy) interrupt is not being requested, but a low level during the pci int[a:d], smi#, and isa (legacy) iochk# frame indicates that an active-low interrupt is being requested. ? recovery phase: during this phase, the device drives the serirq line high if in the sample phase it was driven low. if it was not driven in the sample phase, it is tri-stated in this phase. ? turn-around phase: the device tri-states serirq. 30.5.4 stop frame after all the data frames, a stop frame is driven by the iich. the serirq signal is driven low for two or three pci clocks. the number of clocks is determined by the serirq configuration register (scnt.md field in d31, f0 configuration space). the number of clocks determines the next mode as shown in ta b l e 3 0 - 2 9 . 30.5.5 serial interrupts not supported via serirq there are three interrupts seen through the serial stream that are not supported by the iich. these interrupts are generated internally, and are not sharable with other devices within the system. these interrupts are: ? irq0:heartbeat interrupt generated off of the internal 8254 counter 0. ? irq8#:rtc interrupt can only be generated internally. ? irq13:..... floating point error interrupt generated off of the processor assertion of ferr#. the iich ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. table 30-29. stop frame definition stop frame width next mode 2 pci clocks quite mode: any serirq device initiates a start frame 3 pci clocks continuous mode: only the iich may initiate a start frame
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1144 order number: 320066-003us 30.5.6 special notes on irq14 and irq15 irq14 and irq15 are special interrupts, used by the sata controller when it is not running in native ide mode. if in a legacy mode, irq14 and irq15 are not accepted from the serial stream, and instead come from these controllers. if the controllers are in native mode, these interrupts are used by the interrupt controller. 30.5.7 data frame format ta b l e 3 0 - 3 0 shows the format of the data frames for the associated interrupts. for the legacy (pci) interrupts (a ? d), the output from the iich is anded with the legacy (pci) input signal. this way, the interrupt can be signaled via both the legacy (pci) interrupt input signal and via the serirq signal (they are shared). table 30-30. data frame format data frame # interrupt clocks past start frame comment 1 irq0 2 ignored. irq0 can only be generated via the internal 8524. 2 irq1 5 before port 60h latch 3 smi# 8 causes smi# if low. sets bit 15 in the smi_sts register. 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9 irq8 26 ignored. irq8# can only be generated internally. 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 before port 60h latch 14 irq13 41 ignored. irq13 can only be generated from ferr#. 15 irq14 44 not attached to pata or sata logic 16 irq15 47 not attached to pata or sata logic 17 iochck# 50 same as isa (legacy) iochck# going active. 18 pci inta# 53 drive pirqa# 19 pci intb# 56 drive pirqb# 20 pci intc# 59 drive pirqc# 21 pci intd# 62 drive pirqd#
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1145 intel ? ep80579 integrated processor 31.0 8254 timers 31.1 overview the iich contains three counters which have fixed uses. all registers and functions associated with the 8254 timers are in the core power well. the 8254 unit is clocked by a 14.31818 mhz clock. there is one signal associated with the 8254. it is used to drive the pc speaker. 31.2 8254 timer i/o-mapped register details note: for more information on the format of the register description tables that follow in this chapter, see section 7.1.1, ?register description tables? on page 183 . table 31-1. spkr signal signal name s3 s5 spkr off off table 31-2. summary of 8254 timer registers mapped in i/o space offset start offset end register id - description default value 43h 43h ?offset 43h: tcw - timer control word register? on page 1146 xxh 40h at 01h 40h at 01h ?offset 40h: tsb[0-2] - interval timer status byte format register? on page 1147 0xxxxxxxb 40h at 01h 40h at 01h ?offset 40h: tcap[0-2] - interval timer counter access ports register? on page 1148 xxh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1146 order number: 320066-003us 31.2.1 timer registers 31.2.1.1 offset 43h: tcw - timer control word register this register is programmed prior to any counter being accessed to specify counter modes. following reset, the control words for each register are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. there are two special commands that can be issued to the counters through this register, the read back command ( section 31.5.3 ) and the counter latch command ( section 31.5.2 ). when these commands are chosen, several bits within this register are redefined. these register formats are described in section 31.5 . 31.2.1.2 offset 40h: tsb[0-2] - interval timer status byte format register each counter's status byte can be read following a read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. the status byte returns the values shown in ta b l e 3 1 - 4 . table 31-3. offset 43h: tcw - timer control word register description: view: ia f base address: 0000h (io) offset start: offset end: 43h 43h size: 8 bit default: xxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :06 cntsel counter select: the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits[07:06] are both one. 00 counter 0 select 01 counter 1 select 10 counter 2 select 11 read back command xxb wo 05 :04 rwmd read/write mode selection: these bits are the read/ write control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2) 00 counter latch command 01 read/write least significant byte (lsb) 10 read/write most significant byte (msb) 11 read/write lsb then msb xxb rws 03 :01 cntmd counter mode selection: these bits select one of six possible modes of operation for the selected counter. 000 0 out signal on end of count (=0) 001 1 hardware retriggerable one-shot x10 2 rate generator (divide by n counter) x11 3 square wave output 100 4 software triggered strobe 101 5 hardware triggered strobe xxxb wo 00 bcdcnt binary/bcd countdown select: 0 = binary countdown is used. the largest possible binary count is 2 16 . 1 = binary coded decimal (bcd) count is used. the largest possible bcd count is 10 4 . xb wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1147 intel ? ep80579 integrated processor table 31-4. offset 40h: tsb[0-2] - interval timer status byte format register description: these i/o ports can also function as tcap (see section 31.2.1.3 ) based on the settings of tcw (see section 31.2.1.1 ). view: ia f base address: 0000h (io) offset start: offset end: 40h at 01h 40h at 01h size: 8 bit default: 0xxxxxxxb power well: core bit range bit acronym bit description sticky bit reset value bit access 7cops counter out pin state: 0 = the out pin of the counter is a 0 1= the out pin of the counter is a 1 0b ro 6crs count register status: this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value is incorrect. 0 = count has been transferred from cr to ce and is available for reading. 1 = null count. count has not been transferred from cr to ce and is not yet available for reading. xb ro 05 :04 rwss read/write selection status: these reflect the read/ write selection made through bits[05:04] of the control register. the binary codes returned during the status read match the codes used to program the counter read/write selection. 00 counter latch command 01 read/write least significant byte (lsb) 10 read/write most significant byte (msb) 11 read/write lsb then msb xxb ro 03 :01 mss mode selection status: these bits return the counter mode programming. the binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 0 out signal on end of count (=0) 001 1 hardware retriggerable one-shot x10 2 rate generator (divide by n counter) x11 3 square wave output 100 4 software triggered strobe 101 5 hardware triggered strobe xxxb ro 00 cts countdown type status: this bit reflects the current countdown type; ether 0 for binary countdown or a 1 for binary coded decimal (bcd) countdown. xb ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1148 order number: 320066-003us 31.2.1.3 offset 40h: tcap[0-2] - interval timer counter access ports register 31.3 counters 31.3.1 counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value and repeats the cycle, alternately asserting and negating irq0. 31.3.2 counter 1, refresh request signal this counter provides the refresh request signal and is typically programmed for mode 2 operation and only impacts the period of the ref_toggle bit in port 61. the initial count value is loaded one counter period after being written to the counter i/o address. the ref_toggle bit has square wave behavior (alternate between 0 and 1) and toggles at a rate based on the value in the counter. programming the counter to anything other than mode 2 results in undefined behavior for the ref_toggle bit. 31.3.3 counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h. table 31-5. offset 40h: tcap[0-2] - interv al timer counter access ports register description: these i/o ports can also function as tsb (see section 31.2.1.2 ) based on the settings of tcw (see section 31.2.1.1 ). view: ia f base address: 0000h (io) offset start: offset end: 40h at 01h 40h at 01h size: 8 bit default: xxh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 cntp counter port: each counter port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register at port 43h. the counter port is also used to read the current count from the count register, and return the status of the counter programming following a read back command. xxh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1149 intel ? ep80579 integrated processor 31.3.4 counter operating modes ta bl e 3 1 - 6 lists the six operating modes for the interval counters. 31.4 timer programming the counter/timers are programmed as follows: 1. write a control word to select a counter. 2. write an initial count for that counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. 4. repeat with other counters. only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting is affected as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter is loaded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command: specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command: latches the current count so that it can be read by the system. the countdown process continues. ? read back command: reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. table 31-6. counter operating modes mode function description 0 out signal on end of count (=0) output is ?0?. when count goes to 0, output goes to ?1? and stays at ?1? until counter is reprogrammed. 1 hardware retriggerable one-shot output is ?0?. when count goes to 0, output goes to ?1? for one clock time. 2 rate generator (divide by n counter) output is ?1?. output goes to ?0? for one clock time, then back to ?1? and counter is reloaded. 3square wave output output is ?1?. output goes to ?0? when counter rolls over, and counter is reloaded. output goes to ?1? when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is ?1?. output goes to ?0? when count expires for one clock time. 5 hardware triggered strobe output is ?1?. output goes to ?0? when count expires for one clock time.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1150 order number: 320066-003us 31.5 reading from the interval timer it is often desirable to read the value of a counter without disturbing the count in progress. there are three methods for reading the counters: a simple read operation, counter latch command, and the read-back command. each is explained in the following sections. with the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read sequentially. read, write, or programming operations for other counters may be inserted between them. 31.5.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count can be stopped by writing to the gate bit in port 61h. 31.5.2 counter latch command the counter latch command ( ta b l e 3 1 - 7 ), written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. the count value is then read from each counter's count register through the counter port?s access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count is held in the latch until it is read or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of the counters on the fly without affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. counter latch commands do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read is the count at the time the first counter latch command was issued. table 31-7. counter latch command bits description 07:06 counter selection: these bits select the counter for latching. 00 counter 0 01 counter 1 10 counter 2 11 the write is interpreted as a read back command. 05:04 counter latch command: write ?00? to select the counter latch command. 03:00 reserved. must be 0.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1151 intel ? ep80579 integrated processor 31.5.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and nu ll count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter outputs at one time. this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's latched count is held until it is read or reprogrammed. once read, a co unter is unlatched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. if both are latched, the first read operation from that counter returns the latched status. the next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. subsequent reads return an unlatched count. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/ o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored. both count and status of the selected counters may be latched simultaneously in any or all of the counters by selecting the counter during the register write. this is functionally the same as issuing two consecutive, separate read back commands. if multiple count and/or status read back commands are issued to the same counters without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter will return the latched status, regardless of which was latched first. the next one or two reads, depending on whether the counter is programmed for one or two type counts, return the latched count. subsequent reads return unlatched count. table 31-8. read back command bits description 07:06 read back command: must be ?11? to select the read back command. 05 latch count of selected counters: 0 = current count value of the selected counters are latched 1 = current count value of the selected counters are not latched 04 latch status of selected counters: 0 = status of the selected counters are latched 1 = status of the selected counters are not latched 03 counter 2 select: 0 = counter 2 count and/or status are not latched 1 = counter 2 count and/or status are latched 02 counter 1 select: 0 = counter 1 count and/or status are latched 1 = counter 1 count and/or status are not latched 01 counter 0 select: 0 = counter 0 count and/or status are latched. 1 = counter 0 count and/or status are not latched 00 reserved. must be 0.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1152 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1153 intel ? ep80579 integrated processor 32.0 high precision event timers note: this section documents the cmi-specific behavior and the generic hpet (high precision event timers) specification, revision 1.0a. 32.1 overview this function provides a set of timers that can be used by the operating system. the timers are defined such that in the future, the os may be able to assign specific timers to be used directly by specific applications. each timer can be configured to cause a separate interrupt. this specification allows for a block of 32 timers, with support for up to eight blocks, for a total of 256 timers. the timers are implemented as a single counter with a set of comparators. the counter increases monotonically. each timer includes a value register and a comparator. each individual timer can generate an interrupt when the value in its value register matches value in the main counter. some of the timers can be enabled to generate a periodic interrupt. the registers associated with these timers are mapped to a memory space (much like the i/o apic). however, it is not implemented as a standard pci function. the bios reports to the operating system the location of the register space. the hardware can support an assignable decode space; however, the bios sets this space prior to handing it over to the os. it is not expected that the os move the location of these timers once they are set by the bios. note: for additional information see section 1.3, ?referenced documents and related websites? . 32.2 register details the timer registers are memory mapped in a non-indexed scheme. this allows the cpu to directly access each register without having to use an index register. the timer register space is 1024 bytes. the registers are generally aligned on 64-bit boundaries. general behavioral rules: ? software must not attempt to read or write across register boundaries. for example, a 32-bit access must be to offset x0h, x4h, x8h, or xch. ? 32-bit accesses must not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0ah, 0bh, 0dh, 0eh, or 0fh. any accesses to these offsets results in an unexpected behavior and may result in a master abort. however, these accesses may not result in system hangs. ? 64-bit accesses can only be to x0h and must not cross 64-bit boundaries. ? software must not write to read-only registers. ? software must not expect any particular or consistent value when reading reserved registers or bits. ? the timer register space is memory mapped to a 1 k block.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1154 order number: 320066-003us ? there are four possible memory address ranges beginning at: 1. fed0_0000h 2. fed0_1000h 3. fed0_2000h 4. fed0_3000h ? the choice of address ranges will be selected by configuration bits in the high performance timer configuration register (in the memory-mapped chipset configuration area) table 17-26, ?offset 3404h: hptc - high performance precision timer configuration register? on page 705 . ? all registers are implemented in the core well, and all bits are reset by pltrst#. ? reads to reserved registers or bits return a value of 0. note: reads to reserved registers or bits returns a value of 0. note: software must not attempt to lock the memory-mapped i/o ranges for high-precision timers. if attempted, the lock is not honored, which means potential deadlock conditions may occur. table 32-1. summary of hpet registers mapped in memory space offset start offset end register id - description default value 000h 007h ?offset 000h: gcap_id - general capabilities and id register? on page 1155 0429b17f808 6a201h 010h 017h ?offset 010h: gen_conf - general configuration register? on page 1156 00000000000 00000h 020h 027h ?offset 020h: gintr_sta - general interrupt status register? on page 1157 00000000000 00000h 0f0h 0f7h ?offset 0f0h: main_cnt - main counter value register? on page 1158 xh 100h at 20h 107h at 20h ?offset 100h: hptcc[0-2] - timer n configuration and capabilities register? on page 1159 xh 108h at 20h 10fh at 20h ?offset 108h: hptcv[0-2] - timer n comparator value register? on page 1163 xh
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1155 intel ? ep80579 integrated processor 32.2.1 register descriptions 32.2.1.1 offset 000h: gcap_id - general capabilities and id register general behavioral rules: ? writes to this register must not be attempted by software. ? software can read the various bytes in this register using 32-bit or 64-bit accesses. ? 32-bit accesses can be done to offset 00h or 04h, but not to offsets 01h, 02h, 03h, 05h, 06h, or 07h. ? 64-bit accesses can only be done to 00h. table 32-2. offset 000h: gcap_id - general capabilities and id register description: view: ia f base address: hptc offset start: offset end: 000h 007h size: 64 bit default: 0429b17f8086a201h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :32 counter_ clk_per_cap main counter tick period: this read-only field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). this returns 0429b17fh when read indicating a period of 69841279 fs (69.841279 ns). 0429b17fh ro 31 :16 vendor_id_ cap vendor id capability: these bits return 8086h when read. this is a 16-bit value assigned to intel. 8086h ro 15 leg_rt_cap legacy replacement rout capable: this bit is always one when read, as the legacy replacement interrupt rout is supported. 1h ro 14 reserved reserved: this bit returns zero when read. 0h 13 count_size_c ap counter size capability: indicates that the main counter is 64 bits wide. this bit returns one when read. 1h ro 12 :08 num_tim_cap number of timer capability: this field indicates the number of timers in this block. this value in this field is 02h = three timers. 02h ro 07 :00 rev_id revision identification: this field indicates which revision of the specification is implemented. the value in this field is 01h. 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1156 order number: 320066-003us 32.2.1.2 offset 010h: gen_conf - general configuration register general behavioral rules: ? software can access the various bytes in this register using 32-bit or 64-bit accesses. ? 32-bit accesses can be done to offset 010h or 014h, but not to offsets 011h, 012h, 013h, 015h, 016h, or 017h. ? 64-bit accesses can only be done to 010h. table 32-3. offset 010h: gen_conf - general configuration register description: view: ia f base address: hptc offset start: offset end: 010h 017h size: 64 bit default: 0000000000000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :02 reserved reserved: 000000000000 h ro 01 leg_rt_cnf legacy replacement route: if the enable_cnf and leg_rt_cnf bits are set, then the interrupts are routed as follows: timer 0 is routed to irq0 in 8259 or irq2 in the i/o apic timer 1 is routed to irq8 in 8259 or irq8 in the i/o apic timer 2-n is routed as per the routing in the timer n config registers. 0 = if the leg_rt_cnf bit is not set, the individual routing bits for each of the timers are used. 1 = legacy rout: if the leg_rt_cnf bit is set, the individual routing bits for timers 0 and 1 (apic or fsb) have no impact. 0b rw 00 enable_cnf overall enable: 0 = the main counter halts (does not increment) and no interrupts are caused by any of these timers. 1 = enable any of the timers to generate interrupts. for level-triggered interrupts, if an interrupt is pending when the enable_cnf bit is changed from 1 to 0, the interrupt status indications (in the various txx_int_sts bits) are not cleared. software must write to the txx_int_sts bits to clear the interrupts. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1157 intel ? ep80579 integrated processor 32.2.1.3 offset 020h: gintr_sta - general interrupt status register general behavioral rules: ? software can access the various bytes in this register using 32-bit or 64-bit accesses. ? 32-bit accesses can be done to offset 020h or 024h, but not to offsets 021h, 022h, 023h, 025h, 026h, or 027h. ? 64-bit accesses can only be done to 020h. table 32-4. offset 020h: gintr_sta - general interrupt status register description: view: ia f base address: hptc offset start: offset end: 020h 027h size: 64 bit default: 0000000000000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :03 reserved reserved 00h ro 02 t02_int_sts timer 2 interrupt active: same functionality as timer 0. 0h rw 01 t01_int_sts timer 1 interrupt active: same functionality as timer 0. 0h rw 00 t00_int_sts timer 0 interrupt active: the functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: if set to level-triggered mode: this bit is set by hardware if the corresponding timer interrupt is active. once the bit is set, it can be cleared by software writing a 1 to the same bit position. writes of 0 to this bit have no effect. if set to edge-triggered mode: this bit must be ignored by software. software must always write 0 to this bit. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1158 order number: 320066-003us 32.2.1.4 offset 0f0h: main_cnt - main counter value register general behavioral rules: ? software can access the various bytes in this register using 32-bit or 64-bit accesses. ? 32-bit accesses can be done to offset 0f0h or 0f4h. ? 32-bit accesses must not be done starting at: 0f1h, 0f2h, 0f3h, 0f5h, 0f6h, or 0f7h. ? 64-bit accesses can be done to 0f0h. ? writes to this register must only be done while the counter is halted. ? reads to this register return the current value of the main counter. ? 32-bit counters will always return zero for the upper 32 bits of this register. ? if 32-bit software attempts to read a 64-bit counter, it must first halt the counter. since this will delay the interrupts for all of the timers, this must be done only if the consequences are understood. it is strongly recommended that 32-bit software only operate the timer in 32-bit mode. table 32-5. offset 0f0h: main_cnt - main counter value register description: view: ia f base address: hptc offset start: offset end: 0f0h 0f7h size: 64 bit default: xh power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :00 counter_val_ 63_0 counter value: bits 63:00 of the counter. notes: 1. writes to this register must only be done while the counter is halted. 2. reads to this register return the current value of the main counter. 3. 32-bit counters always return zero for the upper 32 bits of this register. 4. if 32-bit software attempts to read a 64-bit counter, it must first halt the counter. since this delays the interrupts for all of the timers, this must be done only if the consequences are understood. it is strongly recommended that 32- bit software only operates the timer in 32-bit mode. 5. reads to this register are monotonic. no two consecutive reads return the same value. the second of two reads always returns a larger value, unless the timer has rolled over to 0. xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1159 intel ? ep80579 integrated processor 32.2.1.5 offset 100h: hptcc[0-2] - timer n configuration and capabilities register general behavioral rules: ? software can access the various bytes in this register using 32-bit or 64-bit accesses. ? 32-bit accesses can be done to offset 1x0h or 1x4h. 64-bit accesses can be done to 1x0h. ? 32-bit accesses must not be done to 1x1h, 1x2h, 1x3h, 1x5h, 1x6h, 1x7h. note: the letter n can be 0, 1 or 2, referring to timer 0, 1 or 2. table 32-6. offset 100h: hptcc[0-2] - timer n configuration and capabilities register (sheet 1 of 3) description: timer 0: 100 ? 107h, timer 1: 120 ? 127h, timer 2: 140 ? 147h, timer n : (20h * n ) +100h - (20h * n ) + 107h view: ia f base address: hptc offset start: offset end: 100h at 20h 107h at 20h size: 64 bit default: xh power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :56 reserved reserved: these bits return 0 when read. 0h ro 55 :52 timern_int_r out_cap timer interrupt route capability: timer 0, 1:bits 52, 53, 54, and 55 in this field (corresponding to irq 20, 21, 22, and 23) have a value of 1. writes will have no effect. timer 2:bits 43, 52, 53, 54, and 55 in this field (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. writes will have no effect. if irq 11 is used for high precision event timer #2, software must ensure irq 11 is not shared with any other devices to guarantee the proper operation of high precision event timer #2. xro 51 :44 reserved reserved: these bits return 0 when read. 0h ro 43 timern_int_r out_cap timer interrupt route capability: timer 0, 1:bits 52, 53, 54, and 55 in this field (corresponding to irq 20, 21, 22, and 23) have a value of 1. writes will have no effect. timer 2:bits 43, 52, 53, 54, and 55 in this field (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. writes will have no effect. if irq 11 is used for high precision event timer #2, software must ensure irq 11 is not shared with any other devices to guarantee the proper operation of high precision event timer #2. xro 42 :14 reserved reserved: these bits return 0 when read. 0h ro note: reads or writes to unimplemented timers must not be attempted. reads from any unimplemented registers return an undetermined value.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1160 order number: 320066-003us 13 :09 timern_int_r out_cnf interrupt route: (where n is the timer number: 00 to 31). this 5-bit field indicates the routing for the interrupt to the i/o apic. a maximum value of 32 interrupts is supported. the default is 00h. software writes to this field to select which interrupt in the i/o (x)apic used for this timer?s interrupt. if the value is not supported by this particular timer, then the value read back does not match what is written. the software must only write valid values. notes: 1. if the legacy replacement rout bit is set, then timers 0 and 1 have a different routing, and this bit field has no effect for those two timers. 2. timer 0,1: the software is responsible to make sure it programs a valid value (decimal 20, 21, 22, or 23) for this field. the logic does not check the validity of the value written. 3. timer 2: the software is responsible to make sure it programs a valid value (decimal 11, 20, 21, 22, or 23) for this field. the logic does not check the validity of the value written. xh rw 08 timern_32mod e_cnf 0 = timer n 32-bit mode: (where n is the timer number: 00 to 31). software can set this bit to force a 64-bit timer to behave as a 32-bit timer. timer 0: bit is read/write and defaults to 0.64 bit 1 = 32 bit timers 1 and 2: hardwired to 0. writes have no effect (since these two timers are 32 bits). xh rw or ro 07 reserved reserved: 0b ro 06 timern_val_s et_cnf timer n value set: software uses this bit only for timers that have been set to periodic mode. 0 = disabled. software does not have to write this bit back to 0 (it automatically clears). 1 = by writing this bit to a 1, the software is allowed to directly set the timer?s accumulator. note: software must not write a 1 to this bit position if the timer is set to non-periodic mode. note: this bit returns zero when read. writes will only have an effect for timer 0 if it is set to periodic mode. writes have no effect for timers 1 and 2. xh rw or ro 05 timern_ size_cap timer n size: (where n is the timer number: 00 to 31). this read-only field indicates the size of the timer. 0 = 32 bits 1 = 64 bits timer 0: value is 1 (64 bits). timers 1 and 2: value is 0 (32 bits). xh ro 04 timern_ per_int_ cap periodic interrupt capable: (where n is the timer number: 00 to 31). if this read-only bit is 1, then the hardware supports a periodic mode for this timer?s interrupt. timer 0: hardwired to 1 (supports the periodic interrupt). timers 1 and 2: hardwired to 0 (does not support periodic interrupts), so the bit is always read as zero. xh ro table 32-6. offset 100h: hptcc[0-2] - timer n configuration and capabilities register (sheet 2 of 3) description: timer 0: 100 ? 107h, timer 1: 120 ? 127h, timer 2: 140 ? 147h, timer n : (20h * n ) +100h - (20h * n ) + 107h view: ia f base address: hptc offset start: offset end: 100h at 20h 107h at 20h size: 64 bit default: xh power well: core bit range bit acronym bit description sticky bit reset value bit access note: reads or writes to unimplemented timers must not be attempted. reads from any unimplemented registers return an undetermined value.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1161 intel ? ep80579 integrated processor 32.2.1.6 offset 108h: hptcv[0-2] - timer n comparator value register general behavioral rules: ? software can access the various bytes in this register using 32-bit or 64-bit accesses. ? 32-bit accesses can be done to offset 1x8h or 1xch. 64-bit accesses can be done to 1x8h. ? 32-bit accesses must not be done to 1x9h, 1xah, 1xbh, 1xdh, 1xeh, or 1xfh. ? reads to this register return the current value of the comparator. ? if the timer is configured to non-periodic mode: ? writes to this register load the value against which the main counter must be compared for this timer. ? when the main counter equals the valu e last written to this register, the corresponding interrupt can be generated (if so enabled). 03 timern_ type_cnf timer n type: (where n is the timer number: 00 to 31). timer 0:bit is read/write. 0 = disable timer to generate a periodic interrupt. 1 = enable timer to generate a periodic interrupt. timers 1, 2: hardwired to 0. so bit access is read only. xh rw or ro 02 timern_int_en b_cnf timer n interrupt enable: (where n is the timer number: 00 to 31). this bit must be set to enable timer n to cause an interrupt when it times out. 0 = disable. the timer still counts but does not cause an interrupt. 1 = enable. 0h rw 01 timern_int_ty pe_cnf timer interrupt type: (where n is the timer number: 00 to 31) 0 = the timer interrupt is edge triggered. this means that an edge-type interrupt is generated. if another interrupt occurs, another edge is generated. 1 = the timer interrupt is level triggered. this means that a level-triggered interrupt is generated. the interrupt is held active until it is cleared by writing to the bit in the general interrupt status register. if another interrupt occurs before the interrupt is cleared, the interrupt remains active. 0h rw 00 reserved reserved: this bit returns zero when read. 0h ro table 32-6. offset 100h: hptcc[0-2] - timer n configuration and capabilities register (sheet 3 of 3) description: timer 0: 100 ? 107h, timer 1: 120 ? 127h, timer 2: 140 ? 147h, timer n : (20h * n ) +100h - (20h * n ) + 107h view: ia f base address: hptc offset start: offset end: 100h at 20h 107h at 20h size: 64 bit default: xh power well: core bit range bit acronym bit description sticky bit reset value bit access note: reads or writes to unimplemented timers must not be attempted. reads from any unimplemented registers return an undetermined value.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1162 order number: 320066-003us ? the value in this register does not change based on the interrupt being generated. ? if the timer is configured to periodic mode: ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? after the main counter equals the value in this register, the value in this register is increased by the value last written to the register. ? for example, if the value written to the register is 00000123h, then: ? an interrupt is generated when the main counter reaches 00000123h. ? the value in this register is then adjusted by the hardware to 00000246h. ? another interrupt is generated when the main counter reaches 00000246h. ? the value in this register is then adjusted by the hardware to 00000369h. ? as each periodic interrupt occurs, the value in this register increments. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value wraps around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000, then after the next interrupt the value changes to 00010000h. ? default value for each timer is all 1's for the bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1163 intel ? ep80579 integrated processor table 32-7. offset 108h: hptcv[0-2] - timer n comparator value register description: timer 0: 108 - 10fh timer 1: 128 - 12fh timer 2: 148 - 14fh view: ia f base address: hptc offset start: offset end: 108h at 20h 10fh at 20h size: 64 bit default: xh power well: core bit range bit acronym bit description sticky bit reset value bit access 63 :00 timn_comp timer compare value: reads to this register return the current value of the comparator. timers 0, 1, or 2 are configured to non-periodic mode: writes to this register load the value against which the main counter must be compared for this timer. ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? the value in this register does not change based on the interrupt being generated. timer 0 is configured to periodic mode: ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? after the main counter equals the value in this register, the value in this register is increased by the value last written to the register. ? for example, if the value written to the register is 00000123h, then: 1. an interrupt is generated when the main counter reaches 00000123h. 2. the value in this register is then adjusted by the hardware to 00000246h. 3. another interrupt is generated when the main counter reaches 00000246h. 4. the value in this register is then adjusted by the hardware to 00000369h. ? as each periodic interrupt occurs, the value in this register increments. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value wraps around through zero. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000, then after the next interrupt the value changes to 00010000h. default value for each timer is all 1s for the bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh. xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1164 order number: 320066-003us 32.3 theory of operation 32.3.1 timer accuracy rules ? the timers are expected to be accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. ? within any 100 microsecond period, the timer is permitted to report a time that is up to two ticks too early or too late. each tick must be less than or equal to 100 ns; this represents an error of less than 0.2%. ? the timer must be monotonic. it must never return the same value on two consecutive reads (unless the counter has rolled over and actually reached the same value). ? the main counter is clocked by the 14.31818 mhz clock, synchronized into the 66.666 mhz domain. this results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. the accuracy of the main counter is as accurate as the 14.3818 mhz clock. 32.3.2 interrupt mapping the interrupts associated with the various timers have several interrupt mapping options. when reprogramming the hpet (high precision event timer) interrupt routing scheme (leg_rt_cnf bit in the general config register), a spurious interrupt may occur. this is because the other source of the interrupt (8254 timer) may be asserted. software must mask interrupts prior to clearing the leg_rt_cnf bit. mapping option 1: legacy replacement option in this case, the legacy rout bit (leg_rt_cnf) is set. this forces the mapping found in ta b l e . mapping option 2: standard option in this case, the legacy rout bit (leg_rt_cnf) is zero. each timer has its own routing control. the interrupts can be routed to various interrupts in the i/o apic. a capabilities field indicates which interrupts are valid options for the routing. if a timer is set for edge-triggered mode, the timers must not be shared with any pci interrupts. supported interrupt values are irq 20, 21, 22, and 23. table 32-8. legacy replacement routing timer 8259 mapping apic mapping comment 0 irq0 irq2 in this case, the 8254 timer does not cause any interrupts 1 irq8 irq8 in this case, the rtc does not cause any interrupts. 2 as per irq routing field as per irq routing field
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1165 intel ? ep80579 integrated processor 32.3.3 periodic vs. non-periodic modes 32.3.3.1 non-periodic mode this mode can be thought of as creating a one-shot. timer 0 is configurable to 32-bit or 64-bit mode (default), whereas timers 1 and 2 only support 32-bit mode. all three timers support non-periodic mode. when a timer is set up for non-periodic mode, it generates a value in the main counter that matches the value in the timer?s comparator register. also, another interrupt will be generated when the main counter matches the value in the timer?s comparator register after a wrap around. during run-time, the value in the timer?s comparator value register is not changed by the hardware. software can, of course, change the value. the timer 0 comparator value register cannot be programmed reliably by a single 64- bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. if the actual timer 0 comparator value needs to be reinitialized, then the following software solution always works regardless of the environment: 1. set the lower 32 bits of the timer0 comparator value register. 2. set the upper 32 bits of the timer0 comparator value register. warning: software must be careful when programming the comparator registers. if the value written to the register is not sufficiently far in the future, then the counter may pass the value before it reaches the register and the interrupt will be missed. the bios will pass a data structure to the os to indicate that the os must not attempt to program the periodic timer to a rate faster then x. for the cmi, x is 5 microseconds. every timer is required to support the non-periodic mode of operation. 32.3.3.2 periodic mode when a timer is set up for periodic mode, the software writes a value in the timer?s comparator value register. when the main counter value matches the value in the timer?s comparator value register, an interrupt is generated. the hardware then automatically increases the value in the comparator value register by the last value written to that register. to make the periodic mode work properly, the main counter is typically written with a value of 0 so that the first interrupt occurs at the right point for the comparator. if the main counter is not set to 0, interrupts may not occur as expected. during run-time, the value in the timer?s comparator value register can be read by software to find out when the next periodic interrupt will be generated (not the rate at which it generates interrupts). software is expected to remember the last value written to the comparator?s value register (the rate at which interrupts are generated). if software wants to change the periodic rate, it must write a new value to the comparator value register. at the point when the timer?s comparator indicates a match, this new value is added to derive the next matching point. warning: if the software resets the main counter, the value in the comparator?s value register needs to reset as well. this can be done by setting the timern_val_set_cnf bit. again, to avoid race conditions, this must be done with the main counter halted. as the timer period approaches zero, the interrupts associated with the periodic timer may not
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1166 order number: 320066-003us get completely serviced before the next timer match occurs. interrupts may get lost and/or system performance may be degraded in this case. each timer is not required to support the peri odic mode of operation. a capabilities bit indicates if the particular timer supports periodic mode. the reason for this is that supporting the periodic mode adds a significant number of gates. for cmi, only timer 0 supports periodic mode. the following usage model is expected: 1. software clears the enable_cnf bit to prevent any interrupts. 2. software clears the main counter by writing a value of 00h to it. 3. software sets the timer0_val_set_cnf bit. 4. software writes the new value in the timer0_comparator_val register. 5. software sets the enable_cnf bit to enable interrupts. the timer 0 comparator value register cannot be programmed reliably by a single 64- bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. if the actual timer 0 comparator value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. set timer0_val_set_cnf bit 2. set the lower 32 bits of the timer0 comparator value register 3. set timer0_val_set_cnf bit 4. set the upper 32 bits of the timer0 comparator value register 32.3.4 enabling the timers the bios or operating system pnp code must rout the interrupts. this includes the legacy rout bit, interrupt rout bit (for each timer), interrupt type (to select the edge or level type for each timer). the device driver code must do the following for an available timer: 1. set the overall enable bit (offset 04h, bit 0). 2. set the timer type field (selects one-shot or periodic). 3. set the interrupt enable. 4. set the comparator value. 32.3.5 interrupt levels interrupts directed to the 8259s are active high. see chapter 30.0, ?interrupts,? for information regarding the polarity programming of the i/o apic for detecting internal interrupts. if the interrupts are mapped to the i/o apic and set for level-triggered mode, they can be shared with pci interrupts. if more than one timer is configured to share the same irq (using the timern_int_rout_cnf fields), then the software must configure the timers to level-triggered mode. edge-triggered interrupts cannot be shared. 32.3.6 handling interrupts if each timer has a unique interrupt and the timer has been configured for edge- triggered mode, then there are no specific steps required. no read is required to process the interrupt.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1167 intel ? ep80579 integrated processor if a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. this is done by reading the interrupt status register and writing a one back to the bit position for the interrupt to be cleared. independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. if a timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. 32.3.7 unloading device driver issues when unloading device drivers for the hpet high precision event timer, some precautions may be needed. for example, if the legacy routing is used, when the hpet high precision event timer is disabled, a spurious interrupt could occur. the os must mask interrupts prior to clearing the leg_rt_cnf bit.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1168 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1169 intel ? ep80579 integrated processor 33.0 serial i/o unit and watchdog timer 33.1 overview the serial i/o unit and watchdog timer (siw) is similar to currently available super i/ o controllers. it is specifically designed for integration into the iich. it is connected via the lpc bus and currently consists of two uarts, a serial interrupt controller, a watchdog timer and the lpc interface. 33.2 features lpc interface ? multiplexed command, address and data bus. ? 8-bit i/o transfers. ? 16-bit address qualification for i/o transactions. ? serial irq interface compatible with serialized irq support for pci systems. serial port ? two full function 16550 compatible serial ports. ? configurable i/o addresses and interrupts. ? 16-byte fifos. ? supports up to 115 kbps. ? programmable baud rate generator. ? modem control circuitry. ? 14.7456 mhz and 48 mhz supported for uart baud clock input. watchdog timer (wdt) selectable prescaler ? approximately 1 mhz (1 s to 1 s) and approximately 1 khz (1 ms to 10 min). ? 33 mhz clock (30 ns clock ticks). ? multiple modes (wdt and free-running). ?free-running mode: ? 1 stage timer - toggles wdt_tout# after programmable time. ?wdt mode: ? 2 stage timer (first stage generates interrupt, second stage drives wdt_tout# low). first stage generates an serirq, smi or nmi interrupt (depending on which is enabled) after programmable time. second stage drives wdt_out# low or inverts the previous value. used only after first timeout occurs.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1170 order number: 320066-003us status bit preserved in rtc well for possible error detection and correction. drives wdt_tout# if output is enabled. ? timer can be disabled (default state) or locked (hard reset required to disable wdt). ? wdt automatic reload of preload value when wdt reload sequence is performed. 33.3 functional description 33.3.1 host processor interface (lpc) the host processor communicates with the siw via the lpc bus. access is through a series of read/ write registers and accomplished through i/o cycles. all registers are eight bits wide. the siw registers include global configuration space and device specific regions accessed by setting the logical device number in the siw configuration register 07h (scr7). see section 33.8 for configuration register descriptions and information on setting the base address. 33.4 lpc interface the lpc interface is used to control all the logical blocks on the siw. lpc bus signals use pci 33 mhz electrical signal characteristics. refer to the low pin count (lpc) interface specification rev 1.0. 33.4.1 lpc cycles the following cycle types are supported by the lpc protocol. the siw ignores cycles that it does not support. table 33-1. address map address block name logical device 04eh or 20eh (siu1_dtr# dependent) configuration index 04fh or 20fh (siu1_dtr# dependent) configuration data base+(0-7) serial port 1 04h base+(0-7) serial port 2 05h base+(0-18) watchdog timer 06h table 33-2. supported lpc cycle types cycle type transfer size i/o write 1 byte i/o read 1 byte
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1171 intel ? ep80579 integrated processor 33.4.1.1 i/o read and write cycles the siw is the target for i/o cycles. i/o cycles are initiated by the host for register or fifo accesses and generally have minimal synchronization times. data transfers are assumed to be exactly 1-byte. if the cpu requested a 16-bit or 32- bit transfer, the host must break it up into 8-bit transfers. see the lpc interface specification for the sequence of cycles for the i/o read and write cycles. 33.4.2 policy the following rules govern the reset policy: siw_reset# is tied to the internal pci bus reset. when siw_reset# goes active (low): ? the host drives the lframe# signal high, tri-states the lad[3:0] signals. ? the siu ignores lframe#, tri-states the lad[3:0] pins. note: lpc bus signals from siw are internally tied to the primary lpc interface of the iich device. host lpc and siw lpc names are used interchangeably throughout. 33.4.3 lpc transfers 33.4.3.1 i/o transfers these are generally used for register or fifo accesses, and generally have minimal synchronization times. the minimum number of wait-states between bytes is one. data transfers are assumed to be exactly one byte. the host is responsible for breaking up larger data transfers into 8-bit cycles. 33.5 logical devices 4 and 5: serial ports (uart1 and uart2) this section describes the universal asynchronous receiver/transmitter (uart) serial port used for the two uart integrated into the siw. the uart can be controlled via programmed i/o. the basic programming model is the same for both uarts with the only difference being the logical device number assigned to each. the serial port consists of a uart which supports all the functions of a standard 16550 uart including hardware flow control interface. the uart performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-t o-serial conversion on data characters received from the processor. the processor can read the complete status of the uart at table 33-3. i/o sync bits description bits indication 0000 synchronization achieved with no error. 0101 indicates that synchronization not achieved yet, but the part is driving the bus. 0110 indicates that synchronization not achieved yet, but the part is driving the bus and expects long synchronization 1010 special case: peripheral indicating errors.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1172 order number: 320066-003us any time during the functional operation. available status information includes the type and condition of the transfer operations being performed by the uart and any error conditions (parity, overrun, framing, or break interrupt). the serial port can operate in either fifo or non-fifo mode. in fifo mode, a 16-byte transmit fifo holds data from the processor to be transmitted on the serial link and a 16-byte receive fifo buffers data from the serial link until read by the processor. each uart includes a programmable baud rate generator which is capable of dividing the baud clock input by divisors of one to (2 16 -1) and producing a 16x clock to drive the internal transmitter and receiver logic. each uart has complete modem control capability and a processor interrupt system. interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. each uart can operate in a polled or an interrupt driven environment as configured by software. the baud rate generator input is a function of the uart_clk and a configurable predivide of 1, 8, or 26. see also siw configuration (address 29h) in section 33.8.3.1, ?global control/configuration registers [00h - 2fh]? on page 1208 . the output of the baud rate generator is 16 times the baud rate. 33.5.1 uart feature list ? functionally compatible with national semiconductor's* pc16550d. ? adds or deletes standard asynchronous communications bits (start, stop, and parity) to or from the serial data. ? independently controlled transmit, receive, line status and data set interrupts. ? programmable baud rate generator allows division of clock by 1 to (216 -1) and generates an internal 16x clock. ? modem control functions (cts#, rts#, dsr#, dtr#, ri#, and dcd#). table 33-4. uart clock divider support clock frequency 14.7456 mhz 48.0 mhz predivide value 8 26 generator frequency 1.8432 mhz 1.8462 mhz table 33-5. baud rate example desired baud rate divisor % error @ 1.8432 % error @ 1.8462* 300 384 0.16 1200 96 0.16 2400 48 0.16 4800 24 0.16 9600 12 0.16 19200 6 0.16 38400 3 0.16 56000 2 2.8 3 115200 1 0.16
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1173 intel ? ep80579 integrated processor ? fully programmable serial-interface characteristics: ? 5, 6, 7 or 8-bit characters. ? even, odd, or no parity detection. ? 1, 1-1/2, or 2 stop bit generation. ? baud rate generation (up to 115 kbps). ? false start bit detection. ? 16-byte receive fifo. ? complete status reporting capability. ? line break generation and detection. ? internal diagnostic capabilities include: ? loopback controls for communications link fault isolation. ? break, parity, overrun, and framing error simulation. ? fully prioritized interrupt system controls. 33.5.2 uart operational description the format of a uart data frame is shown in figure 33-1 . each data frame is between seven bits and 12 bits long depending on the size of data programmed, if parity is enabled and if two stop bits is selected. the frame begins with a start bit that is represented by a high to low transition. next, 5 to 8 bits of data are transmitted, beginning with the least significant bit. an optional parity bit follows, which is set if even parity is enabled and an odd number of ones exist within the data byte, or if odd parity is enabled and the data byte contains an even number of ones. the data frame ends with one, one and a half or two stop bits as programmed by the user, which is represented by one or two successive bit periods of a logic one. the unit is disabled upon reset, the user needs to enable the unit by setting bit six of interrupt enable register. when the unit is enabled, the receiver starts looking for the start bit of a frame; the transmitter starts transmitting data to the transmit data pin if there is data available in the transmit fifo. transmit data can be written to the fifo figure 33-1. example uart data frame
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1174 order number: 320066-003us before the unit is enabled. when the unit is disabled, the transmitter/receiver finishes the current byte being transmitted/received if it is in the middle of transmitting/ receiving a byte and stops transmitting/receiving more data. an siu_reset# to the siu forces the internal register and output signals on the serial port to the values listed below. 33.5.2.1 programmable baud rate generator the uart contains a programmable baud rate generator that is capable of taking the uart_clk input and dividing it by any divisor from 1 to (2 16 -1). the output frequency of the baud rate generator is 16 times the baud rate. two 8-bit latches store the divisor in a 16-bit binary format. these divisor latches must be loaded during initialization to ensure proper operation of the baud rate generator. if both divisor latches are loaded with 0, the 16x output clock is stopped. upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. this prevents long counts on initial load. access to the divisor latch can be done with a word write. note: the uart_clk is the siw_clk input divided by the prescalar set by the siw configuration register (offset 29h). the baud rate of the data shifted in/out of the uart is given by: baud rate = uart_clk(mhz)/[16x divisor] for example, if uart_clk is 14.7456mhz and the divisor is 96, the baud rate is 9600. a divisor value of 0 in the divisor latch register is not allowed. the reset value of the divisor is 02. table 33-6. uart register/signal reset states register/signal reset control reset state interrupt enable register reset all bits are low. interrupt id register reset bit 0 is forced high. bits 1-3 and 6-7 are forced low. bits 4-5 are permanently low. line control register reset all bits are forced low. line status register reset bits 0-4,7 are forced low. bits 5 and 6 are forced high. modem control register reset bits 0,1,2,3,4 are forced low. bits 5,6,7 are permanently low. modem status register reset/modem signal, read msr for bits 3-0. low infrared selection register reset all bits are permanently low. txd reset high int reset/ clear line status reg low rts_n reset high dtr_n reset high
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1175 intel ? ep80579 integrated processor 33.5.3 uart register details there are 12 registers in the uart. these registers share eight address locations in the i/o address space. ta bl e 3 3 - 1 0 shows the registers and their addresses as offsets of a base address. the state of the divisor latch bit (dlab), which is the most significant bit of the serial line control register, affects the selection of certain of the uart registers. the dlab bit must be set high by the system software to access the baud rate generator divisor latches. table 33-7. summary of uart registers in i/o space (dlab=0) offset start offset end register id - description default value 00h 00h ?offset 00h: rbr - receive buffer register? on page 1176 00h 00h 00h ?offset 00h: thr - transmit holding register? on page 1177 00h 01h 01h ?offset 01h: ier - interrupt enable register? on page 1177 00h table 33-8. summary of uart registers in i/o space (dlab=1) offset start offset end register id - description default value 00h 00h ?offset 00h: dll - programmable baud rate generator divisor latch register low? on page 1190 02h 01h 01h ?offset 01h: dlh - programmable baud rate generator divisor latch register high? on page 1190 00h table 33-9. summary of uart timer registers in i/o space offset start offset end register id - description default value 02h 02h ?offset 02h: iir - interrupt identification register? on page 1179 01h 02h 02h ?offset 02h: fcr - fifo control register? on page 1180 00h 03h 03h ?offset 03h: lcr - line control register? on page 1182 00h 04h 04h ?offset 04h: mcr - modem control register? on page 1184 00h 05h 05h ?offset 05h: lsr - line status register? on page 1186 60h 06h 06h ?offset 06h: msr - modem status register? on page 1189 00h 07h 07h ?offset 07h: scr - scratchpad register? on page 1190 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1176 order number: 320066-003us note: base address for the uart registers listed in ta b l e 3 3 - 1 0 is configurable. see section 33.8.3, ?siw configuration register summary? on page 1207 for details. 33.5.3.1 offset 00h: rbr - receive buffer register in non-fifo mode, this register holds the character received by the uart's receive shift register. if fewer than eight bits are received, the bits are right-justified and the leading bits are zeroed. reading the register empties the register and resets the data ready (dr) bit in the line status register to zero. other (error) bits in the line status register are not cleared. in fifo mode, this register latches the value of the data byte at the top of the fifo. 33.5.3.2 offset 00h: thr - transmit holding register this register holds the next data byte to be transmitted. when the transmit shift register becomes empty, the contents of the transmit holding register are loaded into the shift register and the transmit data request (tdrq) bit in the line status register is set to one. table 33-10. internal register descriptions uart register addresses (base + offset) dlab bit value register accessed base 0 receive buffer (read-only) base 0 transmit buffer (write-only) base + 01h 0 interrupt enable (read/write) base + 02h x interrupt i.d. (read-only) base + 02h x fifo control (write-only) base + 03h x line control (read/write) base + 04h x modem control (read/write) base + 05h x line status (read-only) base + 06h x modem status (read-only) base + 07h x scratch pad (read/write) base 1 divisor latch (lower byte, read/write) base + 01h 1 divisor latch (upper byte, read/write) table 33-11. offset 00h: rbr - receive buffer register description: view: ia f base address: base (io) (dlab = 0) offset start: offset end: 00h 00h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 rb_7_0 data byte received (bits [7:0]), least significant bit first 00h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1177 intel ? ep80579 integrated processor in fifo mode, writing to thr puts data to the top of the fifo. the data at the bottom of the fifo is loaded to the shift register when it is empty. 33.5.3.3 offset 01h: ier - interrupt enable register this register enables five types of interrupts which independently activate the int signal and set a value in the interrupt identification register. each of the five interrupt types can be disabled by resetting the appropriate bit of the ier register. similarly, by setting the appropriate bits, selected interrupts can be enabled. receiver time out interrupt can be configured to be separated from the receive data available interrupt (using the bit 5: comp) the use of bit 5 to bit 4 is different from the register definition of standard 16550. table 33-12. offset 00h: thr - transmit holding register description: view: ia f base address: base (io) (dlab = 0) offset start: offset end: 00h 00h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 tb_7_0 data byte received (bits [7:0]), least significant bit first 00h wo table 33-13. offset 01h: ier - interrupt enable register (sheet 1 of 2) description: view: ia f base address: base (io) (dlab = 0) offset start: offset end: 01h 01h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :06 rsvd rsvd = 0 00h ro 05 comp compatibility enable: 0 = bit 0 of this register also controls rtoie and bit 4 is rsvd. 1 = bit 4 of this register controls rtoie. 0h rw 04 rtoie receiver time out interrupt enable: 0 = receiver data time out interrupt disabled 1 = receiver data time out interrupt enabled 0h rw 03 mie modem interrupt enable: 0 = modem status interrupt disabled 1 = modem status interrupt enabled 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1178 order number: 320066-003us 33.5.3.4 offset 02h: iir - interrupt identification register in order to minimize software overhead during data character transfers, the uart prioritizes interrupts into four levels (listed in ta bl e 3 3 - 1 4 ) and records these in the interrupt identification register. the interrupt identification register (iir) stores information indicating that a prioritized interrupt is pending and the source of that interrupt. 02 rlse receiver line status interrupt enable: 0 = receiver line status interrupt disabled 1 = receiver line status interrupt enabled 0h rw 01 tie transmit data request interrupt enable: 0 = transmit fifo data request interrupt disabled 1 = transmit fifo data request interrupt enabled 0h rw 00 ravie receiver data available interrupt enable : when bit 5 = 1: 0 = receiver data available (trigger level reached) interrupt disabled 1 = receiver data available (trigger level reached) interrupt enabled when bit 5 = 0: 0 = receiver data time out interrupt also disabled 1 = receiver data time out interrupt enabled 0h rw table 33-13. offset 01h: ier - interrupt enable register (sheet 2 of 2) description: view: ia f base address: base (io) (dlab = 0) offset start: offset end: 01h 01h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access table 33-14. interrupt conditions priority level interrupt origin 1 (highest) receiver line status. one or more error bits were set. 2 received data is available. in fifo mode, trigger level was reached; in non-fifo mode, rbr has data. 2 receiver time out occurred. it happens in fifo mode only, when there is data in the receive fifo but no activity for a time period. 3 transmitter requests data. in fifo mode, the transmit fifo is half or more than half empty; in non-fifo mode, thr is read already. 4 modem status: one or more of the modem input signals has changed state
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1179 intel ? ep80579 integrated processor table 33-15. offset 02h: iir - interrupt identification register description: view: ia f base address: base (io) offset start: offset end: 02h 02h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :06 fifoes_1_0 fifo mode enable status (bits [1:0]): 00 non-fifo mode is selected. 01 reserved 10 reserved 11 fifo mode is selected (trfifoe = 1). 00b ro 05 :04 reserved reserved 00b 03 tod_iid3 time out detected: 0 = no time out interrupt is pending. 1 = time out interrupt is pending. (fifo mode only) 0b ro 02 :01 iid_2_1 interrupt source encoded (bits[2:1]): 00 modem status (cts, dsr, ri, dcd modem signals changed state) 01 transmit fifo requests data 10 received data available 11 receive error (overrun, parity, framing, break, fifo error) 00b ro 00 p_n interrupt pending: 0 = interrupt is pending. (active low) 1 = no interrupt is pending. 1b ro table 33-16. interrupt identification register decode (sheet 1 of 2) interrupt id bits interrupt set/reset function 3210 priorit y type source reset control 0 0 0 1 - none no interrupt is pending. - 0110 highest receiver line status overrun error, parity error, framing error, break interrupt. reading the line status register. 0100 second highest received data available. non-fifo mode: receive buffer is full. non-fifo mode: reading the receiver buffer register. fifo mode: trigger level was reached. fifo mode: reading bytes until receiver fifo drops below trigger level or setting resetrf bit in fcr register. 1100 second highest character timeout indication. fifo mode only: at least 1 character is in receiver fifo and there was no activity for a time period. reading the receiver fifo or setting resetrf bit in fcr register.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1180 order number: 320066-003us 33.5.3.5 offset 02h: fcr - fifo control register fcr is a write-only register that is located at the same address as the iir (iir is a read-only register). fcr enables/disables the transmitter/receiver fifos, clears the transmitter/receiver fifos, and sets the receiver fifo trigger level. 0010 third highest transmit fifo data request non-fifo mode: transmit holding register empty reading the iir register (if the source of the interrupt) or writing into the transmit holding register. fifo mode: transmit fifo has half or less than half data. reading the iir register (if the source of the interrupt) or writing to the transmitter fifo. 0000 fourth highest modem status clear to send, data set ready, ring indicator, received line signal detect reading the modem status register table 33-16. interrupt identification register decode (sheet 2 of 2) table 33-17. offset 02h: fcr - fifo control register (sheet 1 of 2) description: view: ia f base address: base (io) offset start: offset end: 02h 02h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :06 itl_1_0 interrupt trigger level (bits [1:0]): when the number of bytes in the receiver fifo equals the interrupt trigger level programmed into this field and the received data available interrupt is enabled (via ier), an interrupt is generated and appropriate bits are set in the iir. 00 1 byte or more in fifo causes interrupt 01 rsvd 10 8 bytes or more in fifo causes interrupt 11 rsvd 00b wo 05 :03 reserved reserved. must be programmed to 0. 000b 02 resettf reset transmitter fifo: when resettf is set to 1, the transmitter fifo counter logic is set to 0, effectively clearing all the bytes in the fifo. the tdrq bit in lsr are set and iir shows a transmitter requests data interrupt if the tie bit in the ier register is set. the transmitter shift register is not cleared; it completes the current transmission. after the fifo is cleared, resettf is automatically reset to 0. 0 = writing 0 has no effect 1 = the transmitter fifo is cleared (fifo counter set to 0). after clearing, bit is automatically reset to 0 0b wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1181 intel ? ep80579 integrated processor 01 resetrf reset receiver fifo: when resetrf is set to 1, the receiver fifo counter is reset to 0, effectively clearing all the bytes in the fifo. the dr bit in lsr is reset to 0. all the error bits in the fifo and the fifoe bit in lsr are cleared. any error bits, oe, pe, fe or bi, that had been set in lsr are still set. the receiver shift register is not cleared. if iir had been set to received data available, it is cleared. after the fifo is cleared, resetrf is automatically reset to 0. 0 = writing 0 has no effect 1 = the receiver fifo is cleared (fifo counter set to 0). after clearing, bit is automatically reset to 0 0b wo 00 trfifoe transmit and receive fifo enable: trfifoe enables/disables the transmitter and receiver fifos. when trfifoe = 1, both fifos are enabled (fifo mode). when trfifoe = 0, the fifos are both disabled (non-fifo mode). writing a 0 to this bit clears all bytes in both fifos. when changing from fifo mode to non- fifo mode and vice versa, data is automatically cleared from the fifos. this bit must be 1 when other bits in this register are written or the other bits are not programmed. 0 = fifos are disabled 1 = fifos are enabled 0b wo table 33-17. offset 02h: fcr - fifo control register (sheet 2 of 2) description: view: ia f base address: base (io) offset start: offset end: 02h 02h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1182 order number: 320066-003us 33.5.3.6 offset 03h: lcr - line control register in the line control register (lcr), the system programmer specifies the format of the asynchronous data communications exchange. the serial data format consists of a start bit (logic 0), five to eight da ta bits, an optional parity bit, and one or two stop bits (logic 1). the lcr has bits for accessing the divisor latch and causing a break condition. the programmer can also read the contents of the line control register. the read capability simplifies system programming and eliminates the need for separate storage in system memory. table 33-18. offset 03h: lcr - line control register (sheet 1 of 2) description: view: ia f base address: base (io) offset start: offset end: 03h 03h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 dlab divisor register access bit: this bit is the divisor latch access bit. it must be set high (logic 1) to access the divisor latches of the baud rate generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmit holding register, or the interrupt enable register. 0 = access transmit holding register (thr), receive buffer register (rbr) and interrupt enable register. 1 = access divisor latch registers (dll and dlh). 0b rw 06 sb set break: this bit is the set break control bit. it causes a break condition to be transmitted to the receiving uart. when sb is set to a logic 1, the serial output (txd) is forced to the spacing (logic 0) state and remains there until sb is set to a logic 0. this bit acts only on the txd pin and has no effect on the transmitter logic. this feature enables the processor to alert a terminal in a computer communications system. if the following sequence is executed, no erroneous characters are transmitted because of the break: load 00h in the transmit holding register in response to a tdrq interrupt after tdrq goes high (indicating that 00h is being shifted out), set the break bit before the parity or stop bits reach the txd pin wait for the transmitter to be idle (temt = 1) and clear the break bit when normal transmission has to be restored during the break, the transmitter can be used as a character timer to accurately establish the break duration. in fifo mode, wait for the transmitter to be idle (temt=1) to set and clear the break bit. 0 = no effect on txd output 1 = forces txd output to 0 (space) 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1183 intel ? ep80579 integrated processor 05 stkyp sticky parity: this bit is the ?sticky parity? bit, which can be used in multiprocessor communications. when pen and stkyp are logic 1, the bit that is transmitted in the parity bit location (the bit just before the stop bit) is the complement of the eps bit. if eps is 0, then the bit at the parity bit location are transmitted as a 1. in the receiver, if stkyp and pen are 1, then the receiver compares the bit that is received in the parity bit location with the complement of the eps bit. if the values being compared are not equal, the receiver sets the parity error bit in lsr and causes an error interrupt if line status interrupts were enabled. for example, if eps is 0, the receiver expects the bit received at the parity bit location to be 1. if it is not, then the parity error bit is set. by forcing the bit value at the parity bit location, rather than calculating a parity value, a system with a master transmitter and multiple receivers can identify some transmitted characters as receiver addresses and the rest of the characters as data. if pen = 0, stkyp is ignored. 0 = no effect on parity bit 1 = forces parity bit to be opposite of eps bit value 0b rw 04 eps even parity select: this bit is the even parity select bit. when pen is a logic 1 and eps is a logic 0, an odd number of logic ones is transmitted or checked in the data word bits and the parity bit. when pen is a logic 1 and eps is a logic 1, an even number of logic ones is transmitted or checked in the data word bits and parity bit. if pen = 0, eps is ignored. 0 = sends or checks for odd parity 1 = sends or checks for even parity 0b rw 03 pen parity enable: this is the parity enable bit. when pen is a logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of ones when the data word bits and the parity bit are summed.) 0 = no parity function 1 = allows parity generation and checking 0b rw 02 stb stop bits: this bit specifies the number of stop bits transmitted and received in each serial character. if stb is a logic 0, one stop bit is generated in the transmitted data. if stb is a logic 1 when a 5-bit word length is selected via bits 0 and 1, then 1 and one half stop bits are generated. if stb is a logic 1 when either a 6, 7, or 8-bit word is selected, then two stop bits are generated. the receiver checks the first stop bit only, regardless of the number of stop bits selected. 0 = 1 stop bit 1 = 2 stop bits, except for 5-bit character then 1-1/2 bits 0b rw 01 :00 wls_1_0 word length select: the word length select bits specify the number of data bits in each transmitted or received serial character. 00 5-bit character (default) 01 6-bit character 10 7-bit character 11 8-bit character 00b rw table 33-18. offset 03h: lcr - line control register (sheet 2 of 2) description: view: ia f base address: base (io) offset start: offset end: 03h 03h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1184 order number: 320066-003us 33.5.3.7 offset 04h: mcr - modem control register this 8-bit register controls the interface with the modem or data set (or a peripheral device emulating a modem). table 33-19. offset 04h: mcr - modem control register (sheet 1 of 2) description: view: ia f base address: base (io) offset start: offset end: 04h 04h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :05 reserved reserved 000b 04 loop loop back test mode: this bit provides a local loopback feature for diagnostic testing of the uart. when loop is set to a logic 1, the following occurs: the transmitter serial output is set to a logic 1 state. the out2# signal is forced to a logic 1 state. the receiver serial input is disconnected from the pin. the output of the transmitter shift register is ?looped back? into the receiver shift register input. the four modem control inputs (cts#, dsr#, dcd#, and ri#) are disconnected from the pins and the modem control output pins (rts# and dtr#) are forced to their inactive state. ? coming out of the loopback test mode may result in unpredictable activation of the delta bits (bits 3:0) in the modem status register (msr). it is recommended that msr be read once to clear the delta bits in the msr. the lower four bits of the modem control register are connected to the upper four modem status register bits: ? dtr = 1 forces dsr to a 1 ? rts = 1 forces cts to a 1 ? out1 = 1 forces ri to a 1 ? out2= 1 forces dcd to a 1 in the diagnostic mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the uart. the transmit, receive and modem control interrupts are operational, except the modem control interrupts are activated by control register bits, not the modem control inputs. a break signal can also be transferred from the transmitter section to the receiver section in loopback mode. 0 = normal uart operation 1 = test mode uart operation 0b rw 03 out2 out2# signal control: this bit controls the out2# output. when the out2 bit is set, out2# is asserted low. when the out2 bit is cleared, out2# is deasserted (set high). outside of the uart module, the out2# signal is used to connect the uart's interrupt output to the interrupt controller unit. 0 = out2# signal is 1, which disables the uart interrupt. 1 = out2# signal is 0. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1185 intel ? ep80579 integrated processor 33.5.3.8 offset 05h: lsr - line status register this register provides status information to the processor concerning the data transfers. bits 5 and 6 show information about the transmitter section. the rest of the bits contain information about the receiver. in non-fifo mode, three of the lsr register bits, parity error, framing error, and break interrupt, show the error status of the character that has just been received. in fifo mode, these three bits of status are stored with each received character in the fifo. lsr shows the status bits of the character at the top of the fifo. when the character at the top of the fifo has errors, the lsr error bits are set and are not cleared until software reads lsr, even if the character in the fifo is read and a new character is now at the top of the fifo. bits one through four are the error conditions that produce a receiver line status interrupt when any of the corresponding conditions are detected and the interrupt is enabled. these bits are not cleared by reading the erroneous byte from the fifo or receive buffer. they are cleared only by reading lsr. in fifo mode, the line status interrupt occurs only when the erroneous byte is at the top of the fifo. if the erroneous byte being received is not at the top of the fifo, an interrupt is generated only after the previous bytes are read and the erroneous byte is moved to the top of the fifo. 02 out1 test bit: this bit is used only in loopback test mode. see (loop) above. 0b rw 01 rts request to send: this bit controls the request to send (rts#) output pin. bit 1 affects the rts# output in a manner identical to that described below for the dtr bit. 0 = rts# pin is 1 1 = rts# pin is 0 0b rw 00 dtr data terminal ready: this bit controls the data terminal ready output. when bit 0 is set to a logic 1, the dtr# output is force to a logic 0. when bit 0 is reset to a logic 0, the dtr# output pin is forced to a logic 1. ? the dtr# output of the uart may be applied to an eia inverting line driver (such as the ds1488) to obtain the proper polarity input at the succeeding modem or data set. 0 = dtr# pin is 1 1 = dtr# pin is 0 0b rw table 33-19. offset 04h: mcr - modem control register (sheet 2 of 2) description: view: ia f base address: base (io) offset start: offset end: 04h 04h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1186 order number: 320066-003us table 33-20. offset 05h: lsr - line status register (sheet 1 of 3) description: view: ia f base address: base (io) offset start: offset end: 05h 05h size: 8 bit default: 60h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 fifoe fifo error status: this bit is reset only when all the error bytes have been read from the fifo. a processor read to the line status register does not reset this bit. non-fifo mode: 0 = bit is always ?0? indicating no fifo. fifo mode: 0 = all error bytes have been read from the fifo 1 = at least one character in the receiver fifo contains a parity error, framing error, or break indication. when dma requests are enabled (ier bit7 is set to 1) and fifoe is set to 1, no receive dma request is generated even though the receive fifo reaches the trigger level and the error interrupt is generated. when dma requests are not enabled (ier bit7 is set to 0), fifoe set to 1 does not generate interrupt. 0b ro 06 temt transmitter empty: non-fifo mode: 0 = either the transmit holding register or the tansmitter shift register contain a data character. 1 = the transmit holding register and the transmitter shift register are both empty. fifo mode: 0 = either the transmitter fifo or the transmit shift register contain a data character. 1 = the transmitter fifo and the transmit shift register are both empty. 1b ro 05 trdq transmit data request: tdrq indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the processor when the transmit data request interrupt enable is set high. non-fifo mode: 0 = no character transferred from the transmit holding register into the transmit shift register. 1 = a character has transferred from the transmit holding register into the transmit shift register. note: bit is reset to logic 0 with the loading of the transmit holding register by the processor. fifo mode: 0 = when at least one byte is written to the transmit fifo. when more than 16 characters are loaded into the fifo, the excess characters are lost. 1 = transmit fifo is empty or the resettf bit in fcr, has been set to 1. 1b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1187 intel ? ep80579 integrated processor 04 bi break interrupt: bi is set to a logic 1 when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits).the bi is reset to a logic ?0? when the processor reads the line status register. 0 = no break signal has been received. 1 = break signal occurred. in fifo mode, only one character (equal to 00h), is loaded into the fifo regardless of the length of the break condition. bi shows the break condition for the character at the top of the fifo, not the most recently received character. 0h ro 03 fe framing error: fe indicates that the received character did not have a valid stop bit. this bit is reset to a logic ?0? when the processor reads the line status register. 0 = no framing error. 1 = invalid stop bit has been detected. fe is set to a logic 1 when the bit following the last data bit or parity bit is detected as a logic 0 (spacing level). if the line control register had been set for two stop bit mode, the receiver does not check for a valid second stop bit. the fe indicator is reset when the processor reads the line status register. the uart resynchronizes after a framing error. to do this it assumes that the framing error was due to the next start bit, so it samples this ?start? bit twice and then takes in the ?data?. in fifo mode fe shows a framing error for the character at the top of the fifo, not for the most recently received character. 0h ro 02 pe parity error: pe indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. the pe is set to logic 1 upon detection of a parity error and is reset to a logic 0 when the processor reads the line status register. in fifo mode, pe shows a parity error for the character at the top of the fifo, not the most recently received character. 0 = no parity error. 1 = parity error has occurred. 0h ro table 33-20. offset 05h: lsr - line status register (sheet 2 of 3) description: view: ia f base address: base (io) offset start: offset end: 05h 05h size: 8 bit default: 60h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1188 order number: 320066-003us 33.5.3.9 offset 06h: msr - modem status register this 8-bit register provides the current state of the control lines from the modem or data set (or a peripheral device emulating a modem) to the processor. in addition to this current state information, four bits of the modem status register provide change information. bits 03:00 are set to a logic 1 when a control input from the modem changes state. they are reset to a logic 0 when the processor reads the modem status register. when bits 0, 1, 2, or 3 are set to logic 1, a modem status interrupt is generated if bit 3 of the interrupt enable register is set. 01 oe overrun error: in non-fifo mode, oe indicates that data in the receiver buffer register was not read by the processor before the next character was transferred into the receiver buffer register, thereby destroying the previous character. in fifo mode, oe indicates that all 16 bytes of the fifo are full and the most recently received byte has been discarded. the oe indicator is set to a logic ?1? upon detection of an overrun condition and reset when the processor reads the line status register. 0 = no data has been lost 1 = received data has been lost. 0h ro 00 dr data ready: dr is set to logic 1 when complete incoming character has been received and transferred into the receiver buffer register (rbr) or the fifo. in non-fifo mode, dr is reset to 0 when the receive buffer is read. in fifo mode, dr is reset to a logic 0 if the fifo is empty (last character has been read from receiver buffer register) or the resetrf bit is set in fcr. 0 = no data has been received 1 = data available in rbr or the fifo. 0h ro table 33-20. offset 05h: lsr - line status register (sheet 3 of 3) description: view: ia f base address: base (io) offset start: offset end: 05h 05h size: 8 bit default: 60h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1189 intel ? ep80579 integrated processor table 33-21. offset 06h: msr - modem status register description: view: ia f base address: base (io) offset start: offset end: 06h 06h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 dcd data carrier detect: this bit is the complement of the data carrier detect (dcd#) input. this bit is equivalent to bit out2 of the modem control register if loop in the mcr is set to 1. 0 = dcd# pin is 1 1 = dcd# pin is 0 0b ro 06 ri ring indicator: this bit is the complement of the ring indicator (ri#) input. this bit is equivalent to bit out1 of the modem control register if loop in the mcr is set to 1. 0 = ri# pin is 1 1 = ri# pin is 0 0b ro 05 dsr data set ready: this bit is the complement of the data set ready (dsr#) input. this bit is equivalent to bit dtr of the modem control register if loop in the mcr is set to 1. 0 = dsr# pin is 1 1 = dsr# pin is 0 0b ro 04 cts clear to send: this bit is the complement of the clear to send (cts#) input. this bit is equivalent to bit rts of the modem control register if loop in the mcr is set to 1. 0 = cts# pin is 1 1 = cts# pin is 0 0b ro 03 ddcd delta data carrier detect: 0 = no change in dcd# pin since last read of msr 1 = dcd# pin has changed state 0b ro 02 teri trailing edge ring indicator: 0 = ri# pin has not changed from 0 to 1 since last read of msr 1 = ri# pin has changed from 0 to 1 0b ro 01 ddsr delta data set ready: 0 = no change in dsr# pin since last read of msr 1 = dsr# pin has changed state 0b ro 00 dcts delta clear to send: 0 = no change in cts# pin since last read of msr 1 = cts# pin has changed state 0b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1190 order number: 320066-003us 33.5.3.10 offset 07h: scr - scratchpad register this 8-bit read/write register has no effect on the uart. it is intended as a scratchpad register for use by the programmer. 33.5.3.11 offset 00h: dll - programmable baud rate generator divisor latch register low see section 33.5.2.1, ?programmable baud rate generator? on page 1174 . 33.5.3.12 offset 01h: dlh - programmable baud rate generator divisor latch register high see section 33.5.2.1, ?programmable baud rate generator? on page 1174 . table 33-22. offset 07h: scr - scratchpad register description: view: ia f base address: base (io) offset start: offset end: 07h 07h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 sp_7_0 no effect on uart functionality 00h rw table 33-23. offset 00h: dll - programmable ba ud rate generator divisor latch register low description: view: ia f base address: base (io) (dlab = 1) offset start: offset end: 00h 00h size: 8 bit default: 02h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 br_7_0 low byte compare value to generate baud rate 02h rw table 33-24. offset 01h: dlh - programmable ba ud rate generator divisor latch register high description: view: ia f base address: base (io) (dlab = 1) offset start: offset end: 01h 01h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 :00 br_15_8 high byte compare value to generate baud rate 00h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1191 intel ? ep80579 integrated processor 33.5.4 fifo operation 33.5.4.1 fifo interrupt mode operation 33.5.4.1.1 receiver interrupt when the receive fifo and receiver interrupts are enabled (fcr[0]=1 and ier[0]=1), receiver interrupts occur as follows: ? the receive data available interrupt is invoked when the fifo has reached its programmed trigger level. the interrupt is cleared when the fifo drops below the programmed trigger level. ? the iir receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt, the bits are cleared when the fifo drops below the trigger level. ? the receiver line status interrupt (iir = c6h), as before, has the highest priority. the receiver data available interrupt (iir=c4h) is lower. the line status interrupt occurs only when the character at the top of the fifo has errors. ? the data ready bit (dr in lsr register) is set to 1 as soon as a character is transferred from the shift register to the receive fifo. this bit is reset to 0 when the fifo is empty. 33.5.4.1.2 character timeout interrupt when the receiver fifo and receiver time out interrupt are enabled, a character timeout interrupt occurs when all of the following conditions exist: ? at least one character is in the fifo. ? the last received character was longer than four continuous character times ago (if two stop bits are programmed the second one is included in this time delay). ? the most recent processor read of the fifo was longer than four continuous character times ago. ? the receive fifo trigger level is greater than one. the maximum time between a received character and a timeout interrupt is 160 ms at 300 baud with a 12-bit receive character (i.e., one start, eight data, one parity, and two stop bits). when a time out interrupt occurs, it is cleared and the timer is reset when the processor reads one character from the receiver fifo. if a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or after the processor reads the receiver fifo. 33.5.4.1.3 transmit interrupt when the transmitter fifo and transmitter interrupt are enabled (fcr[0]=1, ier[1]=1), transmit interrupts occur as follows: the transmitter holding register interrupt occurs when the transmit fifo is empty; it is cleared as soon as the transmitter holder register is written to (1 to 16 characters may be written to the transmit fifo while servicing this interrupt) or the iir is read. the transmitter fifo empty indications are delayed one character time minus the last stop bit time whenever the following occurs: thre = 1 and there have not been at least two bytes at the same time in the transmit fifo since the last thre = 1. the first transmitter interrupt after changing fcro is immediate if it is enabled.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1192 order number: 320066-003us 33.5.4.2 fifo polled mode operation with the fifos enabled (trfifoe bit of fcr set to 1), setting ier[3:0] to all zeros puts the serial port in the fifo polled mode of operation. since the receiver and the transmitter are controlled separately, either one or both can be in the polled mode of operation. in this mode, software checks receiver and transmitter status via the lsr. as stated in the register description: ? lsr[0] is set as long as there is one byte in the receiver fifo. ? lsr[1] through lsr[4] specify which error(s) has occurred for the character at the top of the fifo. character error status is handled the same way as interrupt mode. the iir is not affected since ier[2] = 0. ? lsr[5] indicates when the transmitter fifo needs data. ? lsr[6] indicates that both the transmitter fifo and shift register are empty. ? lsr[7] indicates whether there are any errors in the receiver fifo. 33.6 logical device 6: watchdog timer 33.6.1 overview this device is a watchdog timer that provides a resolution that ranges from 1 s to 10 minutes. the timer uses a 35-bit down-counter. the counter is loaded with the value from the 1 st preload register. the timer is then enabled and it starts counting down. the time at which the wdt first starts counting down is called the first stage. if the host fails to reload the wdt before the 35-bit down counter reaches zero the wdt generates an internal interrupt. after the interrupt is generated the wdt loads the value from the 2 nd preload register into the wdt?s 35-bit down-counter and starts counting down. the wdt is now in the second stage. if the host still fails to reload the wdt before the second timeout, the wdt drives the wdt_tout# pin low and sets the timeout bit (wdt_timeout). this bit indicates that the system has become unstable. the wdt_tout# pin is held low until the system is reset or the wdt times out again (depends on tout_cnf). the process of reloading the wdt involves the following sequence of writes: 1. write ?80? to offset bar1 + 0ch 2. write ?86? to offset bar1 + 0ch 3. write ?1? to wdt_reload in reload register. the same process is used for setting the values in the preload registers. the only difference exists in step 3. instead of writing a ?1? to the wdt_reload, you write the desired preload value into the corresponding preload register. this value is not loaded into the 35-bit down counter until the next time the wdt reenters the stage. for example, if preload value 2 is changed, it is not loaded into the 35-bit down counter until the next time the wdt enters the second stage.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1193 intel ? ep80579 integrated processor figure 33-2. wdt block diagram lpc interface timeout/interrupt control logic down-counter wdt_int (internal) wdt_tout# (external) lpc preload value 1 preload value 2
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1194 order number: 320066-003us 33.6.2 watchdog timer register details all registers not mentioned are reserved. note: base address for the watchdog timer registers, listed in this section, is configurable. see section 33.8.3, ?siw configuration register summary? on page 1207 for details. 33.6.2.1 offset 00h: pv1r0 - preload value 1 register 0 table 33-25. summary of watchdog timer registers in i/o space offset start offset end register id - description default value 00h 00h ?offset 00h: pv1r0 - preload va lue 1 register 0? on page 1194 ffh 01h 01h ?offset 01h: pv1r1 - preload va lue 1 register 1? on page 1195 ffh 02h 02h ?offset 02h: pv1r2 - preload va lue 1 register 2? on page 1195 0fh 04h 04h ?offset 04h: pv2r0 - preload va lue 2 register 0? on page 1196 ffh 05h 05h ?offset 05h: pv2r1 - preload va lue 2 register 1? on page 1196 ffh 06h 06h ?offset 06h: pv2r2 - preload va lue 2 register 2? on page 1197 0fh 08h 08h ?offset 08h: gisr - general interrupt status register? on page 1197 00h 0ch 0ch ?offset 0ch: rr0 - reload register 0? on page 1198 00h 0dh 0dh ?offset 0dh: rr1 - reload register 1? on page 1199 00h 10h 10h ?offset 10h: wdtcr - wdt configuration register? on page 1199 00h 18h 18h ?offset 18h: wdtlr - wdt lock register? on page 1201 00h table 33-26. offset 00h: pv1r0 - preload value 1 register 0 description: view: ia f base address: base (io) offset start: offset end: 00h 00h size: 8 bit default: ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pload1_7_0 preload_value_1 [7:0]: this register is used to hold the bits 0 through 7 of the preload value 1 for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down counter every time the wdt enters the first stage. the value loaded into the preload register needs to be one less than the intended period. this is because the timer makes use of zero-based counting (i.e. zero is counted as part of the decrement). refer to section 33.6.3.2 for details on how to change the value of this register. ffh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1195 intel ? ep80579 integrated processor 33.6.2.2 offset 01h: pv1r1 - preload value 1 register 1 33.6.2.3 offset 02h: pv1r2 - preload value 1 register 2 table 33-27. offset 01h: pv1r1 - preload value 1 register 1 description: view: ia f base address: base (io) offset start: offset end: 01h 01h size: 8 bit default: ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pload1_15_8 preload_value_1 [15:8]: this register is used to hold the bits 8 through 15 of the preload value 1 for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down counter every time the wdt enters the first stage. the value loaded into the preload register needs to be one less than the intended period. this is because the timer makes use of zero-based counting (i.e. zero is counted as part of the decrement). refer to section 33.6.3.2 for details on how to change the value of this register. ffh rw table 33-28. offset 02h: pv1r2 - preload value 1 register 2 description: view: ia f base address: base (io) offset start: offset end: 02h 02h size: 8 bit default: 0fh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 : 00 pload_19_16 preload_value_1 [19:16]: this register is used to hold the bits 16 through 19 of the preload value 1 for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down counter every time the wdt enters the first stage. the value loaded into the preload register needs to be one less than the intended period. this is because the timer makes use of zero-based counting (i.e. zero is counted as part of the decrement). refer to section 33.6.3.2 for details on how to change the value of this register. fh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1196 order number: 320066-003us 33.6.2.4 offset 04h: pv2r0 - preload value 2 register 0 33.6.2.5 offset 05h: pv2r1 - preload value 2 register 1 table 33-29. offset 04h: pv2r0 - preload value 2 register 0 description: view: ia f base address: base (io) offset start: offset end: 04h 04h size: 8 bit default: ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pload2_7_0 preload_value_2 [7:0]: this register is used to hold the bits 0 through 7 of the preload value2 for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down counter every time the wdt enters the second stage. the value loaded into the preload register needs to be one less than the intended period. this is because the timer makes use of zero-based counting (i.e., zero is counted as part of the decrement). refer to section 33.6.3.2 for details on how to change the value of this register. ffh rw table 33-30. offset 05h: pv2r1 - preload value 2 register 1 description: view: ia f base address: base (io) offset start: offset end: 05h 05h size: 8 bit default: ffh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pload2_15_8 preload_value_2 [15:8]: this register is used to hold the bits 8 through 15 of the preload value2 for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down counter every time the wdt enters the second stage. the value loaded into the preload register needs to be one less than the intended period. this is because the timer makes use of zero-based counting (i.e., zero is counted as part of the decrement). refer to section 33.6.3.2 for details on how to change the value of this register. ffh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1197 intel ? ep80579 integrated processor 33.6.2.6 offset 06h: pv2r2 - preload value 2 register 2 33.6.2.7 offset 08h: gisr - general interrupt status register table 33-31. offset 06h: pv2r2 - preload value 2 register 2 description: view: ia f base address: base (io) offset start: offset end: 06h 06h size: 8 bit default: 0fh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 reserved reserved 0h 03 : 00 pload2_19_16 preload_value_2 [19:16]: this register is used to hold the bits 16 through 19 of the preload value2 for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down counter every time the wdt enters the second stage. the value loaded into the preload register needs to be one less than the intended period. this is because the timer makes use of zero-based counting (i.e. zero is counted as part of the decrement). refer to section 33.6.3.2 for details on how to change the value of this register. fh rw table 33-32. offset 08h: gisr - general interrupt status register (sheet 1 of 2) description: view: ia f base address: base (io) offset start: offset end: 08h 08h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 00h 02 smiact watchdog timer smi interrupt active (1st stage): this bit is set when the first stage of the 35-bit down counter reaches zero. an smi interrupt is generated if wdt_int_type is configured to do so (see wdt configuration register). this is a sticky bit and is only cleared by writing a ?1?. this smi interrupt will be routed to gpio6 so that bios can use the existing smm handler to service this interrupt. 0 = no interrupt 1 = interrupt active note: this bit is not set in free running mode. also note that to route the smi interrupt to gpi6, the gpi_rout[13:12] register in d31:f0:b8h must be set to ?01? to generate the wdt smi interrupt and gpio6 cannot be used as a general purpose input pin. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1198 order number: 320066-003us 33.6.2.8 offset 0ch: rr0 - reload register 0 01 nmiact watchdog timer nmi interrupt active (1st stage): this bit is set when the first stage of the 35-bit down counter reaches zero. an nmi interrupt is generated if wdt_int_type is configured to do so (see wdt configuration register). this is a sticky bit and is only cleared by writing a ?1?. 0 = no interrupt 1 = interrupt active note: this bit is not set in free running mode. 0h rwc 00 serirqact watchdog timer serirq interrupt active (1st stage): this bit is set when the first stage of the 35-bit down counter reaches zero. an serirq interrupt is generated if wdt_int_type is configured to do so (see wdt configuration register). this is a sticky bit and is only cleared by writing a ?1?. 0 = no interrupt 1 = interrupt active note: this bit is not set in free running mode. 0h rwc table 33-33. offset 0ch: rr0 - reload register 0 description: view: ia f base address: base (io) offset start: offset end: 0ch 0ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 reserved reserved. must be programmed to 0. 00h table 33-32. offset 08h: gisr - general interrupt status register (sheet 2 of 2) description: view: ia f base address: base (io) offset start: offset end: 08h 08h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1199 intel ? ep80579 integrated processor 33.6.2.9 offset 0dh: rr1 - reload register 1 33.6.2.10 offset 10h: wdtcr - wdt configuration register table 33-34. offset 0dh: rr1 - reload register 1 description: view: ia f base address: base (io) offset start: offset end: 0dh 0dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved reserved 00h 01 tout wdt_timeout: this bit is located in the rtc well and it?s value is not lost if the host resets the system. it is set to ?1? if the host fails to reset the wdt before the 35-bit down-counter reaches zero for the second time in a row. this bit is cleared by performing the register unlocking sequence followed by a ?1? to this bit. 0 = normal (default) 1 = system has become unstable. note: in free running mode this bit is set every time the down counter reaches zero. 0h rw 00 reload wdt_reload: to prevent a timeout the host must perform the register unlocking sequence followed by a ?1? to this bit. refer to section 33.6.3.2 for details on how to change the value of this register. 0h rw table 33-35. offset 10h: wdtcr - wdt configuration register (sheet 1 of 2) description: view: ia f base address: base (io) offset start: offset end: 10h 10h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 06 reserved reserved 00h 05 wdt_tout_en wdt timeout output enable: this bit indicates whether or not the wdt toggles the external wdt_tout# pin if the wdt times out. 0 = enabled (default) 1 = disabled 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1200 order number: 320066-003us 04 : 03 reserved reserved 00h 02 wdt_pre_sel wdt prescaler select: the wdt provides two options for prescaling the main down counter. the preload values are loaded into the main down counter right justified. the prescaler adjusts the starting point of the 35-bit down counter. 0 = the 20-bit preload value is loaded into bits 34:15 of the main down counter. the resulting timer clock is the pci clock (33 mhz) divided by 2 15 . the approximate clock generated is 1 khz, (1 ms to 10 min). (default) 1 = the 20-bit preload value is loaded into bits 24:05 of the main down counter. the resulting timer clock is the pci clock (33 mhz) divided by 2 5 . the approximate clock generated is 1 mhz, (1 s to 1sec) 0h rw 01 : 00 wdt_int_type wdt_int_type: the wdt timer supports programmable routing of interrupts. the set of bits allows the user to choose the type of interrupt desired if the wdt reached the end of the first stage without being reset. the interrupt status is reported in the wdt general interrupt status register. 00 serirq (default) 01 nmi 10 smi 11 disabled note: serirq is active low 00h rw table 33-35. offset 10h: wdtcr - wdt configuration register (sheet 2 of 2) description: view: ia f base address: base (io) offset start: offset end: 10h 10h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1201 intel ? ep80579 integrated processor 33.6.2.11 offset 18h: wdtlr - wdt lock register table 33-36. offset 18h: wdtlr - wdt lock register description: view: ia f base address: base (io) offset start: offset end: 18h 18h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved reserved 0h 02 wdt_tout_cn f wdt timeout configuration: this register is used to choose the functionality of the timer. 0 = watchdog timer mode: when enabled (i.e. wdt_enable goes from ?0? to ?1?) the timer reloads preload value 1 and start decrementing. (default) upon reaching the second stage timeout the wdt_tout# is driven low once and does not change again until power is cycled or a hard reset occurs. 1 = free running mode: wdt_tout# changes from previous state when the next timeout occurs. the timer ignores the first stage. the timer only uses preload value 2. in this mode the timer is restarted whenever wdt_enable goes from a 0 to a 1. this means that the timer reloads preload value 2 and start decrementing every time it is enabled. in free running mode it is not necessary to reload the timer as it is done automatically every time the descrementer reaches zero. 0h rw 01 wdt_enable watchdog timer enable: the following bit enables or disables the wdt. 0 = disabled (default) 1 = enabled note: this bit cannot be modified if wdt_lock has been set. note: in free-running mode preload value 2 is reloaded into the down counter every time wdt_enable goes from ?0? to ?1?. note: in wdt mode preload value 1 is reloaded every time wdt_enable goes from ?0? to ?1? or the wdt_reload bit is written using the proper sequence of writes (see register unlocking sequence). when the wdt second stage timeout occurs, a reset must happen. note: software must guarantee that a timeout is not about to occur before disabling the timer. a reload sequence is suggested. 0h rw 00 wdt_lock watchdog timer lock: setting this bit locks the values of this register until a hard-reset occurs or power is cycled. 0 = unlocked (default) 1 = locked note: writing a ?0? has no effect on this bit. write is only allowed from ?0? to ?1? once. it cannot be changed until either power is cycled or a hard- reset occurs. 0h rwl
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1202 order number: 320066-003us 33.6.3 theory of operation 33.6.3.1 rtc well and wdt_tout# functionality the wdt_timeout bit is set to a ?1? when the wdt 35-bit down counter reaches zero for the second time in a row. then the wdt_tout# pin is toggled low by the wdt from the iich. the board designer must attach the wdt_tout# to the appropriate external signal. if wdt_tout_cnf is a ?1? the wdt toggles wdt_tout# again the next time a time out occurs. otherwise wdt_tout# is driven low until the system is reset or power is cycled. 33.6.3.2 register unlocking sequence the register unlocking sequence is necessary whenever writing to the reload register or either preload_value registers. the host must write a sequence of two writes to offset bar1 + 0ch before attempting to write to either the wdt_reload and wdt_timeout bits of the reload register or the preload_value registers. the first writes are ?80? and ?86? (in that order) to offset bar1 + 0ch. the next write is to the proper memory mapped register (e.g., reload, preload_value_1, preload_value_2). any deviation from the sequence (writes to memory-mapped registers) causes the host to have to restart the sequence. when performing register unlocking, software must issue the cycles using byte access only. otherwise the unlocking sequence will not work properly. the following is an example of how to prevent a timeout: 1. write ?80? to offset bar1 + 0ch. 2. write ?86? to offset bar1 + 0ch. 3. write a ?1? to reload [8] (wdt_reload) of the reload register. note: any subsequent writes require that this sequence be performed again. 33.6.3.3 reload sequence to keep the timer from causing an interrupt or driving wdt_tout#, the timer must be updated periodically. other timers refer to ?updating the timer? as ?kicking the timer?. the frequency of updates required is dependent on the value of the preload values. to update the timer the register unlocking sequence must be performed followed by writing a ?1? to bit 8 at offset bar1 + 0ch within the watchdog timer memory mapped space. this sequence of events is referred to as the ?reload sequence?. 33.6.3.4 low power state the watchdog timer does not operate when pciclk is stopped.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1203 intel ? ep80579 integrated processor 33.7 serial irq the siw supports the serial interrupt to transmit interrupt information to the host system. the serial interrupt scheme adheres to the serial irq specification . 33.7.1 timing diagrams for siw_serirq cycle notes: 1. h=host control; r=recovery; t=turn-around; sl=slave control; s=sample 2. start frame pulse can be 4-8 clocks wide depending on the location of the device in the pci bridge hierarchy in a synchronous bridge design. notes: 1. h=host control; r=recovery; t=turn-around; s=sample; i=idle 2. stop pulse is two clocks wide for quiet mode, three clocks wide for continuous mode. 3. there may be none, one or more idle states during the stop frame. 4. the next siw_serirq cycle?s start frame pulse may or may not start immediately after the turn- around clock of the stop frame. 33.7.1.1 siw_serirq cycle control there are two modes of operation for the siw_serirq start frame. 1. quiet (active) mode : any device may initiate a start frame by driving the siw_serirq low for one clock, while the siw_serirq is idle. after driving low for one clock the siw_serirq is immediately tri-stated without at any time driving high. a start frame may not be initiated while the siw_serirq is active. the siw_serirq is idle between stop and start frames. the siw_serirq is active figure 33-3. start frame timing with source sampled a low pulse on irq1 figure 33-4. stop frame timing with host using quiet mode sampling period
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1204 order number: 320066-003us between start and stop frames. this mode of operation allows the siw_serirq to be idle when there are no irq/data transitions which should be most of the time. once a start frame has been initiated the host controller takes over driving the siw_serirq low in the next clock and continues driving the siw_serirq low for a programmable period of three to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller drives the siw_serirq back high for one clock, then tri-state. any siw_serirq device (i.e., the siu and wdt) which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host controller unless the si w_serirq is already in an siw_serirq cycle and the irq/data transition can be delivered in that siw_serirq cycle. 2. continuous (idle) mode : only the host controller can initiate a start frame to update irq/ data line information. all other siw_serirq agents become passive and may not initiate a start frame. siw_serirq is driven low for four to eight clocks by host controller. this mode has two functions. it can be used to stop or idle the siw_serirq or the host controller can operate siw_serirq in a continuous mode by initiating a start frame at the end of every stop frame. an siw_serirq mode transition can only occur during the stop frame. upon reset, siw_serirq bus is defaulted to continuous mode, therefore only the host controller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next siw_serirq cycle?s mode. 33.7.1.2 siw_serirq data frame once a start frame has been initiated, the siw watches for the rising edge of the start pulse and start counting irq/data frames fr om there. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase the siw drives the siw_serirq low, if and only if, its last detected irq/data value was low. if its detected irq/data value is high, siw_serirq is left tri-stated. during the recovery phase the siw drives the siw_serirq high, if and only if, it had driven the siw_serirq low during the previous sample phase. during the turn-around phase the siw tri-states the siu_serirq. the siw drives the siw_serirq line low at the appropriate sample point if its associated irq/data line is low, regardless of which device initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minus one. (e.g., the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17th clock after the rising edge of the start pulse). table 33-37. siw_serirq sampling periods (sheet 1 of 2) siw_serirq period signal sampled # of clocks past start 1not used 2 2irq1 5 3irq2 8 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9irq8 26 10 irq9 29 11 irq10 32
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1205 intel ? ep80579 integrated processor siw_serirq period 14 is used to transfer irq13. logical devices 4 (serial port 1), 5 (serial port 2) and 6 (wdt) shall have irq13 as a choice for their primary interrupt. 33.7.1.3 stop cycle control once all irq/data frames have completed the host controller terminates siw_serirq activity by initiating a stop frame. only the host controller can initiate the stop frame. a stop frame is indicated when the siw_serirq is low for two or three clocks. if the stop frame?s low time is two clocks then the next siw_serirq cycle?s sampled mode is the quiet mode; and any siw_serirq device may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. if the stop frame?s low time is three clocks then the next siw_serirq cycle?s sampled mode is the continuous mode; and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. 33.7.1.4 latency latency for irq/data updates over the siw_serirq bus in bridge-less systems with the minimum host supported irq/data frames of seventeen, ranges up to 96 clocks (2.88 s with a 33 mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/ data updates from the secondary or tertiary buses are a few clocks longer for synchronous buses, and approximately double for asynchronous buses. 33.7.1.5 eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transition that it should have followed. this could cause a system fault. the host interrupt controller is responsible for ensuring that these latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the siw_serirq cycle latency in order to ensure that these events do not occur out of order. 33.7.1.6 reset and initialization the siw_serirq bus uses siw_lreset# as its reset signal. the siw_serirq pin is tri-stated by all agents while siw_lreset# is active. with reset, siw_serirq slaves are put into the (continuous) idle mode. the host controller is responsible for starting the initial siw_serirq cycle to collect system?s irq/data default values. the system then follows with the continuous/ quiet mode protocol (stop frame pulse width) for subsequent siw_serirq cycles. it is host controller?s responsibility to provide the default values to the interrupt controller and other system logic before the first siw_serirq cycle is performed. for siw_serirq system suspend, insertion, or removal application, the host controller must be programmed into continuous (idle) mode first. this is to guarantee siw_serirq bus is in idle state before the system configuration changes. 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 table 33-37. siw_serirq sampling periods (sheet 2 of 2) siw_serirq period signal sampled # of clocks past start
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1206 order number: 320066-003us 33.8 configuration the configuration of the siw is very flexible and is based on the configuration architecture implemented in typical plug-and-play components. the siw is designed for motherboard applications in which the resources required by their components are known. with its flexible resource allocation architecture, the siw allows the bios to assign resources at post. 33.8.1 configuration port address the siw configuration port addresses for index and data are controlled by the strap pin siu1_dtr# during reset. when siu1_dtr# is driven to ?1? or left floating during reset siw configuration port addresses are fixed at 4eh/4fh. when siu1_dtr# is driven to ?0? during reset siw configuration port addresses are fixed at 20eh/20fh. 33.8.2 primary configur ation address decoder after a pci reset (siw_lreset# pin asserted) or power on reset the siw is in the run mode with the uarts and watchdog timer disabled. they may be configured through two standard configuration i/o ports (index and data) by placing the siw into configuration mode. the bios uses these configuration ports to initialize the logical devices at post. the index and data ports are only valid when the siw is in configuration mode. the index and data ports are effective only when the chip is in the configuration state. when the siw is not in the configuration state, reads return ffh and write data is ignored. 33.8.2.1 entering the configuration state the device enters the configuration state by the following contiguous sequence: 1. write 80h to configuration index port. 2. write 86h to configuration index port. 33.8.2.2 exiting the configuration state the device exits the configuration state by the following contiguous sequence: 1. write 68h to configuration index port. 2. write 08h to configuration index port. 33.8.2.3 configuration sequence to program the configuration registers, the following sequence must be followed. 1. enter configuration mode. 2. configure the configuration registers. 3. exit configuration mode. 33.8.2.4 configuration mode the system sets the logical device information and activates desired logical devices through the index and data ports. in configuration mode, the index port is located at the config port address and the data port is at index port address + 1.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1207 intel ? ep80579 integrated processor the desired configuration registers are accessed in two steps: 1. write the index of the logical device number configuration register (i.e., 07) to the index port and then write the number of the desired logical device to the data port. 2. write the address of the desired configuration register within the logical device to the index port and then write or read the configuration register through the data port. note: if accessing the global configuration registers, step (1) is not required. the chip returns to the run state. note: only two states are defined (run and configuration). in the run state the chip is always ready to enter the configuration state. 33.8.3 siw configurat ion register summary the default values are defined with an h for hex, a bi for binary, or 00 for zero. if there is not a letter following the default value, assume it is a binary number. warning: address locations that are not listed are considered reserved register locations. reads to reserved registers may re turn non-zero values. writes to reserved locations may cause system failure. note: reserved bits are read only. table 33-38. configuration register summary (sheet 1 of 2) global configuration registers index type default configuration register 07h rw 00h logical device number 20h r 00h device id 21h r 01h device rev 28h rw 01h siw i/f (wait states) 29h rw 02h sirq configuration 2eh rw 00h test mode configuration register logical device 4 registers (serial port 1) 30h rw 00h enable 60h rw 00h base i/o address msb 61h rw 00h base i/o address lsb 70h rw 00h primary interrupt select 74h rw 04h rsvd 75h rw 04h rsvd f0h rw 00h rsvd logical device 5 registers (serial port 2) 30h rw 00h enable 60h rw 00h base i/o address msb 61h rw 00h base i/o address lsb 70h rw 00h primary interrupt select
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1208 order number: 320066-003us 33.8.3.1 global control/configuration registers [00h - 2fh] the chip-level (global) registers lie in the address range [00h-2fh]. the design must use all eight bits of the address port for register selection. all unimplemented registers and bits ignore writes and return zero when read. the index port is used to select a configuration register in the chip. the data port is then used to access the selected register. these registers are accessible only in the configuration mode. 74h rw 04h rsvd 75h rw 04h rsvd f0h rw 00h rsvd logical device 6 registers (watchdog timer) 30h rw 00h enable 60h rw 00h base i/o address msb 61h rw 00h base i/o address lsb 70h rw 00h primary interrupt select table 33-38. configuration register summary (sheet 2 of 2) register address (type) description logical device #` default = 00h 07h (rw) logical device select : a write to this register selects the current logical device. this allows access to the control and configuration registers for each logical device. device id default = 00h 20h (r) device id: a read only register which provides the device id. device rev default = 01h 21h (r) device rev: a read only register which provides device revision information. siw interface default = 01h 28h c bit 7:1 rsvd = 0 bit 0 lpc bus wait states 0 = not supported 1 = long wait states (sync 6) siw configuration default = 02h 29h (rw - bit 0, 2, 3) (r - bit 1) bit 0 sirq enable 1 =enabled; enabled logical devices participate in interrupt generation 0 =disabled; serial interrupts disabled bit 1 irq mode (read only, writes ignored) 1 =continuous mode 0 =quiet mode bit 3:2 uart_clk predivide 00 = divide by 1 01 = divide by 8 10 = divide by 26 11 = reserved bit 7:4 rsvd = 0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1209 intel ? ep80579 integrated processor 33.8.3.2 logical device configuration registers [30h ? ffh] used to access the registers that are assigned to each logical unit. this chip supports three logical units and has three sets of logical device registers. the three logical devices are uart1, uart2 and watchdog timer. a separate set (bank) of control and configuration registers exists for each logical device and is selected with the logical device # register. the index port is used to select a specific logical device register. these registers are then accessed through the data port. the logical device registers are accessible only when the device is in the configuration state. the logical register addresses are shown in the tables below. siw monitor port control register default = 00h 2d (ro - bit 7) (rw - bits 6:0) bit 0 uart1 monitor port enable (uart1_monporten): setting this bit enables the monitor port for uart1. this signal turns on all 8 uart2 monitor ports. note: wdt_monporten, uart2_monporten and uart1_monporten must be set in a mutually exclusive manner i.e., only one monitor port enable must be set at one time. bit 1 uart2 monitor port enable (uart2_monporten): setting this bit enables the monitor port for uart2. this signal turns on all 8 uart1 monitor ports. note: wdt_monporten, uart2_monporten and uart1_monporten must be set in a mutually exclusive manner i.e., only one monitor port enable must be set at one time. bit 2 wdt monitor port enable (wdt_monporten): setting this bit enables the monitor port for wdt. this signal turns on all 16 siw monitor ports. note: wdt_monporten, uart2_monporten and uart1_monporten must be set in a mutually exclusive manner i.e., only one monitor port enable must be set at one time. bit 6:3 monitor port slot select[3:0] (monportsel): these bits select which monitor port slot is enabled. these bits are used to select up to 16 slots within each uart1 and uart2 source group. note: wdt has only 1 slot. so, port slot selection is not required. bit 7 rsvd = 0 default = 00h 2eh reserved register address (type) description
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1210 order number: 320066-003us table 33-39. logical device 4 (serial port 1) logical device register address description enable default = 00h 30h (rw) bits[7:1] reserved, set to zero. bit[0] 1 =enable the logical device currently selected through the logical device # register. 0 =logical device currently selected is inactive i/o base address default = 00h 60h (rw) 61h (bits 7:3 rw bits 2:0 ro) registers 60h (msb) and 61h (lsb) set the base address for the device. note: decode is on 8 byte boundaries comm decode ranges 3f8 - 3ff (com 1) 2f8 - 2ff (com 2) 220 - 227 228 - 22f 238 - 23f 2e8 - 2ef (com 4) 338 - 33f 3e8 - 3ef (com 3) primary interrupt select default = 00h 70h (rw) bits[3:0] selects which interrupt level is used for the primary interrupt. 00= no interrupt selected 01= irq1 02= irq2 03= irq3 04= irq4 05= irq5 06= irq6 07= irq7 08= irq8 09= irq9 0a= irq10 0b= irq11 0c= irq12 0d= irq13 0e= irq14 0f= irq15 bits[7:4] reserved note: an interrupt is activated by enabling this device (offset 30h), setting this register to a non-zero value and setting any combination of bits 0-4 in the corresponding uart ier and the occurrence of the corresponding uart event (i.e. modem status change, receiver line error condition, transmit data request, receiver data available or receiver time out) and setting the out2 bit in the mcr. reserved default = 04h 74h bit 7:0 - reserved reserved default = 04h 75h bit 7:0 - reserved reserved default = 00h f0h bit 7:0 - reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1211 intel ? ep80579 integrated processor table 33-40. logical device 5 (serial port 2) logical device register address description enable default = 00h 30h (rw) bits[7:1] reserved, set to zero. bit[0] 1 =enable the logical device currently selected through the logical device # register. 0 =logical device currently selected is inactive i/o base address default = 00h 60h (rw) 61h (bits 7:3 rw bits 2:0 ro) registers 60h (msb) and 61h (lsb) set the base address for the device. note: decode is on 8 byte boundaries comm decode ranges 3f8 - 3ff (com 1) 2f8 - 2ff (com 2) 220 - 227 228 - 22f 238 - 23f 2e8 - 2ef (com 4) 338 - 33f 3e8 - 3ef (com 3) primary interrupt select default = 00h 70h (rw) bits[3:0] selects which interrupt level is used for the primary interrupt. 00= no interrupt selected 01= irq1 02= irq2 03= irq3 04= irq4 05= irq5 06= irq6 07= irq7 08= irq8 09= irq9 0a= irq10 0b= irq11 0c= irq12 0d= irq13 0e= irq14 0f= irq15 bits[7:4] reserved note: an interrupt is activated by enabling this device (offset 30h), setting this register to a non-zero value and setting any combination of bits 0-4 in the corresponding uart ier and the occurrence of the corresponding uart event (i.e. modem status change, receiver line error condition, transmit data request, receiver data available or receiver time out) and setting the out2 bit in the mcr. reserved default = 04h 74h bit 7:0 - reserved reserved default = 04h 75h bit 7:0 - reserved reserved default = 00h f0h bit 7:0 - reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1212 order number: 320066-003us table 33-41. logical device 6 (watch dog timer) logical device register address description enable default = 00h 30h (rw) bits[7:1] reserved, set to zero. bit[0] 1 =enable the logical device currently selected through the logical device # register. 0 =logical device currently selected is inactive i/o base address default = 00h 60h (rw) 61h (bits 7:5 rw bits 4:0 ro) registers 60h (msb) and 61h (lsb) set the base address for the device. note: decode is on 32 byte boundaries. wdt base address is generated by using the lpc generic decode range 1 register (lg1), see d31:f0:84h for more details. this base address must be within the 128 bytes of lg1 base register. also the last byte accessed by the wdt must not exceed the lg1 base address +128 bytes. primary interrupt select default = 00h 70h (rw) bits[3:0] selects which interrupt level is used for the primary interrupt. 00= no interrupt selected 01= irq1 02= irq2 03= irq3 04= irq4 05= irq5 06= irq6 07= irq7 08= irq8 09= irq9 0a= irq10 0b= irq11 0c= irq12 0d= irq13 0e= irq14 0f= irq15 bits[7:4] reserved note: an interrupt is activated by enabling this device (offset 30h), setting this register to a non-zero value and when the first stage has been allowed to reach zero. an interrupt is not generated if wdt_tout_cnf is set to change output after every timeout (see wdt lock register).
order number: 320066-003us acceleration and i/o complex, volume 4 of 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1214 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1215 intel ? ep80579 integrated processor 34.0 pci-to-pci bridge 34.1 summary the pci-to-pci bridge provides an interface between the aioc and the mch/ia. pci-to- pci bridge forwards data and commands from aioc memory target to the pci-to-pci bridge (upstream interface). it also provide the ia a path into the aioc via the pci-to- pci bridge (downstream interface). 34.2 pci-to-pci bridge detailed register descriptions table 34-1. bus 0, device 4, function 0: summary of pci-to-pci bridge pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 0h 1h ?offset 0h: vid: vendor identification register? on page 1217 8086h 2h 3h ?offset 2h: did: device identification register? on page 1217 5037h 4h 5h ?offset 4h: pcicmd: device command register? on page 1217 0h 6h 7h ?offset 6h: pcists: pci device status register? on page 1218 10h 8h 8h ?offset 8h: rid: revision id register? on page 1219 variable 9h bh ?offset 9h: cc: class code register? on page 1219 060400h ch ch ?offset ch: cls: cacheline size register? on page 1219 00h dh dh ?offset dh: lt: latency timer register? on page 1220 00h eh eh ?offset eh: hdr: header type register? on page 1220 1h 10h 14h ?offset 10h: csrbar0: control and status registers base address register? on page 1220 00h 14h 17h ?offset 14h: csrbar1: control and status registers base address register? on page 1221 00h 18h 18h ?offset 18h: pbnum: primary bus number register? on page 1221 00h 19h 19h ?offset 19h: secbnm: secondary bus number register? on page 1221 00h 1ah 1ah ?offset 1ah: subbnm: subordinate bus number register? on page 1222 00h 1bh 1bh ?offset 1bh: seclt: secondary latency timer register? on page 1222 00h 1ch 1ch ?offset 1ch: iob: i/o base register? on page 1222 f0 1dh 1dh ?offset 1dh: iol: i/o limit register? on page 1223 0 1eh 1fh ?offset 1eh: secsta: secondary status register? on page 1223 0h 20h 21h ?offset 20h: memb: memory base register? on page 1224 fff0 22h 23h ?offset 22h: meml: memory limit register? on page 1224 0 24h 25h ?offset 24h: pmase: prefetchable memory base register? on page 1225 fff1h 26h 27h ?offset 26h: pmlimit: prefetchable memory limit register? on page 1225 1h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1216 order number: 320066-003us 34.2.1 pci-to-pci bridge header the pci-to-pci bridge header format is given in ta bl e 3 4 - 2 . 28h 28h ?offset 28h: pmbasu: memory limit register? on page 1226 fh 2ch 2ch ?offset 2ch: pmlmtu: prefetchable memory limit upper register? on page 1226 0 30h 31h ?offset 30h: iobu: i/o base upper register? on page 1227 0 32h 33h ?offset 32h: iolu: i/o limit upper register? on page 1227 0 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1227 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1228 0 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1228 0 3eh 3fh ?offset 3eh: bctl: bridge control register? on page 1228 0000h dch dch ?offset dch: pcid: power management capability id register? on page 1229 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1230 00h deh dfh ?offset deh: pmcap: power management capability register? on page 1230 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1231 0008h e2h e2h ?offset e2h: pmcse: power management control and status extension register? on page 1232 0000h table 34-1. bus 0, device 4, function 0: summary of pci-to-pci bridge pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 34-2. pci-to-pci bridge pci header byte offset +7 +6 +5 +4 +3 +2 +1 +0 status command device id vendor id bist type lt cls class code rev base address 1 base address 0 secondary status i/o limit i/o base scdry. lat. timer subord. bus num scdry. bus num primary bus num pref. mem. limit pref. mem. base memory limit memory base prefetchable limit upper 32 bits prefetchable base upper 32 bits reserved cp i/o limit upper i/o base upper bridge control irq p irq l expansion rom base
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1217 intel ? ep80579 integrated processor 34.2.2 pci-to-pci bridge configuration space 34.2.2.1 offset 0h: vid ? vendor identification register 34.2.2.2 offset 2h: did ? device identification register 34.2.2.3 offset 4h: pcicmd ? device command register table 34-3. offset 0h: vid: vendor identification register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 0h 1h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor id 8086h ro table 34-4. offset 2h: did: device identification register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 2h 3h size: 16 bit default: 5037h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device id 5037h ro table 34-5. offset 4h: pcicmd: device command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 4h 5h size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 rv reserved 0h rv 10 intd interrupt disable 0h rw 09 fbtb fast back-to-back enable 0h ro 08 ser serr# enable 0h rw 07 rv reserved 0h rv 06 per parity error response 0h rw 05 vps vga palette snoop 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1218 order number: 320066-003us 34.2.2.4 offset 6h: pcists ? device status register 04 mwe memory write and invalidate 0h ro 03 ss special cycle 0h ro 02 bm bus master capable 0h rw 01 mem memory space enable 0h rw 00 io i/o space enable 0h rw table 34-6. offset 6h: pcists: pci device status register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 6h 7h size: 16 bit default: 10h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error 0h ro 14 sse signaled system error 0h ro 13 rma received master abort 0h ro 12 rta received target abort 0h ro 11 sta signaled target abort 0h ro 10 : 09 dst devsel timing 00b ro 08 mdpe master data parity error 0h ro 07 fb2b fast back-to-back capable 0h ro 06 rv reserved 0h rv 05 mc66 66 mhz capable 0h ro 04 cl capabilities list 1 ro 03 is interrupt status 0h ro 02 : 00 rv reserved 0h rv table 34-5. offset 4h: pcicmd: device command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 4h 5h size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1219 intel ? ep80579 integrated processor 34.2.2.5 offset 8h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. 34.2.2.6 offset 9h: cc ? class code register 34.2.2.7 offset ch: cls ? cacheline size register table 34-7. offset 8h: rid: revision id register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 8h 8h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision id. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 34-8. offset 9h: cc: class code register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 9h bh size: 24 bit default: 060400h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code 060400h ro table 34-9. offset ch: cls: cacheline size register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: ch ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cls cacheline size 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1220 order number: 320066-003us 34.2.2.8 offset dh: lt ? latency timer register 34.2.2.9 offset eh: hdr ? header type register 34.2.2.10 offset 10h: csrbar0 ? control and status registers base address register table 34-10. offset dh: lt: latency timer register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: dh dh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 lt latency timer 0h ro table 34-11. offset eh: hdr: header type register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: eh eh size: 8 bit default: 1h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type 1 ro table 34-12. offset 10h: csrbar0: control an d status registers base address register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 10h 14h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 zero these bits of the address are hardwired to zero for 128 kbyte. 0h ro 03 pref prefetchable 0h ro 02 : 01 typ bar type (64-bit) 00b ro 00 mem memory space indicator 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1221 intel ? ep80579 integrated processor 34.2.2.11 offset 14h: csrbar1 ? control and status registers base address register 34.2.2.12 offset 18h: pbnum ? primary bus number register 34.2.2.13 offset 19h: secbnm ? secondary bus number register table 34-13. offset 14h: csrbar1: control and status registers base address register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 14h 17h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 zero these bits of the address are hardwired to zero for 128 kbyte. 0h ro 03 pref prefetchable 0h ro 02 : 01 typ bar type (64-bit) 0b ro 00 mem memory space indicator 0h ro table 34-14. offset 18h: pbnum: primary bus number register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 18h 18h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pbnum primary bus number 0h rw table 34-15. offset 19h: secbnm: secondary bus number register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 19h 19h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 secbnm secondary bus number 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1222 order number: 320066-003us 34.2.2.14 offset 1ah: subbnm ? subordinate bus number register 34.2.2.15 offset 1bh: seclt ? secondary latency timer register 34.2.2.16 offset 1ch: iob ? i/o base register this register (together with iobu) specifies the starting i/o address of devices in the aioc infrastructure. the range is aligned to a 4k boundary, so address bits [11:0] are assumed to be zero. table 34-16. offset 1ah: subbnm: subordinate bus number register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 1ah 1ah size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 subbnm subordinate bus number 0h rw table 34-17. offset 1bh: seclt: secondary latency timer register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 1bh 1bh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 seclt secondary latency timer 0h ro table 34-18. offset 1ch: iob: i/o base register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 1ch 1ch size: 8 bit default: f0 power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 iob these bits correspond to address bits [15:12] of the i/o transaction. address bits [13:16] are matched with iobu. fh rw 03 : 00 ioaw the value ?1? means that we implement 32-bit i/o space. 0 ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1223 intel ? ep80579 integrated processor 34.2.2.17 offset 1dh: iol ? i/o limit register this register (together with iolu) specifies the ending i/o address of devices in the aioc infrastructure. the range is aligned to a 4k boundary, so address bits [11:0] are assumed to be fff. 34.2.2.18 offset 1eh: secsta ? secondary status register table 34-19. offset 1dh: iol: i/o limit register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 1dh 1dh size: 8 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 iol these bits correspond to address bits [15:12] of the i/o transaction. address bits [13:16] are matched with iolu. 0h rw 03 : 00 ioaw the value ?1? means that we implement 32-bit i/o space. 0 ro table 34-20. offset 1eh: secsta: secondary status register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 1eh 1fh size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error 0h ro 14 rse received system error 0h ro 13 rma received master abort 0h ro 12 rta received target abort 0h ro 11 sta signaled target abort 0h ro 10 : 09 dst devsel timing 00b ro 08 mdpe master data parity error 0h ro 07 fb2b fast back-to-back capable 0h ro 06 rv reserved 0h rv 05 mc66 66 mhz capable 0h ro 04 : 00 rv reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1224 order number: 320066-003us 34.2.2.19 offset 20h: memb ? memory base register this register specifies the starting memory address of devices in the aioc infrastructure. the range is aligned to a 1m boundary, so address bits [19:0] are assumed to be zero. 34.2.2.20 offset 22h: meml ? memory limit register this register specifies the ending memory address of devices in the aioc infrastructure. the range is aligned to a 1m boundary, so address bits [19:0] are assumed to be fffff. table 34-21. offset 20h: memb: memory base register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 20h 21h size: 16 bit default: fff0 power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 memb these bits correspond to address bits [31:20] of the transaction. fffh rw 03 : 00 rv reserved 0h ro table 34-22. offset 22h: meml: memory limit register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 22h 23h size: 16 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 meml these bits correspond to address bits [31:20] of the transaction. 0h rw 03 : 00 rv reserved 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1225 intel ? ep80579 integrated processor 34.2.2.21 offset 24h: pmbase ? prefetchable memory base register note: prefetchable memory space is not used by aioc in the ep80579. bios and enumeration software must be checked to make sure these default values are never modified to enable prefetchable memory space. writing to this register can result in undefined behavior. 34.2.2.22 offset 26h: pmlimit ? prefetchable memory limit register note: prefetchable memory space is not used by aioc in the ep80579. bios and enumeration software must be checked to make sure these default values are never modified to enable prefetchable memory space. writing to this register can result in undefined behavior. table 34-23. offset 24h: pmase: prefetchable memory base register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 24h 25h size: 16 bit default: fff1h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 pmbase these bits correspond to address bits [31:20] of the transaction. fffh rw 03 : 01 mamb memory addressing mode. 0h ro 0mbaue 0 = disabled 1 = enabled. base address is further defined by the bits of the memory base upper register 1ro table 34-24. offset 26h: pmlimit: prefetchable memory limit register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 26h 27h size: 16 bit default: 1h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 04 meml these bits correspond to address bits [31:20] of the transaction. 0h rw 03 : 01 maml memory addressing mode. 0h ro 0mlaue 0 = disabled 1 = enabled. base address is further defined by the bits of the memory base upper register 1ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1226 order number: 320066-003us 34.2.2.23 offset 28h: pmbasu ? prefetchable memory base upper register note: prefetchable memory space is not used by aioc. bios and enumeration software must be checked to make sure these default values are never modified to enable prefetchable memory space. writing to this register can result in undefined behavior. 34.2.2.24 offset 2ch: pmlmtu ? prefetchable memory limit upper register note: prefetchable memory space is not used by aioc. bios and enumeration software must be checked to make sure these default values are never modified to enable prefetchable memory space. writing to this register can result in undefined behavior. table 34-25. offset 28h: pmbasu: memory limit register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 28h 28h size: 8bit default: fh power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 rsv these bits are reserved 0h ro 03 : 00 bua base upper address fh rw table 34-26. offset 2ch: pmlmtu: prefetchable memory limit upper register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 2ch 2ch size: 8 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 04 rsv reserved 0h ro 03 : 00 lua limit upper address 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1227 intel ? ep80579 integrated processor 34.2.2.25 offset 30h: iobu ? i/o base upper register this register provides the upper 16 bits for iob. 34.2.2.26 offset 32h: iolu ? i/o limit upper register this register provides the upper 16 bits for iol. 34.2.2.27 offset 34h: cp ? capabilities pointer register table 34-27. offset 30h: iobu: i/o base upper register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 30h 31h size: 16 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 iobu these bits correspond to address bits [31:16] of the i/o transaction. 0h ro table 34-28. offset 32h: iolu: i/o limit upper register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 32h 33h size: 16 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 iolu these bits correspond to address bits [31:16] of the i/o transaction. 0h ro table 34-29. offset 34h: cp: capabilities pointer register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp capabilities pointer dch ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1228 order number: 320066-003us 34.2.2.28 offset 3ch: irql ? interrupt line register 34.2.2.29 offset 3dh: irqp ? interrupt pin register 34.2.2.30 offset 3eh: bctl ? bridge control register bits in this register such as vga enable and isa enable are rw bits for software compatibility, but don?t affect the behavior of the bridge. table 34-30. offset 3ch: irql: interrupt line register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 3ch 3ch size: 8 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irql interrupt line 0h ro table 34-31. offset 3dh: irqp: interrupt pin register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 3dh 3dh size: 8 bit default: 0 power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irqp interrupt pin 1 ro table 34-32. offset 3eh: bctl: bridge control register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 3eh 3fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 12 irqp interrupt pin 0 ro 11 dtse discard timer serr enable 0h ro 10 dts discard timer status 0h ro 09 sdt secondary discard timer 0h ro 08 pdt primary discard timer 0h ro 07 fb2b fast back to back enable 0h ro 06 secr secondary bus reset 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1229 intel ? ep80579 integrated processor 34.2.2.31 offset dch: pcid ? power management capability id register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . 05 mamode master abort mode 0h ro 04 vga16 vga 16-bit decode 0h ro 03 vgaen vga enable 0h rw 02 isaen isa enable 0h rw 01 serren serr# enable 0h rw 00 pren parity error response enable 0h rw table 34-32. offset 3eh: bctl: bridge control register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: 3eh 3fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access table 34-33. offset dch: pcid: power management capability id register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management capability) 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1230 order number: 320066-003us 34.2.2.32 offset ddh: pcp ? power management next capability pointer register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . 34.2.2.33 offset deh: pmcap ? power management capability register for an overview of the power management capability of the ep80579 integrated processor aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . table 34-34. offset ddh: pcp: power manage ment next capability pointer register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: ddh ddh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro table 34-35. offset deh: pmcap: powe r management capability register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: deh dfh size: 16 bit default: 0023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support 0h ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 reserved reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1231 intel ? ep80579 integrated processor 34.2.2.34 offset e0h: pmcs ? power management control and status register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . table 34-36. offset e0h: pmcs: power management control and status register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: e0h e1h size: 16 bit default: 0008h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status - this bit is sticky for device 0 which is on suspend well, but not for the other 2 which aren?t on a power well. 0h ro 14 : 13 data_scale data scale 00b ro 12 : 09 data_sel data select 0000b ro 08 pme_en pme enable - this bit is sticky for device 0 which is on suspend well, but not for the other 2 which aren?t on a power well. 0h ro 07 : 04 reserved reserved 0000b ro 03 nsr no soft reset 1 ro 02 reserved reserved 0h ro 01 : 00 ps power state 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1232 order number: 320066-003us 34.2.2.35 offset e2h: pmcse ? power management control and status extension register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . table 34-37. offset e2h: pmcse: power manage ment control and status extension register description: view: pci bar: configuration bus:device:function: 0:4:0 offset start: offset end: e2h e2h size: 8 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 7bpcc_en bus power/clock control enable) - a ?0? indicates that the bus power/clock control policies have been disabled. when the bus power/clock control mechanism is disabled, the bridge?s pmcsr powerstate field cannot be used by the system software to control the power or clock of the bridge?s secondary bus. 0h ro 6 b2_b3_n b2/3 support. with bpcc_en a ?0? this bit is a don?t care 0b ro 5:0 rsv reserved 0000b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1233 intel ? ep80579 integrated processor 35.0 pci-to-pci bridge: aioc configuration 35.1 overview the pci-to-pci bridge provides the ia-32 core/mch fabric an interface to the aioc. it implements pci configuration registers that enable the ia-32 core to enumerate and configure the aioc devices. 35.2 feature list the pci-to-pci bridge implements the following: ? provides the ia-32 core/mch complex access into the aioc. 35.3 pci configuration registers the aioc type 1 pci configuration registers can only be accessed using type 1 config read/write request types. 35.3.1 description of pci co nfiguration header space the pci configuration headers expose the various pci devices on the aioc to the ia infrastructure. the pci specification requires implementation of 64 bytes of pci configuration registers as shown in ta b l e 3 5 - 1 . after a system reset, these registers are initially configured by the bios, and/or ?plug and play? aware operating system. device drivers will then read these registers to determin e what resources (interrupt number, memory mapping location, etc.), the bios and/or os assigned to the device. table 35-1. type 0 pci configuration header byte offset +7 +6 +5 +4 +3 +2 +1 +0 status command device id vendor id bist ty pe lt cl s class code rev base address 1 base address 0 base address 3 base address 2 base address 5 base address 4 subsys id subsys id cardbus cis pointer reserved cp expansion rom base mx l mn g irq p irq l reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1234 order number: 320066-003us the fields shaded in grey are required in all pci devices, and the other fields are optional. in each device section (below) the implemented fields are listed. an explanation of various pci registers is provided below: 1. vendor id this uniquely identifies all intel pci products. a value of 0x8086 is the default for this field upon power up. 2. device id this uniquely identifies the device. 3. command reg .layout is shown below. un-used bits are hard-wired to 0. 4. status register layout is shown below. shaded bits are not used by this implementation and are hard?wired to 0. . figure 35-1. pci configuration command register layout bit(s) initial value description 0 0 i/o access enable 1 0 memory access enable 2 0 enable mastering; device in pci-x mode is permitted to initiate a split completion transaction regardless of the state of this bit 3 0 special cycle monitoring 4 0 memory write and invalidate enable, ignored by the device in pci-x mode 5 0 palette snoop enable 6 0 parity error response 7 0 wait cycle enable 8 0 serr# enable 9 0 fast back-to-back enable, ignored by the device in pci-x mode 10 0 interrupt disable. 15:10 0 reserved figure 35-2. pci configuration status register layout bit(s) initial value description 2:0 0 reserved 3 0 interrupt status. 4 1 new capabilities: indicates that a device implements extended capabilities. a device sets this bit, and implements a capabilities list, to indicate that it supports pci power management, pci-x, and message signaled interrupts. 5 1 66mhz capable 6 0 udf supported 7 0 fast back-to-back capable, this bit must be set to 0 in pci-x mode. 8 0 data parity reported 10:9 01 devsel timing (indicates medium device): indicates conventional devsel timing regardless of the operating mode. 11 0 signaled target abort 12 0 received target abort 13 0 received master abort 14 0 signaled system error 15 0 detected parity error
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1235 intel ? ep80579 integrated processor 5. revision: this is the 1st version of this device, so the revision number is 0x00. 6. class code: the class code, 0x020000 identifies this device as an ethernet adapter. 7. cache line size : used to store the cache line size. the value is in units of 4 bytes. a system with a cache line size of 64b sets the value of this register to 0x10. the only sizes that are supported are 16, 32, 64, and 128 bytes. all other sizes are treated as 0. see exceptions in section 2.11.8 the default value at power up in 0x00. 8. unsupported values affect pci cache line support. all writes default to using the memory write (mw) command, and memory read command determination uses a cache-line size of 32 bytes. 9. latency timer: the lower 2 bits are not implemented and return 0. the upper 6 bits are rw. the default value of the latency timer register is 64 in pci-x mode. 10. header type : this indicates if a device is single function or multifunction. the ep80579 returns a value of 0x00, indicating that it is a normal single function device. 11. bist: bit (built in self-test) will be not be implemented as supportable from pci config space in this version of the device. 12. base address register: the base address registers (or bars) are used to map the ep80579 register space to system memory space. 35.4 interrupt handling for aioc devices interrupts from the aioc devices are routed towards the ia-32 core as either an msi or by asserting the level-sensitive signal intx. the configuration provides a mechanism via the pci configuration header space for functional units in the aioc to interrupt the ia-32 core. most pci configuration headers for aioc devices implement two capability records to support interrupt and signal handling. ? a message signalled interrupt capability record that follows the standard pci format and describes the format of an ia msi. ? an ep80579-specific signal target capability record that is unique to the ep80579 and describes how to target signals from the device. the hardware will provide these capabilities to most of the devices implemented in the configuration bridge except for mdio and the local expansion bus. the software is responsible to enabling/disabling this functionality for each of the devices. table 35-2. messaging and signalling capability record per pci device (sheet 1 of 2) pci device function message capable? signal capable? interrupts (max 8 per device) comment 0 (gbe0) gbe yes yes gbe0 interrupt 0 gbe0 interrupt 1 gbe0 error interrupt 1 (gbe 1) gbe yes yes gbe1 interrupt 0 gbe1 interrupt 1 gbe1 error interrupt 2 (gbe 2) gbe yes yes gbe2 interrupt 0 gbe2 interrupt 1 gbe2 error interrupt
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1236 order number: 320066-003us 35.5 power management of aioc devices the aioc devices support pci bus power management (pm). the supported states are: ? d0: device is on and running which maximum power dissipation ? d3: device is off and power can be removed. the device has lost its context information and will have be re-booted before it can enter the d0 state again. the pm capabilities for the aioc devices are de fined as part of the ca pabilities list in the pci configuration space for each device. figure 35-3 describes the contents of a power management entry in the capability list. pmcsr control bits are provided in part of pci pm registers. these bits control the state of the device. the default value of this bit is 0 and corresponds to the d0 state. note: it is the responsibility of software to ensure that the devices and all of its function are in quiescent state it is also the responsibility of software to disable memory, i/o space (as appropriate) disabled, and interrupts (as appropriate) in the pcicmd register prior to powering down the device. 3 (mdio) mdio no no 4 (can 0) can yes yes can0 system interrupt can0 parity interrupt 5 (can 1) can yes yes can1 system interrupt can1 parity interrupt 6 (ssp) ssp yes yes ssp interrupt 7 (1588) 1588 interface yes yes ieee 1588 interrupt 8 (local expansion bus) local expansion bus yes yes exp expansion-bus parity error internal interrupt table 35-2. messaging and signalling capability record per pci device (sheet 2 of 2) pci device function message capable? signal capable? interrupts (max 8 per device) comment figure 35-3. pci power management register block byte 3 byte 2 byte 1 byte 0 power management capabilities (pmc) next item ptr capability id data pmcsr_bse bridge support extensions power management control / status register (pmcsr)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1237 intel ? ep80579 integrated processor 35.6 gigabit ethernet mac config uration spaces: bus m, device 0-2, function 0 gigabit mac 0, 1, and 2 are devices 0, 1, and 2 of bus m, respectively, and are accessed using type 1 configuration cycles. all macs implement configuration spaces as defined in this section. during an eeprom read the configuration space will stall any configuration read or write cycles until after the eeprom read has completed. for mem/io transfers it is up to the mac to stall the transfer. 35.6.1 register details table 35-3. bus m, device 0, function 0: su mmary of gigabit ethernet mac interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1241 8086h 02h 03h ?offset 02h: did: device identification register? on page 1241 5040h 04h 05h ?offset 04h: pcicmd: device command register? on page 1243 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1244 10h 08h 08h ?offset 08h: rid: revision id register? on page 1245 variable 09h 0bh ?offset 09h: cc: class code register? on page 1245 020000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1246 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1246 00000000h 14h 17h ?offset 14h: iobar: csr i/o mapped bar register? on page 1247 00000001h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1248 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1248 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1249 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1249 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1250 01h dch dch ?offset dch: pcid: power management capability id register? on page 1251 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1251 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1252 x023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1253 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1254 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1254 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1255 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1255 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1256 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1257 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1258 05h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1238 order number: 320066-003us f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1258 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1259 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1259 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1260 0000h table 35-3. bus m, device 0, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 35-4. bus m, device 1, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1241 8086h 02h 03h ?offset 02h: did: device identification register? on page 1242 5044h 04h 05h ?offset 04h: pcicmd: device command register? on page 1243 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1244 10h 08h 08h ?offset 08h: rid: revision id register? on page 1245 variable 09h 0bh ?offset 09h: cc: class code register? on page 1245 020000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1246 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1246 00000000h 14h 17h ?offset 14h: iobar: csr i/o mapped bar register? on page 1247 00000001h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1248 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1248 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1249 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1249 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1250 01h dch dch ?offset dch: pcid: power management capability id register? on page 1251 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1251 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1252 x023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1253 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1254 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1254 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1255 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1255 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1256 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1257 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1258 05h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1239 intel ? ep80579 integrated processor f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1258 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1259 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1259 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1260 0000h table 35-4. bus m, device 1, function 0: su mmary of gigabit ethernet mac interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 35-5. bus m, device2, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1241 8086h 02h 03h ?offset 02h: did: device identification register? on page 1242 5048h 04h 05h ?offset 04h: pcicmd: device command register? on page 1243 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1244 10h 08h 08h ?offset 08h: rid: revision id register? on page 1245 variable 09h 0bh ?offset 09h: cc: class code register? on page 1245 020000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1246 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1246 00000000h 14h 17h ?offset 14h: iobar: csr i/o mapped bar register? on page 1247 00000001h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1248 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1248 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1249 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1249 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1250 01h dch dch ?offset dch: pcid: power management capability id register? on page 1251 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1251 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1252 x023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1253 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1254 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1254 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1255 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1255 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1256 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1257 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1258 05h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1240 order number: 320066-003us 35.6.1.1 offset 00h: vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1258 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1259 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1259 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1260 0000h table 35-5. bus m, device2, function 0: summary of gigabit ethernet mac interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1241 intel ? ep80579 integrated processor 35.6.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. each gigabit mac has its own unique did. table 35-6. offset 00h: vid: vendor identification register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 00h 01h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 00h 01h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel 8086h. 8086h ro table 35-7. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:0:0 offset start: offset end: 02h 03h size: 16 bit default: 5040h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 2 didh device identification number high: this is the upper 14-bits of the full did 16-bit value which is assigned to gigabit ethernet mac #0. 1410h ro 1 : 00 didl device identification number low: this is the lower 2- bits of the full did 16-bit value which is assigned to gigabit ethernet mac #0. fuse ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1242 order number: 320066-003us 35.6.1.3 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. each gigabit mac has its own unique did. 35.6.1.4 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. each gigabit mac has its own unique did. table 35-8. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:1:0 offset start: offset end: 02h 03h size: 16 bit default: 5044h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 2 didh device identification number high: this is the upper 14-bits of the full did 16-bit value which is assigned to gigabit ethernet mac #1. 1411h ro 1: 00 didl device identification number low: this is the lower 2- bits of the full did 16-bit value which is assigned to gigabit ethernet mac #1. fuse ro table 35-9. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:2:0 offset start: offset end: 02h 03h size: 16 bit default: 5048h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 2 didh device identification number high: this is the upper 14-bits of the full did 16-bit value which is assigned to gigabit ethernet mac #2. 1412h ro 1: 00 didl device identification number low: this is the lower 2- bits of the full did 16-bit value which is assigned to gigabit ethernet mac #2. fuse ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1243 intel ? ep80579 integrated processor 35.6.1.5 offset 04h: pcicmd ? device command register table 35-10. offset 04h: pcicmd: device command register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 04h 05h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 04h 05h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h rv 10 intd interrupt disable 0h rw 09 fbtb fast back-to-back enable 0h ro 08 ser serr# enable 0h ro 07 reserved reserved 0h rv 06 per parity error response 0h ro 05 vps vga palette snoop 0h ro 04 mwe memory write and invalidate 0h ro 03 ss special cycle 0h ro 02 bm bus master capable 0h rw 01 mem memory space enable: setting this bit enables access to the memory regions the device claims through its bars. 0h rw 00 io i/o space enable: setting this bit enables access to the i/o regions the device claims through its bars. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1244 order number: 320066-003us 35.6.1.6 offset 06h: pcists ? device status register table 35-11. offset 06h: pcists: pci device status register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 06h 07h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 06h 07h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 06h 07h size: 16 bit default: 10h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 14 sse signaled system error 0h ro 13 rma received master abort 0h ro 12 rta received target abort 0h ro 11 sta signaled target abort 0h ro 10 : 09 dst devsel timing 00b ro 08 mdpe master data parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 07 fb2b fast back-to-back capable 0h ro 06 reserved reserved 0h rv 05 mc66 66 mhz capable 0h ro 04 cl capabilities list 1 ro 03 is interrupt status 0h ro 02 : 00 reserved reserved 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1245 intel ? ep80579 integrated processor 35.6.1.7 offset 08h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. 35.6.1.8 offset 09h: cc ? class code register table 35-12. offset 08h: rid: revision id register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 08h 08h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 08h 08h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the aioc device. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 35-13. offset 09h: cc: class code register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 09h 0bh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 09h 0bh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 09h 0bh size: 24 bit default: 020000h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code: this value indicates the base class, subclass, and interface. 020000h = network controller / ethernet controller 020000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1246 order number: 320066-003us 35.6.1.9 offset 0eh: hdr ? header type register 35.6.1.10 offset 10h: csrbar ? control and status registers base address register the csrbar is a pci bar in memory space that allows access to the csrs of a gigabit ethernet mac. see section 37.6, ?gbe controller register summary? for a description of the individual registers that this region exposes. table 35-14. offset 0eh: hdr: header type register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 0eh 0eh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 0eh 0eh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type: the header type of the device. 00h = single-function device with standard header layout. 0h ro table 35-15. offset 10h: csrbar: control an d status registers base address register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 10h 13h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 10h 13h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 17 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 16 : 04 zero lower bits: hardwired to 0 to set the region size to 128kb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1247 intel ? ep80579 integrated processor 35.6.1.11 offset 14h: iobar ? csr i/o mapped bar register the iobar is a pci bar in i/o space that allows access to the gigabit mac structures through ia i/o space. see section 35.7, ?gigabit ethernet mac i/o spaces: bus m, device 0-2, function 0? on page 1261 for a description of the individual registers this region exposes. reads and writes to addresses mapped through this bar are redirected to structures exposed through the csrbar (see section 35.6.1.10, ?offset 10h: csrbar ? control and status registers base address register? on page 1246 ). table 35-16. offset 14h: iobar: csr i/o mapped bar register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 14h 17h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 14h 17h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 14h 17h size: 32 bit default: 00000001h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 05 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 04 : 02 zero lower bits: hardwired to 0 to set the region size to 32b. 0h ro 01 reserved reserved 0h ro 00 typ addressing type: hardwired to 1 to identify the region as in i/o space. 1ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1248 order number: 320066-003us 35.6.1.12 offset 2ch: svid ? subsystem vendor id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.6.1.13 offset 2eh: sid ? subsystem id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.6.1.14 offset 34h: cp ? capabilities pointer register the cp provides the offset to the location in configuration space where the first set of capabilities registers is located. table 35-17. offset 2ch: svid: subsystem vendor id register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 2ch 2dh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 2ch 2dh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: this field must be programmed during bios initialization. 0h rwo table 35-18. offset 2eh: sid: subsystem id register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 2eh 2fh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 2eh 2fh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: this field must be programmed during bios initialization. 0h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1249 intel ? ep80579 integrated processor 35.6.1.15 offset 3ch: irql ? interrupt line register table 35-19. offset 34h: cp: capabilities pointer register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 34h 34h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 34h 34h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp pointer to first capability structure: value is dch which is the config space offset of the first capability structure. dch ro table 35-20. offset 3ch: irql: interrupt line register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 3ch 3ch view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 3ch 3ch view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irql interrupt line: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller this device is connected to. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1250 order number: 320066-003us 35.6.1.16 offset 3dh: irqp ? interrupt pin register table 35-21. offset 3dh: irqp: interrupt pin register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: 3dh 3dh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: 3dh 3dh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irqp interrupt pin: set to 01h to indicate the device always uses inta# as its interrupt pin. 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1251 intel ? ep80579 integrated processor 35.6.1.17 offset dch: pcid ? power management capability id register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . 35.6.1.18 offset ddh: pcp ? power ma nagement next capability pointer register for an overview of the power management capability of ep80579 integrated processor aioc devices, see section 35.5, ?power management of aioc devices? . table 35-22. offset dch: pcid: power management capability id register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: dch dch view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: dch dch view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management) 01h ro table 35-23. offset ddh: pcp: power management next capability pointer register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: ddh ddh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: ddh ddh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: ddh ddh size: 8 bit default: e4h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to e4h to indicate the offset of the next capability. e4h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1252 order number: 320066-003us 35.6.1.19 offset deh: pmcap ? power management capability register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . note that device 0 supports pme, device 1 and 2 do not. table 35-24. offset deh: pmcap: powe r management capability register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: deh dfh view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: deh dfh view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: deh dfh size: 16 bit default: x023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support x ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 reserved reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1253 intel ? ep80579 integrated processor 35.6.1.20 offset e0h: pmcs ? power management control and status register for an overview of the power management capability of the ep80579 integrated processoraioc devices, see section 35.5, ?power management of aioc devices? . table 35-25. offset e0h: pmcs: power management control and status register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: e0h e1h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: e0h e1h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: e0h e1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status (sticky) this bit is sticky for device 0 which is on suspend well, but not for the other 2 which aren?t on a power well. 0 = writing a 0 has no effect. 1 = set when gbe would normally assert the pme# signal independent of the state of the pme_en bit. note: writing a 1 to this bit will clear it and cause the internal pme to de-assert (if enabled). this bit must be explicitly cleared by the operating note: on a write this register will be updated after a 100ns delay. y0h rwc 14 : 13 data_scale data scale hardwired to ?00? because it does not support the associated data register. 00b ro 12 : 09 data_sel data select hardwired to ?0000? because it does not support the associated data register. 0000b ro 08 pme_en pme enable (sticky) this bit is sticky for device 0 which is on suspend well, but not for the other 2 which aren?t on a power well. a ?1? enables gbe to generate an internal pme signal when pme_status is ?1?. this bit must be explicitly cleared by the operating system each time it is initially loaded. note: on a write this register will be updated after a 100ns delay. y0h rw 07 : 04 reserved reserved 0000b ro 03 nsr no soft reset 0h ro 02 reserved reserved 0h ro 01 : 00 ps power state this 2-bit field is used both to determine the current power state of gbe function and to set a new power state. the definition of the field values are: 00b ? d0 state 11b ? d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1254 order number: 320066-003us 35.6.1.21 offset e4h: scid ? signal target capability id register the signal target capability record defines how the device targets it signals to ia agents. it is an 9b vendor-specific capability record and includes the scid, scp, sbc, styp, smia, and sint fields of the configuration header. for more information on signaling by aioc devices, see section 35.4, ?interrupt handling for aioc devices? . 35.6.1.22 offset e5h: scp ? signal target next capability pointer register table 35-26. offset e4h: scid: signal target capability id register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: e4h e4h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: e4h e4h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: e4h e4h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scid capability id: pci sig assigned capability record id (09h, vendor specific) 09h ro table 35-27. offset e5h: scp: signal target next capability pointer register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: e5h e5h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: e5h e5h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: e5h e5h size: 8 bit default: f0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scp next capability pointer: hardwired to f0h to indicate the offset of the next capability. f0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1255 intel ? ep80579 integrated processor 35.6.1.23 offset e6h: sbc ? signal target byte count register 35.6.1.24 offset e7h: styp ? signal target capability type register table 35-28. offset e6h: sbc: signal target byte count register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: e6h e6h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: e6h e6h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: e6h e6h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 sbc capability record byte count: hardwired to the number of bytes in the vendor-specific capability record. 09h ro table 35-29. offset e7h: styp: signal target capability type register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: e7h e7h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: e7h e7h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: e7h e7h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 styp capability record type: vendor assigned capability record type (01h, ep80579 signal target capability) 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1256 order number: 320066-003us 35.6.1.25 offset e8h: smia ? signal target ia mask register 35.6.1.26 offset e9h: reserved register writing to this register will result in undefined behavior. 35.6.1.27 offset eah: reserved register writing to this register will result in undefined behavior. table 35-30. offset e8h: smia: signal target ia mask register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: e8h e8h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: e8h e8h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: e8h e8h size: 8 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved 0h rw 02 smia2 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect gbex_interrupt0 which carries all interrupt sources (functional plus aioc internal bus errors and internal memory errors) and the functional interrupts are throttled by a timer 0h rw 01 smia1 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect gbex_interrupt1 which carries all interrupt sources (functional plus aioc internal bus errors and internal memory errors) but the functional interrupts are not throttled 0h rw 00 smia0 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect gbex_error_interrupt which carries only aioc internal bus errors and internal memory parity or uncorrectable ecc errors 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1257 intel ? ep80579 integrated processor 35.6.1.28 offset ech: sint ? signal target raw interrupt register table 35-31. offset ech: sint: signal target raw interrupt register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: ech ech view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: ech ech view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: ech ech size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 03 reserved 0h ro 02 sint2 interrupt: read-only view of gbex_interrupt0 which carries all interrupt sources (functional plus aioc internal bus errors and internal memory errors) and the functional interrupts are throttled by a timer 0h ro 01 sint1 interrupt: read-only view of gbex_interrupt1 which carries all interrupt sources (functional plus aioc internal bus errors and internal memory errors) but the functional interrupts are not throttled 0h ro 00 sint0 interrupt: read-only view of gbex_error_interrupt which carries only aioc internal bus errors and internal memory parity or uncorrectable ecc errors 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1258 order number: 320066-003us 35.6.1.29 offset f0h: mcid ? message signalled interrupt capability id register the message signalled interrupt capability record defines how the device generates pci msi messages. it is an 10b pci sig-defined capability record and includes the mcid, mcp, mctl, madr, and mdata fields of the configuration header. 35.6.1.30 offset f1h: mcp ? message signalled interrupt next capability pointer register table 35-32. offset f0h: mcid: message signalled interrupt capability id register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: f0h f0h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: f0h f0h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: f0h f0h size: 8 bit default: 05h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcid capability id: pci sig assigned capability record id (05h, msi capability) 05h ro table 35-33. offset f1h: mcp: message signalled interrupt next capability pointer register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: f1h f1h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: f1h f1h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: f1h f1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1259 intel ? ep80579 integrated processor 35.6.1.31 offset f2h: mctl ? message signalled interrupt control register 35.6.1.32 offset f4h: madr ? message signalled interrupt address register table 35-34. offset f2h: mctl: message signalled interrupt control register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: f2h f3h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: f2h f3h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: f2h f3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved 0h ro 08 mc per-vector masking capable: hardwired to 0 to indicate the device is not capable of per-vector masking. 0h ro 07 c64 64 bit address capable: hardwired to 0 to indicate the device does not generate 64b message addresses. 0h ro 06 : 04 mme multiple message enable: system software writes to this field to indicate the number of allocated messages (less than or equal to the number of requested messages in mmc). a value of 0 corresponds to one message. 000h rw 03 : 01 mmc multiple message capable: system software reads this field to determine the number of requested messages. hardwired to 0 to request one message. 000h ro 00 msie msi enable : system software sets this bit to enable msi signaling. a device driver is pr ohibited from writing this bit to mask a device?s service request. if 1, the device can use an msi to request service. if 0, the device cannot use an msi to request service. 0h rw table 35-35. offset f4h: madr: message signalled interrupt address register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: f4h f7h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: f4h f7h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: f4h f7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 addr message address: written by the system to indicate the lower 32-bits of the address to use for the msi memory write transaction. the lower two bits will always be written as 0. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1260 order number: 320066-003us 35.6.1.33 offset f8h: mdata ? message signalled interrupt data register table 35-36. offset f8h: mdata: message signalled interrupt data register description: view: pci 1 bar: configuration bus:device:function: m:0:0 offset start: offset end: f8h f9h view: pci 2 bar: configuration bus:device:function: m:1:0 offset start: offset end: f8h f9h view: pci 3 bar: configuration bus:device:function: m:2:0 offset start: offset end: f8h f9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 data message data: written by the system to indicate the lower 16 bits of the data written in the msi memory write dword transaction. the upper 16 bits of the transaction are written as 0. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1261 intel ? ep80579 integrated processor 35.7 gigabit ethernet mac i/o spaces: bus m, device 0-2, function 0 the pci-to-pci bridge implements ioaddr and iodata registers in ia i/o space to allow access to gigabit mac structures through the iobar of a gigabit mac (see section 35.6.1.11, ?offset 14h: iobar ? csr i/o mapped bar register? on page 1247 ). these registers are used to indirectly access gigabit mac structures before the entire system memory map is available to use the membar. there are two registers for each mac during an eeprom read the configuration space will stall any configuration read or write cycles until after the eeprom read has completed. mem/io transfers generate an aioc internal bus command and it is up to the gig to stall the transfer.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1262 order number: 320066-003us 35.7.1 register details . 35.7.1.1 offset 0000h: ioaddr - ioaddr register the ioaddr register specifies the structure within a gbe device that should be accessed on reads or writes to the iodata register (see section 35.7.1.2, ?offset 0004h: iodata - iodata register? on page 1264 ). table 35-37. bus m, device 0, function 0: gigabit ethernet mac i/o spaces registers offset start offset end register id - description default value 0000h 0003h ?offset 0000h: ioaddr - ioaddr register? on page 1263 0000000h 0004h 0007h ?offset 0004h: iodata - iodata register? on page 1264 0000000h table 35-38. bus m, device 1, function 0: gigabit ethernet mac i/o spaces registers offset start offset end register id - description default value 0000h 0003h ?offset 0000h: ioaddr - ioaddr register? on page 1263 0000000h 0004h 0007h ?offset 0004h: iodata - iodata register? on page 1264 0000000h table 35-39. bus m, device 2, function 0: gigabit ethernet mac i/o spaces registers offset start offset end register id - description default value 0000h 0003h ?offset 0000h: ioaddr - ioaddr register? on page 1263 0000000h 0004h 0007h ?offset 0004h: iodata - iodata register? on page 1264 0000000h table 35-40. gigabit ethernet mac i/o iobar register summary offset mnemonic name rw size 00h - 03h ioaddr internal register or internal memory address. 0000_0000h - 0001_ffffh: internal registers/memories 0002_0000h - ffff_ffffh: undefined rw 4 byte 04h - 07h iodata data field for reads or writes to the internal register or internal memory as identified by the current value in ioaddr. all 32 bits of this register are read/ write-able. rw 4 byte 08h - 3fh reserved reserved n/a n/a
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1263 intel ? ep80579 integrated processor the ioaddr register must always be written as a dword access. writes that are less than 32 bits will be ignored. reads of any size will return a dword of data. however, the chipset or cpu may only return a subset of that dword. ioaddr must be dword aligned. because only a particular range is addressable, the upper bits of this register are hard coded to zero. bits 31 through 17 are not write-able and always read back as 0b. at hardware reset, this register value resets to 00000000h. once written, the value is retained until the next write or reset. table 35-41. offset 0000h: ioaddr - ioaddr register description: view: pci 1 bar: iobar bus:device:function: m:0:0 offset start: offset end: 0000h 0003h view: pci 2 bar: iobar bus:device:function: m:1:0 offset start: offset end: 0000h 0003h view: pci 3 bar: iobar bus:device:function: m:2:0 offset start: offset end: 0000h 0003h size: 32 bit default: 0000000h power well: vcc bit range bit acronym bit description sticky bit reset value bit access 31 : 17 reserved reserved 0000h ro 16 : 00 ioaddr address for i/o operation: provides the address for accesses to the gbe internal registers and memories allows access to full 128kb of space. 00000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1264 order number: 320066-003us 35.7.1.2 offset 0004h: iodata - iodata register the iodata register exposes the internal structures within the gbe identified by the last value written to the ioaddr register (see section 35.7.1.1, ?offset 0000h: ioaddr - ioaddr re gister? on page 1262 ) to read and write accesses. the iodata register must always be written as a dword access when the ioaddr register contains a value for the internal registers and memories. in this case, writes that are less than 32 bits will be ignored. reads to iodata of any size will return a dword of data. however, the chipset or cpu may only return a subset of that dword. writes and reads to iodata when the ioaddr register value is in an undefined range (0002_0000h -ffff_ffffh) should not be performed. results are indeterministic. note: there are no special software timing requirements on accesses to ioaddr or iodata. all accesses will be immediate except when data is not readily available or acceptable. in this case, the gbe will delay the results through normal bus methods (e.g., split transaction or np complete). note: because a register/read or write takes two io cycles to complete, software must provide a guarantee that the two io cycles occur as an atomic operation. otherwise, results can be non-deterministic from the software viewpoint. table 35-42. offset 0004h: iodata - iodata register description: view: pci 1 bar: iobar bus:device:function: m:0:0 offset start: offset end: 0004h 0007h view: pci 2 bar: iobar bus:device:function: m:1:0 offset start: offset end: 0004h 0007h view: pci 3 bar: iobar bus:device:function: m:2:0 offset start: offset end: 0004h 0007h size: 32 bit default: 0000000h power well: vcc bit range bit acronym bit description sticky bit reset value bit access 31 : 00 iodata data for i/o operation: exposes the gbe device structure that ioaddr identifies to read and write accesses. 00000000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1265 intel ? ep80579 integrated processor 35.8 gcu configuration space: bus m, device 3, function 0 the gcu and mdio port is device 3 of bus m, and is accessed using type 1 configuration cycles. 35.8.1 register details 35.8.1.1 offset 00h: vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. table 35-43. bus m, device 3, function 0: summary of gcu pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1265 8086h 02h 03h ?offset 02h: did: device identification register? on page 1266 503eh 04h 05h ?offset 04h: pcicmd: device command register? on page 1266 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1267 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1268 variable 09h 0bh ?offset 09h: cc: class code register? on page 1268 ff0000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1268 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1269 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1269 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1270 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1270 dch dch dch ?offset dch: pcid: power management capability id register? on page 1270 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1271 00h deh dfh ?offset deh: pmcap: power management capability register? on page 1271 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1272 0000h table 35-44. offset 00h: vid: vendor identification register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel, 8086h. 8086h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1266 order number: 320066-003us 35.8.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. 35.8.1.3 offset 04h: pcicmd ? device command register table 35-45. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 02h 03h size: 16 bit default: 503eh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the gcu device. 503e ro table 35-46. offset 04h: pcicmd: device command register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h rv 10 intd interrupt disable: setting this bit disables generation of interrupts by the gcu. 0h ro 09 fbtb fast back-to-back enable: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 08 ser serr# enable: this bit is not implemented in the gcu and is hardwired to 0. the ep80579 uses signals for errors. 0h ro 07 reserved reserved 0h rv 06 per parity error enable: this bit is not implemented in the gcu and is hardwired to 0. the ep80579 uses signals for errors. 0h ro 05 vps vga palette snoop enable: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 04 mwe memory write and invalidate enable: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 03 ss special cycle enable: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 02 bm bus master enable: this bit is not implemented in the gcu and is hardwired to 0. gcu cannot be a bus master. 0h ro 01 mem memory space enable: setting this bit enables access to the memory regions the device claims through its bars. 0h rw 00 io i/o space enable: the device does not implement this functionality since it claims no i/o regions. the bit is hardwired to 0. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1267 intel ? ep80579 integrated processor 35.8.1.4 offset 06h: pcists ? device status register 35.8.1.5 offset 08h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. table 35-47. offset 06h: pcists: pci device status register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 14 sse signaled system error: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 13 rma received master abort status: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 12 rta received target abort status: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 11 sta signaled target abort status: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 10 : 09 dst devsel timing: these bits are not implemented in the gcu and is hardwired to 0. 00b ro 08 mdpe master data parity error detected: this bit is not implemented in the gcu and is hardwired to 0. the ep80579 uses signals for errors. 0h ro 07 fb2b fast back-to-back capable: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 06 reserved reserved 0h rv 05 mc66 66 mhz capable: this bit is not implemented in the gcu and is hardwired to 0. 0h ro 04 cl capabilities list: this bit is hardwired to 1 to indicate that the device has a capabilities list. 1ro 03 is interrupt status: this bit is not implemented in the gcu and is hardwired to 0. the gcu does not interrupt. 0h ro 02 : 00 reserved reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1268 order number: 320066-003us 35.8.1.6 offset 09h: cc ? class code register 35.8.1.7 offset 0eh: hdr ? header type register table 35-48. offset 08h: rid: revision id register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the aioc device. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 35-49. offset 09h: cc: class code register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 09h 0bh size: 24 bit default: ff0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code: this value indicates the base class, subclass, and interface. 020000h = network controller / ethernet controller ff0000h ro table 35-50. offset 0eh: hdr: header type register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type: the header type of the device. 00h = single-function device with standard header layout. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1269 intel ? ep80579 integrated processor 35.8.1.8 offset 10h: csrbar ? control and status registers base address register the csrbar is a pci bar in memory space that allows access to the gcu in the aioc. see section 38.4, ?register summary? on page 1561 for a description of the individual registers that this region exposes. 35.8.1.9 offset 2ch: svid ? subsystem vendor id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. table 35-51. offset 10h: csrbar: control and status registers base address register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 11 : 04 zero lower bits: hardwired to 0 to set the region size to 4kb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro table 35-52. offset 2ch: svid: subsystem vendor id register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: this field must be programmed during bios initialization. 0h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1270 order number: 320066-003us 35.8.1.10 offset 2eh: sid ? subsystem id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.8.1.11 offset 34h: cp ? capabilities pointer register the cp provides the offset to the location in configuration space where the first set of capabilities registers is located. 35.8.1.12 offset dch: pcid ? power management capability id register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . table 35-53. offset 2eh: sid: subsystem id register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: this field must be programmed during bios initialization. 0h rwo table 35-54. offset 34h: cp: capabilities pointer register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp pointer to first capability structure: value is dch which is the config space offset of the first capability structure. dch ro table 35-55. offset dch: pcid: power management capability id register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management capability) 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1271 intel ? ep80579 integrated processor 35.8.1.13 offset ddh: pcp ? power ma nagement next capability pointer register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . 35.8.1.14 offset deh: pmcap ? power management capability register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . table 35-56. offset ddh: pcp: power management next capability pointer register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: ddh ddh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro table 35-57. offset deh: pmcap: power management capability register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: deh dfh size: 16 bit default: 0023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support 0h ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 reserved reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1272 order number: 320066-003us 35.8.1.15 offset e0h: pmcs ? power management control and status register for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . table 35-58. offset e0h: pmcs: power management control and status register description: view: pci bar: configuration bus:device:function: m:3:0 offset start: offset end: e0h e1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status - 0h ro 14 : 13 data_scale data scale 00b ro 12 : 09 data_sel data select 0000b ro 08 pme_en pme enable - 0h ro 07 : 04 reserved reserved 0000b ro 03 nsr no soft reset 0h ro 02 reserved reserved 0h ro 01 : 00 ps power state 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1273 intel ? ep80579 integrated processor 35.9 can controller configuration spaces: bus m, device 4-5, function 0 can controllers 0 and 1 are devices 4 and 5 of bus m, respectively and are accessed using type 1 configuration cycles. both controllers implement configuration spaces as defined in this section. 35.9.1 register details table 35-59. bus m, device 4, function 0: summary of can interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1275 8086h 02h 03h ?offset 02h: did: device identification register? on page 1275 5039h 04h 05h ?offset 04h: pcicmd: device command register? on page 1276 0h 06h 07h ?offset 06h: pcists: pci device status register? on page 1277 10h 08h 08h ?offset 08h: rid: revision id register? on page 1278 variable 09h 0bh ?offset 09h: cc: class code register? on page 1278 0c0900h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1279 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1279 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1280 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1280 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1281 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1281 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1282 01h 40h 40h ?offset 40h: canctl - can control register? on page 1282 00h dch dch ?offset dch: pcid: power management capability id register? on page 1283 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1283 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1284 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1284 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1285 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1285 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1286 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1286 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1287 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1287 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1288 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1288 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1274 order number: 320066-003us f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1289 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1289 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1290 0000h table 35-59. bus m, device 4, function 0: summary of can interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 35-60. bus m, devices 5, function 0: summary of can interface pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1275 8086h 02h 03h ?offset 02h: did: device identification register? on page 1276 503ah 04h 05h ?offset 04h: pcicmd: device command register? on page 1276 0h 06h 07h ?offset 06h: pcists: pci device status register? on page 1277 10h 08h 08h ?offset 08h: rid: revision id register? on page 1278 variable 09h 0bh ?offset 09h: cc: class code register? on page 1278 0c0900h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1279 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1279 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1280 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1280 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1281 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1281 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1282 01h 40h 40h ?offset 40h: canctl - can control register? on page 1282 00h dch dch ?offset dch: pcid: power management capability id register? on page 1283 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1283 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1284 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1284 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1285 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1285 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1286 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1286 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1287 0h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1287 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1288 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1288 00h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1275 intel ? ep80579 integrated processor 35.9.1.1 offset 00h: vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. 35.9.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. each can controller has its own device id. writes to this register have no effect. f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1289 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1289 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1290 0000h table 35-60. bus m, devices 5, function 0: summary of can interface pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 35-61. offset 00h: vid: vendor identification register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 00h 01h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel, 8086h. 8086h ro table 35-62. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:4:0 offset start: offset end: 02h 03h size: 16 bit default: 5039h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the can controller #1 device. 5039h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1276 order number: 320066-003us 35.9.1.3 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. each can controller has its own device id. writes to this register have no effect. 35.9.1.4 offset 04h: pcicmd ? device command register table 35-63. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:5:0 offset start: offset end: 02h 03h size: 16 bit default: 503ah power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the can controller #2 device. 503ah ro table 35-64. offset 04h: pcicmd: device command register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 04h 05h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 04h 05h size: 16 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h rv 10 intd interrupt disable 0h rw 09 fbtb fast back-to-back enable 0h ro 08 ser serr# enable 0h ro 07 reserved reserved 0h rv 06 per parity error response 0h ro 05 vps vga palette snoop 0h ro 04 mwe memory write and invalidate 0h ro 03 ss special cycle 0h ro 02 bm bus master capable 0h ro 01 mem memory space enable: setting this bit enables access to the memory regions the device claims through its bars. 0h rw 00 io i/o space enable: the device does not implement this functionality since it claims no i/o regions. the bit is hardwired to 0. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1277 intel ? ep80579 integrated processor 35.9.1.5 offset 06h: pcists ? device status register table 35-65. offset 06h: pcists: pci device status register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 06h 07h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 06h 07h size: 16 bit default: 10h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 14 sse signaled system error 0h ro 13 rma received master abort 0h ro 12 rta received target abort 0h ro 11 sta signaled target abort 0h ro 10 : 09 dst devsel timing 00b ro 08 mdpe master data parity error 0h ro 07 fb2b fast back-to-back capable 0h ro 06 reserved reserved 0h rv 05 mc66 66 mhz capable 0h ro 04 cl capabilities list 1 ro 03 is interrupt status 0h ro 02 : 00 reserved reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1278 order number: 320066-003us 35.9.1.6 offset 08h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. 35.9.1.7 offset 09h: cc ? class code register table 35-66. offset 08h: rid: revision id register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 08h 08h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the aioc device. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 35-67. offset 09h: cc: class code register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 09h 0bh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 09h 0bh size: 24 bit default: 0c0900h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code: this value indicates the base class, subclass, and interface. 020000h = network controller / ethernet controller 0c0900h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1279 intel ? ep80579 integrated processor 35.9.1.8 offset 0eh: hdr ? header type register 35.9.1.9 offset 10h: csrbar ? control and status registers base address register the csrbar is a pci bar in memory space that allows access to the can controllers in the aioc. see section 39.6, ?register summary? on page 1585 for a description of the individual registers that this region exposes. table 35-68. offset 0eh: hdr: header type register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 0eh 0eh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type: the header type of the device. 00h = single-function device with standard header layout. 0h ro table 35-69. offset 10h: csrbar: control and status registers base address register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 10h 13h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 11 : 04 zero lower bits: hardwired to 0 to set the region size to 4kb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1280 order number: 320066-003us 35.9.1.10 offset 2ch: svid ? subsystem vendor id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.9.1.11 offset 2eh: sid ? subsystem id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. table 35-70. offset 2ch: svid: subsystem vendor id register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 2ch 2dh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: this field must be programmed during bios initialization. 0h rwo table 35-71. offset 2eh: sid: subsystem id register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 2eh 2fh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: this field must be programmed during bios initialization. 0h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1281 intel ? ep80579 integrated processor 35.9.1.12 offset 34h: cp ? capabilities pointer register the cp provides the offset to the location in configuration space where the first set of capabilities registers is located. 35.9.1.13 offset 3ch: irql ? interrupt line register table 35-72. offset 34h: cp: capabilities pointer register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 34h 34h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp pointer to first capability structure: value is dch which is the config space offset of the first capability structure. dch ro table 35-73. offset 3ch: irql: interrupt line register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 3ch 3ch view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irql interrupt line: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller this device is connected to. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1282 order number: 320066-003us 35.9.1.14 offset 3dh: irqp ? interrupt pin register 35.9.1.15 offset 40h: canctl ? can control register table 35-74. offset 3dh: irqp: interrupt pin register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 3dh 3dh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irqp interrupt pin: set to 01h to indicate the device always uses inta# as its interrupt pin. 01h ro table 35-75. offset 40h: canctl - can control register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: 40h 40h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: 40h 40h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 rsvd reserved 00h ro 00 parity can ram parity : 1 even parity for can sram, 0 odd parity. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1283 intel ? ep80579 integrated processor 35.9.1.16 offset dch: pcid ? power management capability id register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . 35.9.1.17 offset ddh: pcp ? power ma nagement next capability pointer register table 35-76. offset dch: pcid: power management capability id register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: dch dch view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management capability). 01h ro table 35-77. offset ddh: pcp: power management next capability pointer register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: ddh ddh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: ddh ddh size: 8 bit default: e4h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to e4h to indicate the offset of the next capability. e4h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1284 order number: 320066-003us 35.9.1.18 offset deh: pmcap ? power management capability register 35.9.1.19 offset e0h: pmcs ? power management control and status register table 35-78. offset deh: pmcap: powe r management capability register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: deh dfh view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: deh dfh size: 16 bit default: 0023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support 0h ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 reserved reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro table 35-79. offset e0h: pmcs: power management control and status register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: e0h e1h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: e0h e1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status (sticky) 0h ro 14 : 13 data_scale data scale 00b ro 12 : 09 data_sel data select 0000b ro 08 pme_en pme enable (sticky) 0h ro 07 : 04 reserved reserved 0000b ro 03 nsr no soft reset 0h ro 02 reserved reserved 0h ro 01 : 00 ps power state 00b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1285 intel ? ep80579 integrated processor 35.9.1.20 offset e4h: scid ? signal target capability id register the signal target capability record defines how the device targets it signals to ia agents. it is an 9b vendor-specific capability record and includes the scid, scp, sbc, styp, smia, and sint fields of the configuration header. for more information on signaling by aioc devices, see section 35.4, ?interrupt handling for aioc devices? on page 1235 . 35.9.1.21 offset e5h: scp ? signal target next capability pointer register table 35-80. offset e4h: scid: signal target capability id register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: e4h e4h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: e4h e4h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scid capability id: pci sig assigned capability record id (09h, vendor specific) 09h ro table 35-81. offset e5h: scp: signal target next capability pointer register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: e5h e5h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: e5h e5h size: 8 bit default: f0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scp next capability pointer: hardwired to f0h to indicate the offset of the next capability. f0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1286 order number: 320066-003us 35.9.1.22 offset e6h: sbc ? signal target byte count register 35.9.1.23 offset e7h: styp ? signal target capability type register table 35-82. offset e6h: sbc: signal target byte count register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: e6h e6h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: e6h e6h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 sbc capability record byte count: hardwired to the number of bytes in the vendor-specific capability record. 09h ro table 35-83. offset e7h: styp: signal target capability type register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: e7h e7h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: e7h e7h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 styp capability record type: vendor assigned capability record type (01h, ep80579 signal target capability). 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1287 intel ? ep80579 integrated processor 35.9.1.24 offset e8h: smia ? signal target ia mask register 35.9.1.25 offset e9h: reserved register writing to this register will result in undefined behavior 35.9.1.26 offset eah: reserved register writing to this register will result in undefined behavior. 35.9.1.27 offset ech: sint ? signal target raw interrupt register table 35-84. offset e8h: smia: signal target ia mask register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: e8h e8h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: e8h e8h size: 8 bit default: 0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved 0h rw 01 smia1 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect canx parity interrupt 0h rw 00 smia0 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect canx system interrupt. 0h rw table 35-85. offset ech: sint: signal target raw interrupt register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: ech ech view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: ech ech size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved 0h ro 01 sint1 interrupt: read-only view of canx parity interrupt 0h ro 00 sint0 interrupt: read-only view of canx system interrupt 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1288 order number: 320066-003us 35.9.1.28 offset f0h: mcid ? message signalled interrupt capability id register the message signalled interrupt capability record defines how the device generates pci msi messages. it is an 10b pci sig-defined capability record and includes the mcid, mcp, mctl, madr, and mdata fields of the configuration header. 35.9.1.29 offset f1h: mcp ? message signalled interrupt next capability pointer register table 35-86. offset f0h: mcid: message signalled interrupt capability id register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: f0h f0h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: f0h f0h size: 8 bit default: 05h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcid capability id: pci sig assigned capability record id (05h, msi capability) 05h ro table 35-87. offset f1h: mcp: message signalled interrupt next capability pointer register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: f1h f1h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: f1h f1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1289 intel ? ep80579 integrated processor 35.9.1.30 offset f2h: mctl ? message signalled interrupt control register 35.9.1.31 offset f4h: madr ? message signalled interrupt address register table 35-88. offset f2h: mctl: message signalled interrupt control register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: f2h f3h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: f2h f3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved 0h ro 08 mc per-vector masking capable: hardwired to 0 to indicate the device is not capable of per-vector masking. 0h ro 07 c64 64 bit address capable: hardwired to 0 to indicate the device does not generate 64b message addresses. 0h ro 06 : 04 mme multiple message enable: system software writes to this field to indicate the number of allocated messages (less than or equal to the number of requested messages in mmc). a value of 0 corresponds to one message. 000h rw 03 : 01 mmc multiple message capable: system software reads this field to determine the number of requested messages. hardwired to 0 to request one message. 000h ro 00 msie msi enable: system software sets this bit to enable msi signaling. a device driver is pr ohibited from writing this bit to mask a device?s service request. if 1, the device can use an msi to request service. if 0, the device cannot use an msi to request service. 0h rw table 35-89. offset f4h: madr: message signalled interrupt address register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: f4h f7h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: f4h f7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 addr message address: written by the system to indicate the lower 32-bits of the address to use for the msi memory write transaction. the lower two bits will always be written as 0. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1290 order number: 320066-003us 35.9.1.32 offset f8h: mdata ? message signalled interrupt data register table 35-90. offset f8h: mdata: message signalled interrupt data register description: view: pci 1 bar: configuration bus:device:function: m:4:0 offset start: offset end: f8h f9h view: pci 2 bar: configuration bus:device:function: m:5:0 offset start: offset end: f8h f9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 data message data: written by the system to indicate the lower 16 bits of the data written in the msi memory write dword transaction. the upper 16 bits of the transaction are written as 0. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1291 intel ? ep80579 integrated processor 35.10 ssp controller configuration space: bus m, device 6, function 0 the ssp controller is device 6 of bus m, and is accessed using type 1 configuration cycles 35.10.1 register details table 35-91. bus m, device 6, function 0: summary of ssp controller pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1292 8086h 02h 03h ?offset 02h: did: device identification register? on page 1292 503bh 04h 05h ?offset 04h: pcicmd: device command register? on page 1292 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1293 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1294 variable 09h 0bh ?offset 09h: cc: class code register? on page 1295 078000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1295 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1295 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1296 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1296 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1297 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1297 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1297 01h dch dch ?offset dch: pcid: power management capability id register? on page 1298 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1298 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1298 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1299 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1300 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1300 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1300 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1301 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1301 00h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1302 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1302 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1302 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1303 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1303 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1304 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1292 order number: 320066-003us 35.10.1.1 offset 00h: vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. 35.10.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. 35.10.1.3 offset 04h: pcicmd ? device command register table 35-92. offset 00h: vid: vendor identification register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel, 8086h. 8086h ro table 35-93. offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 02h 03h size: 16 bit default: 503bh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the ssp controller device. 503bh ro table 35-94. offset 04h: pcicmd: device command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h rv 10 intd interrupt disable 0h rw 09 fbtb fast back-to-back enable 0h ro 08 ser serr# enable 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1293 intel ? ep80579 integrated processor 35.10.1.4 offset 06h: pcists ? device status register 07 reserved reserved 0h rv 06 per parity error response 0h ro 05 vps vga palette snoop 0h ro 04 mwe memory write and invalidate 0h ro 03 ss special cycle 0h ro 02 bm bus master capable 0h ro 01 mem memory space enable: setting this bit enables access to the memory regions the device claims through its bars. 0h rw 00 io i/o space enable: the device does not implement this functionality since it claims no i/o regions. the bit is hardwired to 0. 0h ro table 35-95. offset 06h: pcists: pci device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 14 sse signaled system error: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 13 rma received master abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 12 rta received target abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 11 sta signaled target abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 10 : 09 dst devsel timing: the device does not implement this functionality. these bits are hardwired to 0. 00b ro 08 mdpe master data parity error detected: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 07 fb2b fast back-to-back capable: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 06 reserved reserved 0h rv table 35-94. offset 04h: pcicmd: device command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1294 order number: 320066-003us 35.10.1.5 offset 08h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. 05 mc66 66 mhz capable: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 04 cl capabilities list: this bit is hardwired to 1 to indicate that the device has a capabilities list. 1ro 03 is interrupt status: 0h ro 02 : 00 reserved reserved 0h rv table 35-95. offset 06h: pcists: pci device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access table 35-96. offset 08h: rid: revision id register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the aioc device. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1295 intel ? ep80579 integrated processor 35.10.1.6 offset 09h: cc ? class code register 35.10.1.7 offset 0eh: hdr ? header type register 35.10.1.8 offset 10h: csrbar ? control and status registers base address register the csrbar is a pci bar in memory space that allows access to the control and status registers for the ssp unit. see section 40.4, ?register summary? on page 1606 for a description of the registers this region exposes. table 35-97. offset 09h: cc: class code register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 09h 0bh size: 24 bit default: 078000h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code: this value indicates the base class, subclass, and interface. 020000h = network controller / ethernet controller 078000h ro table 35-98. offset 0eh: hdr: header type register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type: the header type of the device. 00h = single-function device with standard header layout. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1296 order number: 320066-003us 35.10.1.9 offset 2ch: svid ? subsystem vendor id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.10.1.10 offset 2eh: sid ? subsystem id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset, table 35-99. offset 10h: csrbar: control an d status registers base address register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 11 : 04 zero lower bits: hardwired to 0 to set the region size to 4kb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro table 35-100.offset 2ch: svid: subsystem vendor id register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: this field must be programmed during bios initialization. 0h rwo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1297 intel ? ep80579 integrated processor 35.10.1.11 offset 34h: cp ? capabilities pointer register 35.10.1.12 offset 3ch: irql ? interrupt line register table 35-101.offset 2eh: sid: subsystem id register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: this field must be programmed during bios initialization. 0h rwo table 35-102.offset 34h: cp: capabilities pointer register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp pointer to first capability structure: value is dch which is the config space offset of the first capability structure. dch ro table 35-103.offset 3ch: irql: interrupt line register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irql interrupt line: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller this device is connected to. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1298 order number: 320066-003us 35.10.1.13 offset 3dh: irqp ? interrupt pin register 35.10.1.14 offset dch: pcid ? power management capability id register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . table 35-104.offset 3dh: irqp: interrupt pin register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irqp interrupt pin: set to 01h to indicate the device always uses inta# as its interrupt pin. 01h ro table 35-105.offset dch: pcid: power management capability id register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management capability) 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1299 intel ? ep80579 integrated processor 35.10.1.15 offset ddh: pcp ? power ma nagement next capability pointer register 35.10.1.16 offset deh: pmcap - power management capability table 35-106.offset ddh: pcp: power management next capability pointer register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: ddh ddh size: 8 bit default: e4h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to e8h to indicate the offset of the next capability. e4h ro table 35-107.offset deh: pmcap: power management capability register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: deh dfh size: 16 bit default: 0023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support 0h ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 rv reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1300 order number: 320066-003us 35.10.1.17 offset e0h: pmcs ? power management control and status register 35.10.1.18 offset e4h: scid ? signal target capability id register the signal target capability record defines how the device targets it signals to ia agents. it is an 9b vendor-specific capability record and includes the scid, scp, sbc, styp, smia, and sint fields of the configuration header. for more information on signaling by aioc devices, see section 35.4, ?interrupt handling for aioc devices? on page 1235 . table 35-108.offset e0h: pmcs: power ma nagement control and status register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: e0h e1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status (sticky) 0h ro 14 : 13 data_scale data scale 00b ro 12 : 09 data_sel data select 0000b ro 08 pme_en pme enable (sticky) 0b ro 07 : 04 rv reserved 0000b ro 03 nsr no soft reset 0h ro 02 rv reserved 0h ro 01 : 00 ps power state 00b rw table 35-109.offset e4h: scid: signal target capability id register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: e4h e4h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scid capability id: pci sig assigned capability record id (09h, vendor specific) 09h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1301 intel ? ep80579 integrated processor 35.10.1.19 offset e5h: scp ? signal target next capability pointer register 35.10.1.20 offset e6h: sbc ? signal target byte count register 35.10.1.21 offset e7h: styp ? signal target capability type register table 35-110.offset e5h: scp: signal target next capability pointer register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: e5h e5h size: 8 bit default: f0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scp next capability pointer: hardwired to f0h to indicate the offset of the next capability. f0h ro table 35-111.offset e6h: sbc: signal target byte count register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: e6h e6h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 sbc capability record byte count: hardwired to the number of bytes in the vendor-specific capability record. 09h ro table 35-112.offset e7h: styp: signal target capability type register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: e7h e7h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 styp capability record type: vendor assigned capability record type (01h, ep80579 signal target capability) 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1302 order number: 320066-003us 35.10.1.22 offset e8h: smia ? signal target ia mask register 35.10.1.23 offset e9h: reserved register writing to the register will result in undefined behavior. 35.10.1.24 offset eah: reserved register writing to this register will result in undefined behavior. 35.10.1.25 offset ech: sint ? signal target raw interrupt register 35.10.1.26 offset f0h: mcid ? message signalled interrupt capability id register the message signalled interrupt capability record defines how the device generates pci msi messages. it is an 10b pci sig-defined capability record and includes the mcid, mcp, mctl, madr, and mdata fields of the configuration header. table 35-113.offset e8h: smia: si gnal target ia mask register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: e8h e8h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved 0h rw 00 smia ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect ssp interrupt 0h rw table 35-114.offset ech: sint: signal target raw interrupt register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: ech ech size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved 0h ro 00 sint interrupt: read-only view of ssp interrupt 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1303 intel ? ep80579 integrated processor 35.10.1.27 offset f1h: mcp ? message signalled interrupt next capability pointer register 35.10.1.28 offset f2h: mctl ? message signalled interrupt control register table 35-115.offset f0h: mcid: message signalled interrupt capability id register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: f0h f0h size: 8 bit default: 05h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcid capability id: pci sig assigned capability record id (05h, msi capability) 05h ro table 35-116.offset f1h: mcp: message signalled interrupt next capability pointer register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: f1h f1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro table 35-117.offset f2h: mctl: message signalled interrupt control register (sheet 1 of description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: f2h f3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved 0h ro 08 mc per-vector masking capable: hardwired to 0 to indicate the device is not capable of per-vector masking. 0h ro 07 c64 64 bit address capable: hardwired to 0 to indicate the device does not generate 64b message addresses. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1304 order number: 320066-003us 35.10.1.29 offset f4h: madr ? message signalled interrupt address register 35.10.1.30 offset f8h: mdata ? message signalled interrupt data register 06 : 04 mme multiple message enable: system software writes to this field to indicate the number of allocated messages (less than or equal to the number of requested messages in mmc). a value of 0 corresponds to one message. 000h rw 03 : 01 mmc multiple message capable: system software reads this field to determine the number of requested messages. hardwired to 0 to request one message. 000h ro 00 msie msi enable: system software sets this bit to enable msi signaling. a device driver is pr ohibited from writing this bit to mask a device?s service request. if 1, the device can use an msi to request service. if 0, the device cannot use an msi to request service. 0h rw table 35-118.offset f4h: madr: message signalled interrupt address register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: f4h f7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 addr message address: written by the system to indicate the lower 32-bits of the address to use for the msi memory write transaction. the lower two bits will always be written as 0. 0h rw table 35-119.offset f8h: mdata: message signalled interrupt data register description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: f8h f9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 data message data: written by the system to indicate the lower 16 bits of the data written in the msi memory write dword transaction. the upper 16 bits of the transaction are written as 0. 0h rw table 35-117.offset f2h: mctl: message signalled interrupt control register (sheet 2 of description: view: pci bar: configuration bus:device:function: m:6:0 offset start: offset end: f2h f3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1305 intel ? ep80579 integrated processor 35.11 ieee 1588 hardware assist unit configuration space: bus m, device 7, function 0 the ieee 1588 hardware assist unit (device 7 of bus m) is accessed using type 1 configuration cycles. . 35.11.1 register details table 35-120.bus m, device 7, function 0: summary of ieee 1588 timestamp unit pci configuration registers offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1306 8086h 02h 03h ?offset 02h: did: device identification register? on page 1306 503ch 04h 05h ?offset 04h: pcicmd: device command register? on page 1306 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1307 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1308 variable 09h 0bh ?offset 09h: cc: class code register? on page 1308 111000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1309 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1309 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1310 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1310 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1310 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1311 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1311 01h dch dch ?offset dch: pcid: power management capability id register? on page 1312 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1312 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1313 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1313 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1314 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1314 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1314 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1315 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1315 00h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1316 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1316 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1317 00h f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1317 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1318 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1318 0000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1306 order number: 320066-003us 35.11.1.1 offset 00h: vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. 35.11.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. 35.11.1.3 offset 04h: pcicmd ? device command register table 35-121.offset 00h: vid: vendor identification register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel, 8086h. 8086h ro table 35-122.offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 02h 03h size: 16 bit default: 503ch power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the ieee 1588 hardware assist unit. 503ch ro table 35-123.offset 04h: pcicmd: device command register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h rv 10 intd interrupt disable 0h rw 09 fbtb fast back-to-back enable 0h ro 08 ser serr# enable 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1307 intel ? ep80579 integrated processor 35.11.1.4 offset 06h: pcists ? device status register 07 reserved reserved 0h rv 06 per parity error response 0h ro 05 vps vga palette snoop 0h ro 04 mwe memory write and invalidate 0h ro 03 ss special cycle 0h ro 02 bm bus master capable 0h ro 01 mem memory space enable: setting this bit enables access to the memory regions the device claims through its bars. 0h rw 00 io i/o space enable: the device does not implement this functionality since it claims no i/o regions. the bit is hardwired to 0. 0h ro table 35-124.offset 06h: pcists: pci device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 14 sse signaled system error: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 13 rma received master abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 12 rta received target abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 11 sta signaled target abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 10 : 09 dst devsel timing: the device does not implement this functionality. these bits are hardwired to 0. 00b ro 08 mdpe master data parity error detected: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 07 fb2b fast back-to-back capable: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 06 reserved reserved 0h rv table 35-123.offset 04h: pcicmd: device command register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1308 order number: 320066-003us 35.11.1.5 offset 08h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. 35.11.1.6 offset 09h: cc ? class code register 05 mc66 66 mhz capable: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 04 cl capabilities list: this bit is hardwired to 1 to indicate that the device has a capabilities list. 1ro 03 is interrupt status: 0h ro 02 : 00 reserved reserved 0h rv table 35-124.offset 06h: pcists: pci device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access table 35-125.offset 08h: rid: revision id register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the aioc device. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro table 35-126.offset 09h: cc: class code register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 09h 0bh size: 24 bit default: 111000h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code: this value indicates the base class, subclass, and interface. 020000h = network controller / ethernet controller 111000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1309 intel ? ep80579 integrated processor 35.11.1.7 offset 0eh: hdr ? header type register 35.11.1.8 offset 10h: csrbar ? control and status registers base address register the csrbar is a pci bar in memory space that allows access to the control and status registers for the 1588 hardware assist unit. see section 41.6, ?register summary? on page 1637 for a description of the registers this region exposes. table 35-127.offset 0eh: hdr: header type register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type: the header type of the device. 00h = single-function device with standard header layout. 0h ro table 35-128.offset 10h: csrbar: control and status registers base address register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 11 : 04 zero lower bits: hardwired to 0 to set the region size to 4kb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1310 order number: 320066-003us 35.11.1.9 offset 2ch: svid ? subsystem vendor id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.11.1.10 offset 2eh: sid ? subsystem id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.11.1.11 offset 34h: cp ? capabilities pointer register table 35-129.offset 2ch: svid: subsystem vendor id register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: this field must be programmed during bios initialization. 0h rwo table 35-130.offset 2eh: sid: subsystem id register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: this field must be programmed during bios initialization. 0h rwo table 35-131.offset 34h: cp: capabilities pointer register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp pointer to first capability structure: value is dch which is the config space offset of the first capability structure. dch ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1311 intel ? ep80579 integrated processor 35.11.1.12 offset 3ch: irql ? interrupt line register 35.11.1.13 offset 3dh: irqp ? interrupt pin register table 35-132.offset 3ch: irql: interrupt line register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irql interrupt line: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller this device is connected to. 0h rw table 35-133.offset 3dh: irqp: interrupt pin register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irqp interrupt pin: set to 01h to indicate the device always uses inta# as its interrupt pin. 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1312 order number: 320066-003us 35.11.1.14 offset dch: pcid ? power management capability id register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? on page 1236 . 35.11.1.15 offset ddh: pcp ? power management next capability pointer register table 35-134.offset dch: pcid: power management capability id register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management capability) 01h ro table 35-135.offset ddh: pcp: power manage ment next capability pointer register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: ddh ddh size: 8 bit default: e4h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to e8h to indicate the offset of the next capability. e4h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1313 intel ? ep80579 integrated processor 35.11.1.16 offset deh: pmcap ? power management capability register 35.11.1.17 offset e0h: pmcs ? power management control and status register table 35-136.offset deh: pmcap: power management capability register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: deh dfh size: 16 bit default: 0023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support 0h ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 rv reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro table 35-137.offset e0h: pmcs: power management control and status register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: e0h e1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status (sticky) 0h ro 14 : 13 data_scale data scale 00b ro 12 : 09 data_sel data select 0000b ro 08 pme_en pme enable (sticky) 0h ro 07 : 04 rv reserved 0000b ro 03 nsr no soft reset 0h ro 02 rv reserved 0h ro 01 : 00 ps power state 00b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1314 order number: 320066-003us 35.11.1.18 offset e4h: scid ? signal target capability id register the signal target capability record defines how the device targets it signals to ia agents. it is an 9b vendor-specific capability record and includes the scid, scp, sbc, styp, smia, and sint fields of the configuration header. for more information on signaling by aioc devices, see section 35.4, ?interrupt handling for aioc devices? on page 1235 . 35.11.1.19 offset e5h: scp ? signal target next capability pointer register 35.11.1.20 offset e6h: sbc ? signal target byte count register table 35-138.offset e4h: scid: signal target capability id register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: e4h e4h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scid capability id: pci sig assigned capability record id (09h, vendor specific) 09h ro table 35-139.offset e5h: scp: signal target next capability pointer register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: e5h e5h size: 8 bit default: f0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scp next capability pointer: hardwired to f0h to indicate the offset of the next capability. f0h ro table 35-140.offset e6h: sbc: signal target byte count register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: e6h e6h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 sbc capability record byte count: hardwired to the number of bytes in the vendor-specific capability record. 09h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1315 intel ? ep80579 integrated processor 35.11.1.21 offset e7h: styp ? signal target capability type register 35.11.1.22 offset e8h: smia ? signal target ia mask register 35.11.1.23 offset e9h: reserved register writing to this register will result in undefined behavior. 35.11.1.24 offset eah: reserved register writing to this register will result in undefined behavior. table 35-141.offset e7h: styp: signal target capability type register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: e7h e7h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 styp capability record type: vendor assigned capability record type (01h, ep80579 signal target capability) 01h ro table 35-142.offset e8h: smia: signal target ia mask register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: e8h e8h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved 0h rw 00 smia ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect ieee 1588 interrupt 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1316 order number: 320066-003us 35.11.1.25 offset ech: sint ? signal target raw interrupt register 35.11.1.26 offset f0h: mcid ? message signalled interrupt capability id register the message signalled interrupt capability record defines how the device generates pci msi messages. it is an 10b pci sig-defined capability record and includes the mcid, mcp, mctl, madr, and mdata fields of the configuration header. table 35-143.offset ech: sint: signal target raw interrupt register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: ech ech size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 01 reserved 0h ro 00 sint interrupt: read-only view of ieee 1588 interrupt 0h ro table 35-144.offset f0h: mcid: message signalled interrupt capability id register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: f0h f0h size: 8 bit default: 05h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcid capability id: pci sig assigned capability record id (05h, msi capability) 05h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1317 intel ? ep80579 integrated processor 35.11.1.27 offset f1h: mcp ? message signalled interrupt next capability pointer register 35.11.1.28 offset f2h: mctl ? message signalled interrupt control register table 35-145.offset f1h: mcp: message signalled interrupt next capability pointer register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: f1h f1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro table 35-146.offset f2h: mctl: message signalled interrupt control register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: f2h f3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved 0h ro 08 mc per-vector masking capable: hardwired to 0 to indicate the device is not capable of per-vector masking. 0h ro 07 c64 64 bit address capable: hardwired to 0 to indicate the device does not generate 64b message addresses. 0h ro 06 : 04 mme multiple message enable: system software writes to this field to indicate the number of allocated messages (less than or equal to the number of requested messages in mmc). a value of 0 corresponds to one message. 000h rw 03 : 01 mmc multiple message capable: system software reads this field to determine the number of requested messages. hardwired to 0 to request one message. 000h ro 00 msie msi enable: system software sets this bit to enable msi signaling. a device driver is pr ohibited from writing this bit to mask a device?s service request. if 1, the device can use an msi to request service. if 0, the device cannot use an msi to request service. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1318 order number: 320066-003us 35.11.1.29 offset f4h: madr ? message signalled interrupt address register 35.11.1.30 offset f8h: mdata ? message signalled interrupt data register table 35-147.offset f4h: madr: message signalled interrupt address register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: f4h f7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 addr message address: written by the system to indicate the lower 32-bits of the address to use for the msi memory write transaction. the lower two bits will always be written as 0. 0h rw table 35-148.offset f8h: mdata: message signalled interrupt data register description: view: pci bar: configuration bus:device:function: m:7:0 offset start: offset end: f8h f9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 data message data: written by the system to indicate the lower 16 bits of the data written in the msi memory write dword transaction. the upper 16 bits of the transaction are written as 0. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1319 intel ? ep80579 integrated processor 35.12 expansion bus configuration space: bus m, device 8, function 0 the expansion bus is device 8 of bus m, and is accessed using type 1 configuration cycles. 35.12.1 register details table 35-149.bus m, device 8, function 0: summary of local expansion bus pci configuration registers (sheet 1 of 2) offset start offset end register id - description default value 00h 01h ?offset 00h: vid: vendor identification register? on page 1320 8086h 02h 03h ?offset 02h: did: device identification register? on page 1320 503dh 04h 05h ?offset 04h: pcicmd: device command register? on page 1321 0000h 06h 07h ?offset 06h: pcists: pci device status register? on page 1321 0010h 08h 08h ?offset 08h: rid: revision id register? on page 1322 variable 09h 0bh ?offset 09h: cc: class code register? on page 1323 068000h 0eh 0eh ?offset 0eh: hdr: header type register? on page 1323 00h 10h 13h ?offset 10h: csrbar: control and status registers base address register? on page 1323 00000000h 14h 17h ?offset 14h: mmbar: expansion bus base address register? on page 1324 00000000h 2ch 2dh ?offset 2ch: svid: subsystem vendor id register? on page 1325 0000h 2eh 2fh ?offset 2eh: sid: subsystem id register? on page 1325 0000h 34h 34h ?offset 34h: cp: capabilities pointer register? on page 1326 dch 3ch 3ch ?offset 3ch: irql: interrupt line register? on page 1326 00h 3dh 3dh ?offset 3dh: irqp: interrupt pin register? on page 1326 01h 40h 43h ?offset 40h: lebctl: leb control register? on page 1327 00h dch dch ?offset dch: pcid: power management capability id register? on page 1327 01h ddh ddh ?offset ddh: pcp: power management next capability pointer register? on page 1328 e4h deh dfh ?offset deh: pmcap: power management capability register? on page 1328 0023h e0h e1h ?offset e0h: pmcs: power management control and status register? on page 1329 0000h e4h e4h ?offset e4h: scid: signal target capability id register? on page 1329 09h e5h e5h ?offset e5h: scp: signal target next capability pointer register? on page 1330 f0h e6h e6h ?offset e6h: sbc: signal target byte count register? on page 1330 09h e7h e7h ?offset e7h: styp: signal target capability type register? on page 1330 01h e8h e8h ?offset e8h: smia: signal target ia mask register? on page 1331 00h ech ech ?offset ech: sint: signal target raw interrupt register? on page 1331 00h f0h f0h ?offset f0h: mcid: message signalled interrupt capability id register? on page 1332 05h f1h f1h ?offset f1h: mcp: message signalled interrupt next capability pointer register? on page 1332 00h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1320 order number: 320066-003us 35.12.1.1 offset 00h: vid ? vendor identification register 35.12.1.2 offset 02h: did ? device identification register this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. f2h f3h ?offset f2h: mctl: message signalled interrupt control register? on page 1333 0000h f4h f7h ?offset f4h: madr: message signalled interrupt address register? on page 1333 00000000h f8h f9h ?offset f8h: mdata: message signalled interrupt data register? on page 1334 0000h table 35-149.bus m, device 8, function 0: summary of local expansion bus pci configuration registers (sheet 2 of 2) offset start offset end register id - description default value table 35-150.offset 00h: vid: vendor identification register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 00h 01h size: 16 bit default: 8086h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 vid vendor identification: this register field contains the pci standard identification for intel, 8086h. 8086h ro table 35-151.offset 02h: did: device identification register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 02h 03h size: 16 bit default: 503dh power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 did device identification number: this is a 16-bit value assigned to the expansion bus device. 503dh ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1321 intel ? ep80579 integrated processor 35.12.1.3 offset 04h: pcicmd ? device command register 35.12.1.4 offset 06h: pcists ? device status register table 35-152.offset 04h: pcicmd: device command register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 04h 05h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 reserved reserved 0h rv 10 intd interrupt disable 0h rw 09 fbtb fast back-to-back enable 0h ro 08 ser serr# enable 0h ro 07 reserved reserved 0h rv 06 per parity error response 0h ro 05 vps vga palette snoop 0h ro 04 mwe memory write and invalidate 0h ro 03 ss special cycle 0h ro 02 bm bus master capable 0h rw 01 mem memory space enable: setting this bit enables access to the memory regions the device claims through its bars. 0h rw 00 io i/o space enable: the device does not implement this functionality since it claims no i/o regions. the bit is hardwired to 0. 0h ro table 35-153.offset 06h: pcists: pci device status register (sheet 1 of 2) description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 dpe detected parity error: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 14 sse signaled system error: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 13 rma received master abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 12 rta received target abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 11 sta signaled target abort status: the device does not implement this functionality. the bit is hardwired to 0. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1322 order number: 320066-003us 35.12.1.5 offset 08h: rid ? revision id register the value of this register comes from the ich compatibility rev id registers. 10 : 09 dst devsel timing: the device does not implement this functionality. these bits are hardwired to 0. 00b ro 08 mdpe master data parity error detected: the device does not implement this functionality. the bit is hardwired to 0. the ep80579 uses signals for errors. 0h ro 07 fb2b fast back-to-back capable: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 06 reserved reserved 0h rv 05 mc66 66 mhz capable: the device does not implement this functionality. the bit is hardwired to 0. 0h ro 04 cl capabilities list: this bit is hardwired to 1 to indicate that the device has a capabilities list. 1ro 03 is interrupt status: 0h ro 02 : 00 reserved reserved 0h rv table 35-153.offset 06h: pcists: pci device status register (sheet 2 of 2) description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 06h 07h size: 16 bit default: 0010h power well: core bit range bit acronym bit description sticky bit reset value bit access table 35-154.offset 08h: rid: revision id register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 08h 08h size: 8 bit default: variable power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 rid revision identification number: this value indicates the revision identification number for the aioc device. the 4 most significant bits are always 0. the 4 least significant bits follow the ich revision id scheme as defined in section 19.2.1.4, ?offset 08h: rid - revision id register? on page 736 . variable ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1323 intel ? ep80579 integrated processor 35.12.1.6 offset 09h: cc ? class code register 35.12.1.7 offset 0eh: hdr ? header type register 35.12.1.8 offset 10h: csrbar ? control and status registers base address register the csrbar is a pci bar in memory space that allows access to the control and status registers for the local expansion bus. see chapter 42.0, ?register summary? for a description of the registers this region exposes. table 35-155.offset 09h: cc: class code register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 09h 0bh size: 24 bit default: 068000h power well: core bit range bit acronym bit description sticky bit reset value bit access 23 : 00 cc class code: this value indicates the base class, subclass, and interface. 020000h = network controller / ethernet controller 068000h ro table 35-156.offset 0eh: hdr: header type register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 0eh 0eh size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 hdr pci header type: the header type of the device. 00h = single-function device with standard header layout. 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1324 order number: 320066-003us 35.12.1.9 offset 14h: mmbar ? expansion bus base address register the mmbar is a pci bar in memory space that allows access to the devices on the external local expansion bus. expansion device 0 occupies the first 16mb/32mb of the region, device 1 occupies the next 16mb/32mb, etc. refer to section 42.0, ?local expansion bus controller? for a description of the local expansion bus. table 35-157.offset 10h: csrbar: control an d status registers base address register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 10h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 addr upper programmable base address: these bits are set by bios to locate the base address of the region. 0h rw 11 : 04 zero lower bits: hardwired to 0 to set the region size to 4kb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro table 35-158.offset 14h: mmbar: expansion bus base address register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 14h 17h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 25 addr upper programmable base address: these bits are set by bios to locate the base address of the region. their behavior is described in table 35-159 . 0h rw 24 : 04 zero lower bits: hardwired to 0 to set the region size to 32mb. 0h ro 03 pref prefetchable: hardwired to 0 to indicate that the region is not prefetchable. 0h ro 02 : 01 typ addressing type: hardwired to 0 to indicate a 32-bit region. 00b ro 00 mem memory space indicator: hardwired to 0 to identify the region as in memory space. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1325 intel ? ep80579 integrated processor table 35-159 defines the behavior of the addr field in mmbar along with the resulting number of devices (chip selects) that the leb supports for the configuration. the device count depends on the 16/32mb mode that the exp_timing_cs[0-7] registers in the leb controller select (refer to section 42.5.1.1, ?exp_timing_cs0 - expansion bus timing register? and section 42.5.1.2, ?exp_timing_cs[1-7] - expansion bus timing registers? ). specifically, the leb is in 32mb mode if bit 9 (this bit is in the cnfg_4_0 field) in any of these registers is set, otherwise it is in 16mb mode. table 35-159 defines the behavior of the addr field in mmbar. 35.12.1.10 offset 2ch: svid ? subsystem vendor id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. 35.12.1.11 offset 2eh: sid ? subsystem id register this register is a write-once register. once any byte in the register has been written, the register locks against further writes until reset. table 35-159.mmbar addr field behavior lebsize addr field bar size number of leb devices supported a rw bits ro zero bits 16mb mode 32mb mode 0 none 31:25 zero none none 1 31:25 none 32 mb 2 1 2 31:26 25 64 mb 4 2 3 31:27 26:25 128 mb 8 4 4 31:28 27:25 256 mb 8 8 a. the number of leb devices supported depends on the device mode (16mb or 32mb) mode selected of the exp_timing_cs[0-7] registers in the leb controller. table 35-160.offset 2ch: svid: subsystem vendor id register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 2ch 2dh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 svid subsystem vendor id: this field must be programmed during bios initialization. 0h rwo
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1326 order number: 320066-003us 35.12.1.12 offset 34h: cp ? capabilities pointer register 35.12.1.13 offset 3ch: irql ? interrupt line register table 35-161.offset 2eh: sid: subsystem id register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 2eh 2fh size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 sid subsystem id: this field must be programmed during bios initialization. 0h rwo table 35-162.offset 34h: cp: capabilities pointer register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 34h 34h size: 8 bit default: dch power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 cp pointer to first capability structure: value is dch which is the config space offset of the first capability structure. dch ro table 35-163.offset 3ch: irql: interrupt line register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 3ch 3ch size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irql interrupt line: bios writes the interrupt routing information to this register to indicate which input of the interrupt controller this device is connected to. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1327 intel ? ep80579 integrated processor 35.12.1.14 offset 3dh: irqp ? interrupt pin register 35.12.1.15 offset 40h: lebctl ? leb control register 35.12.1.16 offset dch: pcid ? power management capability id register the power management capability record controls power management in the device. it is a 6b pci sig-defined capability record and includes the pcid, pcp, pmcap, and pmcs fields of the configuration header. for an overview of the power management capability of aioc devices, see section 35.5, ?power management of aioc devices? . table 35-164.offset 3dh: irqp: interrupt pin register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 3dh 3dh size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 irqp interrupt pin: set to 01h to indicate the device always uses inta# as its interrupt pin. 01h ro table 35-165.offset 40h: lebctl: leb control register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: 40h 43h size: 32 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 01 rsv reserved 0ro 00 bsen byte swap control for leb controller. ?0? -> byte swap not enabled ?1? -> byte swap enabled. 0rw table 35-166.offset dch: pcid: power management capability id register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: dch dch size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcid capability id: pci sig assigned capability record id (01h, power management capability) 01h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1328 order number: 320066-003us 35.12.1.17 offset ddh: pcp ? power management next capability pointer register 35.12.1.18 offset deh: pmcap ? powe r management capability register table 35-167.offset ddh: pcp: power manage ment next capability pointer register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: ddh ddh size: 8 bit default: e4h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 pcp next capability pointer: hardwired to e4h to indicate the offset of the next capability. e4h ro table 35-168.offset deh: pmcap: powe r management capability register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: deh dfh size: 16 bit default: 0023h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 11 pme_spt pme# support 0h ro 10 d2_spt d2 support 0h ro 09 d1_spt d1 support 0h ro 08 : 06 aux_crnt aux current 0h ro 05 dsi device specific initialization 1 ro 04 rv reserved 0h rv 03 pme_cli pme clock 0h ro 02 : 00 ver version 011b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1329 intel ? ep80579 integrated processor 35.12.1.19 offset e0h: pmcs ? power management control and status register 35.12.1.20 offset e4h: scid ? signal target capability id register the signal target capability record defines how the device targets it signals to ia agents. it is an 9b vendor-specific capability record and includes the scid, scp, sbc, styp, smia, and sint fields of the configuration header. for more information on signaling by aioc devices, see section 35.4, ?interrupt handling for aioc devices? on page 1235 . table 35-169.offset e0h: pmcs: power management control and status register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: e0h e1h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 pme_status pme status (sticky) 0h ro 14 : 13 data_scale data scale 00b ro 12 : 09 data_sel data select 0000b ro 08 pme_en pme enable (sticky) 0h ro 07 : 04 rv reserved 0000b ro 03 nsr no soft reset 0h ro 02 rv reserved 0h ro 01 : 00 ps power state 00b rw table 35-170.offset e4h: scid: signal target capability id register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: e4h e4h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scid capability id: pci sig assigned capability record id (09h, vendor specific) 09h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1330 order number: 320066-003us 35.12.1.21 offset e5h: scp ? signal target next capability pointer register 35.12.1.22 offset e6h: sbc ? signal target byte count register 35.12.1.23 offset e7h: styp ? signal target capability type register table 35-171.offset e5h: scp: signal target next capability pointer register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: e5h e5h size: 8 bit default: f0h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 scp next capability pointer: hardwired to f0h to indicate the offset of the next capability. f0h ro table 35-172.offset e6h: sbc: signal target byte count register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: e6h e6h size: 8 bit default: 09h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 sbc capability record byte count: hardwired to the number of bytes in the vendor-specific capability record. 09h ro table 35-173.offset e7h: styp: signal target capability type register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: e7h e7h size: 8 bit default: 01h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 styp capability record type: vendor assigned capability record type (01h, ep80579 signal target capability) 01h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1331 intel ? ep80579 integrated processor 35.12.1.24 offset e8h: smia ? signal target ia mask register 35.12.1.25 offset e9h: reserved register writing to this register will result in undefined behavior. 35.12.1.26 offset eah: reserved register writing to this register will result in undefined behavior. 35.12.1.27 offset ech: sint ? signal target raw interrupt register table 35-174.offset e8h: smia: signal target ia mask register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: e8h e8h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved 0h rw 01 smia1 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect expansion bus parity error 0h rw 00 smia0 ia mask bit: if set to 1h, an interrupt is sent to the ia as either an intx or msi based on the pci signaling configuration when detect expansion bus system interrupt 0h rw table 35-175.offset ech: sint: signal target raw interrupt register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: ech ech size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 02 reserved 0h ro 01 sint1 interrupt: read-only view of expansion bus parity error 0h ro 00 sint0 interrupt: read-only view of expansion bus system interrupt 0h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1332 order number: 320066-003us 35.12.1.28 offset f0h: mcid ? message signalled interrupt capability id register the message signalled interrupt capability record defines how the device generates pci msi messages. it is an 10b pci sig-defined capability record and includes the mcid, mcp, mctl, madr, and mdata fields of the configuration header. 35.12.1.29 offset f1h: mcp ? message signalled interrupt next capability pointer register table 35-176.offset f0h: mcid: message signalled interrupt capability id register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: f0h f0h size: 8 bit default: 05h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcid capability id: pci sig assigned capability record id (05h, msi capability) 05h ro table 35-177.offset f1h: mcp: message signalled interrupt next capability pointer register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: f1h f1h size: 8 bit default: 00h power well: core bit range bit acronym bit description sticky bit reset value bit access 07 : 00 mcp next capability pointer: hardwired to 0 to indicate this is the last capability. 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1333 intel ? ep80579 integrated processor 35.12.1.30 offset f2h: mctl ? message signalled interrupt control register 35.12.1.31 offset f4h: madr ? message signalled interrupt address register table 35-178.offset f2h: mctl: message signalled interrupt control register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: f2h f3h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 09 reserved reserved 0h ro 08 mc per-vector masking capable: hardwired to 0 to indicate the device is not capable of per-vector masking. 0h ro 07 c64 64 bit address capable: hardwired to 0 to indicate the device does not generate 64b message addresses. 0h ro 06 : 04 mme multiple message enable: system software writes to this field to indicate the number of allocated messages (less than or equal to the number of requested messages in mmc). a value of 0 corresponds to one message. 000h rw 03 : 01 mmc multiple message capable: system software reads this field to determine the number of requested messages. hardwired to 0 to request one message. 000h ro 00 msie msi enable: system software sets this bit to enable msi signaling. a device driver is pr ohibited from writing this bit to mask a device?s service request. if 1, the device can use an msi to request service. if 0, the device cannot use an msi to request service. 0h rw table 35-179.offset f4h: madr: message signalled interrupt address register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: f4h f7h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 addr message address: written by the system to indicate the lower 32-bits of the address to use for the msi memory write transaction. the lower two bits will always be written as 0. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1334 order number: 320066-003us 35.12.1.32 offset f8h: mdata ? message signalled interrupt data register table 35-180.offset f8h: mdata: message signalled interrupt data register description: view: pci bar: configuration bus:device:function: m:8:0 offset start: offset end: f8h f9h size: 16 bit default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 15 : 00 data message data: written by the system to indicate the lower 16 bits of the data written in the msi memory write dword transaction. the upper 16 bits of the transaction are written as 0. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1335 intel ? ep80579 integrated processor 36.0 aioc interfaces 36.1 overview the aioc interfaces include: ? gigabit ethernet macs ?tdm interface note: this interface is only available on the intel ? ep80579 integrated processor with intel ? quickassist technology. see table 47-1, ?base features of ep80579 skus? on page 1730 . ? local expansion bus interface ? controller area network interfaces ? ieee-1588 time synchronization hardware assist unit ? synchronous serial port (ssp) the details for the tdm interface are available in the software for the intel ? ep80579 integrated processor product line enabling documentation. 36.2 gigabit ethernet (gbe) the three gigabit ethernet controllers off-load various tasks from the ia-32 core to improve performance. this off-load is often times referred to as ?network interface card? or nic functionality. provided features fall into these five general categories: ?mac features ?host off-loading ?link interface ? power management (wake on lan) ?serial eeprom interface ?integrated dma the gbe controller is based on an intel fourth-generation gigabit mac to provide a standard ieee 802.3 ethernet interface for 1000base-t, 100base-t, and 10base-t applications (802.3, 802.3u, and 802.3ab). the controller is capable of transmitting and receiving data rates of 1,000 mbps, 100 mbps or 10 mbps. by using hardware acceleration, the controller is able to off-load tasks, such as checksum calculations and tcp segmentation from the host processor. the native interfaces supported by the gbe controller are mii and gmii. protocol translation gaskets are used to provide the rmii and rgmii interfaces.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1336 order number: 320066-003us power management features include support for apm and apci. each controller supports the d0 and d3 states including internal clock gating for reduced power consumption in the d3 state. further, one controller is located in an independent auxiliary power well for particularly power sensitive applications. the dma function provides the capability for packet data transfer and descriptor management. the gbe controller is able to cache up to 64-packet descriptors. a 64-kbyte, on-chip packet buffer mainta ins performance as available bandwidth changes. finally, each controller is capable of self-configuration via an optional, external serial eeprom. 36.2.1 integrated dma features ? performs descriptor-driven receive packet transfers from rx mac to system memory. ? performs descriptor-driven transmit packet transfers from system memory to tx mac. ? separate transmit and receive dma engines. ? 64-entry descriptor caches for transmit and receive. ? descriptor ring management hardware. ? configurable 64kb packet buffer. 36.2.2 mac features the mac controller?s scsma/cd unit handles all the ieee 802.3 receive and transmit mac functions while interfacing between the dma and link interface (rmii/rgmii) the mac unit supports: ? complete csma/cd function supporting ieee 802.3 (10mb/s), 802.3u (100mb/s), 802.3z and 802.3ab (1000mb/s). ? half- and full-duplex operation at 10/100. ? full-duplex operation at 1000 mbps. ? up to 16 addresses for exact match unicast/multicast address filtering. ? multicast address filtering based on 4,096-bit vectors in addition to promiscuous unicast and promiscuous multicast filtering. ? mac strips ieee 802.1q vlan tags and filters packets based on their vlan id. up to 4,096 vlan tags are supported. ? transmit path supports insertion of vlan tag information on a packet-by-packet basis. ? flow control as defined in ieee 802.3x as well as specific operation of asymmetrical flow control defined by ieee 802.3z and software controllable pause times and threshold values. ? programmable host memory receive buffers (256 byte to 16 kbyte) and cache line size (16 to 256 byte). ? 16 kbyte configurable transmit and receive fifo buffers with ecc protection. ?wakeup. ? acpi down functionality supporting d0 & d3 states.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1337 intel ? ep80579 integrated processor 36.2.3 host off-loading features the gbe controller provides the ability to off-load ip, tcp, and udp checksum for transmit, packet filtering, and hardware vlan support. the functionality provided by these features significantly reduce the ia processor utilization by shifting the burden of the functions from the driver to the hardware. ? ipv4 checksum calculation ? tcp/udp checksum calculation ? 16 kbyte jumbo-frame support ? interrupt coalescing (multiple packets per interrupt) ? tcp segmentation for transmits that off-loads packet segmentation and encapsulation ? rmon statistics ? ipv6 support for ip/tcp and ip/udp receive checksum off-load ?ipv6 wake-up filters ?ipv6 tcp segmentation 36.2.4 interfaces the gbe controller provides the following serial interfaces: ? rmii ? 8-pin interface ? rgmii ? 12-pin interface ?mdio/mdc interface note: for information on phy selection: 1. go to http://www.intel.com/go/soc. 2. select the "technical documentation" tab. 3. search for "ethernet phy selection criteria for the intel ? ep80579 integrated processor product line?. 36.2.5 power management each controller supports the following power management related features: ? power states of d0 & d3hot with optional d3cold support. ? d3cold support on gbe0 only. ?wake on lan. each gbe may be configured to generate a pme signal on the reception of a magic packet or a network wake-up packet. a combination of pre-defined and user configurable filters are provided to support this functionality. the pme_n wake-up signals from all gbe units are wired-or together and brought out to a single external pin. this pin should be externally wired to the pme_n pin of the ich. when transitioned to the d3hot state, the gbe controller internally performs clock- gating on many of its blocks to reduce power.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1338 order number: 320066-003us additionally, one of the gbe controllers (gbe0) is located in the auxiliary power well. this allows monitoring of lan traffic on this interface while the rest of the ep80579 is in ultra-low-power mode. the details of power well manipulation is outside the scope of this chapter and the reader is referred to chapter 37.0, ?gigabit ethernet controller? for details. 36.2.6 serial eeprom interface a single four-wire microwire* interface is provided for connection of an optional, externally connected serial eeprom. the serial eeprom may be used to provide configuration information to the gbe controllers upon power-up or reset. all three controllers share the same eeprom. a fixed priority arbiter controls access to the eeprom where highest priority is given to gbe 0 then gbe 1 and finally gbe 2. software may also access this eeprom. it can either use the controller built in to the mac to read the eeprom, or access the eeprom directly using the eeprom's 4-wire interface via registers also provided in the mac. 36.3 local expansion bus interface (leb) the local expansion bus controller (leb) provides a low-speed interface to external expansion target devices. the expansion bus controller includes a 25-bit address bus and a 16-bit-wide data path. the expansion bus controller maps transfers between the ep80579 and external devices. the expansion bus supports these target devices: ? intel multiplexed ? intel non-multiplexed ?intel strataflash ? technology ?intel strataflash ? synchronous memory ? micron* flow-through zbt ? motorola* multiplexed ? motorola* non-multiplexed ? texas instruments* host port interface* (hpi) applications having less than 16-bit, external target devices may connect to an 8-bit interface. for ti dsps that support an internal bus width of 32 bits, the multiplexed hpi-8 or hpi-16 interface can be used to complete these transfers. the expansion bus controller features include: ? outbound transfers ? the ep80579 is the master to an external target device. ? eight programmable target chip selects. ? twenty-five bits of a ddress; 16 bits of data. ? supports intel-mode and motorola-mode bus cycles. ? supports intel strataflash. ? supports 66-mhz synchronous intel strataflash memory (16-bit only). ? supports 16-bit micron* flow-through zbt (zero bus turnaround) srams. ? supports 8-bit and 16-bit texas instruments* hpi specifications . ? multiplexed or non-multiplexed address/ data buses for intel/motorola/hpi bus cycles.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1339 intel ? ep80579 integrated processor ? supports even- and odd-parity generation and calculation. ? maximum clock input frequency of 80 mhz. 36.4 serial synchronous port (ssp) the ssp is a full-duplex, synchronous, serial interface. it can connect to a variety of external analog-to-digital (a/d) converters, audio and telecom codecs, and many other devices that use serial protocols for transferring data. the interface supports national microwire*, texas instruments* synchronous serial protocol (ssp), and motorola* serial peripheral interface (spi) protocol. key features of the ssp port are: ? operates in master mode (the attached peripheral functions as a slave). ? supports serial bit rates from 7.2 kb/s to 1.84 mb/s. ? serial data formats may range from 4 to 16 bits in length. ? two on-chip register blocks function as independent fifos for data, one for each direction. ? the buffers are 16 entries deep x 16 bits wide. buffers may be burst-loaded or emptied by the system processor using sram-like burst transfers, from 1 to 8 words per transfer. ea ch 32-bit word from the system fills one entry in a fifo using the lower half 16-bits of a 32-bit word. 36.5 controller area network (can) the controller area network (can) is a serial bus system used in a broad range of embedded as well as automation control systems. it usually links two or more microcontroller-based physical devices. can protocol is based on a broadcast co mmunication mechanism. this broadcast communication is achieved by using a message-oriented transmission protocol. in this protocol, station and station addresses are not defined. only messages are defined. these messages are identified by using a message identifier. the message identifier has to be unique within the whole network and it defines not only the content but also the priority of the message. a high degree of system and configuration flexibility is achieved as a result of the content-oriented addressing scheme.this content-oriented addressing scheme allows for a high degree of system and configuration flexibility. it is very easy to add stations to a existing can network without making any hardware or software modifications to the existing stations as long as the new stations are purely receivers. this allows the concept of modular electronics and also permits multiple reception and the synchronization of distributed processes. data needed as information by several stations can be transmitted via the network in such a way that it is unnecessary for each station to have to know who the producer of the data is. this allows easy servicing and upgrading of networks as data transmission is not based on the availability of specific types of stations. key features include: ? support for can 2.0b protocol ? support for 11-bit and 29-bit identifiers ? bit rates up to 1 mbps
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1340 order number: 320066-003us ? clock frequency of 40 mhz 36.6 ieee 1588 time synchroniz ation hardware assist in a distributed control system containing multiple clocks, individual clocks tend to drift apart. some kind of correction mechanism is necessary to synchronize the individual clocks to maintain global time, which is accurate to some requisite clock resolution. the ieee 1588 standard for a precision-clock-synchronization protocol for networked measurement and control systems can be used for this purpose. the ieee standard defines several messages that can be used to exchange timing information. the hardware-assist logic required to achieve precision clock synchronization using the ieee 1588 standard is left to implementation. the time-synchronization logic monitors the internal mii/gmii signals on two of the three gigabit ethernet interfaces. additionally , this block monitors both can interfaces. an interrupt signal to the ia-32 core is generated when any of the following conditions occur and are enabled: ? target time expiration ? auxiliary master mode snapshot is taken ? auxiliary slave mode snapshot is taken the system time and target time registers are both 64 bits wide. when the system time is greater than or equal to the target time, the target time expiration condition will set. an interrupt enable mask must be set to allow the target time interrupt to pass to the core.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1341 intel ? ep80579 integrated processor 37.0 gigabit ethernet controller 37.1 overview the three gigabit ethernet controllersoff load various tasks from the ia-32 core to improve performance. this off load is often times referred to ?network interface card? or nic functions. the gigabit ethernet controller is based on an intel fourth generation gigabit mac to provide a standard ieee 802.3 ethernet interface for 1000base-t, 100base-tx, and 10base-t applications. the controller is capable of transmitting and receiving data rates of 10/100/1000 mbps. the convergence and pmd sublayer communication of the physical layer are implemented in mii/gmii (internally) and rmii/rgmii (externally). note: the rgmii, and rmii, while not natively supported in the gigabit ethernet controller are supported by protocol translators between the gigabit ethernet controller and the pins. note: for information on phy selection: 1. go to http://www.intel.com/go/soc. 2. select the "technical documentation" tab. 3. search for "ethernet phy selection criteria for the intel ? ep80579 integrated processor product line?. 37.1.1 terminology and conventions 37.1.1.1 register and bit references this document refers to device register names with all capital letters. to refer to a specific bit in a register the convention register.bit is used. for example, ctrl .bem refers to the big endian mode bit in the device control register ( ctrl ). 37.1.1.2 byte and bit designations this document uses ?b? to abbreviate quantities of bytes, i.e. a 4kb represents 4096 bytes. similarly, ?b? is used to represent quantities of bits, i.e. 100mbps represents 100 megabits per second. 37.1.1.3 numbering all numbers are in decimal unless otherwise indicated. hexadecimal numbers will be preceded by a 0x or followed by an h. if not clear from the context, binary numbers will be followed by a b or (b). single bits are generally given as simply 0 or 1, since the value is identical in binary or decimal.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1342 order number: 320066-003us 37.1.1.4 memory alignment terminology some gbe data structures have special memory alignment requirements. this implies that the starting physical address of a data structure must be aligned as specified in this gbe chapter. the following terms are used for this purpose: ? byte alignment implies that the physical addresses can be odd or even. examples: 0fecbd9a1h, 02345adc6h. ? word alignment implies that physical addresses must be aligned on even boundaries; i.e., the last nibble of the address may only end in 0, 2, 4, 6, 8, ah, ch, or eh. for example, 0fecbd9a2h. ? dword (double-word) alignment implies that the physical addresses may only be aligned on 4-byte boundaries; i.e., the last nibble of the address may only end in 0, 4, 8, or ch. for example, 0fecbd9a8h. ? qword (quad-word) alignment: implies that the physical addresses may only be aligned on 8byte boundaries; i.e., the last nibble of the address may only end in 0, or 8. for example, 0fecbd9a8h. ? paragraph alignment implies that the physical addresses may only be aligned on 16-byte boundaries; i.e., the last nibble must be a 0. for example, 02345adc0h. 37.1.1.5 alignment and byte ordering it should be noted that the data stream in ethernet has no notion of byte alignment. all data on the wire is referenced as bit ordered. data is presented ?on the wire? least significant bit (lsb) first. for example: a big-endian destination address in the ethernet header may be represented in as 0x00_11_22_33_44_55. in this case, the data is seen on the wire in the byte order as written from left to right, however the bits are seen lsb first, i.e. bit 0 of the first ?00? byte occurs first. representations of these fields internal to the ep80579 may reverse the byte ordering as shown above. care must be taken to av oid byte ordering errors when programming the device. refer to section 37.5.14, ?endianness? on page 1422 and section 3.6, ?endianness? on page 119 . 37.1.1.6 packet buffer the gbe packet buffer (pb) is an ecc protected 64kb dedicated memory used for buffering transmit and receive packets as they are communicated. the proportions of the pb dedicated to tx and rx operations is software configurable. throughout this chapter, the tx portion of pb is referred to as the tx fifo and the rx portion of the pb is referred to as the rx fifo. these terms are interchangeable. it is also worthwhile to note that any information in the pb, either for incoming or outgoing data, is volatile. the gbe will receive packets into the rx pb and transfer the rx descriptor(s) and payload into host memory for the host cpu before sending interrupt notification. conversely, the host cpu will transfer tx descriptor(s) and payload into host memory for the gbe before notifying the gbe that the packet information is available. after this notification, the gbe transfers the tx information to the tx pb and sends the data out on the wire. the host cpu will never have to directly access the gbe?s pb, however diagnostic access is supported.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1343 intel ? ep80579 integrated processor 37.1.2 wake on lan the gbe does not support preservation of magic packets for wake on lan. additionally, the storage of other packets received after a qualifying wake event is not supported until the gbe has been returned to a d0a state. if the gbe was in d3 then it must be specifically moved to d0 by the ia software writing to the power capability register or reset must be cycled and the gbe re-initialized. software intervention is required to move the gbe to d0a and restart packet receive processing. 37.2 feature list the following is a list of gbe mac features: ? compliant with the 1000 mbps ethernet/802.3z specification. ? half-duplex mii operation. ? full-duplex operation at all mii and gmii speeds. ? programmable system memory receive buffers (256b to 16kb). ? 64b cache-line size. ? 64kb rx/tx packet buffer (defaulted to 48 kb rx and 16 kb tx, but configurable). ? descriptor ring management hardware for tx packet buffer. ? support for little-endian or big-endian byte ordering. ? flow control support: send/receive pause frames & receive fifo thresholds. ? statistics for local management and software optimization. ? a mechanism for delaying/reducing transmit interrupts. ? functional and error interrupt signals. ? software-controlled reset bit. ? frame formats supported by the ep80579?s gbe include: ? ethernet 802.3 ? ieee 802.1q vlan (ethernet 802.3ac) ? ethernet type 2 ? ethernet snap ? ipv4 headers with options ? ipv6 headers with ip option next headers. ? ipv6 packet tunneled in ipv4. ? tcp with options. ? udp with options. ? multi-speed operation: 10/100/1000 mbps. ? all local memories and buffers are protected.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1344 order number: 320066-003us 37.3 functional block diagram the internal bus interfaces provide the access to the gbe csrs as well as the medium over which ethernet packets are transferred between the ethernet client and the ep80579. the dma engine buffers the packets between system memory and the mac core. the mac core transfers packets between the dma engine and the ethernet client. the internal bus interface accepts the pci configuration transactions and routes those transactions to the proper internal module. these blocks all operate in the lan clock domain. figure 37-1. gbe controller block diagram gbe controller target logic dma engine mac core host interface descriptor engine data memory interface 1 kbyte tx descriptor memory 1 kbyte rx descriptor memory 64- kbyte packet buffer mac filtering tx mac interface translation internal bus mii gmii rx mac internal bus clock domain lan clock domain internal bus interface
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1345 intel ? ep80579 integrated processor 37.4 usage model the ep80579 implements three gbe controllers. in addition to the three controllers, protocol translation gaskets and an mdio interface are provided. also, a multiplexor to allow the three gbe controllers to share access to a common serial eeprom is implemented. a block diagram of these units is shown in figure 37-2 : figure 37-2. gbe ethernet complex mii / rmii translator gmii / rgmii translator eeprom arbiter select gcu gbe 1 pins gbe 2 pins gbe 0 auxiliary power well core power well rcomp logic io well 2.5v or 3.3v aux_pwr_present isolation_n pwr_ok pme_wake reset mii/gmii mii / rmii translator gmii / rgmii translator select gbe 1 aux_pwr_present isolation_n pwr_ok pme_wake reset mii/gmii mii / rmii translator gmii / rgmii translator select gbe 2 aux_pwr_present isolation_n pwr_ok pme_wake reset mii/gmii ?0? ?0? ?1? ?1? reset reset reset ?or? of all 3 pme_wake?s mdio 1 pins io well 2.5v or 3.3v micro-wire interface aux_pwr_good pme_wake gbe 0 pins sys_pwr_ok core power well
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1346 order number: 320066-003us 37.4.1 protocol translation while the gbe?s does not natively support rgmii or rmii a protocol translator is implemented between the gbe and the pins that converts rgmii to gmii and rmii to mii for the gbe. even though the pins may be using an rgmii or rmii protocol the gbe is still only communicating in its native gmii and/or mii protocols. the selection of the appropriate translator is controlled by the auxiliary device control register. refer to section 37.6.2.4, ?ctrl_aux ? auxiliary device control/status register? note that when the translator selection register has enabled rgmii, the gbe must be configured to gmii/mii operation. likewise, when the settings have enabled rmii, the gbe must be configured to mii operation. 37.4.2 power management as shown in figure 37-2, ?gbe ethernet complex? on page 1345 , gbe0 is located in a separate auxiliary power well. this gives the user the ability to bring the rest of the chip into an ultra-low power mode (power removed) while gbe0 continues to operate in d3cold to support wake on lan. if a separate auxiliary power source is used for gbe0, then platform must also supply an aux_pwr_good signal which is asserted to indicate that the auxiliary power supply is stable and that the reference clock for the gbe is stable. additionally, the eedi pin should be pulled-up to provide the internal aux_pwr_present signal indicating that an auxiliary supply is being used. if an auxiliary power supply is not being used and the power supplied to the auxiliary well is the same as that for the core logic, then eedi must be tied low. in this situation the same signal as provided to sys_pwr_ok is also routed to aux_pwr_good. note that if an auxiliary supply is used for gbe0 then the corresponding phy and also the serial eeprom, if present, must be powered. refer to the section 6.3.2, ?power management support? and section 37.5.10, ?wake on lan? for more details. 37.4.3 software initialization and diagnostics this section discusses general software notes for the gbe, especially initialization steps. this includes general hardware power-up state, basic device configuration, initialization of transmit and receive operation, link configuration, software reset capability, statistics, and diagnostic hints. 37.4.3.1 power up state when the mac powers up it will read the optional eeprom. the eeprom contains sufficient information to bring the link up and configure the mac for manageability and/ or apm wakeup. however, software initialization is required for normal operation and if the eeprom is not present. the power-up sequence, as well as transitions between power states, is described in section 37.7.3, ?power states? on page 1550 . the detailed timing is given in section 37.7.4, ?timing of power-state transitions? on page 1551 . section 37.6, ?gbe controller register summary? on page 1425 gives detailed registers descriptions with details on power on defaults.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1347 intel ? ep80579 integrated processor 37.4.3.2 memory initialization the gbe?s internal memory must be initialized after the gbe unit has been powered-up, to insure that no ecc or parity errors are generated from the random state of memory after a power-up. if an ecc or parity error is encountered, a soft reset must be issued, then the entire affected memory (that report ed the error) must be re-initialized to remove the error, so that it doesn?t re-occur. after each power-up and soft reset, and after the memories have been initialized as described below, software must clear the appropriate ecc disable bits described in section 37.6.8.3, ?mem_sts ? memory error status register? on page 1546 . neither ecc nor parity errors will be reported nor will the gbe error handling be enabled (as described in section 37.5.12, ?error handling? on page 1418 ) until these bits have been cleared out. these may be cleared immediately after a soft reset if the error condition that resulted in the soft reset did not involve an ecc or parity error from one of these memories. 37.4.3.2.1 packet buffer memory the packet buffer memory is initialized through write accesses to the pbm locations. a single pbm access will initialize four locations within the packet buffer memory, using address bits 15:4 of the pbm access to select the 128bit packet buffer memory location. therefore, 4096 writes are required to initialize the 64kb of packet memory, writing every four pbm locations (pbm(0), pbm(4), pbm(8), etc.). 37.4.3.2.2 descriptor tx and rx memory the descriptor tx and rx memories are each initialized through write accesses to the txdescm and rxdescm locations. a single de sctx or descrx access will initialize four locations within the descriptor memory, using address bits 15:4 of the access to select the 128bit descriptor memory location. therefore, 64 writes are required to initialize the 1kb of descriptor memory, writing every four desc locations (descrx(0), descrx(4), descrx(8), etc.). 37.4.3.2.3 multicast filter and special packets memory the multicast and vlan filter memories are each initialized through write accesses to the mta and vfta locations as described in section 37.6.4.14, ?mta[0-127] ? 128 multicast table array registers? on page 1488 and section 37.6.4.17, ?vfta[0-127] ? 128 vlan filter table array registers? on page 1490 . initialization will require 128 writes to initialize the 512b of descriptor memory, writing every mta or vlan filter location. 37.4.3.2.4 flexible filter memory the flexible filter memories are each initialized through write accesses to the ffvt and ffmt locations as described in section 37.6.7.12, ?ffvt[0-127] ? flexible filter value table registers? on page 1543 and section 37.6.7.11, ?ffmt[0-127] ? flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1542 . initialization will require 128 writes to initialize the 512b of descriptor memory, writing every mta or vlan filter location. initialization will require 256 writes to initialize the memories, writing every one of the 128 ffmt and ffvt locations. 37.4.3.2.5 statistics memory the statistics memory provides no write access, but is initialized by the gbe automatically after a power-up reset or software reset.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1348 order number: 320066-003us 37.4.3.3 general configuration several values in the ctrl ? device control register , ctrl_ext ? extended device control register and ctrl_aux ? auxiliary device control/status register need to be set upon power up or after a device reset for normal operation. ? convergence layer mode of the mac is programmed by the ctrl_ext.link_mode setting. this value may also be read by software from the status ? device status register at status.tbimode. ? duplex mode is determined via auto-negotiation between the external phy and it?s link partner. software either continuously polls the phy registers via mdio until a link is detected or the host cpu is interrupted when the link is established via the phy?s mdint capability. software then programs ctrl.fd per the interface negotiation. status information can be found at status.fd. ? speed is determined via auto-negotiation between the external phy and it?s link partner. software either continuously polls the phy registers via mdio until a link is detected or the host cpu is interrupted when the link is established. software then programs ctrl.speed per the interface negotiation. status information can be found at status.speed. ? desired endianness configuration must be set in ctrl_aux. 37.4.3.4 link setup mechanisms and control/status bit summary ? mac duplex and speed settings forced by software based on resolution of phy ? ctrl.fd and ctrl.speed is set by software based on reading phy status register after phy has successfully auto-negotiated a link with the link partner. ? ctrl.rfce and ctrl.tfce must be set by software after reading flow control resolution from phy registers 37.4.3.5 receive initialization software must program the receive address low register (ral) and receive address high register (rah) registers to represent the receive address(es) per the station address. the station address (a.k.a the mac address) is ral/rah(0), fifteen additional receive addresses can be programmed in addition to this. software must also set up the 128 multicast table array registers (mta[127:0]). this probably means zeroing all entries initially and adding in entries to the multicast table array as requested. figure 37-3 diagrams the multicast lookup algorithm. the destination address shown represents the internally stored ordering of the received destination address. note that bit 0 indicated in this diagram is the first on the wire. refer to ?ethernet addressing? on page 1351 for more details. note that the bank bits is the rctl.mo setting. program the interrupt mask set/read register (ims) to pass any interrupt the driver cares about to the interrupt controller for routing further to the ep80579?s ia-32 core. suggested bits include ims.rxt0, ims.rxo, and ims.rxdmt0. program receive control register (rctl) with appropriate values. if initializing, it is necessary to leave the receive logic disabled, rctl.en = 0, until after the receive descriptor ring has been initialized. if vlans are not used, software should clear rctl.vfe. then there is no need to initialize the 128 vlan filter table array registers (vfta[127:0]). initialize the remainde r of rctl as desired, refer to ? section 37.6.4.1, ?rctl ? receive control register? ? or details.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1349 intel ? ep80579 integrated processor to properly receive packets requires only that the receiver is enabled. this should be done only after all other setup is accomplished. if software uses the receive descriptor minimum threshold interrupt (ims.rxdmt0 = 1), that receive threshold value should be set in the flow control receive threshold low register (fcrtl) and flow control receive threshold high register (fcrth) mmrs. allocate a contiguous region of memory for the receive descriptors. program the receive descriptor region into the following mmrs describing the memory region: ? receive descriptor base address low register (rdbal) ? receive descriptor base address high register (rdbah) ? receive descriptor length register (rdlen) the receive descriptor head register (rdh) and receive descriptor tail register (rdt) pointers are initialized (by hardware) to 0 after a power-on or a software-initiated device reset. receive buffers of appropriate size should be allocated using rctl.bsex and rctl.bsize. pointers to these buffers should be stored in the descriptor ring. the tail pointer should be set to point one descriptor beyond the end. 37.4.3.6 transmit initialization packet transmission is configured via the transmit control register (tctl). for example, values for this mmr could be: figure 37-3. multicast table array algorithm b-0 47:40 39:32 31:24 23:16 15:8 7:0 bank[1:0] pointer[11:5] multicast table array 32 x 128 (4,096-bit vector) ... ... pointer[4:0] word bit ? destination address
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1350 order number: 320066-003us ? tctl.ct = 0x0f ? tctl.cold = 0x200 (512d); for half-duplex mode ? tctl.cold = 0x040 (64d); for full-duplex mode ? tctl.psp = 1 note: not all of these values are needed in all duplex modes, but it is more concise to simply always program them to the values shown regardless of mode. program the transmit ipg register (tipg) with the following values to get the minimum legal inter packet gap (ipg): ? tipg.ipgt = 0x8 (8d) ? tipg.ipgr1 = 0x8 (8d) ? tipg.ipgr2 = 0x6 (6d) note: not all of these values are needed in all duplex modes, but it is more concise to simply always program them to the values shown regardless of mode. allocate a contiguous region of memory for the transmit descriptor list. program the transmit descriptor region into the following mmrs describing the memory region: ? transmit descriptor base address low register (tdbal), ? transmit descriptor base address high register (tdbah), ? transmit descriptor length register (tdlen), ? transmit descriptor head register (tdh), and ? transmit descriptor tail register (tdt). 37.4.3.7 initialization of statistics statistics registers are hardware-initialized to values as detailed in each particular register's description. no initialization of these registers through software is necessary. 37.4.3.8 gbe line rate configuration change the gbe unit must be reconfigured when switching rates with the rgmii gasket. the following guidelines apply: ? disable receiver and transmitter by setting the rctl.en and tctl.en bits to 0. ? wait an appropriate time for any packet being received to finish. ? write ctrl.speed, ctrl.frcspd, ctrl.fd, ctrl.frcdplx with the targeted interface parameters. ? re-enable receiver and transmitter by setting the rctl.en and tctl.en bits to 1. 37.4.3.9 network boot initialization of the gbe controller at power-up and/or reset from an optional serial eeprom is supported. refer to section 37.5.11, ?serial eeprom? on page 1412 for details on the use and configuration of the serial eeprom. note: section 22.2.4 of the ieee 802.3 specification requires that phy devices enter a normal operating state after power-up and/or reset without management intervention. as a result, it is believed that the mac is not required to perform any sort of phy initialization in the support of network boot.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1351 intel ? ep80579 integrated processor 37.4.3.10 diagnostics to assist in test and debug of device-driver software, a set of software-usable features have been provided. these features include controls for specific test-mode usage, as well as some registers for verifying device internal state against what the device-driver might be expecting. the gbe provides software visibility (and controllability) into certain major internal data structures, including all of the transmit & receive fifo space. however, interlocks are not provided for any operations, so diagnostic accesses should only be performed under very controlled circumstances. the device also provides software-controllable support for certain loopback modes, to allow a device-driver to test transmit and receive flows to itself. loopback modes may also be used to diagnose communication problems and attempt to isolate the location of a break in the communications path. 37.4.3.10.1 fifo pointer accessibility the internal pointers into the transmit and receive data fifos are visible through the head and tail diagnostic data fifo registers. diagnostic software may read these fifo pointers to confirm an expected hardware state following a sequence of operations. diagnostic software may further write to these pointers as a partial-step to verify expected fifo contents following specific operation, or to subsequently write data directly to the data fifos. 37.4.3.10.2 fifo data accessibility the internal transmit and receive data fifo contents are accessible through the packet buffer memory (64kb) (pbm[n]) registers. the specific locations read/written are determined by the values of the fifo pointers, which may also be read/written. when accessing the actual fifo data structures, locations must be accessed as 32-bit words. 37.4.3.10.3 loopback operations loopback transmit/receive operation is a recommended debug tool. there are two points where the transmit data can be looped back to the receive path: in the phy and in the mac. it is highly recommended that the phy selected to interface with the gbe has implemented loopback operations in order to assist with system and device debug. loopback operation may be used to test transmit & receive aspects of software drivers, as well as verify electrical integrity of the connections between the gbe and the system. all loopback modes are only allowed when the mac and phy are configured for full duplex operation. 37.5 functional description 37.5.1 ethernet addressing several registers store ethernet addresses in the gbe. two 32-bit registers make up the address, the ?high? and the ?low?. for example, the receive address register is comprised of receive address high (rah) and receive address low (ral). the least significant bit of the least significant byte of the address stored in the register (i.e., bit 0 of ral) is the multicast bit. the ls byte is the first byte to appear on the wire. this notation applies to all ethernet address registers including flow control.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1352 order number: 320066-003us figure 37-4 illustrates the bit/byte addressing order comparison between what is on the wire and the values in the unique receive address registers. the address byte order numbering from the above example maps as shown below in figure 37-5 . byte #1 is the first on the wire. note: the notation in this document follows the above convention. for example, the above address would be indicated as 0x00_aa_00_11_22_33, where the first byte (00_) is the first byte on the wire with bit 0 of that byte transmitted first. 37.5.2 interrupt control & tuning the gbe provides a complete set of interrupts for efficient management by software. the interrupt structure is carefully designed to: ? make accesses thread safe by using set and clear-on-read rather read-modify-write operations. ? minimize the interrupts per work accomplished. ? minimize the processing overhead associated with each interrupt. the interrupt logic consists of four interrupt registers that accomplish the first goal. these registers are described in more detail in section 37.6.3, ?interrupt registers: detailed descriptions? on page 1454 . three actions minimize the number of interrupts: reducing the frequency of all interrupts, accepting multiple receive packets before signaling an interrupt, and by eliminating (or reducing) the need for interrupts on transmit. refer to ?interrupt throttling register? on page 1353 , ?receive interrupts? on page 1360 , and ?transmit interrupts? on page 1378 for details. figure 37-4. example address byte ordering d5 ...55 00 aa 11 22 33 ...xxx preamble & sfd destination address source address bit 0 of this byte is first on the wire. 00 aa 00 11 22 33 destination address stored internally as shown here ... rah ral 00 aa 00 11 22 33 multicast bit 00 = ? dest_addr[0] figure 37-5. da byte ordering ia byte number 1(lsb)2345 6(msb ) byte value (hex) 00 aa 00 11 22 33
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1353 intel ? ep80579 integrated processor 37.5.2.1 interrupt cause set/read registers the read register records the cause of the inte rrupt. all bits set at the time of the read are auto-cleared. the cause bit is set for each bit written as one in the set register. if there is a race between hardware setting a cause and software clearing an interrupt, the bit remains set. no race condition exists on writing the set register. set provides for software posting of an interrupt. reads are auto-cleared to avoid expensive write operations. most systems have write buffering that minimizes overhead, but this typically requires a read operation to guarantee that the write has been flushed from posted buffers. without auto-clear, the cost of clearing an interrupt can be as high as two reads and one write. 37.5.2.2 interrupt mask set (read)/clear registers interrupts appear only if the interrupt cause bit is a one and the corresponding interrupt mask bit is a one. software blocks assertion of the interrupt wire by clearing the bit in the mask register. the cause bit stores the interrupt event regardless of the state of the mask bit. clear and set make this register more ?thread safe? by avoiding a read-modify-write operation on the mask register. the mask bit is set for each bit written to a one in the set register and cleared for each bit written in the clear register. reading the set register returns the current value. 37.5.2.3 interrupt throttling register the frequency of functional interrupts from the network controller can be reduced when inter-interrupt interval value is non-zero. controller asserts pending interrupts only at regularly scheduled intervals. when inter-interrupt interval value is zero, controller asserts pending interrupts immediately. the interrupt throttling register only applies to the gbe functional interrupt 0. 37.5.3 hardware acceleration capability the gbe provides cpu off loading capabilities. the functionality provided by these features may significantly reduce cpu utilization by shifting the burden of the functions from the driver to the hardware. these features include: ? receive & transmit checksum off loading ?tcp segmentation these functions are covered in more detail in ?receive packet checksum off loading? on page 1363 , ?transmit checksum off loading? on page 1379 , and ?tcp segmentation? on page 1380 . the following sections provide a brief overview of these capabilities. 37.5.3.1 checksum off-loading the gbe provides the ability to off load the ipv4, tcp & udp checksum requirements from the software device driver. for common frame types, the hardware automatically calculates, inserts and checks the appropriate checksum values typically handled by software. note: ipv6 headers do not have a checksum. for transmits where the device is doing non-tcp segmentation, every transmitted ethernet packet may have two checksums calculated and inserted by the device. typically these would be the ipv4 and either tcp or udp checksums. the driver
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1354 order number: 320066-003us specifies which portions of the packet are included in the checksum calculations, and where the calculated values are inserted, via descriptor(s). see ?tcp/ip context transmit descriptor format? on page 1369 for details. for receives, the hardware recognizes the packet type and performs the checksum calculations as well as error checking automatically. checksum and error information is provided to software via the receive descriptor(s). refer to ?receive packet checksum off loading? on page 1363 for details. 37.5.3.2 tcp segmentation the gbe implements a tcp segmentation capability for transmits which allows the software device driver to off load packet segmentation and encapsulation to the hardware. the device driver may send the gbe the entire ip (ipv4 or ipv6), tcp, or udp message sent down by the nos for transmission. the device will segment the packet into legal ethernet frames and transmit them on the wire. by handling the segmentation tasks, the hardware alleviates the software from handling some of the framing responsibilities. this reduces the overhead on the cpu for the transmission process thus reducing overall cpu utilization. see ?tcp segmentation? on page 1380 for details. 37.5.4 buffer and descriptor structure software allocates transmit and receive buffers and forms descriptors that contain pointers to and status of those buffers. a conceptual ownership boundary exists between the driver software and the hardware for buffers and descriptors. software gives hardware ownership of a queue of buffers for receive. these buffers store data that software acquires ownership of once a valid packet arrives. for transmit, software maintains a queue of buffers. the software ?owns? a buffer until it is ready to transmit. software commits the buffer to the hardware at which time the hardware ?owns? the buffer until data is transmitted or loaded in the transmit fifo. descriptors store information about the buffers. they contain the physical address, length, and status information about the referenced buffer. an end-of-packet field indicates the last buffer for a packet. the descriptors also contain packet specific information indicating type of packet and specific operations to perform in the context of transmitting a packet such as those for vlan or checksum off load support. the following sections describe descriptor structure and operation in more detail in the context of packet transmission and reception. 37.5.5 packet reception in the general case, packet reception consists of recognizing the presence of a packet on the wire, performing address filtering, storing the packet in the receive data fifo, transferring the data to the receive buffer in host memory, updating the state of a receive descriptor, and setting the interrupt cause register to pass ownership of the received packet information to software. 37.5.5.1 packet address filtering hardware stores incoming packets in host memory subject to the following filter modes. if there is insufficient space in the receive fifo for an incoming packet, hardware drops the packet and indicates the missed packet in the appropriate statistics registers. the following filter modes are supported:
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1355 intel ? ep80579 integrated processor exact unicast/multicast - the destination address must exactly match one of 16 stored addresses. these addresses can be unicast or multicast. promiscuous unicast - receive all unicasts. multicast - the upper bits of the incoming packet's destination address index a bit vector that indicates whether to accept the packet; if the bit in the vector is one, accept the packet, otherwise, reject it. the ep80579?s gbe provides a 4096 bit vector. software provides four choices of which bits are used for indexing. these are [47:36], [46:35], [45:34], or [43:32] of the internally stored representation of the destination address. promiscuous multicast - receive all multicast packets. vlan - receive all vlan packets that are for this station and have the appropriate bit set in the vlan filter table. a detailed discussion and explanation of vlan packet filtering is contained in ?802.1q vlan packet filtering? on page 1401 . normally, only good packets are received. these are defined as those packets with no crc error, symbol error, sequence error, leng th error, alignment error, or where carrier extension or rx_err errors are detected. however, if the store-bad-packet bit is set in the device control register (rctl.sbp), then bad packets that pass the filter function are stored in host memory. packet errors are indicated by error bits in the receive descriptor (rdesc.errors). it is possible to receive all packets, regardless of whether they are bad, by setting the promiscuou s enables and the store-bad-packet bit. 37.5.5.2 receive data storage memory buffers pointed to by descriptors store packet data. hardware supports various receive buffer sizes; explicitly 256b, 512b, 1024b, 2048b, 4096b, 8192b, and 16384b. buffer size is selected by bit settings in the receive control register (rctl.bsize & rctl.bsex). see section 37.6.4.1, ?rctl ? receive control register? for details. the ep80579?s gbe places no alignment restrictions on receive memory buffer addresses. this is desirable in situations where the receive buffer was allocated by higher layers in the networking software stack, as these higher layers may have no knowledge of a specific device's buffer alignment requirements. although alignment is completely unrestricted, it is highly recommended that software allocate receive buffers on cache-line boundaries. 37.5.5.3 receive descriptor format a receive descriptor is a data structure that contains the receive data buffer address and fields for hardware to store packet information. refer to figure 37-6 , where the shaded areas indicate fields that are modified by hardware upon packet reception. figure 37-6. receive descriptor (rdesc) layout 63 48 47 40 39 32 31 16 15 0 0 buffer address[63:0] 8 special errors status packet checksum ? length ? the checksum indicated here is the unadjusted ?16 bit ones complement? of the packet. a software assist may be required to back out appropriate info rmation prior to sending it up to upper software layers. the packet checksum is always reported in the first descriptor (even in the case of multi- descriptor packets). ? the packet checksum is reported in little endian format
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1356 order number: 320066-003us upon receipt of a packet for this device, hardware stores the packet data into the indicated buffer and writes the length, packet checksum, status, errors, and status fields. length covers the data written to a receive buffer including crc bytes (if any). software must read multiple descriptors to determine the complete length for packets that span multiple receive buffers. for standard 802.3 packets (non-vlan) the packet checksum is by default computed over the entire packet from the first byte of the da through the last byte of the crc, including the ethernet and ip headers. software may modify the starting offset for the packet checksum calculation, refer to section 37.6.4.13, ?rxcsum ? receive checksum control register? for details. to verify the tcp checksum using the packet checksum, software must adjust the packet checksum value to back out the bytes that are not part of the true tcp checksum. status information indicates whether the descriptor has been used and whether the referenced buffer is the last one for the packet. refer to figure 37-7 for the layout of the status field. error status information is shown in figure 37-8 . packets that exceed the receive buffer size span multiple receive buffers. eop indicates whether this is the last buffer for an incoming packet. dd indicates whether hardware is done with the descriptor. when set along with eop, the received packet is complete in main memory. software can determine buffer usage by setting the status byte to 0 before making the descriptor available to hardware, and checking it for non-zero content at a later time. for multi-descriptor packets, packet status is provided in the final descriptor of the packet (eop set). if eop is not set for a descriptor, only the address, length, and dd bits are valid. the vp field indicates whether the incoming packet's type matches vet (i.e., if the packet is a vlan (802.1q) type). it will be set if the packet type matches vet and ctrl.vme is set. for a further description of 802.1q vlans please see ?802.1q vlan support? on page 1400 . when the ignore checksum indication bit is deasserted (ixsm = 0), the ipcs and tcpcs bits indicate whether the hardware performed the ipv4 or tcp/udp checksum(s) on the received packet, respectively. pass/fail information regarding the checksum is indicated in the status bits as described below for ipe & tcpe. when ixsm = 1, software should ignore the ipcs and tcpcs bits. figure 37-7. receive status (rdesc.status) layout 76543210 pif ipcs tcpcs rsvd vp ixsm eop dd pif: passed in-exact filter ipcs: ipv4 checksum calculated on packet tcpcs: tcp checksum calculated on packet rsvd: reserved vp: packet is 802.1q (matched vet mmr) ixsm: ignore checksum indication eop: end of packet dd: descriptor done
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1357 intel ? ep80579 integrated processor refer to table 37-1, ?supported receive checksum capabilities? on page 1363 for a description of supported packet types for receive checksum off loading. unsupported packet types will either have the ixsm bit set, or they will not have the ipcs or tcpcs bits set. ipv6 packets will not have the ipcs bit set, but may have the tcpcs bit set if the tcp or udp packet was recognized by the ep80579?s gbe. hardware supplies the pif field to expedite software processing of packets. software must examine any packet with pif set to determine whether to accept the packet. if pif is clear, then the packet is known to be for this station, so software need not look at the packet contents. packets passing only the multicast vector will have pif set. most error information appears only when the store-bad-packet bit (rctl.sbp) is set and a bad packet is received. refer to figure 37-8 below for a definition of the possible errors and their bit positions. the ip and tcp checksum error bits from figure 37-8 are valid only when the ipv4 or tcp/udp checksum(s) is performed on the received packet as indicated via ipcs and tcpcs. these, along with the other error bits, are valid only when the eop and dd bit are set in the descriptor. note: receive checksum errors have no affect on packet filtering. if receive checksum off loading is disabled ( rxcsum .ipofl & rxcsum .tuofl), the ipe and tcpe bits will be 0. in gmii/mii mode, the rxe bit indicates that a data error occurred during the packet reception that has been detected by the phy. this generally corresponds to signal errors occurring during the packet reception. this bit is valid only when the eop and dd bits are set and will not be set in descriptors unless rctl.sbp (store-bad-packets) is set. crc and alignment errors are indicated via the ce bit. software may distinguish between these errors by monitoring the respective statistics registers. hardware stores additional information in the receive descriptor for 802.1q packets. if the packet type is 802.1q (determined when a packet matches vet and rctl.vme = 1), then the special field records the vlan information and the four byte vlan information is stripped from the packet data storage. otherwise, the special field contains 0x0000. figure 37-8. receive errors (rdesc.errors) layout 76543210 rxe ipe tcpe cxe rsvd rsvd rsvd ce rxe: rx data error ipe: ipv4 checksum error tcpe: tcp/udp checksum error cxe: carrier extension error (reserved) rsvd: reserved rsvd: reserved rsvd: reserved ce: crc error or alignment error
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1358 order number: 320066-003us 37.5.5.4 receive descriptor fetching the descriptor fetching strategy has been designed for the ep80579?s gbe to support larger bursts across the internal bus. this is made possible by increasing the number of gbe hardware receive descriptors (from 8 to 64), and by modifying the fetch algorithm. the algorithm attempts to make the best use of the internal bus by fetching a cache- line (or more) of descriptors with each burst. the following paragraphs briefly describe the descriptor fetch algorithm and the software control provided. when the descriptor buffer is empty, a fetch will happen as soon as any descriptors are made available (host writes to the tail pointer). when the descriptor buffer is nearly empty (as defined by rxdctl.pthresh) a prefetch will be performed whenever enough valid descriptors (as defined by rxdctl.hthresh) are available in host memory and no other internal bus activity of greater priority is pending (descriptor fetches, descriptor write-backs, or packet data transfers). when the number of descriptors in host memory is greater than the available descriptor buffer storage, the gbe may elect to perform a fetch which is not a multiple of cache line size. the hardware performs this non-aligned fetch if doing so will result in the next descriptor fetch being aligned on a cache line boundary. this allows the descriptor fetch mechanism to be most efficient in the cases where it has fallen behind software. note: the gbe never fetches descriptors beyond the descriptor tail pointer. 37.5.5.5 receive descriptor write-back processors have cache line sizes that are larger than the receive descriptor size (16 bytes). consequently, writing back descriptor information for each received packet would cause expensive partial cache line updates. two mechanisms minimize the occurrence of partial line write backs: receive descriptor packing and null descriptor padding. 37.5.5.5.1 receive descriptor packing to maximize memory efficiency, receive descriptors are ?packed? together and written as a cache line whenever possible. descriptors accumulate and are opportunistically written out in cacheline-oriented chunks. used descriptors will also be explicitly written out under the following scenarios: ? rxdctl.wthresh descriptors have been used (the specified max threshold of unwritten used descriptors has been reached) ? the last descriptors of the allocated descriptor ring have been used (to allow the hardware to re-align to the descriptor ring start) ? a receive timer expires (radv or rdtr) figure 37-9. special descriptor field layout 802.1q packets 15 thru 8 7 thru 5 4 3 thru 0 vlan[7..0] pri cfi vlan[11:8] all other packets 15 8 7 0 00 00
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1359 intel ? ep80579 integrated processor ? explicit software flush (rdtr.fpd) when the numbers of descriptors specified by rxdctl.wthresh have been used, they are written back, regardless of cacheline alignment it is therefore recommended that wthresh be a multiple of cacheline size. when a receive timer (radv or rdtr) expires, all used descriptors are forced to be written back prior to initiating the interrupt, for consistency. software may explicitly flush accumulated descriptors by writing the rdtr register with the high order bit (fpd) set. 37.5.5.5.2 null descriptor padding hardware stores no data in descriptors with a null data address. software can make use of this property to cause the first condition under receive descriptor packing to occur early. hardware writes back null descriptors with the dd bit set in the status byte and all other bits unchanged. 37.5.5.6 receive descriptor queue structure figure 37-10 shows the structure of the receive descriptor ring. hardware maintains a circular queue of descriptors and writes back used descriptors just prior to advancing the head pointer. head and tail pointers wrap back to base when ?size? descriptors have been processed. software adds receive descriptors by advancin g the tail pointer to refer to the address of the entry just beyond the last valid descriptor. this is accomplished by writing the descriptor tail register with the offset of the entry beyond the last valid descriptor. the hardware adjusts its internal tail pointer accordingly. as packets arrive, they are stored figure 37-10.receive descriptor ring structure circular buffer head base + size base receive queue tail
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1360 order number: 320066-003us in memory and the head pointer is incremented by hardware. when the head pointer is equal to the tail pointer, the queue is empty. hardware stops storing packets in system memory until software advances the tail pointer, making more receive buffers available. the receive descriptor head and tail pointe rs reference 16-byte blocks of memory. shaded boxes in the figure represent descriptors that have stored incoming packets but have not yet been recognized by software. so ftware can determine if a receive buffer is valid by reading descriptors in memory. any descriptor with a non-zero status byte has been processed by the hardware, and is ready to be handled by the software. note: the head pointer points to the next descriptor that will be written back. at the completion of the descriptor write-back operation, this pointer is incremented by the number of descriptors written back. hardware ?owns? all descriptors between the head and tail. any descriptor not in this range is owned by software. the receive descriptor ring is described by the following registers: the receive descriptor base address high register and the receive descriptor base address low register (rdbah and rdbal) - these registers indicate the start of the descriptor ring buffer; this 64-bit address is aligned on a 16b boundary. hardware ignores the lower 4 bits. receive descriptor length register (rdlen) - this register determines the number of bytes allocated to the circular buffer. this value must be a multiple of 128. since each descriptor is 16 bytes in length, the total number of receive descriptors is always a multiple of 8. receive descriptor head register (rdh) - this register holds a value that is an offset from the base, and indicates the in-progress descriptor. there can be up to 64k descriptors in the circular buffer. hardware maintains a shadow copy that includes those descriptors completed but not yet stored in memory. receive descriptor tail register (rdt) - this register holds a value that is an offset from the base, and identifies the location beyond the last descriptor hardware can process. this is the location where software writes the first new descriptor. if software statically allocates buffers, and uses memory read to check for completed descriptors, it simply has to zero the status byte in the descriptor to make it ready for reuse by hardware. this is not a hardware requirement (moving the hardware tail pointer is), but is necessary for performing an in-memory scan. 37.5.5.7 receive interrupts the following sections indicate the presence of new packets. 37.5.5.7.1 receive timer (icr.rxt0) due to absolute timer (radv) ? when a packet is received the absolute timer starts counting down. when it reaches 0 it generates an interrupt and resets itself. it is also reset if an interrupt is generated due to the packet delay timer expiration. the absolute timer is disabled if radv is 0. to use the absolute timer only the rdtr register must be set to an equal or greater value than radv. 37.5.5.7.2 receive timer (icr.rxt0) due to packet delay timer (rdtr) ? when a packet is received the packet delay timer starts counting down. every time an additional packet is received the packet delay timer is reset to its starting value. when it reaches 0 it generates an interrupt and resets itself. it is also reset if an interrupt is generated due to the absolute timer expiration. ? when rdtr is 0 interrupts are immediate. if radv is non-0, and rdtr is equal to or higher than radv then the packet delay timer will never generate any interrupts as the absolute timer will always generate them first.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1361 intel ? ep80579 integrated processor ? writing rdtr with its high order bit 1 forc es an explicit flush of any partial cache lines worth of consumed descriptors. hardware writes all used descriptors to memory and updates the globally visible value of the rdh head pointer. figure 37-11 further describes the packet delay timer operation, in general. figure 37-12 , figure 37-13 , and figure 37-14 illustrate the uses of the two timers. figure 37-11.packet delay timer operation illustrated with a state diagram running packet received & xferred to host mem packet received & xfer to host memory generate int timer expires other receive timer interrupt initial state idle restart count restart count figure 37-12.case a: using only an absolute timer absolute timer value pkt1 pkt2 pkt3 pkt4 interrupt generated due to pkt #1 to use only the absolute timer the rdtr must be set to a value greater than or equal to the radv.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1362 order number: 320066-003us case c in figure 37-14 shows a scenario in which the packet timer expires even though a packet was being transferred to the host memory. illustrating the fact that the packet timer is re-started only after a packet is transferred to host memory. 37.5.5.7.3 small receive packet detect (icr.srpd) the small packet receive detect timer is independent of the other timers. it will generate a receive interrupt when small-packet detection is enabled ( rsrpd is set with a non-zero value) and a packet of size less than or equal to rsrpd .size has been transferred into the host memory. when comparing the size the headers and crc are included (if crc stripping is not enabled). crc and vlan headers are not included if they have been stripped. receiving a small packet does not clear the absolute or packet delay timers, so one packet may generate two receive interrupts, one due to the small packet reception and one due to a timer expiration. figure 37-13.case b: using an absolute timer in conjunction with the packet timer absolute timer value absolute timer value packet timer expires interrupt generated. absolute timer reset. pkt1 pkt2 pkt3 pkt4 pkt5 ?. interrupt generated (due to pkt #4) as absolute timer expires. packet delay timer disabled till nex t packet is received and transferred to host memory figure 37-14.case c: packet timer expires even though a packet was being transferred to the host memory. absolute timer value absolute timer value packet delay timer expires (due to pkt #3); both timers set to idle pkt1 pkt2 pkt3 pkt4 pkt5 ?. interrupt generated (due to pkt #4) as absolute timer expires packet delay timer disabled till ne xt packet is transferred to host memor y
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1363 intel ? ep80579 integrated processor 37.5.5.7.4 receive descriptor minimum threshold (icr.rxdmt) the minimum descriptor threshold helps avoid descriptor under-run by generating an interrupt when the number of free descriptors becomes equal to the minimum. it is measured as a fraction of the receive descriptor ring size. this interrupt would stop and re-initialize all of the active delayed receives interrupt timers until a new packet is observed. 37.5.5.7.5 receiver fifo overrun (icr.rxo) fifo overrun occurs when hardware attempts to write a byte to a full fifo. an overrun could indicate that software has not updated the tail pointer to provide enough descriptors/buffers, or that the internal bus is too slow draining the receive fifo. incoming packets that overrun the fifo are dropped and do not affect future packet reception. this interrupt would stop and re-initialize all of the active delayed receive interrupts. 37.5.5.8 receive packet checksum off loading the gbe supports the off loading of three receive checksum calculations: the packet checksum, the ipv4 header checksum, and the tcp/udp checksum. ethernet ii and ethernet snap frame types are supported. the packet checksum is the one's complement of the receive packet, starting from the byte indicated by rxcsum.pcss (0 corresponds to the first byte of the packet), after stripping. for example, for an ethernet ii frame encapsulated as an 802.3ac vlan packet and with rxcsum.pcss set to 14, the packet checksum would include the entire encapsulated frame, excluding the 14-byte ethernet header (da, sa, type and length) and the 4-byte q-tag. the packet checksum will not include the ethernet crc if the rctl.secrc bit is set. software must make the required offsetting computation (to back out the bytes that should not have been included and to include the pseudo-header) prior to comparing the packet checksum against the tcp checksum stored in the packet. for supported packet/frame types, the entire checksum calculation may be off-loaded to the gbe. if rxcsum.ipofld is set to one, the gbe will calculate the ipv4 checksum and indicate a pass/fail indication to software via the ipv4 checksum error bit (rdesc.ipe) in the error field of the receive descriptor. similarly, if rxcsum.tuofld is set to one, the gbe will calculate the tcp or udp checksum and indicate a pass/fail condition to software via the tcp/udp checksum error bit (rdesc.tcpe). these error bits are valid when the respective status bits indicate the checksum was calculated for the packet (rdesc.ipcs and rdesc.tcpcs respectively). if neither rxcsum.ipofld nor rxcsum.tuofld are set, the checksum error bits (ipe & tcpe) will be 0 for all packets. table 37-1. supported receive checksum capabilities (sheet 1 of 2) packet type hw ip checksum calculation hw tcp/udp checksum calculation ipv4 packets yes yes ipv6 packets n/a yes ipv6 packet with next header options: ? hop-by-hop options ? destinations options ?routing ?fragment n/a n/a n/a n/a yes yes yes no
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1364 order number: 320066-003us ta b l e 3 7 - 1 gives general details about what packets are processed. in more detail, the packets are passed through a series of filters to determine if a receive checksum is calculated. 37.5.5.8.1 mac address filter this filter checks the mac destination address to be sure it is valid (e.g. da match, broadcast, multicast, etc.). the receive configuration settings determine which mac addresses are accepted. see the various receive control configuration registers such as rctl (rctl.upe, rctl.mpe, rctl.bam), mta[127:0], ral, and rah. 37.5.5.8.2 snap/vlan filter this filter checks the next headers looking for an ip header. it is capable of decoding ethernet ii, ethernet snap, and ieee 802.3ac headers. it will skip past any of these intermediate headers and will look for the ip header. the receive configuration settings determine which next headers are accepted. see the various receive control configuration registers such as rctl (rctl.vfe), vet, and vfta[127:0]. 37.5.5.8.3 ipv4 filter this filter checks for valid ipv4 headers. the version field is checked for a correct value (i.e. 4). ipv4 headers are accepted if they are any size greater than or equal to 5 (dwords). if the ipv4 header is properly decoded, the ip checksum will be checked for validity. the rxcsum.ipofl bit must be set for this filter to pass. 37.5.5.8.4 ipv6 filter this filter checks for valid ipv6 headers, which are a fixed size and have no checksum. the ipv6 extension headers accepted are: hop-by-hop, destination options, and routing. the maximum size next header accepted is 16 dwords (64 bytes). all of the ipv6 extension headers supported by the gbe have the same header structure, as shown in figure 37-15 . ipv4 tunnels: ? ipv4 packet in an ipv4 tunnel ? ipv6 packet in an ipv4 tunnel no yes (ipv4) no yes * ipv6 tunnels: ? ipv4 packet in an ipv6 tunnel ? ipv6 packet in an ipv6 tunnel no no no no packet is an ipv4 fragment yes no packet is greater than 1552 bytes ?lpe=1 yes yes packet has 802.3ac tag yes yes ipv4 packet has ip options ? ip header is longer than 20 bytes yes yes packet has tcp or udp options yes yes ip header's protocol field contains a protocol # other than tcp or udp. yes no * the ipv6 header portion can include supported extension headers as described in the ipv6 filter section. table 37-1. supported receive checksum capabilities (sheet 2 of 2) figure 37-15.ipv6 extension header structure byte 0 byte 1 byte 2 byte 3
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1365 intel ? ep80579 integrated processor next header is a value that identifies the header type. the supported ipv6 next headers values are: ? hop-by-hop = 00h ? destination options = 3ch ?routing = 2bh hdr ext len is the 8 byte count of the header length, not including the first 8 bytes. for example, a value of 3 means that the total header size including the next header and hdr ext len fields is 32 bytes (8 + 3*8). 37.5.5.8.5 udp/tcp filter this filter checks for a valid udp or tcp header. the prototype next header values are 11h and 06h, respectively. the rxcsum.tuofl bit must be set for this filter to pass. 37.5.6 packet transmission output packets are made up of pointer-length pairs constituting a descriptor chain (so called descriptor based transmission). software forms transmit packets by assembling the list of pointer-length pairs, storing this information in the transmit descriptor, and then updating the gbe hardware transmit tail pointer to the descriptor. the transmit descriptor and buffers are stored in host memory. hardware typically transmits the packet only after it has completely fetched all packet data from host memory and deposited it into the tx portion of the packet buffer. this permits tcp or udp checksum computation, and avoids problems with internal bus under-runs. another transmit feature of the gbe is tcp segmentation. the hardware has the capability to perform packet segmentation on large data buffers off-loaded from the nos. this feature is discussed in detail in ?tcp segmentation? on page 1380 . 37.5.6.1 transmit data storage data are stored in buffers pointed to by the descriptors. alignment of data is on an arbitrary byte boundary with the maximum size per descriptor limited only to the maximum allowed packet size (16288 bytes 1 ). a packet typically consists of two (or more) descriptors, one (or more) for the header and one for the actual data. some software implementations copy the header(s) and packet data into one buffer and use only one descriptor per transmitted packet. 37.5.6.2 transmit descriptor formats the ep80579?s gbe has an expanded transmit descriptor format in that additional descriptor types have been introduced. the intent of the descriptor type field is to provide an extensible interface to the gbe descriptor mechanisms while maintaining a great deal of compatibility with the existing descriptor format that the 82542 used. next header hdr ext len figure 37-15.ipv6 extension header structure 1. this value is based on the default packet buffer allocation of 16kb transmit; 48kb receive. the maximum allowable transmit packet size is the transmit allocation minus 96 bytes with an upper limit of 24kb due to receive synchronization limitations.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1366 order number: 320066-003us the original (82542 compatible) descriptor will be referred to as the ?legacy? descriptor format and is described in ?legacy transmit descriptor format? on page 1366 . the two new descriptor types are collectively referred to as extended descriptors. one of the new descriptor types is quite similar to the legacy descriptor in that it points to a block of packet data. this descriptor type is called the tcp/ip data descriptor and is offered as a replacement for the legacy descriptor since it offers access to new off loading capabilities. the other new descriptor type is fundamentally different as it does not point to packet data. it merely contains control information which are loaded into registers of the gbe and affect the processing of future packets. the following paragraphs describe the three descriptor formats. note: the extended descriptor types are accessed by setting the tdesc.dext bit to 1. if this bit is set, the tdesc.dtyp field is examined to control the interpretation of the remaining bits of the descriptor. figure 37-16 shows the generic layout for all extended descriptors. fields marked as nr are not reserved for any particular function and are defined on a per-descriptor type basis. notice that the dext and dtyp fields are non- contiguous in order to accommodate legacy mode operation. for legacy mode operation, bit 29 is set to 0 and the descriptor is defined as described in ?legacy transmit descriptor format? on page 1366 . 37.5.6.3 legacy transmit descriptor format to select legacy (82542 compatible) mode operation, bit 29 (tdesc.dext) should be set to 0. in this case, the descriptor format is defined as shown in figure 37-17 . address and length must be supplied by software. bits in the command byte are optional, as are the cso, and css fields. length (tdesc.length) specifies the length in bytes to be fetched from the buffer address provided. the maximum length associated with any single legacy descriptor is 16288 bytes. although a buffer as short as one byte is allowed, the total length of the packet, before padding and crc insertion, must be at least 17 bytes. note: the maximum allowable packet size for transmits changes based on the value written to the packet buffer allocation register, whose settings can modify the size of the transmit fifo. descriptor length(s) may be further limited by the size of the transmit fifo. due to the need to support optional checksum calculation & insertion, all buffers comprising a single packet must be able to be stored simultaneously in the transmit fifo. for any individual packet, the sum of the individual descriptor lengths must be at least 80 bytes less than the allocated size of the transmit fifo. figure 37-16.transmit descriptor (tdesc) layout 63 30 29 28 24 23 20 19 0 0 not-reserved[63:0] 8 nr dext nr dtyp nr figure 37-17.legacy transmit descriptor (tdesc) layout 63 48 47 40 39 36 35 32 31 24 23 16 15 0 0 buffer address[63:0] 8 special css rsvd status cmd cso length
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1367 intel ? ep80579 integrated processor a checksum offset (tdesc.cso) field indicate s where to insert a tcp checksum if this mode is enabled, relative to the start of the packet. a checksum start (tdesc.css) field indicates where to begin computing the checksum. both cso and css are in units of bytes. these must both be in the range of data provided to the device in the descriptor. this means for short packets which are padded by software, css and cso must be in the range of the unpadded data length, not the eventual padded length (64 bytes). hardware will not add the 802.1q ethertype or the vlan field following the 802.1q ethertype to the checksum. so for vlan packets, software can compute the values to back out only on the encapsulated packet rather than on the added fields. note: although the ep80579?s gbe can be programmed to calculate and insert tcp checksum using the legacy descriptor format as described above, it is recommended that software use the newer tcp/ip context transmit descriptor format. this newer descriptor format allows the hardware to calculate both the ip and tcp checksums for outgoing packets. refer to ?transmit checksum off loading? on page 1379 for more information about how the new descriptor format can be used to accomplish this task. the cmd byte stores the applicable command and has the fields shown in figure 37-18 . eop indicates the last descriptor making up the packet when asserted. one or many descriptors can be used to form a packet. hardware inserts a checksum at the offset indicated by the cso field if the insert checks um bit (ic) is set. checksum calculations are for the entire packet starting at the byte indicated by the css field. a value of 0 corresponds to the first byte in the packet. hardware ignores ic, and cso unless eop is set. css must be set in the first descriptor for a packet. in addition, ic is ignored if cso or css are out of range. this occurs if (css >= length) or (cso >= length - 1). software must compute an offsetting entry-to back out the bytes of the header that should not be included in the tcp checksum-and store it in the position where the hardware computed checksum is to be inserted. tdesc.cmd.rs tells the hardware to report the status information. this is used by software that does in-memory checks of the transmit descriptors to determine which ones are done. for example, if software queues up 10 packets to transmit, it can set the rs bit in the last descriptor of the last packet. if software maintains a list of descriptors with the rs bit set, it can look at them to determine if all packets up to (and including) the one with the rs bit set have been buffered in the output fifo. this is done by looking at the status byte and checking the descriptor done (dd) bit. if dd is set, the descriptor has been processed. refer to figure 37-19 on page 1368 for the layout of the status field. figure 37-18.transmit command (tdesc.cmd) layout 76543210 ide vle dext rps rs ic ifcs eop ide: interrupt delay enable vle: vlan packet enable dext: descriptor extension (0 for legacy mode) rps: report packet sent rs: report status ic: insert checksum ifcs: insert fcs eop: end of packet
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1368 order number: 320066-003us note: descriptors with the null address (0), or zero length, transfer no data. if they have the rs bit in the command byte set, then the dd field in the status word is written after hardware processes them. hard ware only sets the dd bit for descriptors with rs set. note: null descriptors are intended for padding descriptor queues, in case a specific alignment of descriptors comprising a packet are desired. null transmit descriptors should not be used to convey any meaningful command information (such as eop); they are consumed with no processing other than status reporting (if requested). note: hardware is considered ?done processing? a descriptor when any data specified in the descriptor has been completely fetched and loaded in the transmit fifo. note: vle, ifcs, and ic are qualified by eop. in other words, hardware interprets these bits only when eop is set. ide activates a transmit interrupt delay timer. hardware loads a countdown register when it writes back a transmit descriptor that has rs and ide set. the value loaded comes from transmit interrupt delay value register (tidv.idv). when the count reaches 0, a transmit interrupt occurs if transmit descriptor write-back interrupts (icr.txdw) are enabled. hardware always loads the transmit interrupt counter whenever it processes a descriptor with ide set even if it is already counting down due to a previous descriptor. if hardware encounters a descriptor that has rs set, but not ide, it generates an interrupt immediately after writing back the descriptor and the interrupt delay timer is cleared. note: although the transmit interrupt may be de layed, the descriptor write-back requested by setting the rs bit is performed without de lay unless descriptor write-back bursting is enabled. see section 37.6.5.10, ?txdctl ? transmit descriptor control register? . vle indicates that the packet is a vlan or isl packet (i.e. that the hardware should add the vlan ethertype and an 802.1q vlan tag to the packet). note: if the vle bit is set, the ctrl.vme bit should also be set to enable vlan tag insertion. if the ctrl.vme bit is not set, the device will not insert vlan tags on outgoing packets, but may instead insert isl headers. three bits provide transmit status. these are only present in cases where rs is set in the command. dd indicates that the descriptor is done and is written back after the descriptor has been processed. the bits ec and lc indicate collision behavior when in half-duplex mode. they have no meaning when in full-duplex mode. table 37-2. vlan tag insertion decision table when vlan mode enabled (ctrl.vme=1) vle action 0 send generic ethernet packet. ifcs controls insertion of fcs in normal ethernet packets. 1 send 802.1q packet; the ethernet type field comes from the vet register and the vlan data comes from the special field of the tx descriptor; hardware always appends the fcs/crc. figure 37-19.transmit status layout (tdesc.status) 3210 tu lc ec dd tu: transmit underrun lc: late collision ec: excess collisions
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1369 intel ? ep80579 integrated processor the special field is used to provide the 802.1q/802.1ac tagging information. the special field is ignored if the vle bit is 0 or if the eop bit is 0. 37.5.6.4 tcp/ip context transmit descriptor format the tcp/ip context transmit descriptor provides access to the enhanced checksum off load and tcp segmentation facilities available in the gbe. these features allow tcp and udp packet types to be handled more efficiently by performing additional work in hardware, thus reducing the software overhead associated with preparing these packets for transmission. the tcp/ip context transmit descriptor is called a ?context? descriptor for a reason. a context descriptor differs from a data descriptor as it does not point to packet data. instead, this descriptor provides access to two, gbe hardware contexts that support the transmit checksum off loading and the segmentation features of the ep80579?s gbe. a ?context? refers to a set of registers loaded or unloaded as a group to provide a particular function. only one context is active at any given time. 37.5.6.4.1 overview of gbe hardware ?contexts? the previous section mentions access to two, separate gbe hardware contexts. there are actually three such contexts corresponding to legacy mode, ?normal? mode, and segmentation mode. the first context (legacy) is an implied context as it is not explicitly specified with a context descriptor. this context is constructed by the device from the first and last descriptors of a legacy transmit and from some internal constants. this context then mimics the behavior of the legacy (82542) device. this is completely transparent to the user and is included here for clarification only. the other two contexts are explicit and directly accessible via the tcp/ip context transmit descriptor. one context is used to control the checksum off loading feature for normal packet transmission. the second context is used to control the packet segmentation capabilities of the device. the tse bit selects which context will be updated. a tcp/ip context transmit descriptor with tse=0 will update the normal (checksum off loading only) context. conversely, the segmentation context is updated when tse=1. refer to figure 37-22 on page 1371 for details on all of the tdesc.tucmd fields, including tse. the device automatically selects the appropriate context to use based on the current packet transmission: legacy, normal, or segmentation. note: while the architecture supports arbitrary ordering rules for the various descriptors, there are restrictions. the context descriptors should not occur in the middle of a packet (or of a segmentation) and data descr iptors of different packet types (legacy, normal, or segmentation) should not be intermingled except at the packet (or segmentation) level. all three contexts control calculation and insertion of up to two checksums. this portion of the context is referred to as the checksum context. in addition to a checksum context, the segmentation context includes information specific to the segmentation capability. this additional information includes the total payload for the message (tdesc.paylen), the total size of the header (tdesc.hdrlen), the amount of payload dd: descriptor done figure 37-19.transmit status layout (tdesc.status) figure 37-20.transmit special field layout (tdesc.special) 15 13 12 11 0 pri cfi vlan
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1370 order number: 320066-003us data that should be included in each packet (tdesc.mss), and information about what type of protocol (tcp, ipv4, ipv6, etc.) is used. this information is specific to the segmentation capability and is therefore ignored for context descriptors that do not have the tse bit set. due to the fact that there are dedicated resources in the gbe hardware for both the normal and segmentation contexts, these contexts will remain constant until they are modified by another context descriptor. this means that a context can be used for multiple packets unless a new context is loaded prior to each new packet. depending on the environment, it may be completely unnecessary to load a new context for each packet. for example, if most traffic generated from a given node is standard tcp frames, this context could be setup once and used for many frames. only when some other frame type is required would a new context need to be loaded by software. after the ?non-standard? frame is transmitted, the ?standard? context would be setup once more by software. this method avoids the ?extra descriptor per packet? penalty for most frames. the penalty can be eliminated altogether if software elects to use tcp/ip checksum off loading only for a single frame type, and thus performing those operations in software for other frame types. a segmentation context similarly describes parameters which are setup once and used for many frames. since a segmentation operation results in the generation of multiple frames, the context parameters such as checksum generation are applied to all frames generated. unlike the ?normal? tcp/ip context, a segmentation context cannot be re- used for multiple tcp messages, however, a new segmentation context is required for each segmentation operation. 37.5.6.4.2 tcp/ip context descriptor layout note: the tcp/ip context transmit descriptor does not transfer any packet data. it merely prepares the checksum and segmentation hardware for the tcp/ip data descriptors that follow. to select the tcp/ip context transmit descriptor format, shown below in figure 37-21 , bit 29 (tdesc.dext) must be set to 1 and tdesc.dtyp must be set to ?0000?. the first qword of this descriptor type contains parameters used to calculate the two checksums which may be off-loaded. tdesc.ipcss, tdesc.ipcso, and tdesc.ipcse specify the start, offset, and ending byte for the ip checksum off-load feature. similarly, tdesc.tucss, tdesc.tucso, tdesc.tucse specify the same parameters for the tcp or udp checksum. setting either cse field to 0 indicates the given ch ecksum will cover from css to the end of packet. while the names imply particular packet types, the mechanisms are generic. note: when setting the tcp segmentation context, ipcss and tucss are used to indicate the start of the ip and tcp headers respectively, and must be set even if checksum insertion is not desired. in certain situations, software may need to calculate a partial checksum (the tcp pseudo-header for instance) to include bytes which are not contained within the range of start and end. if this is the case, this partial checksum should be placed in the figure 37-21.tcp/ip context transmit descriptor (tdesc) - (type = 0000) 63 48 47 40 39 32 31 16 15 8 7 0 0 tucse tucso tucss ipcse ipcso ipcss 8 mss hdrlen rsvd tustatu s tucmd dtyp paylen 63 48 47 40 39 36 35 32 31 24 23 20 19 0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1371 intel ? ep80579 integrated processor packet data buffer, at the appropriate offset for the checksum. if no partial checksum is required, software must write a value of zero at this offset. refer to the ?transmit checksum off loading? on page 1379 for additional details. the second qword of this descriptor primarily contains information to support the tcp segmentation feature. a number of the fields are ignored if the tcp segmentation enable bit indicates that the descriptor does not refer to the tcp segmentation context (tse=0). mss controls the maximum segment size. this specifies the maximum tcp or udp payload ?segment? sent per frame, not including any header. the total length of each frame (or ?section?) sent by the tcp segmentation mechanism (excluding 802.3ac tagging and ethernet crc) will be mss bytes + hrdlen. the one exception is the last packet of a tcp segmentation context which will (typically) be shorter than ?mss + hdrlen?. this field is ignored if tse is not set. hdrlen is used to specify the length (in bytes) of the header to be used for each frame (or ?section?) of a tcp segmentation operation. the first hdrlen bytes fetched from data descriptor(s) will be stored internally and used as a prototype header for each section, and will be prepended to each payload segment to form individual frames. for udp packets this will normally be equal to ?udp checksum offset + 2?. for tcp packets it will normally be equal to ?tcp checksum offset + 4 + tcp header option bytes?. this field is ignored if tdesc.tse is not set. maximum limits for the hdrlen and mss fields are dictated by the length variables. however, there is a further restriction that the for any tcp segmentation operation, the hardware must be capable of storing a complete framed fragment (completely-built frames) in the transmit fifo prior to transmission. therefore, the size of the tx packet buffer must be greater than or equal to ((mss + hdrlen) x number of frames formed for this fragment). the quantity (hdrlen x number of frames) should be set by software in the tcp segmentation pad and minimum threshold register (tspmt.tspbp) to prevent packet buffer overflow. the packet payload length field (tdesc.payle n) is the total number of payload bytes for this tcp segmentation off load context (i.e. the total number of payload bytes that could be distributed across multiple frames after tcp segmentation is performed). following the fetch of the prototype header, paylen specifies the length of data that will be fetched next from data descriptor(s). this field is also used to determine when ?last-frame? processing needs to be performed. typically, a new data descriptor is used to denote the start of the payload data buffer(s), but this is not required. paylen specification should not include any header bytes. there is no restriction on the overall paylen specification with respect to the tr ansmit fifo size, once the mss and hdrlen specifications are legal. this field is ignored if tdesc.tse is not set. refer to ?tcp segmentation? on page 1380 for details on the tcp segmentation off-loading feature. setting the descriptor type (tdesc.dtyp) field to 0000 identifies this descriptor as a tcp/ip context transmit descriptor. the command field (tdesc.tucmd) provides options that control the checksum off- loading and tcp segmentation features, along with some of the generic descriptor processing functions. figure 37-22 shows the bit definitions for the tdesc.tucmd field. the ide, dext, and rs bits are valid regardless of the state of tse. all other bits are ignored if tse=0. figure 37-22.tcp/ip context transmit descriptor command field (tdesc.tucmd) 76543210 ide rsvd dext rsvd rs tse ip tcp ide: interrupt delay enable
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1372 order number: 320066-003us the tcp bit identifies the packet as either tcp or udp (non-tcp). this effects the processing of the header information. the ip bit is used to indicate what type of ip packet is used in the segmentation process. this is necessary for the ep80579?s gbe to know where the ip payload length field is located. this does not override the checksum insertion bit, tdesc.popts ixsm bit. the ip bit must only be set for ipv4 packets and cleared for ipv6 packets. the tcp segmentation feature also provides access to a generic block send function and may be useful for performing ?segmentation offload? in which the header information is constant. by clearing both the tcp and ip bits, a block of data may be broken down into frames of a given size, a constant, arbitrary length header may be prepended to each frame, and two checksums optionally added. tse indicates that this descriptor is setting the tcp segmentation context. if this bit is not set, the checksum off loading context for normal (non-?tcp segmentation?) packets is written. when a descriptor of this type is processed, the device will immediately update the context in question (tcp segmentation or checksum off loading) with values from the descriptor. this means that if any normal packets or tcp segmentation packet are in progress (a descriptor with eop set has not been received for the given context) the results will likely be undesirable. rs tells the hardware to report the status information for this descriptor. because this descriptor does not transmit data, only the dd bit in the status word will be valid. refer to figure 37-23 for the layout of the status field. the reserved bits are reserved values and are ignored, but if written should be set to 0 for future compatibility. the dext bit identifies this descriptor as one of the extended descriptor types and must be set to 1. ide activates the transmit interrupt delay timer. hardware loads a countdown register when it writes back a transmit descriptor that has the rs bit and the ide bit set. the value loaded comes from the transmit interrupt delay value register (tidv.idv). when the count reaches 0, a transmit interrupt occurs. hardware always loads the transmit interrupt counter whenever it processes a descriptor with ide set even if it is already rsvd: reserved dext: descriptor extension (must be 1 for this descriptor type) rsvd: reserved rs: report status tse: tcp segmentation enable ip: ip packet type (ipv4=1, ipv6=0) tcp: packet type (tcp=1,udp=0) figure 37-22.tcp/ip context transmit descriptor command field (tdesc.tucmd) figure 37-23.tcp/ip context transmit descriptor status (tdesc.tustatus) 3210 rsvd dd rsvd: reserved dd: descriptor done
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1373 intel ? ep80579 integrated processor counting down due to a previous descriptor. if hardware encounters a descriptor that has rs set, but not ide, it generates an interrupt immediately after writing back the descriptor and the interrupt delay timer is cleared. four bits are reserved to provide transmit status, although only one is currently assigned for this specific descriptor type. the status word will only be written back to host memory in cases where the rs is set in the command. dd indicates that the descriptor is done and is written back after the descriptor has been processed. 37.5.6.5 tcp/ip data descriptor format the tcp/ip data descriptor is the companion to the tcp/ip context descriptor described in the previous section. this descriptor type provides similar functionality to the legacy mode descriptor but also integrates the checksum off loading and tcp segmentation features. to select the tcp/ip data transmit descriptor format, shown below in figure 37-24 . the first qword of this descriptor type contains the address of a data buffer in host memory which contains a portion of a transmit packet. the second qword of this descriptor contains information about the data pointed to by this descriptor as well as descriptor processing options. setting tdesc.dext to 1 and the descriptor type (tdesc.dtyp) field to ?0001? identifies this descriptor as a tcp/ip data descriptor. the data length field (tdesc.dtalen) is the total length of the data pointed to by this descriptor, in bytes. for data descriptors not associated with a tcp segmentation operation (tdesc.tse not set), the descriptor lengths are subject to the same restrictions specified for legacy descriptors (the sum of the lengths of the data descriptors comprising a single packet must be at least 80 bytes less than the allocated size of the transmit fifo). in addition, although a buffer as short as one byte is allowed, the total length of the packet, before padding and crc insertion, must be at least 17 bytes. the command field (tdesc.dcmd) provides options that control the checksum off- loading tcp segmentation features, along with some of the generic descriptor processing features. figure 37-25 shows the bit definitions for the dcmd field. figure 37-24.tcp/ip data transmit descriptor layout (tdesc) - (type = 0001) 0 address[63:0] 8 vlan popts rsvd dstatus dcmd dtyp dtalen 63 48 47 40 39 36 35 32 31 24 23 20 19 0 figure 37-25.tcp/ip data transmit descriptor command field (tdesc.dcmd) 76543210 ide vle dext rsvd rs tse ifcs eop ide: interrupt delay enable vle: vlan enable dext: descriptor extension (must be 1 for this descriptor type)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1374 order number: 320066-003us tse indicates that this descriptor is part of the current tcp segmentation context. if this bit is not set, the descriptor is part of the ?normal? context. a packet is sent from one or more data buffers in host memory. the eop bit indicates that the buffer associated with this descriptor contains the last data for the packet or given tcp segmentation context. in the case of a tcp segmentation context, the dtalen length of this descriptor should match the amount remaining of the original paylen. if it does not, the tcp segmentation context will be terminated but the end of packet processing may be incorrectly performed. these abnormal termination events will be counted in the tsctfc statistics register detailed in section 37.6.6.53, ?tsctfc ? tcp segmentation context transmit fail count register? . ifcs controls insertion of the ethernet crc. rs tells the hardware to report the status information for this descriptor as soon as the corresponding data buffer has been fetched and stored in the ep80579?s gbe internal packet buffer. refer to figure 37-26 for the layout of the status field. the dext bit identifies this descriptor as one of the extended descriptor types and must be set to 1. vle indicates that the packet is a vlan packet (i.e. that the hardware should add the vlan ethertype and an 802.1q vlan tag to the packet). note: if the vle bit to enable vlan tag insertion, the ctrl.vme bit should also be set. if the ctrl. vme bit is not set, the device will not insert vlan tags on outgoing packets. note: the vle, ifcs, and vlan fields are only are only valid in certain descriptors. if tse is enabled, the vle, ifcs, and vlan fields are only valid in the first data descriptor of the tcp segmentation context. if tse is not enabled, then these fields are only valid in the last descriptor of the given packet (qualified by the eop bit). ide activates the transmit interrupt delay timer. hardware loads a countdown register when it writes back a transmit descriptor that has rs and ide set. the value loaded comes from transmit interrupt delay value register (tidv.idv). when the count reaches 0, a transmit interrupt occurs. hardware always loads the transmit interrupt counter whenever it processes a descriptor with ide set even if it is already counting down due to a previous descriptor. if hardware encounters a descriptor that has rs set, but not ide, it generates an interrupt immediately after writing back the descriptor and the interrupt delay timer is cleared. rsvd: reserved (must be set to 0) rs: report status tse: tcp segmentation enable ifcs insert fcs eop end of packet figure 37-25.tcp/ip data transmit descriptor command field (tdesc.dcmd) table 37-3. vlan tag insertion decision table vle action 0 send generic ethernet packet. ifcs controls insertion of fcs in normal ethernet packets. 1 send 802.1q packet; the ethernet type field comes from the vet register and the vlan data comes from the special field of the tx descriptor; hardware always appends the fcs/crc.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1375 intel ? ep80579 integrated processor four bits are reserved to provide transmit status, although only the dd bit (bit 0) is valid. the status word will only be written back to host memory in cases where the rs bit is set in the command field. the dd bit indicates that the descriptor is done and is written back after the descriptor has been processed. the popts field provides a number of options which control the handling of this packet. this field is ignored except on the first da ta descriptor of a packet or segmentation context. ixsm and txsm are used to control insertion of the ip and tcp/udp checksums, respectively. if the corresponding bit is not set, whatever value software has placed into the checksum field of the packet data will be placed on the wire. these bits are only valid in the first data descriptor for a given packet or tcp segmentation context. the vlan field is used to provide the 802.1q tagging information. the special field is ignored if the vle bit is 0. 37.5.6.6 transmit descriptor structure a pair of hardware registers maintains the transmit descriptor ring in the host memory. new descriptors are added to the queue by software by writing descriptors into the circular buffer memory region and moving the tail pointer associated with that queue. the tail pointer points one entry beyond the last hardware owned descriptor. transmission continues up to the descriptor where head equals tail at which point the queue is empty. descriptors passed to hardware should not be manipulated by software until the head pointer has advanced past them. the transmit descriptor ring structure is shown in figure 37-29 . shaded boxes represent descriptors that have been transmitted but not yet reclaimed by software. reclaiming involves freeing up buffers associated with the descriptors. figure 37-26.tcp/ip data transmit descriptor status (tdesc.dstatus) 3210 rsvd dd rsvd: reserved dd: descriptor done figure 37-27.tcp/ip data transmit descriptor packet options field (tdesc.popts) 76543210 rsvd txsm ixsm rsvd: reserved txsm: insert tcp/udp checksum ixsm: insert ip checksum figure 37-28.tcp/ip data transmit descriptor special field (tdesc.vlan) 15 13 12 11 0 pri cfi vlan id
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1376 order number: 320066-003us the transmit descriptor ring is described by the following registers: the transmit descriptor base address high register and the transmit descriptor base address low register (tdbah and tdbal) - these registers indicate the start of the descriptor ring buffer in the host memory; this 64-bit address is aligned on a 16b boundary. hardware ignores the lower 4 bits. transmit descriptor length register (tdlen) - this register determines the number of bytes allocated to the circular buffer. this value must be 0 modulo 128. transmit descriptor head register (tdh) - this register holds a value which is an offset from the base, and indicates the in-progress descriptor. there can be up to 64k descriptors in the circular buffer. reading this register returns the value of ?head? corresponding to descriptors already loaded in the output fifo. transmit descriptor tail register (tdt) - this register holds a value which is an offset from the base, and indicates the location beyond the last descriptor hardware can process. this is the location where software writes the first new descriptor. the base register indicates the start of the circular descriptor queue and the length register indicates the maximum size of the descriptor ring. the lower seven bits of length are hard-wired to 0. byte addresses within the descriptor buffer are computed as follows: address = base + (pointer * 16), where pointer is the value in the hardware head or tail register. the size chosen for the head and tail registers permit a maximum of 64k descriptors, or approximately 16k packets for the transmit queue given an average of four descriptors per packet. once activated, hardware fetches the descriptor indicated by the hardware head register. the hardware tail register points one beyond the last valid descriptor. software reads the head register to determine which packets (those logically before the head) have been transmitted. figure 37-29.transmit descriptor ring structure circular buffer head base + size base transmit queu e tail
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1377 intel ? ep80579 integrated processor note: software can determine if a packet has been sent by either of two methods: setting the rs bit in the transmit descriptor command fiel d or by performing a host cpu read of the transmit head register. checking the transmit descriptor dd bit in memory eliminates a potential race condition. all descriptor data is written to the host bus prior to incrementing the head register, but a read of the head register could ?pass? the data write in systems performing write buffering. updates to transmit descriptors use the same write path and follow all data writes. consequently, they are not subject to the race. hardware pre-fetches the entire packet data prior to transmission, and updates the value of the head pointer after storing each descriptor's data in the transmit fifo. the process of checking for completed packets consists of one of the following: ? scan memory. ? read the hardware head register. all packets up to but excluding the one pointed to by head have been sent or buffered and can be reclaimed. ? take an interrupt. an interrupt condition is generated whenever a transmit queue goes empty (icr.txqe). this interrupt can either be enabled or masked. 37.5.6.7 transmit descriptor fetching the descriptor processing strategy for transmit descriptors is essentially the same as for receive descriptors except that a different set of thresholds are used. just as with receives, the number of transmit descriptors held in hardware has been increased (from 8 to 64), and the fetch and write-back algorithms modified. when the hardware descriptor buffer is empt y, a fetch will happen as soon as any descriptors are made available (host writes to the tail pointer). when the hardware descriptor buffer is nearly empty (txdctl.pthresh), a prefetch will be performed whenever enough valid descriptors (txdctl.hthresh) are available in host memory and no other dma activity of greater priority is pending (descriptor fetches, descriptor write-backs, or packet data transfers). when the number of descriptors in host memory is greater than the available hardware descriptor storage, the gbe may elect to perform a fetch which is not a multiple of cache line size. the hardware performs this non-aligned fetch if doing so will result in the next descriptor fetch being aligned on a cache line boundary. this allows the descriptor fetch mechanism to be most efficient in the cases where it has fallen behind software. note: the gbe never fetches descriptors beyond the descriptor tail pointer. this is different from the 82542 design. 37.5.6.8 transmit descriptor write-back the descriptor write-back policy for transmit descriptors is similar to that for receive descriptors with a few additional factors. first, since transmit descriptor write-backs are optional (controlled by rs in the transmit descriptor), only descriptors which have one (or both) of these bits set will start the accumulation of write-back descriptors. secondly, to preserve backward compatibility with the 82542, if the txdctl.wthresh value is 0, the device will write back a single byte of the descriptor (tdescr.sta) and all other bytes of the descriptor will be left unchanged. the benefit of delaying and then bursting transmit descriptor write-backs is small at best. in this case, it is recommended the threshold be left at the default value (0) to force immediate write-back of transmit descriptors and to preserve backward compatibility. descriptors are written back in one of three cases:
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1378 order number: 320066-003us ? txdctl.wthresh = 0 and a descriptor whic h has rs set is ready to be written back, ? transmit interrupt delay timer expires, or ? txdctl.wthresh > 0 and txdctl.wthresh descriptors have accumulated. for the first condition, write-backs are immediate. this is the default operation and is backward compatible with the 82542 implementation. for this case, the transmit interrupt delay function works as described in ?delayed transmit interrupts? on page 1378 . the other two conditions are only valid if descriptor bursting is enabled ?txdctl ? transmit descriptor control register? on page 1500 . in the second condition, the ?tidv ? transmit interrupt delay value register? on page 1499 is used to force timely write- back of descriptors. the first packet after timer initialization starts the timer. timer expiration flushes any accumulated descriptors and sets an interrupt event ( icr .txdw). for the final condition, if txdctl.wthresh descriptors are ready for write-back, the write-back is performed. 37.5.6.9 transmit interrupts hardware supplies three transmit interrupts. these interrupts are initiated via the following conditions: transmit descriptor ring empty (icr.txqe) - all descriptors have been processed. the head pointer is equal to the tail pointer. descriptor done (transmit descriptor write-back (icr.txdw)) - set when hardware writes back a descriptor with rs set. this is only expected to be used in cases where, for example, the streams interface has run out of descriptors and wants to be interrupted whenever progress is made. transmit delayed interrupt (icr.txdw) - in conjunction with ide (interrupt delay enable), the icr .txdw indication is delayed per the tidv and/or tadv registers. the interrupt is set when one of the transmit interrupt countdown timers expires. a transmit delayed interrupt is scheduled for a transmit descriptor with its rs and ide bits both set. when a transmit delayed interrupt occurs, the icr.txdw interrupt cause bit is set (just as when a transmit descriptor write-back interrupt occurs). this interrupt may be masked in the same manner as the icr.txdw interrupt. this interrupt will be used frequently by software that performs dynamic transmit chaining, by adding packets one at a time to the transmit chain. note: the transmit delay interrupt is indicated with the same interrupt bit as the transmit write-back interrupt, icr.txdw. the transmit delay interrupt is only delayed in time as discussed above. transmit descriptor ring low threshold hit (icr.txd_low) - set when the total number of transmit descriptors available (as measured by the difference between the tx descriptor ring head and tail pointer) hits the low threshold specified in the txdctl.lwthresh field in the transmit descriptor control register. 37.5.6.9.1 delayed transmit interrupts this mechanism allows software the flexibility of delaying transmit interrupts until no more descriptors are added to a transmit chain for a certain amount of time, rather than when the device's head pointer catches the tail pointer. this will occur if the device is processing packets slightly faster than the software, a likely scenario for gigabit operations.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1379 intel ? ep80579 integrated processor this feature is desirable, because a software driver usually has no knowledge of when it is going to be asked to send another frame, and for performance reasons, it is best to generate only one transmit interrupt after a burst of packets have been sent. refer to ?transmit descriptor formats? on page 1365 for specific details. 37.5.6.10 transmit checksum off loading the previous section on tcp segmentation off load describes the ip/tcp/udp checksum off loading mechanism used in conjunction with tcp segmentation. the same underlying mechanism can also be applied as a standalone feature. the main difference in normal packet mode (non-tcp segmentation) is that only the checksum fields in the ip/tcp/udp headers need to be updated. before taking advantage of the gbe enhanced checksum off load capability, a checksum context must be initialized. for the normal transmit checksum off load feature this is performed by providing the device with a tcp/ip context descriptor with tse=0. setting tse=0 indicates that the normal checksum context is being set, as opposed to the segmentation context. for additional details on contexts, refer to ?overview of gbe hardware ?contexts?? on page 1369 . note: enabling the checksum off loading capability without first initializing the appropriate checksum context will lead to unpredictable results. once the checksum context has been set, that context will be used for all normal packet transmissions until a new context is loaded. also, since checksum insertion is controlled a per packet basis, there is no need to clear/reset the context. the gbe is capable of performing two transmit checksum calculations. typically these would be used for tcp/ip and udp/ip packet types; however, the mechanism is general enough to support other checksums as well. each checksum operates independently and provides identical functionality. only the ip checksum case is discussed below. three fields in the tcp/ip context descriptor set the context of the ipv4 checksum off loading feature: ipcss, ipcso, and ipcse. ipcss specifies the byte offset from the start of the data fetched from host memory to the first byte to be included in the checksum. setting this value to ?0? means the first byte of the data would be included in the checksum. note that the maximum value for this field is 255. this is adequate for typical applications. note: the css value needs to be less than the total dma length for a packet. if this is not the case, the results will be unpredictable. the ipcso field specifies where the resulting checksum should be placed. again, this is limited to the first 256 bytes of the packet and must be less than or equal to the total length of a given packet. if this is not the case, the checksum will not be inserted. ipcse specifies where the checksum should stop. a 16-bit value supports checksum off loading of packets as large as 64kb. setting the ipcse field to all zeros means end-of- packet. in this way, the length of the packet does not need to be calculated. as mentioned in ?overview of gbe hardware ?contexts?? on page 1369 , it is not necessary to set a new context for each new packet. in many cases, the same checksum context can be used for a majority of the packet stream. in this case, some performance can be gained by only changing the context on an as needed basis or electing to use the off load feature only for a particular traffic type, thereby avoiding all context descriptors except for the initial one.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1380 order number: 320066-003us 37.5.7 tcp segmentation hardware tcp segmentation is one of the off-loading options of the windows 2000* tcp/ip stack. this is often referred to as ?l arge send? off loading. this feature allows the tcp/ip stack to pass to the network device driver a message to be transmitted that is bigger than the maximum transmission unit (mtu) of the medium. it is then the responsibility of the device driver and hardware to carve the tcp message into mtu size frames that have appropriate layer 2 (ethernet), 3 (ip), and 4 (tcp) headers. these headers must include sequence number, checksum fields, options and flag values as required. note that some of these values (such as the checksum values) will be unique for each packet of the tcp message, and other fields such as the source ip address will be constant for all packets associated with the tcp message. the off loading of these mechanisms to the device driver and the ep80579?s gbe will save significant cpu cycles. the device driver and the ep80579?s gbe will share the additional tasks in order to support this feature. prior to windows 2000*, the microsoft* tcp/ip stack (tcpip.sys) had always transferred (to the miniport device driver and eventually to the mac) a frame with bytes up to the size of mtu for the media (up to 1514 bytes for 802.3 ethernet packets). note: although the gbe tcp segmentation off load implementation was specifically designed to take advantage of the new ?tcp segmenta tion offload? feature from microsoft, the hardware implementation was made generic enough so that it could also be used to ?segment? traffic from other protocols. for instance this feature could be used any time it is desirable for hw to segment a large block of data for transmission into multiple packets that contain the same generic header. figure 37-30.transmit descriptor and tucmd field (tdesc) layouts - (type = 0000) 63 48 47 40 39 32 31 16 15 8 7 0 0 tucse tucso tucss ipcse ipcso ipcss 8 mss hdrlen rsvd sta tucmd dtyp paylen 63 48 47 40 39 36 35 32 31 24 23 20 19 0 76543210 ide rsvd dext rsvd rs tse ip tcp ide: interrupt delay enable rsvd: reserved dext: descriptor extension (must be 1) rsvd: reserved rs: report status tse: tcp segmentation enable ip: ipv4 header update enable tcp: packet type (tcp=1,udp=0)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1381 intel ? ep80579 integrated processor 37.5.7.1 assumptions the gbe tcp segmentation implementation assumes the rs bit operation is not changed. interrupts are set after data in buff ers pointed to by individual descriptors is transferred from host me mory to gbe hardware. 37.5.7.2 transmission process the transmission process for regular (non-tcp segmentation packets) involves the following: ? the protocol stack receives a block of data that is to be transmitted from an application. ? the protocol stack calculates the number of packets required to transmit this block based on the mtu size of the media and required packet headers. ? for each packet of the data block: ? the stack prepares ethernet, ip and tcp/udp headers. ? the stack interfaces with the device driver and commands the driver to send the individual packet. ? the driver gets the frame and interfaces with the hardware. ? the hardware reads the packet from host memory (via dma transfers). ? the driver returns ownership of the packet to the nos when the hardware has completed the dma transfer of the frame (indicated by an interrupt). the transmission process for the gbe tcp segmentation off load implementation involves the following: ? the protocol stack receives a block of data that is to be transmitted from an application. ? the stack interfaces to the device driver and passes the block down with the appropriate header information. ? the device driver sets up the interface to the hardware (via descriptors) for the tcp segmentation context. ? the hardware transfers the packet data from host memory and performs the ethernet packet segmentation and transmission based on offset and payload length parameters in the tcp/ip context descriptor including: ? packet encapsulation ? header generation and field updates including ip and tcp/udp checksum generation ? the driver returns ownership of the block of data to the nos when the hardware has completed the dma transfer of the entire data block (indicated by an interrupt). 37.5.7.2.1 tcp segmentation data fetch control to perform tcp segmentation in the gbe, the dma must ensure that the entire payload of the segmented packet will fit into the available space in the gbe packet buffer. the segmentation process should be performed without interruption. the dma will do various comparisons between the payload and the packet buffer to ensure no interruptions occur as well as general efficiencies in the operation of the tcp segmentation feature. the ?tspmt ? tcp segmentation pad and minimum threshold register? on page 1503 is used to allow software to program the minimum threshold required for a tcp segmentation payload. consideration should be made for the mtu
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1382 order number: 320066-003us value when writing this field. the tspmt register is also used to program the threshold padding overhead. this padding is necessary due to the indeterminate nature of the mtu and the associated headers. 37.5.7.3 tcp segmentation performance performance improvements for a hardware implementation of tcp segmentation off load include: ? the stack does not need to partition the block to fit the mtu size, saving cpu cycles. ? the stack only computes one ethernet, ip, and tcp header per segment, saving cpu cycles. ? the stack interfaces with the device driver only once per block transfer, instead of once per frame. ? larger internal bus bursts are used which improves bus efficiency (i.e. lowering transaction overhead). ? interrupts are easily reduced to one per tcp message instead of one per packet. ? fewer i/o accesses are required to command the hardware. 37.5.7.4 packet format typical tcp/ip transmit window size is 8760 bytes (about 6 full size frames). today the average size on corporate intranets is 12-14kb, and normally the maximum window size allowed is 64kb. a tcp message can be as large as 64kb and is generally fragmented across multiple pages in host memory. the gbe partitions the data packet into standard ethernet frames prior to transmission. the gbe also supports calculating the ethernet, ip, tcp, and even udp headers, including checksum, on a frame by frame basis. frame formats supported by the gbe include: ? ethernet 802.3, ? ieee 802.1q vlan (ethernet 802.3ac), ?ethernet type 2, ?ethernet snap, ? ipv4 headers with options, ? ipv6 headers with ip option next headers, ? ipv6 packet tunneled in ipv4, ? tcp with options, and ? udp with options. vlan tag insertion is also handled by hardware. note: udp (unlike tcp) is not a ?reliable protocol?, and fragmentation is not supported at the udp level. udp messages that are larger than the mtu size of the given network medium are normally fragmented at the ip layer. this is different from tcp, where large tcp messages can be fragmented at either the ip or tcp layers depending on the software implementation. the gbe has the ability to segment udp traffic (in addition to tcp traffic), but because udp packets are generally fragmented at the ip layer the gbe ?tcp segmentation? feature will normally not be conducive to handling udp traffic. figure 37-31.tcp/ip packet format ethernet ip tcp/udp data fcs
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1383 intel ? ep80579 integrated processor note: ip tunneled packets are not supported for large send operation. 37.5.7.5 tcp segmentation indication software indicates a tcp segmentation transmission context to the hardware by setting up a tcp/ip context transmit descriptor (refer to ?tcp/ip context transmit descriptor format? on page 1369 ). the purpose of this descriptor is to provide information to the hardware to be used during the tcp segmentation off load process. the layout of this descriptor is reproduced in figure 37-32 . setting the tse bit in the command field to ?1? indicates that this descriptor refers to the tcp segmentation context (as opposed to the normal checksum off loading context). this will cause the checksum off loading, packet length, header length, and maximum segment size parameters to be loaded from the descriptor into the device. the tcp segmentation prototype header is ta ken from the packet data itself. software must identity the type of packet that is being sent (ip/tcp, ip/udp, other), calculate appropriate checksum off loading values for the desired checksums, and calculate the length of the header which is prepended. the header may be up to 240 bytes in length. 37.5.7.6 tcp segmentation data descriptors 37.5.7.6.1 tcp segmentation source data once the tcp segmentation context has been set, the next descriptor provides the initial data to transfer. this first descriptor(s) must point to a packet of the type indicated. furthermore, the data it points to may need to be modified by software as it will serve as the prototype header for all packets within the tcp segmentation context. the following sections describe the supported packet types and the various updates which are performed by hardware. this should be used as a guide to determine what must be modified in the original packet header to make it a suitable prototype header. the following summarizes the fields considered by the driver for modification in constructing the prototype header. ?ipv4 header ? length should be set to zero ? identification field should be set as appropriate for first packet of send (if not already) ? header checksum should be zeroed out unless some adjustment is needed by the driver ?ipv6 header ? length should be set to zero ?tcp header figure 37-32.tcp/ip context transmit descriptor & command layout 63 48 47 40 39 32 31 16 15 8 7 0 0 tucse tucso tucss ipcse ipcso ipcss 8 mss hdrlen rsvd sta tucmd dtyp paylen 63 48 47 40 39 36 35 32 31 24 23 20 19 0 76543210 ide rsvd dext rsvd rs tse ip tcp
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1384 order number: 320066-003us ? sequence number should be set as appropriate for first packet of send (if not already) ? psh, and fin flags should be set as appropriate for last packet of send ? tcp checksum should be set to the pa rtial pseudo-header checksum as follows (there is a more detailed discussion of this in ?ip and tcp/udp headers? just before figure 37-40 : ?udp header ? checksum should be set as in tcp header, shown in figure 37-33 and figure 37-34 . the gbe dma function will fetch the ethernet, ip, and tcp/udp prototype header information from the initial descriptor(s) and save them in hardware for individual packet header generation. the following sections describe the updating process performed by the hardware for each frame sent using the tcp segmentation capability. 37.5.7.6.2 tcp segmentation use of multiple data descriptors tcp segmentation allows the packet to be segmented to be describe more than one data descriptor. a large packet contained in a single virtual-address buffer may be more simply described by a series of data descriptors, each referencing a single physical address page. there is only one requirement for multiple data descriptors for tcp segmentation: ? if multiple data descriptors are used to describe the ip/tcp/udp header section, each descriptor must describe one or more complete headers; descriptors referencing only parts of headers are not supported. note: it is recommended that the entire header section, as described by the tcp context descriptor hdrlen field, be coalesced into a single buffer and described using a single data descriptor. 37.5.7.7 ip and tcp/udp headers this section outlines the format and content for the ip, tcp and udp headers. the gbe requires baseline information from the device driver in order to construct the appropriate header information during the segmentation process. header fields that are modified by the gbe are highlighted in the figures below. figure 37-33.tcp partial pseudo-header checksum for ipv4 0 31 ip source address ip destination address zero protocol id zero figure 37-34.tcp partial pseudo-header checksum for ipv6 0 31 ip source address ip destination address zero zero next header
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1385 intel ? ep80579 integrated processor note: the ipv4 header is first shown in the traditional (i.e., rfc 791) representation, and because byte and bit ordering is confusing in that representation. the ip header is also shown in little-endian format, since the actual data will be fetched from memory in little-endian format. figure 37-35 and figure 37-36 : flag bit definition: ? mf: more fragments (hardware does not evaluate or change this bit) ? nf: no fragments (hardware does not evaluate or change this bit) ?rsv: reserved note: the ipv6 header is shown in the traditional (i.e. rfc 2460), big-endian representation. the actual data will be fetched from memory in little-endian format, similar to the ipv4 header shown above. figure 37-35.ipv4 header (traditional representation) 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 version ip hdr length type of service total length identification flags fragment offset time to live layer 4 protocol id header checksum source address destination address options figure 37-36.ipv4 header (little-endian order) byte 3byte 2byte 1byte 0 76543210765432107654321076543210 lsb total length msb type of service version ip hdr length fragment offset low rsv nf mf fragment offset high lsb identification msb header checksum layer 4 protocol id time to live source address destination address options figure 37-37.ipv6 header (traditional representation) 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 version traffic class flow label payload length next header hop limit source address destination address
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1386 order number: 320066-003us a tcp or udp frame uses a 16 bit wide one's complement checksum. the checksum word is computed on the outgoing tcp or udp header and payload, and on the pseudo header. refer to ?transmit checksum off loading with tcp segmentation? on page 1388 for details on checksum computations. note: tcp requires the use of checksum, where it is optional for udp. note: the tcp header is first shown in the traditional (i.e. rfc 793) representation, and because byte and bit ordering is confusing in that representation, the tcp header is also shown in little-endian format. the actual data will be fetched from memory in little-endian format. the tcp header is always a multiple of 32 bit words. tcp options may occupy space at the end of the tcp header and are a multiple of 8 bits in length. all options are included in the checksum. the checksum also covers a pseudo header conceptually prefixed to the tcp header (see figure 37-40 and figure 37-41 below). the ipv4 pseudo header contains the ipv4 source address, the ipv4 destination address, the ipv4 protocol field, and tcp length. the ipv6 pseudo header contains the ipv6 source address, the ipv6 destination address, the ipv6 payload length, and the ipv6 next header field. software pre- calculates the partial pseudo header sum, which includes ip sa, da and protocol type/ next header, but not the tcp/payload length, and stores this value into the tcp checksum field of the packet. note: when calculating the tcp pseudo header, the byte ordering can be tricky. one common question is whether the protocol id field is added to the ?lower? or ?upper? byte of the 16 bit sum. the protocol id field should be added the least significant byte (lsb) of the 16 bit pseudo header sum, where the most significant byte (msb) of the 16 bit sum is the byte that corresponds to the first checksum byte out on the wire. figure 37-38.tcp header (traditional representation) 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 source port destination port sequence number acknowledge number tcp hdr length reserved urg ack psh rst syn fin window checksum urgent pointer options figure 37-39.tcp header (little-endian order) byte 3 byte 2 byte 1 byte 0 76543210765432107654321076543210 destination port source port lsb sequence number msb acknowledge number window rsv urg ack psh rst syn fin tcp hdr length reserved urgent pointer checksum options
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1387 intel ? ep80579 integrated processor the tcp length field is the tcp header length including option fields plus the data length in bytes, which is calculated by ha rdware on a frame by frame basis. the tcp length does not count the 12 bytes of the pseudo header. the tcp length of the packet is determined by hardware as: tcp length = payload + hdrlen - tucss ?payload? is normally mss except for the last packet where it represents the remainder of the payload. note: the ip destination address is the final destination of the packet. therefore, if a routing header is used, the last address in the route list is used in this calculation. the upper- layer packet length is the length of the tcp header and tcp payload. the udp header is always 8 bytes in size with no options. udp pseudo header has the same format as the tcp pseudo header. the ipv4 pseudo header conceptually prefixed to the udp header contains the ipv4 source address, the ipv4 destination address, the ipv4 protocol field, and the udp length (same as the tcp length discussed above). the ipv6 pseudo header for udp is the same as the ipv6 pseudo header for tcp. the checksum procedure is the same as is used in tcp. figure 37-40.tcp pseudo header content (traditional representation) 0 31 ip source address ip destination address zero protocol id tcp length figure 37-41.tcp pseudo-header content for ipv6 0 31 ip source address ip destination address upper layer packet length zero next header figure 37-42.udp header (traditional representation) 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 source port destination port length checksum figure 37-43.udp header (little-endian order) byte 3byte 2byte 1byte 0 76543210765432107654321076543210 destination port source port checksum length
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1388 order number: 320066-003us note: the ip destination address is the final destination of the packet. therefore, if a routing header is used, the last address in the route list is used in this calculation. the upper- layer packet length is the length of the udp header and udp payload. unlike the tcp checksum, the udp checksum is optional. software must set the txsm bit in the tcp/ip context transmit descriptor to indicate that a udp checksum should be inserted. hardware will not update the udp checksum unless the txsm bit is set. 37.5.7.8 transmit checksum off loading with tcp segmentation the gbe supports checksum off-loading as a component of the tcp segmentation off load feature and as a standalone capability. refer to ?tcp/ip context transmit descriptor format? on page 1369 for details on the interface for controlling the checksum off-loading feature. this section describes the feature as it relates to tcp segmentation. the gbe supports ip and tcp/udp header options in the checksum computation for packets that are derived from the tcp segmentation feature. note: the gbe is capable of computing one level of ip header checksum and one tcp/udp header and payload checksum. in the case of multiple ip headers, the driver will have to compute all but one ip header checksum. the gbe calculates checksums on the fly on a frame by frame basis and inserts the result in the ip/tcp/udp headers of each frame. tcp and udp checksum are a result of performing the checksum on all bytes of the payload and the pseudo header. three specific types of checksum are supported by the hardware in the context of the tcp segmentation off load feature ipv4 checksum (ipv6 does not have a checksum), tcp checksum, and udp checksum. each packet that is sent via the tcp segmentation off load feature optionally includes the ipv4 checksum and either the tcp or udp checksum. all checksum calculations use a 16-bit wide one's complement checksum calculated of all 16-bit words in the range of css to cse, including the checksum field itself. the checksum field is written with this hardware computed value. figure 37-44.udp pseudo header diagram for ipv4 0 31 ip source address ip destination address zero protocol id udp length figure 37-45.udp pseudo-header diagram for ipv6 0 31 ip source address ip destination address upper layer packet length zero next header
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1389 intel ? ep80579 integrated processor 37.5.7.9 ip/tcp/udp header updating ip/tcp/udp header is updated for each outgoing frame based on the ip/tcp header prototype which hardware dma?s from the first descriptor(s) and stores in hardware. the ip/tcp/udp headers are fetched from host memory into a 240 byte header buffer once for each tcp segmentation context (for performance reasons, this header is not fetched again for each additional packet that will be derived from the tcp segmentation process). the checksum fields and other header information are later updated on a frame by frame basis. the updating process is performed concurrently with the packet data fetch. the following sections define what fields are modified by hardware during the tcp segmentation process by the gbe. 37.5.7.9.1 tcp/ip/udp header for the first frame the hardware makes the following changes to the headers of the first packet that is derived from each tcp segmentation context. ?ipv4 header ? ip total length = mss + hdrlen - ipcss ?ip checksum ?ipv6 header ? payload length = mss + hdrlen - ipcss ?tcp header ? sequence number: the value is the sequence number of the first tcp byte in this frame. ? if fin flag = 1, it is cleared in the first frame. ? if psh flag =1, it is cleared in the first frame. ? tcp checksum ?udp header ? udp length: mss + hdrlen - tucss ?udp checksum 37.5.7.9.2 tcp/ip/udp header for the subsequent frames the hardware makes the following changes to the headers for subsequent packets that are derived as part of a tcp segmentation context: note: number of bytes left for transmission = paylen - (n * mss). where n is the number of frames that have been transmitted. ?ipv4 header ? ip identification: incremented from last value (wraps around) ? ip total length = mss + hdrlen - ipcss ?ip checksum ?ipv6 header ? payload length = mss + hdrlen - ipcss ?tcp header ? sequence number update: add previous tcp payload size to the previous sequence number value. this is equivalent to adding the mss to the previous sequence number.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1390 order number: 320066-003us ? if fin flag = 1, it is cleared in these frames. ? if psh flag =1, it is cleared in these frames. ? tcp checksum ?udp header ? udp length: mss + hdrlen - tucss ?udp checksum 37.5.7.9.3 tcp/ip/udp header for the last frame the hardware makes the following changes to the headers for the last frame of a tcp segmentation context: note: last frame payload bytes = paylen - (n * mss) ?ipv4 header ? ip total length = (last frame payload bytes + hdrlen) - ipcss ? ip identification: incremented from last value (wraps around) ?ip checksum ?ipv6 header ? payload length = mss + hdrlen - ipcss ? tcp header ? sequence number update: add previous tcp payload size to the previous sequence number value. this is equivalent to adding the mss to the previous sequence number. ? if fin flag = 1, set it in this last frame ? if psh flag =1, set it in this last frame ? tcp checksum ?udp header ? udp length: (last frame payload bytes + hdrlen) - tucss ?udp checksum
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1391 intel ? ep80579 integrated processor 37.5.7.10 data flow 37.5.8 ethernet interfaces the gbe mac provides a complete csma/cd function supporting ieee 802.3 (10mbps), 802.3u (100mbps), 802.3z and 802.3ab (1000mbps) implementations. the device performs all of the functions required for transmission, reception and collision handling called out in the standards. the gbe may be configured to be used with different media interfaces. the following native configurations are supported: ? external rgmii/rmii device (these interfaces are provided via gasket between the gbe?s native gmii/mii interfaces) figure 37-46.data flow ip/tcp header packet data packet data packet data dd r memor y fifo ip/tcp header buffer checksum calculation t x packet fifo tcp segmentation data flow descriptors fetch ip/tcp header prototype fetch packet data fetch header processing checksum calculations data fetch pause checksum header insertion data fetch resume header processing checksum calculations data fetch pause checksum header insertion events scheduling time header update
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1392 order number: 320066-003us selection between the various configurations is programmable via the mac extended device control register ( ctrl_ext .link_mode bits). tgmii/mii interface used to communicate between the mac and he rgmii/rmii gasket supports 10/100/1000 mbps operation, with both half- and full-duplex operation at 10/ 100 mbps, and full-duplex operation at 1000 mbps. note: the gbe mac is optimized for full-duplex operation in 1000 mbps mode. half-duplex 1000 mbps operation is not supported. 37.5.8.1 mac/phy gmii/mii interface the gbe mac communicates through a gmii/mii interface which may be configured for either 1000 mbps operation (gmii) or 10/100 mbps (mii) mode of operation. for proper network operation, both the internal mac and the external phy must be properly configured to identical speed & duplex settings. additionally, the translators may need to be configured in the ?ctrl_aux ? auxiliary device control/status register? . all mac configuration is performed using device control registers mapped into system memory. the phy will either auto-negotiate the link with the link partner?s phy at the other end of the copper line, or will be forced into it?s configuration by software. 37.5.8.1.1 gmii - 1000 mbps operation during 1000mbps operation, the mac/phy communication occurs via an interface utilizing a pair of 8-bit buses operating at 125 mhz and accompanied by a handful of additional clocks and/or qualifiers. this signaling (gmii mode) includes the following communication: crs (carrier sense): carrier sense is detected by the phy and indicates activity on the cable, either incoming or outgoing. this signal is driven by the phy to the mac to enable the mac to generate link status-change alerts, and suspend transmit / ignore receive symbols when no link is present. col (collision detection): collision detection is performed by the phy, signaled to the mac upon detection of a collision on the medium, and remains asserted while the collision condition persists. for half-duplex operation, col indicates detection of simultaneous transmission and reception. since collisions do not occur between full-duplex transceivers, the gbe mac ignores any errant collision- signaling when in full-duplex mode. tx_er (transmit code error): this signaling is used by the mac to indicate carrier extension and ipg during packet bursts to the phy, as well as to force propagation of transmit errors. note that the gbe will not transmit error codes. tx_en (transmit enable): this signal is asserted from the mac to the phy while transmitting, and used to indicate when the mac is presenting frame data on the gmii interface to the phy for transmission. the mac asserts tx_en synchronously with the first byte of the preamble, and it remains asserted until the final data byte in a frame, deasserted after the final byte. gtx _clk (transmit data clock): in gmii mode, the mac provides a 125 mhz transmit clock to the phy accompanying any transmit data. tx_data (transmit data): data is transmitted from the mac to phy in 8-bit quantities at 125 mhz when in gmii mode. rx_clk (receive clock): in gmii mode, receive data provided from the phy to the mac is accompanied by a 125 mhz receive clock. rx_data (receive data): data received by the phy is transferred to the mac in 8-bit quantities at 125 mhz in gmii mode. rx_er (receive error): receive errors are detected by the phy and signaled to the mac. receive errors may include link coding errors, or any other error detected by the phy. if receive errors are signaled during packet reception, the mac can be configured to either receive or drop these packets.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1393 intel ? ep80579 integrated processor rx_dv (receive data valid): this signal is asserted from the phy to the mac to transfer valid frame data to the mac. it is asserted from the first through the final bytes of a frame, de-asserted after the final byte. the phy asserts carrier sense with this data-valid signal de-asserted to indicate to the mac reception of broken packet headers (fragments). 37.5.8.1.2 mii - 10/100 mbps operation during 10/100 mbps operation (mii mode), the communication between the gbe mac and the external phy occurs via the same interface as in gmii mode, used in a similar way. in mii mode, transmit and receive data is transferred in nibble-wide (4-bit) quantities instead of 8-bit quantities, and at either 25mhz (100 mbps operation) or 2.5 mhz (10 mbps operation). differences in signaling between gmii and mii modes are as follows: mtx_clk (transmit clock): in mii mode, this clock is supplied from the phy to the mac, and is used by the mac for transmit-data synchronization. this clock operates at either 25mhz (for 100base-t) or 2.5mhz (for 10base-t). tx_data (transmit data): transmit data is transferred from the mac to the phy in 4-bit (nibble) quantities at either 25 mhz or 2.5 mhz. in mii mode. rx_clk (receive clock): in mii mode, the receive clock provided from the phy to the mac operates at either 25 mhz (for 100base-t) or 2.5mhz (for 10base-t). rx_data (receive data): receive data is transferred from the phy to the mac in 4-bit (nibble) quantities at either 25 mhz or 2.5 mhz in mii mode. if a pin is listed in gmii mode, but not mii mode, then it functions identically to gmii mode. 37.5.8.2 duplex operation the gbe supports half-duplex mii mode and full-duplex gmii/mii mode. configuration of the duplex operation of the device must be programmed by software. 37.5.8.2.1 full duplex all aspects of the ieee 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full duplex operation. during full duplex operation, the gbe may transmit and receive packets simultaneously across the link interface. in full-duplex gmii/mii mode, transmission and reception are delineated independently by the control signals. transmission starts upon the assertion of tx_en which indicates there is valid data on the tx_data bus driven from the mac to the phy. reception is signaled by the phy by the assertion of the rx_dv signal which indicates valid receive data on the rx_data lines to the mac. the gbe can receive carrier-extended packets, although it cannot transmit carrier- extended packets. note that errors received the extended portion of the packet (carrier-extend errors) will not be detected by the gbe. 37.5.8.2.2 half duplex the gbe mac may operate in half duplex when configured for mii mode, but gmii mode does not support half duplex operation. in half duplex operation, the mac attempts to avoid contention with other traffic on the link by monitoring the crs signal provided by the phy and deferring to passing traffic. when the crs signal is de-asserted or after a sufficient inter-packet gap (ipg) has elapsed after a transmission, frame transmission may begin. the mac signals the phy with tx_en at the start of transmission.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1394 order number: 320066-003us in the case of a collision, the phy detects the collision and asserts the col signal to the mac. transmission of the frame stops within four link clock times, and the gbe sends a jam sequence onto the link. after the end of a collided transmission, the gbe will back off and attempt to retransmit per the standard csma/cd method. note that the re- transmissions are done from the data stored internally in the gbe transmit packet buffer (no re-access to the data in host memory is necessary). in the case of a successful transmission, the gbe is ready to transmit any other frame(s) queued in the transmit fifo, after the minimum inter-frame spacing (ifs) of the link has elapsed. during transmit, the phy is expected to signal a carrier-sense (assert the crs signal) back to the mac before one slot time has elapsed. the transmission will complete successfully even if the phy fails to indicate crs within the slot time window. if this situation occurs, the phy may either be configured incorrectly or be in a link down situation. such an event will be counted in the statistic register space, refer to ?tncrs ? transmit with no crs count register? on page 1510 . mii mode half duplex reception occurs exactly as indicated in ?full duplex? on page 1393 . reception is signaled by the phy by the assertion of the rx_dv signal which indicates valid receive data on the rx_data lines to the mac. 37.5.8.3 physical layer auto-negotiation & link setup features the method for configuring the link between two link partners is highly dependent on the mode of operation as well as the functionality provided by the specific physical layer device. for gmii/mii mode, the pcs and auto-negotiation functions are expected to be maintained within the external phy. configuration of the link may be accomplished by several methods ranging from software's forcing link settings, to software-controlled negotiation, to auto-negotiation initiated by the phy. the following sections describe processes of bringing the link up including configuration of the gbe and the transceiver, as well as the various methods of determining duplex and speed configuration in order to configure the mac. when operating in a gmii/mii mode, the external phy performs auto-negotiation per 802.3ab clause 40 and extensions to clause 28. link resolution is obtained by software from the phy after the link has been established and programs the mac with these settings. 37.5.8.3.1 gmii/mii/copper link configuration when operating in gmii/mii mode, link configuration is generally determined by auto- negotiation between the phy and it?s link partner. the driver must poll the configuration in cases after a successful link is established or the user desires to manually configure the link. the following sections discuss the methods of link configuration for copper phy operation. 37.5.8.3.2 gmii/mii/copper auto-negotiation (speed, duplex, flow-control) when using a copper phy, the phy performs the auto-negotiation function. the actual operational details of this operation are described in the ieee p802.3ab draft standard, and are not included here. auto-negotiation provides a method for two link partners to exchange information in a systematic manner in order to establish a link configuration providing the highest level of functionality supported by both partners. once configured, the link partners exchange configuration information to resolve link settings such as: ? speed (10/100/1000 mbps)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1395 intel ? ep80579 integrated processor ? duplex (full or half) ? flow control operation phy specific information required for establishing the link is also exchanged. note: if flow control is enabled in the gbe, the settings for the desired flow control behavior must be set by software in the phy registers and auto-negotiation restarted. after auto-negotiation is complete, the driver must read the phy registers to determine the resolved flow control behavior of the link and reflect these in the mac register settings (ctrl.tfce and ctrl.rfce). note: there are two recommended methods for coordination between the phy/phy auto- negotiation and the gbe. first, the phy can be programmed to issue an mdint to the host cpu when the link changes. when the ep80579 receives the mdint indicator via an interrupt, the isr routine will poll the phy?s mdio interface and programs the gbe accordingly. second, software may continuously poll the phy?s configuration registers through the mdio interface and reprogram the gbe when the configuration changes from the previous state. mac speed resolution for proper link operation, both the mac and phy must be configured for the same speed of link operation. the speed of the link may be determined and set by one of the following methods: ? hardware uses the default mac speed of 1 gbps and no software action is necessary, or ? software reads the phy registers to determine the phy's auto-negotiated speed and configures the mac by setting ctrl.frcspeed to 1 and ctrl.speed to the proper speed value (refer to ?ctrl ? device control register? on page 1438 for details), or ? software writes the non auto-negotiated phy registers with the desired speed and configures the mac by to the same setting by programming ctrl.frcspeed to 1 and ctrl.speed to the proper speed value (refer to ?ctrl ? device control register? on page 1438 for details). note: forcing the mac speed using ctrl .frcspd can yield non-functional links if the mac and phy are not operating at the same speed/configuration. note: the forcing of the speed settings by ctrl .speed may also be accomplished by setting the ctrl_ext .spd_byps bit. this bit bypasses the mac?s internal clock switching logic and allows the driver complete control of when the speed setting takes place. the ctrl .frcspd bit uses the mac's internal clock switching logic, which does slightly delay the affect of the speed change. mac full/half duplex resolution the duplex configuration of the link is also resolved by the phy during the auto- negotiation process. for proper link operation, both the mac and phy must be also configured for the same duplex configuration. the duplex configuration of the link may be determined and set by one of the following methods: ? hardware uses the default mac speed of full duplex and no software action is necessary (the phy configuration must be known to be full-duplex for this option), or ? software reads the phy registers to determine the phy's auto-negotiated duplex setting and configures the mac by setting ctrl .frcdplx to 1 and ctrl .fd to the proper value (refer to ?ctrl ? device control register? on page 1438 for details), or
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1396 order number: 320066-003us ? software writes the non auto-negotiated phy registers with the desired duplex configuration and configures the mac by to the same setting by programming ctrl .frcdplx to 1 and ctrl .fd to the proper speed value (refer to ?ctrl ? device control register? on page 1438 for details). using phy registers the driver may be required under some circumstances to read from, or write to, the mii management registers in the phy. these accesses are performed via the mdio registers in the gcu (refer to the gcu eas chapter for details). the mii registers allow the driver to have direct control over the phy's operation which may include: ? resetting the phy, ? setting preferred link configuration for advertisement during the auto-negotiation process, ? restarting the auto-negotiation process, ? reading auto-negotiation status from the phy, and ? forcing the phy to a specific link configuration. the set of phy management registers required for all phy devices may be found in the ieee p802.3ab draft standard. comments regarding forcing link forcing link in gmii/mii mode requires the driver to configure both the mac and phy in a consistent manner with respect to each other as well as the link partner. after initialization, the driver configures the desired modes in the mac, then accesses the phy registers to set the phy to the same configuration. before enabling the link, the speed and duplex settings of the mac may be forced by software using the ctrl .frcspd, ctrl .frcdpx, ctrl .speed, and ctrl .fd bits. after the phy and mac have both been configured, the driver should write a 1 to the ctrl .slu bit. 37.5.8.4 10/100mbps specific performance enhancements 37.5.8.4.1 adaptive ifs the gbe supports back-to-back transmit inter-frame-spacing (ifs) of 960 ns in 100 mbit operation and 9.6 us in 10m bit operation. although back-to-back transmission is normally desirable, sometimes it can actually hurt performance in half-duplex environments due to excessive collisions. excessive collisions are likely to occur in environments where one station is attempting to send large frames back-to-back, while another station is attempting to send acknowledge (ack) packets. the gbe contains the ait register that enables the implementation of a driver based adaptive ifs algorithm for collision reduction, which is similar to intel's other ethernet products (e.g. pro/100 adapters). refer to ?ait ? adaptive ifs throttle register? on page 1495 for explicit details. essentially, the adaptive ifs throttles back-to-back transmissions in the transmit mac and delays their transfer to the csma/cd transmit function, and thus can be used to delay the transmission of back-to-back packets on the wire. normally, this register should be set to 0. however, if additional delay is desired between back-to-back transmits, then this register may be set with a value greater than zero. the ait.aifs provides a similar function to tipg.igpt (see ?tipg ? transmit ipg register? on page 1493 ). however this adaptive ifs throttle register counts in units of gtx/mtx_clk clocks (which are 8ns, 80ns, 800ns for 10, 100, 1000 mb/s mode respectively), and is 16 bits wide, thus providing a greater maximum delay value.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1397 intel ? ep80579 integrated processor using values lower than a certain minimum (determined by the ratio of gtx/mtx_clk clock to link speed), will have no effect on back-to-back transmission. this is because the device will not start transmission until the minimum ieee ifs (9.6 us at 10mb, 960 ns at 100 b, and 96 ns at 1 gb) has been met regardless of the value of adaptive ifs. for example, if the gbe is configured for 100 mbps operation, the minimum ieee ifs at 100 mbps is 960 nanoseconds. setting aifs to a value of 10 (decimal) would not effect back-to-back transmission time on the wire, because the 800 ns delay introduced (10 * 80n s = 800 ns) is less than the minimum ieee ifs delay of 960 ns. however, setting this register with a value of 20, which corresponds to 1600 ns for the above example, would delay back-to-back transmits because the ensuing 1600 ns delay is greater than the minimum ifs time of 960 ns. it is important to note that this register has no effect on transmissions that occur immediately after receives, or on transmissions that are not back-to-back (unlike the tipg.ipgr1 and tipg.ipgr2 settings -- see ?tipg ? transmit ipg register? on page 1493 ). in addition, adaptive ifs also has no effect on re-transmission timing (re- transmissions occur after collisions). therefore, ait.aifs is only enabled in back-to- back transmission. note: the ait.aifs value is not additive to the tipg.ipgt value; instead, the actual ipg equals the larger of ait.aifs and tipg.ipgt. 37.5.8.5 flow control flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow control defined by 802.3z, is supported in the mac. the following six registers are defined for the implementation of flow control: the flow control address high register and the flow control address low register (fcah and fcal) - 6 byte flow control multicast address flow control type register (fct) - 16 bit field to indicate flow control type flow control receive threshold high register (fcrth) - 13 bit high water mark indicating receive buffer fullness flow control receive threshold low register (fcrtl) - 13 bit low water mark indicating receive buffer emptiness flow control transmit timer value register (fcttv ) - 16 bit timer value to include in transmitted pause frame flow control is implemented as a means of reducing the possibility of receive buffer overflows which result in the dropping of received packets, and allows for local controlling of network congestion levels. this may be accomplished by sending an indication to a transmitting station of a nearly-full receive buffer condition at a receiving station. the implementation of asymmetric flow control allows for one link partner to send flow control packets while being allowed to ignore their reception; i.e. not required to respond to pause frames. 37.5.8.5.1 mac control frames & reception of flow control packets three comparisons are used to determine the validity of a flow control frame: ? a match on the six byte multicast address for mac control frames or to the station address of the device (receive address register 0). ? a match on the type field. ? a comparison of the mac control opcode field. the 802.3x standard defines the mac control frame multicast address as 01-80-c2- 00-00-01. this address must be loaded into the flow control address high register and the flow control address low register (fcah and fcal).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1398 order number: 320066-003us the flow control type register (fct) contains a 16 bit field which is compared against the flow control packet?s type field to determine if it is a valid flow control packet: xon or xoff. 802.3x reserves this as 0x8808. this value must be loaded into the fct . the final check for a valid pause frame is the mac control opcode. at this time only the pause control frame opcode is defined. it has a value of 0x0001. frame based flow control differentiates xoff from xon based on the value of the pause timer field. non-zero values constitute xoff frames while a value of zero constitutes an xon frame. values in the timer field are in units of slot time. a ?slot time? is hard wired to 64 byte times, or 512ns. note: an xon frame signals the cancellation of the ?pause? initiated by an xoff frame. ?pause for zero slot times.? where ?s? is the start-of-packet delimiter and ?t? is the first part of the end-of-packet delimiters for 802.3z encapsulation. the receiver is enabled to receive flow control frames via the device control register (ctrl.rfce). note: flow control capability must be negotiated between link partners via the auto- negotiation process. the auto-negotiation process may modify the value of these bits based on the resolved capability between the local device and the link partner. once the receiver has validated the reception of an xoff, or pause frame, the device will: ? increment the appropriate statistics register(s) ? set the status.txoff bit ? initialize the pause timer based on the packet's pause timer field figure 37-47.802.3x mac control frame format (min_framesize -160)/8 bytes preamble... sfd s fcs t up to 6 bytes 1 byte 1 byte destination address 6 bytes source address 6 bytes type/length 2 bytes mac control opcode 2 bytes mac control parameters 1 byte 4 bytes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1399 intel ? ep80579 integrated processor ? disable packet transmission or schedule the disabling of transmission after the current packet completes. resumption of transmission may occur after: ? expiration of the pause timer ? reception of on xon frame (a frame with its pause timer set to 0) either condition clears the device status register (status.txoff) and transmission may resume. hardware records the number of received xon frames. 37.5.8.5.2 ?discard pause frames? & ?pass mac control frames? two bits in the receive control register are implemented specifically for control over receipt of pause and mac control frames. these bits are discard pause frames (rctl.dpf) and pass mac control frames (rctl.pmcf). see ?rctl ? receive control register? on page 1474 for explicit definitions. rctl.dpf bit will force the discarding of any valid pause frame addressed to the device's station address. if the packet is a valid pause frame and is addressed to the station address (receive address [0]), the device will not pass the packet to host memory if rctl.dpf bit is set to logic high. however, if a flow control packet is sent to the station address, and is a valid flow control frame, it will be dma'd when rctl.dpf is set to zero. this bit has no affect on pause operation, only the dma function. rctl.pmcf bit allows for the passing of any valid mac control frames to the system which do not have a valid pause opcode. in other words, the frame must have the correct mac control frame multicast address (or the mac station address) as well as the correct type field match with the fct register, but will not have the defined pause opcode of 0x0001. frames of this type are dma'd to host memory when rctl.pmcf is logic high. 37.5.8.5.3 transmission of pause frames transmission of pause frames is enabled by software with the device control register ( ctrl .tfce). note: similar to the reception flow control packets mentioned above, xoff packets may be transmitted only if this configuration has been negotiated between the link partners via the auto-negotiation process. in other words, the setting of this bit indicates the desired configuration. the resolution of the auto-negotiation process is indicated in ?physical layer auto-negotiation & link setup features? on page 1394 . the content of the flow control receive threshold high register determines at what point hardware transmits a pause frame. hardware monitors the fullness of the receive fifo and compares it with the contents of fcrth. when the threshold is reached, hardware sends a pause frame with its pause time field equal to fcttv register. once the receive buffer fullness reaches the low water mark, hardware sends an xon message (a pause frame with a timer value of 0). software enables this capability with the flow control receive threshold low register (fcrtl.xone). hardware will send one more pause frame if it has previously sent one and the fifo overflows (so the threshold must not be set greater than the fifo size). this is intended to minimize the amount of packets dropped if the first pause frame does not reach its target. since the secure receive packets use the same data path, the behavior is identical when secure packets are received. note: the transmission of flow control frames should only be enabled in full duplex mode per the ieee 802.3 standard. software should ensure that the transmission of flow control packets is disabled when the device is operating in half-duplex mode.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1400 order number: 320066-003us 37.5.8.5.4 software initiated pause frame transmission the gbe has the added capability to transmit an xoff frame via software. this is accomplished by software using the transmit control register (tctl.swxoff). once this bit is set, hardware will initiate the transmission of a pause frame in a manner similar to that automatically generated by hardware. tctl .swxoff is self clearing after the pause frame has been transmitted. the state of the ctrl .tfce bit or the negotiated flow control configuration does not affect software generated pause frame transmission. note: software sends an xon frame by programming a zero in the pause timer field of the fcttv register. xoff transmission is not supported in 802.3x for half duplex links. software should not initiate an xoff or xon transmission if the device is configured for half duplex operation. 37.5.9 802.1q vlan support the gbe provides specific mechanisms to support 802.1q vlans, namely: ? optional adding (for transmits) and ping (for receives) of ieee 802.1q vlan tags. ? optional ability to filter packets belonging to certain 802.1q vlans. the difference between an untagged 802.3 ethernet packet and an 802.1q vlan tagged packet is minimal, as shown in table 37-4 . 37.5.9.0.1 802.1q tagged frames for 802.1q, the tag header field consists of four octets comprised of the tag protocol identifier (tpid) and tag control information (tci); each taking 2 octets. the first 16 bits of the tag header makes up the tpid. it contains the ?protocol type? which identifies the packet as a valid 802.1q tagged packet. the two octets making up the tci contain three fields: ? user priority (up) ? canonical form indicator (cfi), which should be ?0? for transmits. for receives, the device has the capability to filter out packets that have this bit set. refer to rctl.cfien and rctl.cfi described in section 37.6.4.1, ?rctl ? receive control register? . ? vlan identifier (vid) table 37-4. untagged 802.3 packet vs 802.1q vlan tagged packet 802.3 packet number of octets 802.1q vlan packet number of octets da 6 da 6 sa 6 sa 6 type/length 2 802.1q tag 4 data 46-1500 type/length 2 crc 4 data 46-1500 crc * 4 * the crc for the 802.1q tagged frame is re-computed, so that it covers the entire tagged frame including the 802.1q tag header. also, max frame size for an 802.1q vlan packet is 1522 octets as opposed to 1518 octets for a normal 802.3z ethernet packet.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1401 intel ? ep80579 integrated processor 37.5.9.1 transmitting and receiving 802.1q packets since the 802.1q tag is only four bytes, adding and stripping of tags could be done completely in software. (i.e., for transmits, software inserts the tag into packet data before it builds the transmit descriptor list, and for receives, software strips the 4 byte tag from the packet data before delivering the packet to upper layer software.) however, because adding and stripping of tags in software results in more over-head for the host, the gbe has additional capabilities to add and strip tags in hardware. 37.5.9.1.1 adding 802.1q tags on transmits software may command the gbe to insert an 802.1q vlan tag on a per packet basis. if ctrl.vme is set to 1, and the vle bit in the transmit descriptor is set to 1, then the ep80579?s gbe will insert a vlan tag into the packet that it transmits over the wire. the tag protocol identifier (tpid) field of the 802.1q tag comes from the vet register, and the tag control information (tci) of the 802.1q tag comes from the special field figure 37-9, ?special descriptor field layout? on page 1358 of the transmit descriptor. refer to table 37-2, ?vlan tag insertion decision table when vlan mode enabled (ctrl.vme=1)? on page 1368 , for more information regarding hardware insertion of tags for transmits. similarly, software can instruct the gbe to insert an 802.1q vlan tag for secure packets. software gives the command ?transmit with vlan? to the security subsystem to instruct hardware that a vlan tag should be inserted before the packet is sent on the wire. the tag protocol identifier (tpid) field of the 802.1q tag comes from the vet register, and the tag control information (tci) of the 802.1q tag is specified in the ?transmit with vlan? command itself. 37.5.9.1.2 stripping 802.1q tags on receives software may instruct the gbe to strip 802.1q vlan tags from received packets. if the ctrl.vme bit is set to 1, and the incoming packet is an 802.1q vlan packet (i.e. it's ethernet type field matched the vet register), then the ep80579?s gbe strips the 4 byte vlan tag from the packet, and stores the tci in the special field (see figure 37-9, ?special descriptor field layout? on page 1358 ) of the receive descriptor. the ep80579?s gbe also sets the vp bit in the receive descriptor to indicate that the packet had a vlan tag that was stripped. if the ctrl.vme bit is not set, the 802.1q packets can still be received if they pass the receive filter, but the vlan tag will not be stripped and the vp bit will not be set. refer to table 37-5 on page 1402 for more information regarding receive packet filtering. 37.5.9.2 802.1q vlan packet filtering vlan filtering is enabled by setting the rctl.vfe bit to 1. if enabled, hardware compares the type field of the incoming packet to a 16 bit field in the vlan ethertype register (vet). if the vlan type field in the incoming packet matches the vet register, the packet is then compared against the vlan filter table array for acceptance. figure 37-48.tci bit ordering octet 1 octet 2 up cfi vid
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1402 order number: 320066-003us the virtual lan id field indexes a 4096 bit vector. if the indexed bit in the vector is one; there is a virtual lan match. software may set the entire bit vector to ones if the node does not implement 802.1q filtering. the register description of the vlan filter table array is described in detail in ?vfta[0-127] ? 128 vlan filter table array registers? on page 1490 . in summary, the 4096 bit vector is comprised of 128, 32-bit registers. matching to this bit vector follows the same algorithm as indicated in section 0 for multicast address filtering. the vlan identifier (vid) field consis ts of 12 bits. the upper 7 bits of this field are decoded to determine the 32-bit register in the vlan filter table array to address and the lower 5 bits determine which of the 32 bits in the register to evaluate for matching. two other bits rctl.cfien and rctl.cfi (refer to ?rctl ? receive control register? on page 1474 ), are also used in conjunction with 802.1q vlan filtering operations. rctl.cfien enables the comparison of the value of the rctl.cfi bit to the 802.1q packet data as an acceptance criteria for the packet. note: the vfe bit does not effect whether the vlan tag is stripped. it only effects whether the vlan packet passes the receive filter. the following table lists reception actions per control bit settings. note: a packet is defined as a vlan/802.1q packet if its type field matches the vet . 37.5.10 wake on lan two types of wakeup mechanisms are supported: ? advanced power management (apm) wakeup ? acpi power management wakeup when so configured, if a wake-up packet is received, the gbe_pme_wake signal will be asserted. the gbe_pme_wake signal of all three gbe macs are wired-or together and brought to the external pin gbe_pme_wake. the user must externally connect this pin to the pme_n input pin. 37.5.10.1 advanced power management wakeup ?advanced power management wakeup?, or ?apm wakeup?, was previously known as ?wake on lan?. it is an feature that has existed in ethernet nics for several generations. the basic premise is to receive a broadcast or unicast packet with an table 37-5. packet reception decision table is packet 802.1q? ctrl. vme rctl. vfe action no x x normal packet reception yes 0 0 receive a vlan packet if it passes the standard filters (only). leave the packet as received in the data buffer. vp bit in receive descriptor is clear. yes 0 1 receive a vlan packet if it passes the standard filters and the vlan filter table. leave the packet as received in the data buffer (e.g. the vlan tag would not be stripped). vp bit in receive descriptor is clear. yes 1 0 receive a vlan packet if it passes the standard filters (only). strip off the vlan information (four bytes) from the incoming packet and store in the descriptor. set vp bit in receive descriptor. yes 1 1 receive a vlan packet if it passes the standard filters and the vlan filter table. strip off the vlan information (four bytes) from the incoming packet and store in the descriptor. set vp bit in receive descriptor.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1403 intel ? ep80579 integrated processor explicit data pattern, and then to assert a signal to wake-up the system. in the earlier generations, this was accomplished by using a special signal that ran across a cable to a defined connector on the motherboard. the nic would assert the signal for approximately 50ms to signal a wakeup. in more recent implementations, the pci pme# signal has been used to wake-up the system. on power-up, the apm enable bits from the eeprom initialization control word 2 are read into the apm enable (apme) bits of the wakeup control register (wcr). these bits control enabling of apm wakeup. when apm wakeup is enabled, the controller checks all incoming packets for ?magic packets?. once a matching magic packet is received, the following occurs: ? if the assert pme on apm wakeup (apmpme) bit is set in the wake up control register (wucr): ? set the pme_status bit in the power management control / status register (pmcsr) and assert gbe_pme_wake. ? set the magic packet received bit in the wake up status register (wus). the controller will assert gbe_pme_wake until the driver does one of the following: ? clears the magic packet received amag bit in the wake up status register (wus) ? clears the assert pme on apm wakeup (apmpme) bit in the wake up control register (wuc) ?disables apm wakeup. ?apm wakeup? is supported in all power states and only disabled if a subsequent eeprom read results in the apm wake up bi t being cleared or the software explicitly writes a 0 to the apm wake up (apm) bit of the wuc register. 37.5.10.2 acpi power management wakeup three sources of acpi power management based wakeups are supported: ? reception of a ?magic packet?. reception of a network wakeup packet. activating acpi power management wakeup requires the following steps: ? the driver programs the wake up filter control register (wufc) to indicate the packets it wishes to wake up and supplies the necessary data to the ipv4/v6 address table (ip4at, ip6at) and the flexible filter mask table (f), flexible filter length table (fflt), and the flexible filter value table (ffvt). the os writes a 1 to the pme_en bit of the power management control / status register (pmcsr.8). normally, after enabling wakeup, the os will write (11)b to the lower two bits of the pmcsr to put the gbe controller into low-power mode. once wakeup is enabled, the controller monitors incoming packets, first filtering them according to its standard address filtering method, then filtering them with all of the enabled wakeup filters. if a packet passes both the standard address filtering and at least one of the enabled wakeup filters, the controller will: ? set the pme_status bit in the power management control / status register (pmcsr) ? if the pme_en bit in the power management control / status register (pmcsr) is set, assert gbe_pme_wake.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1404 order number: 320066-003us ? set one or more of the ?received? bits in the wake up status register (wus). (the controller will set more than one bit if a packet matches more than one filter.) gbe_pme_wake will remain asserted until the os either writes a 1 to the pme_status bit of the pmcsr register or writes a 0 to the pme_en bit. after receiving a wakeup packet, the controller will ignore any subsequent wakeup packets until the driver clears all of the ?received? bits in the wake up status register (wus). 37.5.10.3 wake-up packets: pre-defined filters various wakeup packets are supported using two types of filters: ? pre-defined filters ?flexible filters each of these filters will be enabled if the corresponding bit in the wake up filter control register (wufc) is set to 1. this section describes the functioning of the pre-defined filters. the following packets are supported by the pre-defined filters: ? directed packet (including exact, multicast indexed, and broadcast) ?magic packet ? arp/ipv4 request packet ? directed ipv4 packet ? directed ipv6 packet each of these filters will be enabled if the corresponding bit in the wakeup filter control register (wufc) is set to 1. the explanation of each filter includes a table showing which bytes at which offsets are compared to determine if the packet passes the filter. vlan and llc/snap packets various tables may also include a reference to a possible vlan tag and llc/snap header. the controller detects vlan and llc/snap frames by checking the initial size/ type field. it first checks for a vlan header by comparing the size/type field to the value programmed in the vlan ethertype register. if the field matches then the frame is considered a vlan frame. it will then check the vlan id against the values programmed in the vlan filter table array. if the id matches the packet processing continues. if the id doesn't match, or the ctrl.vme bit is 0, and the vlan tag is listed as ?compare? in the table, the packet will not be considered a wakeup packet. after processing a possible vlan tag the controller will check for a llc/snap header. if the size/type field is less than or equal to 1500 bytes, the controller will check the following 6 bytes for the pattern aa_aa_03_00_00_00. if the pattern matches then the packet processing continues. if the patter n doesn't match, and the llc/sap header is listed as ?compare? or ?check? in the table the packet will not be considered a wakeup packet.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1405 intel ? ep80579 integrated processor 37.5.10.3.1 directed exact packet the gbe controller will generate a wakeup event upon reception of any packet whose destination address matches one of the 16 valid programmed receive addresses if the directed exact wake up enable bit is set in the wake up filter control register (wufc.ex). 37.5.10.3.2 directed multicast packet for multicast packets, the upper bits of the incoming packet's destination address index a bit vector in the multicast table array, that indicates whether to accept the packet. if the directed multicast wake up enable bit set in the wake up filter control register (wufc.mc) and the indexed bit in the vector is one then the controller will generate a wakeup event. the exact bits used in the comparison are programmed by software in the multicast offset field of the receive control register (rctl.mo). if the mac has been configured for promiscuous mode, a multicast wakeup will occur if a broadcast packet is received. this is because a broadcast message is a special type of multicast message. refer to 802.3, section 3.2.3.1. 37.5.10.3.3 broadcast if the broadcast wake up enable bit in the wake up filter control register (wufc.bc) is set the controller will generate a wake up event when it receives a broadcast packet. 37.5.10.3.4 magic packet magic packet technology details: once the lan controller has been put into the magic packet mode, it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller that this is a magic packet frame. a magic packet frame must also meet the basic requirements for the lan technology chosen, such as source address, destination address (which may be the receiving station's ieee address or a multicast address which includes the broadcast address), and crc. the specific data sequence consists of 16 duplications of the ieee address of this node, with no breaks or interruptions. this sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. the synchronization stream allows the scanning state machine to be much simpler. the synchronization stream is defined as 6 bytes of ffh. the device will also accept a broadcast frame, as long as the 16 duplications of the ieee address match the address of the machine to be awakened. the controller will expect the destination address to either: offset # of bytes field value action comment 06 destination address programmable compare match any pre-programmed address offset # of bytes field value action comment 06 destination address compare see paragraph offset # of bytes field value action comment 06 destination address ff * 6 compare
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1406 order number: 320066-003us ? be the broadcast address (ff.ff.ff.ff.ff.ff) ? match the value in receive address register 0 (rah0, ral0). this is initially loaded from the eeprom but may be changed by the driver. ? match any other address filtering enabled by the driver. the controller will search for the contents of receive address register 0 (rah0, ral0) as the embedded ieee address. it will consider any non-ff byte after a series of at least 6 ffs to be the start of the ieee address for comparison purposes. (i.e. it will catch the case of 7 ffs followed by the ieee address). as soon as one of the first 96 bytes after a string of ffs doesn't match, it will continue to search for anther set of at least 6 ffs followed by the 16 copies of the ieee address later in the packet. note that this definition precludes the first byte of the destination address from being ff. a magic packet's destination address must match the address filtering enabled in the configuration registers with the exception that broadcast packets will be considered to match even if the broadcast accept bit of the receive control register (rctl.bam) is 0. if apm wakeup is enabled in the eeprom, the controller will start up with the receive address register 0 (rah0, ral0) loaded from the eeprom. this is to permit the controller to accept packets with the matching ieee address before the driver comes up. 37.5.10.3.5 arp/ipv4 request packet the gbe controller will support reception of arp request packets for wake up if the arp bit is set in the wake up filter control register (wufc). four ipv4 addresses are supported which are programmed in the ipv4 address table (ip4at). a successfully matched packet must contain a broadcast mac address, a type of 0x0806, an arp opcode of 0x01, and one of the four programmed ipv4 addresses. the gbe controller also handles arp request packets that have vlan tagging on both ethernet ii and ethernet snap types. offset # of bytes field value action comment 06 destination address compare mac header- processed by main address filter ... ... ... skip any 6 synchronizing stream ff ff ff ff ff ff + compare any + 6 96 16 copies of node address node address*16 compare compared to receive address register 0 (rah0, ral0) offset # of bytes field value action comment 06 destination address compare mac header- processed by main address filter 6 6 source address skip 12 s=(0/4) possible vlan tag 8100h + check id check 12+s d=(0/8) possible llc/ snap header type <= 1500 + aaaa03000000h check 12+d+ s 2 type 0806h compare arp arp header 14+d+ s 2 hw type 0001h compare
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1407 intel ? ep80579 integrated processor 37.5.10.3.6 directed ipv4 packet the lan controller will support reception of directed ipv4 packets for wake up if the ipv4 bit is set in the wake up filter control register (wufc). four ipv4 addresses are supported which are programmed in the ipv4 address table (ip4at). a successfully matched packet must contain the station's mac address, a type of 0x0800, and one of the four programmed ipv4 addresses. the gbe controller also handles directed ipv4 packets that have vlan tagging on both ethernet ii and ethernet snap types. 16+d+ s 2 protocol type 0800h compare 18+d+ s 1 hardware size 06h compare 19+d+ s 1 protocol address length 04h compare 20+d+ s 2 operation 0001h compare 22+d+ s 6 sender hw address -ignore 28+d+ s 4 sender ip address -ignore 32+d+ s 6 ta r g e t h w address -ignore 38+d+ s 4 target ip address ip4at compare may match any of 4 values in ip4at offset # of bytes field value action comment offset # of bytes field value action comment 06 destination address -compare mac header- processed by main address filter 6 6 source address skip 12 s=(0/4) possible vlan tag 8100h + check id check 12 12+s d=(0/8) possible llc/ snap header type <= 1500 + aaaa03000000h ch eck 12 12+d+ s 2 type 0800h compare ip arp header 14 14+d+ s 1 version(4-bit) / hdr length(4- bit) 4xh compare check ipv4 and header length 15 15+d+ s 1 type of service - ignore 16 16+d+ s 2 packet length - ignore 18 18+d+ s 2 identification - ignore
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1408 order number: 320066-003us 37.5.10.3.7 directed ipv6 packet the lan controller will support reception of directed ipv6 packets for wake up if the ipv6 bit is set in the wake up filter control register (wufc). one ipv6 address is supported and it is programmed in the ipv6 address table (ip6at). a successfully matched packet must contain the station's mac address, a type of 0x0800, and the programmed ipv6 address. this mac also handles directed ipv6 packets that have vlan tagging on both ethernet ii and ethernet snap types. 20 20+d+ s 2 fragment info - ignore 22 22+d+ s 1time to live - ignore 23 23+d+ s 1 protocol - ignore 24 24+d+ s 2 header checksum - ignore 26 26+d+ s 4 source ip address - ignore 30 30+d+ s 4 destination ip address ipv4at compare may match any of four values in ipv4at offset # of bytes field value action comment offset # of bytes field value action comment 06 destination address compare mac header- processed by main address filter 6 6 source address ignore 12 s=(0/4) possible vlan tag 8100h + check id check 12+s d=(0/8) possible llc/ snap header type <= 1500 + aaaa03000000h check 12+d+ s 2 type 86ddh compare ipv6 arp header 14+d+ s 1 version/ traffic class 6xh compare check ipv6 16+d+ s 3 traffic class/flow label -ignore 18+d+ s 2 payload length - ignore 20+d+ s 1next header ipv6 next header types check
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1409 intel ? ep80579 integrated processor 37.5.10.4 wake-up packets: flexible filters various wakeup packets are supported using two types of filters: ? pre-defined filters ? flexible filters each of these filters will be enabled if the corresponding bit in the wake up filter control register (wufc) is set to 1. this section describes the functioning of flexible filters. a total of four flexible filters are supported. each filter is can be configured to recognize any arbitrary pattern within the first 128 byte of the packet to configure the flexible filter, the software programs the mask values into the flexible filter mask table (ffmt) and the required values into the flexible filter value table (ffvt), and the minimum packet length into the flexible filter length table (fflt). these contain separate values for each filter. the software must also enable the filter in the wake up filter control register (wufc), and enable the overall wake up functionality must be enabled by setting pme_en in the power management control status register or the wake up control register. once enabled, the flexible filters will scan incoming packets for a match. if the filter encounters any byte in the packet where the mask bit is one and the byte doesn't match the byte programmed in the flexible filter value table (ffvt) then the filter will fail that packet. if the filter reaches the required length without failing the packet, it passes the packet and generates a wake up event. it will ignore any mask bits set to one beyond the required length. the flexible filter does not have any way to automatically skip vlan or llc/snap headers. if such headers are included the offsets of the subsequent fields must be adjusted accordingly. the following packets are listed for reference purposes only. the flexible filter could be used to filter these packets. 37.5.10.4.1 ipx diagnostic responder request packet an ipx diagnostic responder request packet must contain a valid mac address, a protocol type of 0x8137, and an ipx diagnostic socket of 0x0456. it may include llc/ snap headers and vlan tags. since filtering this packet relies on the flexible filters, which use offsets specified by the operating system directly, the operating system must account for the extra offset llc/snap headers and vlan tags. 21+d+ s 1 hop limit - ignore 22+d+ s 16 source address - ignore 38+d+ s 16 destination address ip6at compare match value in ip6at offset # of bytes field value action comment
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1410 order number: 320066-003us . 37.5.10.4.2 directed ipx packet a valid directed ipx packet contain the station's mac address, a protocol type of 0x8137, and an ipx node address that equals to the station's mac address. it may include llc/snap headers and vlan tags. since filtering this packet relies on the flexible filters, which use offsets specified by the operating system directly, the operating system must account for the extra offset llc/snap headers and vlan tags. 37.5.10.4.3 ipv6 neighbor discovery filter in ipv6, a neighbor discovery packet is used for address resolution. a flexible filter can be used to check for a ?neighborhood discovery packet?. offset # of bytes field value action comment 06 destination address compare 6 6 source address skip 12 s=(0/4) possible vlan tag compare or skip 12+s d=(0/8) possible llc/ snap header compare or skip 12+d+ s 2 type 8137h compare ipx ipx header/info 14+d+ s 16 some ipx stuff - ignore 30+d+ s 2 ipx diagnostic socket 0x0456 compare offset # of bytes field value action comment 06 destination address compare 6 6 source address skip 12 s=(0/4) possible vlan tag compare or skip 12+s d=(0/8) possible llc/ snap header compare or skip 12+d+ s 2 type 8137h compare ipx ipx header/info 14+d+ s 16 some ipx stuff - ignore 24+d+ s 2 ipx node address receive address 0 compare
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1411 intel ? ep80579 integrated processor offset # of bytes field value action comment 06 destination address compare mac header - processed by main address filter, or broadcast 6 6 source address skip 12 4 possible vlan tag see text 12+s 8 possible llc/ snap header see text 12+d+ s 2 type 86ddh compare ip ipv6 header 14+d+ s 1 version/traffic class 6x compare check ipv6 15+d+ s 3 traffic class/flow label -ignore 18+d+ s 2 payload length - ignore 20+d+ s 1 next header 3ah, 00h, 2bh, or 3ch check icmp, or ipv6 next headers: + routing (2bh) + dest options (3ch) + hop-by-hop (00h) 21+d+ s 1hop limit ffh check 22+d+ s 16 source ip address - ignore 38+d+ s 16 destination ip address -ignore 54+d+ s n possible ipv6 next headers -check process headers to get next header. header type must be routing, destination options, or hop-by-hop. icmp header 54+d+ s+n 1 type 87h check neighbor solicitation 55+d+ s 1 code 00h check 56+d+ s 2 icmp header checksum ignore neighbor discover info 58+d+ s+n 4reserved - ignore 62+d+ s+n 16 target address - check match ipv6at[0] 78+d+ s+n n possible source link-layer address -ignore ... any - - ignore packet data 58+d+ s+n 4 crc - compare validate correct
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1412 order number: 320066-003us 37.5.11 serial eeprom the gbe controller uses an eeprom device for storing product configuration information. the eeprom is divided into two general regions: ? hardware accessed - loaded by gbe controller after power-up, unit reset deassertion, d3>d0 transition, or software commanded eeprom read (ctrl_ext.ee_rst). ? software accessed - used by software only. the meaning of these registers as listed here is a convention for the software only and is ignored by the controller. 37.5.11.1 eeprom device the eeprom interface supports a microwire* interface. it expects the eeprom to be capable of 1mhz operation. the ep80579 is compatible with a 4096 bit 4-wire serial eeprom such as is compatible with a nm93c66 eeprom. this eeprom is accessed in 16-bit words, containing 256 words. the ep80579 will automatically determine whether an eeprom is connected. note: the ep80579 will only detect presence of the eeprom during power-up. 37.5.11.2 software accesses the mac provides two different methods for software access to the eeprom. it can either use the built-in controller to read the eeprom, or access the eeprom directly using the eeprom's 4-wire interface. software can use the eeprom read register (eerd) to cause the gbe controller to read a word from the eeprom that the software can then use. to do this, software writes the address to read to the read address (eerd.addr) field and simultaneously writes a 1 to the start read bit (eerd.start). the controller will read the word from the eeprom, set the read done bit (eerd.done), and put the data in the read data field (eerd.data). software can poll the eeprom read register until it sees the read done bit set, then use the data from the read data field. any words read this way are not written to internal registers. software can also directly access the eeprom's 4-wire interface through the eeprom control register (eec). it can use this for reads, writes, or other eeprom operations. to directly access the eeprom, software should follow these steps: ? write a 1 to the eeprom request bit (eec.ee_req) ? read the eeprom grant bit (eec.ee_gnt) until it becomes 1. it will remain 0 as long as the hardware is accessing the eeprom. ? write or read the eeprom using the direct access to the 4-wire interface as defined in the eeprom control & data register (eec). the exact protocol used depends on the eeprom placed on the board and can be found in the appropriate datasheet. ? write a 0 to the eeprom request bit (eec.ee_req). finally, software can cause the controller to re-read the hardware accessed fields of the eeprom (setting the mac's internal registers appropriately) by writing a 1 to the eeprom reset bit of the extended device control register (ctrl_ext.ee_rst). note: this will only cause the eeprom to be re-read. the gbe will not attempt to re-detect the presence of an eeprom.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1413 intel ? ep80579 integrated processor 37.5.11.3 signature field the only way the mac has to tell if an eeprom is present is by trying to read the eeprom. the mac will first read the initialization control word 1. it will check the received value for bits 15 and 14. if bit 15 is 0 and bit 14 is 1, it considers the eeprom to be present and valid and will read additional eeprom words and program its internal registers based on the values read. otherwise, it will ignore the values it read from the initialization control word 1 and not read any other words. 37.5.11.4 eeprom map note: if any one of the gbe interfaces is disabled then the corresponding memory locations in the eeprom for that device must be initialized to all ?0?s. the following table indicates the eeprom map to be used. table 37-6. eeprom address map word offset used by mac upper byte - bits 15:8 lower byte - bits 7:0 00h 0,1,2 init control word 1 01h 02h 03h s/w use only compatibility high compatibility low 04h s/w use only compatibility high compatibility low 05h s/w use only compatibility high compatibility low 06h s/w use only compatibility high compatibility low 07h s/w use only compatibility high compatibility low 08h s/w use only pba, byte 1 pba, byte 2 09h s/w use only pba, byte 3 pba, byte 4 0ah 0bh 0ch 0dh 0eh 0fh 10h 0 management control 11h 0 init control word 2 init control word 3 12h 0 ia byte 2 ia byte 1 13h 0 ia byte 4 ia byte 3 14h 0 ia byte 6 ia byte 5 15h 0 ipv4 byte 2 ipv4 byte 1 16h 0 ipv4 byte 4 ipv4 byte 3 17h 0 ipv6 byte 2 ipv6 byte 1 18h 0 ipv6 byte 4 ipv6 byte 3 19h 0 ipv6 byte 6 ipv6 byte 5 1ah 0 ipv6 byte 8 ipv6 byte 7 1bh 0 ipv6 byte 10 ipv6 byte 9 1ch 0 ipv6 byte 12 ipv6 byte 11
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1414 order number: 320066-003us 1dh 0 ipv6 byte 14 ipv6 byte 13 1eh 0 ipv6 byte 16 ipv6 byte 15 1fh 20h 1 management control 21h 1 init control word 2 init control word 3 22h 1 ia byte 2 ia byte 1 23h 1 ia byte 4 ia byte 3 24h 1 ia byte 6 ia byte 5 25h 1 ipv4 byte 2 ipv4 byte 1 26h 1 ipv4 byte 4 ipv4 byte 3 27h 1 ipv6 byte 2 ipv6 byte 1 28h 1 ipv6 byte 4 ipv6 byte 3 29h 1 ipv6 byte 6 ipv6 byte 5 2ah 1 ipv6 byte 8 ipv6 byte 7 2bh 1 ipv6 byte 10 ipv6 byte 9 2ch 1 ipv6 byte 12 ipv6 byte 11 2dh 1 ipv6 byte 14 ipv6 byte 13 2eh 1 ipv6 byte 16 ipv6 byte 15 2fh 30h 2 management control 31h 2 init control word 2 init control word3 32h 2 ia byte 2 ia byte 1 33h 2 ia byte 4 ia byte 3 34h 2 ia byte 6 ia byte 5 35h 2 ipv4 byte 2 ipv4 byte 1 36h 2 ipv4 byte 4 ipv4 byte 3 37h 2 ipv6 byte 2 ipv6 byte 1 38h 2 ipv6 byte 4 ipv6 byte 3 39h 2 ipv6 byte 6 ipv6 byte 5 3ah 2 ipv6 byte 8 ipv6 byte 7 3bh 2 ipv6 byte 10 ipv6 byte 9 3ch 2 ipv6 byte 12 ipv6 byte 11 3dh 2 ipv6 byte 14 ipv6 byte 13 3eh 2 ipv6 byte 16 ipv6 byte 15 3fh s/w use only software checksum 40h s/w use only pxe word 0 (software use) config 41h s/w use only pxe word 1 (software use) config 42h s/w use only pxe word (software use) pxe version 43h s/w use only pxe word (software use) efi version 44h s/w use only pxe word table 37-6. eeprom address map word offset used by mac upper byte - bits 15:8 lower byte - bits 7:0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1415 intel ? ep80579 integrated processor 37.5.11.5 hardware accessed words this section describes the eeprom words that are loaded and used by the mac. most of these bits are located into a configuration registers. the words will only be read and used if the signature field in the initialization control word 1 field correct. 37.5.11.5.1 initialization control word 1 the first word read by the mac and common for all macs. 45h s/w use only pxe word 46h s/w use only pxe word 47h s/w use only pxe word 48h s/w use only pxe word 49h s/w use only pxe word 4ah s/w use only pxe word 4bh s/w use only pxe word 4ch s/w use only pxe word 4eh s/w use only pxe word 4fh reserved 50h . . ffh available for software table 37-6. eeprom address map word offset used by mac upper byte - bits 15:8 lower byte - bits 7:0 table 37-7. initialization control word 1 bit bit acronym bit description 15:14 signature the signature field is a signature of (01)b, indicating to the device that there is a valid eeprom present. if the signature field is not (01)b, the other bits in this word are ignored, no further eeprom read is performed, and default values are used for the configuration space ids. 13:12 reserved reserved 11 reserved reserved. must be set to ?1? 10 fd full duplex. controls the mac duplex setting. 0 = half duplex 1 = full duplex in half-duplex mode, the ep80579?s gbe transmits carrier extended packets and can receive both carrier extended packets, and packets transmitted with bursting. this bit overrides the in register ctrl.fd 9 reserved reserved. must be set to ?1? 8:4 reserved reserved 3 power management 0 - the power management registers set is read only, and the mac will not execute a hardware transition to d3. 1 - full support for power management 2:0 reserved reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1416 order number: 320066-003us 37.5.11.5.2 initialization control word 2 each mac has a unique initialization control word 2. 37.5.11.5.3 initialization control word 3 each mac has a unique initialization control word 3. 37.5.11.5.4 management control word this register is unique for each mac. table 37-8. initialization control word 2 bit range bit acronym bit description 7 apm pme# enable initial value of the assert pme on apm wakeup bit in the wake up control register (wuc.apmpme). 6:0 reserved these bits must be set to ?0? table 37-9. initialization control word 3 bit range bit acronym bit description 7 d3cold_wakeup_ _adv_en configures the initial hw default value of the advd3wuc bit in the device control register (ctrl) following powerup 6:5 reserved this bit must be set to ?0? 4rgmii/rmii rgmii/rmii translation gasket select ??0? - rgmii ??1? - rmii ? initializes ctrl_aux.rgmii/rmii bit 3 reserved this bit must be set to ?0? 2apm enable initial value of advanced power management wake up enable in the wake up control register (wuc.apme). this bit is also used to initialize the slu bit in the ctrl register. 1:0 link mode initial value of link mode bits of the extended device control register (ctrl_ext.link_mode), specifying which link interface and protocol is used by the mac. 00 = mac operates in gmii/mii mode 01 = reserved 10 = reserved 11 = reserved table 37-10. management control word bit bit acronym bit description 15:13 reserved reserved. set to 0. 12:8 reserved reserved. set to 0. 7 ipv6 address valid ipv6 address in the ip address eeprom register is valid. this is written to bit 16 of the ip address valid (ipav[16]) register. 6 ipv4 address valid ipv4 address in the ip address eeprom register is valid. this is written to bit 0 of the ip address valid (ipav[0]) register. 5:0 reserved reserved. set to 0.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1417 intel ? ep80579 integrated processor 37.5.11.5.5 ethernet address the ethernet individual address (ia) is a 6 byte field that must be unique for each adapter card, and thus unique for each mac. the first three bytes define a group of individual addresses which are allocated to a specific vendor - for example, [00 aa 00] or [e9 07 00] was allocated for certain intel products. the remaining three-bytes are allocated in manufacturing to form a unique value for each eeprom image. these values change regularly as new products are introduced and/or allocated during in production. the value from this eeprom field is loaded into the receive address register 0 (ral0/rah0). for the purpose of this specification, the ia byte numbering convention is indicated below: 37.5.11.5.6 ipv4 address 37.5.11.5.7 ipv6 address 37.5.11.6 software accessed words 37.5.11.6.1 compatibility fields five words in the eeprom image are reserved for compatibility information. hardware does not use these fields or impose any restrictions on their use. 37.5.11.6.2 pba number two words in the eeprom image are reserved for pba information. hardware does not use these fields or impose any restrictions on their use. ia byte / value 12 3 4 5 6 field vendor- specific vendor- specific vendor- specific unique unique unique example e9 07 00 variable variable variable table 37-11. ipv4 address bit name bit description 31:0 ipv4 address the initial value of ip4at address table entry 0. (ip4at[0]) see the eeprom map for an indication of how the bytes are stored. table 37-12. ipv6 address bit name bit description 127:0 ipv6 address the initial value of ipv6 address table entry 0. (ip6at[0]) see the eeprom map for an indication of how the bytes are stored.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1418 order number: 320066-003us 37.5.11.6.3 checksum word calculation the checksum word (3fh) is used to ensure that the base eeprom image is a valid image. the value of this word should be calculated by adding all the words (00h-3fh), including the checksum word itself. note: hardware does not calculate the word 3fh checksum during eeprom write; it must be calculated by software independently and included in the eeprom write data. hardware does not compute a checksum over words 00h-3fh during eeprom reads in order to determine validity of the eeprom image; this field is provided strictly for sw verification of eeprom validity. all hardware configuration based on word 00h-3fh content is based on the validity of the signature field of eeprom initialization control word 1 (signature must be 01b). 37.5.12 error handling the overall principles and goals of error handling for the ep80579 are covered in chapter 5.0, ?error handling? . this section covers the specifics of error handling including bus errors and soft errors for this unit. 37.5.12.1 csr (target) accesses the following conditions must be met for a csr access to be considered valid: ? command must be csr read or csr write ? length must be 0 (e.g.-4 bytes) ? byte mask must be 0x0f, 0xf0, or 0x00 if the command violates any of the above conditions then the icr.err_intbus condition is asserted: ? all unsupported command types (i.e. those other than csr read or csr write) are undefined operations and will result in indeterminate behavior by the gbe target. ? all single csr writes are assumed to be 32-bit and will complete normally regardless of the byte mask value. writes using an unsupported byte mask will still be flagged as an error as currently documented but will nonetheless be processed as a 32-bit write ? read and write burst operations (length > 0) will be completed on the push/pull buses as single operations. reads will return 0xffff_ffff for data and will assert the push_data_err signal to the requestor. write operations will discard the pull data and the requested csr or memory write will not be performed. ? if the data source of a csr write operation asserts the internal_bus_data_error signal, then the gbe target discards the data and the write operation is not performed. the generation of the icr .err_intbus condition causes the intbus_err_stat register to be updated. 37.5.12.2 dma host (master) accesses if the gbe is a master and receives a push data error during a read transaction, then an icr .err_intbus condition is generated and the intbus_err_stat register is updated. all transactions are terminated. this condition is considered fatal and further host transaction requests from the gbe unit are inhibited, until a soft reset is issued.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1419 intel ? ep80579 integrated processor 37.5.12.3 internal memories the internal memories are protected via various means to reduce the ser associated with this unit. all memories must be scrubbed to ensure proper operation. the gbe ecc/parity protected memories indicated in figure 37-49 may be tested with the memory error test register (met). the register will force an error to be written into the memory area selected with the met.select field. the met.mask field will be xor?d with the ecc or parity bits to insert a parity error into the selected memory, which will cause an error when the memory is read at a later time. errors will be reported in the appropriate bits of the three icr registers. functional or error interrupt(s) may be generated if enabled. the specifics of the memory protection for each of the memories is shown in table 37-13, ?memory protection? on page 1419 . figure 37-49.memory protection in the gbe dma engine pb rx filter rx descr buffer tx descr buffer rx mac tx mac crc checked here internal bus ethernet rx ethernet crc added here ecc parity ecc ecc statistic registers ecc ethernet tx flex filters parity table 37-13. memory protection memory size protection type protection bits description statistic registers 64 x 32 ecc 8 8-bit ecc code is computed on 32-bit data padded with 0s out to 64 bits for a total of 8 ecc bits (64x40) rx filters 128 x 32 parity 4 parity computed on each byte for a total of 4 parity bits (128x36) rx flex filters 128 x 36 parity 4 parity computed on each of 4 of the filter value and on 4 bits of the filter mask for a total of 5 parity bits (128x41)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1420 order number: 320066-003us statistic registers: in the event of a multi-bit ecc error, an interrupt event will be generated in icrx.err_stat and the gbe unit will stop all host transmit and receive access to memory, as well as inhibit gbe transmit data. the gbe unit will still remain accessible through the gbe target interface. it is a software task to detect the event, issue the soft reset to clear the icrx.err_stat bit and decide what to do with the erroneous data from the statistics register. rx filters: in the event of an error from either the multicast filter memory or the special packets filter memory the packet will be rejected, appropriate statistic registers will be updated, and an icrx.err_mcfspf event will be generated. further gbe dma read/write transactions will not be inhibited, nor will transmit traffic be inhibited. rx flex filters: in the event of a parity error from either any of the flex filter memories the appropriate statistic re gisters will be updated, and an icrx.err_mcfspf event will be generated. additionally, if wake on lan filtering is enabled, a pme_wake event will be generated. dma tx descriptor buffer: in the event of an ecc error, a icrx.err_txds event will be generated and the gbe unit will stop all host transmit and receive access to memory, as well as inhibit gbe transmit data. the gbe unit will still remain accessible through the gbe target interface. the error indicates the descriptor memory has become untrustworthy and host accesses are stopped to avoid corruption of other interfaces. it is a software task to detect the event and issue the required soft reset for recovery. dma rx descriptor buffer : in the event of an ecc error, a icrx.err_rxds event will be generated and the gbe unit will stop all host transmit and receive access to memory, as well as inhibit gbe transmit data. the gbe unit will still remain accessible through the gbe target interface. the error indicates the descriptor memory has become untrustworthy and host accesses are stopped to avoid corruption of other interfaces. it is a software task to detect the event and issue the required soft reset for recovery. dma packet buffer during transmit or receive: in the event of an ecc error, a icrx.err_pb event will be generated and the gbe unit will stop all host transmit and receive access to memory, as well as inhibit gbe transmit data. the gbe unit will still remain accessible through the gbe target interface. the error indicates the packet buffer memory has become untrustworthy and host accesses are stopped to avoid corruption of other interfaces. it is a software task to detect the event and issue the required soft reset for recovery. 37.5.13 reset operation the gbe implements multiple hardware and software-initiated reset mechanisms which should be understood and distinguished: dma tx descriptor buffer 64 x 128 ecc 16 8-bit ecc code is computed on each of the upper and lower 64-bits of the 128-bit data for a total of 16 ecc bits (64x144) dma rx descriptor buffer 64 x 128 ecc 16 8-bit ecc code is computed on each of the upper and lower 64-bits of the 128-bit data for a total of 16 ecc bits (64x144) dma packet buffer 4k x 128 ecc 16 8-bit ecc code is computed on each of the upper and lower 64-bits of the 128-bit data for a total of 16 ecc bits (4kx144) table 37-13. memory protection memory size protection type protection bits description
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1421 intel ? ep80579 integrated processor ? sys_pwr_ok reset - the sys_pwr_ok pin acts as a master reset of the entire chip. it is level sensitive, and while it is 0 will hold all hw registers (state and configuration) in reset. sys_pwr_ok is interpreted to be an indication that device power supplies are all stable and the reference clock input is stable. ? unit reset /reset_n - this pin indicates the reset state of the internal bus. when asserted, the ep80579 will force all gbe output signals to an inactive state. upon deassertion, the gbe will generate an inte rnal hardware reset, clearing all states, and resetting all configuration registers to hw defaults as specified in ?registers overview? on page 1425 . ? d3->d0 transition - this is also known as acpi reset. the gbe generates an internal hardware reset on the transition from d3 power state to d0, which clears all and resets nearly all configuration to hw defaults as specified in this document. ? soft reset - software can reset the gbe by writing the ?ctrl ? device control register? on page 1438 (ctrl .rst). a soft reset clears all states and resets nearly all device control registers to hw defaults as specified in ?registers overview? on page 1425 . note: software must wait a minimum of 5 ms after initiating a soft- reset before accessing any csr. ? eeprom reset - writing a 1 to the eeprom reset bit of the extended device control register (ctrl_ext.ee_rst) will cause the gbe to re-read the eeprom, setting the appropriate bits in the mac registers whose hw default values are derived from the eeprom. the various resets affect the following registers and logic: 1. if aux_power=0 the wakeup context is reset 2. n/a 3. the configuration registers include: ? general registers ? interrupt registers ? receive registers table 37-14. gbe reset effects reset operation pwr_good reset unit reset d3-> d0 soft (ctrl.rst) link (los deassert) eeprom notes effects to: enable/disable lan xx tri-state output pins xx data path xxxx configuration registers xxxxx 3 read eeprom xxxx 4 wake up context x111 5 wake up control register x wake up status registers x
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1422 order number: 320066-003us ?transmit registers ? statistics registers ? diagnostic registers of these registers, rah/ral, mta[127:0], vfta[127:0], tdbah/tdbal, and rdbah/rdbal registers have no default value. if the functions associated with the registers are enabled they must be programmed by software. once programmed, their value is preserved through all resets as long as power is applied to the be. 4. see explanation of ?eeprom resets? above 5. the wake up context is defined in the pci bus power management interface specifications. if includes: ? pme_en bit of the power management control/status register (pmcsr) ? pme_status bit of the power management control/status register (pmcsr) ? the shadow copies of these bits in the wakeup control register are treated identically. note: in situations where the device is reset using ctrl.rst, the tx data lines will be forced to all zeros. this will cause a substantial number of symbol errors to be detected by the link partner. 37.5.13.1 soft reset this section describes software considerations when using the soft reset. a soft reset operation is invoked by software via the device control register (ctrl.rst). the internal hardware reset is delayed until the internal bus is observed to be idle, in order to ensure that no hardware bus protocols are violated. for the next 5 msec, the gbe component is undergoing a low-level hardware reset and re-read of eeprom in order to re-establish hw defaults. during this time, the gbe will not respond to accesses to the device for a duration of approximately 5 msec. note: software must not access the gbe device for a minimum of 5 msec after writing the soft-reset bit. failure to do so may result in a system hang condition. an explicit software wait of 5 milliseconds is necessary to ensure that the device has completed its reset and will respond again. ctrl.rst self clears upon completion of the reset operation. while the above required wait interval is necessary to ensure that the reset operation is complete, a read of the device control register may be done after the wait interval to confirm the completion of the reset. 37.5.13.2 mac disable this feature allows the mac and the i/o pins to be put into a very low-power mode. the intended usage of this feature is when the gbe will not be used in the system (no phy connected). when the gbe is disabled, all internal clocks are disabled and the gbe is held in reset. the device does not respond to internal bus transactions. effectively, the unit becomes invisible to the system. 37.5.14 endianness bytes for a receive packet arrive in the order shown from left to right: da0 da1 da2 da3 da4 da5 sa0 sa1 and so on. if the data were to be written to memory in the order of arrival with the first byte written to the lowest address and each subsequent
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1423 intel ? ep80579 integrated processor byte written at the next higher address then the data would appear in memory as shown in table 37-15, ?long word little endian, byte little endian ordering? on page 1423 . to allow flexibility in software models, two bits are provided to allow the endianness swizzling described below to be applied to ei ther the descriptor data or the packet data or both or neither. these bits are also located in the ctrl_aux ? auxiliary device control/status register . the modes corresponding to these two bits is shown below: table 37-15. long word little endian, byte little endian ordering byte address bit 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 0 sa1 sa0 da5 da4 da3 da2 da1 da0 8 tos 45 00 08 sa5 sa4 sa3 sa2 16 06 ttl frag lsb f/f msb id lsb id msb len lsb len msb 24 ipda1 ipda0 ipsa3 ipsa2 ipsa1 ipsa0 hcs lsb hcs msb 32 pb5 pb4 pb3 pb2 pb1 pb0 ipda3 ipda2 table 37-16. endianness control for gigabit ethernet macs csr value meaning 00 lw little-endian, byte big-endian ( table 37-17 ) 01 lw little-endian, byte little-endian ( table 37-18 ) 10 lw big-endian, byte big-endian ( table 37-19 ) 11 lw big-endian, byte little-endian ( table 37-20 ) table 37-17. endianness mode 0: long word little endian, byte big endian byte address bit 63:56 bit 55:48 bit 47:40 bit 39:32 bit 31:24 bit 23:16 bit 15:8 bit 7:0 0 da4 da5 sa0 sa1 da0 da1 da2 da3 8 08 00 45 tos sa2 sa3 sa4 sa5 16 f/f msb frag lsb ttl 06 len msb len lsb id msb id lsb 24 ipsa2 ipsa3 ipda0 ipda1 hcs msb hcs lsb ipsa0 ipsa1 32 pb2 pb3 pb4 pb5 ipda2 ipda3 pb0 pb1 table 37-18. endianness mode 1: long word little endian, byte little endian (default) byte address bit 63:56 bit 55:48 bit 47:40 bit 39:32 bit 31:24 bit 23:16 bit 15:8 bit 7:0 0 sa1 sa0 da5 da4 da3 da2 da1 da0 8 tos 45 00 08 sa5 sa4 sa3 sa2 16 06 ttl frag lsb f/f msb id lsb id msb len lsb len msb 24 ipda1 ipda0 ipsa3 ipsa2 ipsa1 ipsa0 hcs lsb hcs msb 32 pb5 pb4 pb3 pb2 pb1 pb0 ipda3 ipda2
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1424 order number: 320066-003us table 37-19. endianness mode 2: long word big endian, byte big endian byte address bit 63:56 bit 55:48 bit 47:40 bit 39:32 bit 31:24 bit 23:16 bit 15:8 bit 7:0 0 da0 da1 da2 da3 da4 da5 sa0 sa1 8 sa2 sa3 sa4 sa5 08 00 45 tos 16 len msb len lsb id msb id lsb f/f msb frag lsb ttl 06 24 hcs msb hcs lsb ipsa0 ipsa1 ipsa2 ipsa3 ipda0 ipda1 32 ipda2 ipda3 pb0 pb1 pb2 pb3 pb4 pb5 table 37-20. endianness mode 3: long word big endian, byte little endian byte address bit 63:56 bit 55:48 bit 47:40 bit 39:32 bit 31:24 bit 23:16 bit 15:8 bit 7:0 0 da3 da2 da1 da0 sa1 sa0 da5 da4 8 sa5 sa4 sa3 sa2 tos 45 00 08 16 id lsb id msb len lsb len msb 06 ttl frag lsb f/f msb 24 ipsa1 ipsa0 hcs lsb hcs msb ipda1 ipda0 ipsa3 ipsa2 32 pb1 pb0 ipda3 ipda2 pb5 pb4 pb3 pb2
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1425 intel ? ep80579 integrated processor 37.6 gbe controller register summary this section details the programmer-visible state inside the gbe controller. in some cases, it describes hardware structures invisible to software in order to clarify a concept. the gbe address space is directly memory-mapped to 128 kbyte of internal registers and memories. this register and memory space is divided into the following categories: ? general ? receive ?transmit ? statistics ? diagnostics (including packet buffer memory access) ? the external phy registers are accessed through the mdio interface. (for more information on mdio, see ?global configuration unit?.) 37.6.1 registers overview the gigabit ethernet controller registers materialize in pci space. for more information on the conventions the following register summaries adopt, see section 7.1, ?overview of register descriptions and summaries? on page 183 . note: the completion of any csr access will be held off (maximum estimated delay 5ms) if initiated prior to completion of hw initialization (e.g.-eeprom read). this behavior is transparent to software. table 37-21 , table 37-22 , and table 37-23 summarize the gigabit ethernet interface #0, #1, and #2 materializations from the pci perspective. table 37-21. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 1 of 4) offset start offset end register id - description default value 0000h 0003h ?ctrl: device control register? on page 1438 00000a09h 0008h 000bh ?status: device status register? on page 1441 0000xxxxh 0018h 001bh ?ctrl_ext: extended device control register? on page 1442 00000000h 00e0h 00e3h ?ctrl_aux: auxiliary device control register? on page 1444 00000100h 0010h 0013h ?eeprom_ctrl - eeprom control register? on page 1446 00000x1xh 0014h 0017h ?eeprom_rr ? eeprom read register? on page 1448 xxxxxx00h 0028h 002bh ?fcal: flow control address low register? on page 1449 00c28001h 002ch 002fh ?fcah: flow control address high register? on page 1450 00000100h 0030h 0033h ?fct: flow control type register? on page 1451 00008808h 0038h 003bh ?vet: vlan ethertype register? on page 1452 00008100h 0170h 0173h ?fcttv: flow control transmit timer value register? on page 1452 00000000h 1000h 1003h ?pba: packet buffer allocation register? on page 1453 00100030h 00c0h 00c3h ?icr0: interrupt 0 cause read register? on page 1454 00000000h 00c4h 00c7h ?itr0: interrupt 0 throttling register? on page 1457 00000000h 00c8h 00cbh ?ics0: interrupt 0 cause set register? on page 1458 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1426 order number: 320066-003us 00d0h 00d3h ?ims0: interrupt 0 mask set/read register? on page 1459 00000000h 00d8h 00dbh ?imc0: interrupt 0 mask clear register? on page 1460 00000000h 08c0h 08c3h ?icr1: interrupt 1cause read register? on page 1462 00000000h 08c8h 08cbh ?ics1: interrupt 0 cause set register? on page 1464 00000000h 08d0h 08d3h ?ims1: interrupt 1 mask set/read register? on page 1466 00000000h 08d8h 08dbh ?imc1: interrupt 1 mask clear register? on page 1467 00000000h 08e0h 08e3h ?icr2: error interrupt cause read register? on page 1469 00000000h 08e8h 08ebh ?ics2: error interrupt cause set register? on page 1471 00000000h 08f0h 08f3h ?ims2: error interrupt mask set/read register? on page 1472 00000000h 08f8h 08fbh ?imc2: error interrupt mask clear register? on page 1473 00000000h 0100h 0103h ?rctl: receive control register? on page 1474 00000000h 2160h 2163h ?fcrtl: flow control receive threshold low register? on page 1478 00000000h 2168h 216bh ?fcrth: flow control receive threshold high register? on page 1479 00000000h 2800h 2803h ?rdbal: receive descriptor base address low register? on page 1480 xxxxxxx0h 2804h 2807h ?rdbah: receive descriptor base address high register? on page 1480 xxxxxxxxh 2808h 280bh ?rdlen: receive descriptor length register? on page 1481 00000000h 2810h 2813h ?rdh: receive descriptor head register? on page 1481 00000000h 2818h 281bh ?rdt: receive descriptor tail register? on page 1482 00000000h 2820h 2823h ?rdtr: rx interrupt delay timer (packet timer) register? on page 1483 00000000h 2828h 282bh ?rxdctl: receive descriptor control register? on page 1483 00010000h 282ch 282fh ?radv: receive interrupt absolute delay timer register? on page 1485 00000000h 2c00h 2c03h ?rsrpd: receive small packet detect interrupt register? on page 1486 00000000h 5000h 5003h ?rxcsum: receive checksum control register? on page 1487 00000000h 5200h at 4h 5203h at 4h ?mta[0-127] ? 128 multicast table array registers? on page 1488 xxxx_xxxxh 5400h at 8h 5403h at 8h ?ral[0-15] - receive address low register? on page 1488 xxxxxxxxh 5404h at 8h 5407h at 8h ?rah[0-15] - receive address high register? on page 1489 000xxxxxh 5600h at 4h 5603h at 4h ?vfta[0-127] - 128 vlan filter table array registers? on page 1490 xxxxxxxxh 0400h 0403h ?tctl: transmit control register? on page 1491 00000008h 0410h 0413h ?tipg: transmit ipg register? on page 1493 00602008h 0458h 045bh ?ait: adaptive ifs throttle register? on page 1495 00000000h 3800h 3803h ?tdbal: transmit descriptor base address low register? on page 1496 xxxxxxx0h 3804h 3807h ?tdbah: transmit descriptor base address high register? on page 1496 xxxxxxxxh 3808h 380bh ?tdlen: transmit descriptor length register? on page 1497 00000000h 3810h 3813h ?tdh: transmit descriptor head register? on page 1497 00000000h 3818h 381bh ?tdt: transmit descriptor tail register? on page 1498 00000000h 3820h 3823h ?tidv: transmit interrupt delay value register? on page 1499 00000000h 3828h 382bh ?txdctl: transmit descriptor control register? on page 1500 00000000h 382ch 382fh ?tadv: transmit absolute interrupt delay value register? on page 1502 00000000h 3830h 3833h ?tspmt: tcp segmentation pad and minimum threshold register? on page 1504 01000400h table 37-21. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 2 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1427 intel ? ep80579 integrated processor 4000h 4003h ?crcerrs: crc error count register? on page 1505 00000000h 4004h 4007h ?algnerrc: alignment error count register? on page 1506 00000000h 400ch 400fh ?rxerrc: receive error count register? on page 1506 00000000h 4010h 4013h ?mpc: missed packet count register? on page 1507 00000000h 4014h 4017h ?scc: single collision count register? on page 1507 0000h 4018h 401bh ?ecol: excessive collisions count register? on page 1508 00000000h 401ch 401fh ?mcc: multiple collision count register? on page 1508 00000000h 4020h 4023h ?latecol: late collisions count register? on page 1509 00000000h 4028h 402bh ?colc: collision count register? on page 1509 00000000h 4030h 4033h ?dc: defer count register? on page 1510 00000000h 4034h 4037h ?tncrs: transmit with no crs count register? on page 1510 00000000h 403ch 403fh ?cexterr: carrier extension error count register? on page 1511 00000000h 4040h 4043h ?rlec: receive length error count register? on page 1511 00000000h 4048h 404bh ?xonrxc: xon received count register? on page 1512 00000000h 404ch 404fh ?xontxc: xon transmitted count register? on page 1512 00000000h 4050h 4053h ?xoffrxc: xoff received count register? on page 1513 00000000h 4054h 4057h ?xofftxc: xoff transmitted count register? on page 1513 00000000h 4058h 405bh ?fcruc: fc received unsupported count register? on page 1514 00000000h 405ch 405fh ?prc64: good packets received count (64 bytes) register? on page 1514 00000000h 4060h 4063h ?prc127: good packets received count (65-127 bytes) register? on page 1515 00000000h 4064h 4067h ?prc255: good packets received count (128-255 bytes) register? on page 1515 00000000h 4068h 406bh ?prc511 - good packets received count (256-511 bytes) register? on page 1516 00000000h 406ch 406fh ?prc1023: good packets received count (512-1023 bytes) register? on page 1516 00000000h 4070h 4073h ?prc1522: good packets received count (1024 to max bytes) register? on page 1517 00000000h 4074h 4077h ?gprc: good packets received count (total) register? on page 1518 00000000h 4078h 407bh ?bprc: broadcast packets received count register? on page 1518 00000000h 407ch 407fh ?mprc: multicast packets received count register? on page 1519 00000000h 4080h 4083h ?gptc: good packets transmitted count register? on page 1519 00000000h 4088h 408ah ?gorcl: good octets received count low register? on page 1520 00000000h 408ch 408fh ?gorch: good octets received count high register? on page 1521 00000000h 4090h 4093h ?gotcl: good octets transmitted count low register? on page 1522 00000000h 4094h 4097h ?gotch: good octets transmitted count high register? on page 1522 00000000h 40a0h 40a3h ?rnbc: receive no buffers count register? on page 1523 00000000h 40a4h 40a7h ?ruc: receive undersize count register? on page 1523 00000000h 40a8h 40abh ?rfc: receive fragment count register? on page 1524 00000000h 40ach 40afh ?roc: receive oversize count register? on page 1524 00000000h 40b0h 40b3h ?rjc: receive jabber count register? on page 1525 00000000h 40c0h 40c3h ?torl: total octets received low register? on page 1526 00000000h table 37-21. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 3 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1428 order number: 320066-003us 40c4h 40c7h ?torh: total octets received high register? on page 1526 00000000h 40c8h 40cfh ?totl: total octets transmitted low register? on page 1527 00000000h 40cch 40cfh ?toth: total octets transmitted high register? on page 1528 00000000h 40d0h 40d3h ?tpr: total packets received register? on page 1528 00000000h 40d4h 40d7h ?tpt: total packets transmitted register? on page 1529 00000000h 40d8h 40dbh ?ptc64 - packets transmitted count (64 bytes) register? on page 1529 00000000h 40e0h 40e3h ?ptc255: packets transmitted count (128-255 bytes) register? on page 1530 00000000h 40e4h 40e7h ?ptc511: packets transmitted count (256-511 bytes) register? on page 1530 00000000h 40e8h 40ebh ?ptc1023: packets transmitted count (512-1023 bytes) register? on page 1531 00000000h 40ech 40efh ?ptc1522: packets transmitted count (1024-1522 bytes) register? on page 1531 00000000h 40f0h 40f3h ?mptc: multicast packets transmitted count register? on page 1532 00000000h 40f4h 40f7h ?bptc: broadcast packets transmitted count register? on page 1532 00000000h 40f8h 40fbh ?tsctc: tcp segmentation context transmitted count register? on page 1533 00000000h 40fch 40ffh ?tsctfc: tcp segmentation context transmit fail count register? on page 1533 00000000h 5800h 5803h ?wuc - wake up control register (0x05800; rw)? on page 1534 00000000h 5808h 580bh ?wufc - wake up filter control register (0x05808; rw)? on page 1535 00000000h 5810h 5813h ?wus - wake up status register (0x05810; rw)? on page 1536 00000000h 5838h 583bh ?ipav - ip address valid register (0x05838; rw)? on page 1537 00000000h 5840h at 8h 5843h at 8h ?ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers? on page 1538 xxxxxxxxh 5880h 5883h ?ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4? on page 1539 xxxxxxxxh 05884h 5887h ?ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8? on page 1539 xxxxxxxxh 5888h 588bh ?ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12? on page 1540 xxxxxxxxh 588ch 588fh ?ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16? on page 1541 xxxxxxxxh 5f00h at 8h 5f03h at 8h ?fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw)? on page 1542 00000000h 9000h at 8h 9003h at 8h ?ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1543 0000000xh 9800h at 8h 9803h at 8h ?ffvt[0-127]: flexible filter value table registers? on page 1544 xxxxxxxxh 0510h 0513h ?intbus_err_stat - internal bus error status register? on page 1544 00000000h 0900h 0903h ?mem_tst - memory error test register? on page 1546 00000000h 0904h 0907h ?mem_sts - memory error status register? on page 1547 007f0000h table 37-21. bus m, device 0, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 4 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1429 intel ? ep80579 integrated processor table 37-22. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 1 of 4) offset start offset end register id - description default value 0000h 0003h ?ctrl: device control register? on page 1438 00000a09h 0008h 000bh ?status: device status register? on page 1441 0000xxxxh 0018h 001bh ?ctrl_ext: extended device control register? on page 1442 00000000h 00e0h 00e3h ?ctrl_aux: auxiliary device control register? on page 1444 00000100h 0010h 0013h ?eeprom_ctrl - eeprom control register? on page 1446 00000x1xh 0014h 0017h ?eeprom_rr ? eeprom read register? on page 1448 xxxxxx00h 0028h 002bh ?fcal: flow control address low register? on page 1449 00c28001h 002ch 002fh ?fcah: flow control address high register? on page 1450 00000100h 0030h 0033h ?fct: flow control type register? on page 1451 00008808h 0038h 003bh ?vet: vlan ethertype register? on page 1452 00008100h 0170h 0173h ?fcttv: flow control transmit timer value register? on page 1452 00000000h 1000h 1003h ?pba: packet buffer allocation register? on page 1453 00100030h 00c0h 00c3h ?icr0: interrupt 0 cause read register? on page 1454 00000000h 00c4h 00c7h ?itr0: interrupt 0 throttling register? on page 1457 00000000h 00c8h 00cbh ?ics0: interrupt 0 cause set register? on page 1458 00000000h 00d0h 00d3h ?ims0: interrupt 0 mask set/read register? on page 1459 00000000h 00d8h 00dbh ?imc0: interrupt 0 mask clear register? on page 1460 00000000h 08c0h 08c3h ?icr1: interrupt 1cause read register? on page 1462 00000000h 08c8h 08cbh ?ics1: interrupt 0 cause set register? on page 1464 00000000h 08d0h 08d3h ?ims1: interrupt 1 mask set/read register? on page 1466 00000000h 08d8h 08dbh ?imc1: interrupt 1 mask clear register? on page 1467 00000000h 08e0h 08e3h ?icr2: error interrupt cause read register? on page 1469 00000000h 08e8h 08ebh ?ics2: error interrupt cause set register? on page 1471 00000000h 08f0h 08f3h ?ims2: error interrupt mask set/read register? on page 1472 00000000h 08f8h 08fbh ?imc2: error interrupt mask clear register? on page 1473 00000000h 0100h 0103h ?rctl: receive control register? on page 1474 00000000h 2160h 2163h ?fcrtl: flow control receive threshold low register? on page 1478 00000000h 2168h 216bh ?fcrth: flow control receive threshold high register? on page 1479 00000000h 2800h 2803h ?rdbal: receive descriptor base address low register? on page 1480 xxxxxxx0h 2804h 2807h ?rdbah: receive descriptor base address high register? on page 1480 xxxxxxxxh 2808h 280bh ?rdlen: receive descriptor length register? on page 1481 00000000h 2810h 2813h ?rdh: receive descriptor head register? on page 1481 00000000h 2818h 281bh ?rdt: receive descriptor tail register? on page 1482 00000000h 2820h 2823h ?rdtr: rx interrupt delay timer (packet timer) register? on page 1483 00000000h 2828h 282bh ?rxdctl: receive descriptor control register? on page 1483 00010000h 282ch 282fh ?radv: receive interrupt absolute delay timer register? on page 1485 00000000h 2c00h 2c03h ?rsrpd: receive small packet detect interrupt register? on page 1486 00000000h 5000h 5003h ?rxcsum: receive checksum control register? on page 1487 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1430 order number: 320066-003us 5200h at 4h 5203h at 4h ?mta[0-127] ? 128 multicast table array registers? on page 1488 xxxx_xxxxh 5400h at 8h 5403h at 8h ?ral[0-15] - receive address low register? on page 1488 xxxxxxxxh 5404h at 8h 5407h at 8h ?rah[0-15] - receive address high register? on page 1489 000xxxxxh 5600h at 4h 5603h at 4h ?vfta[0-127] - 128 vlan filter table array registers? on page 1490 xxxxxxxxh 0400h 0403h ?tctl: transmit control register? on page 1491 00000008h 0410h 0413h ?tipg: transmit ipg register? on page 1493 00602008h 0458h 045bh ?ait: adaptive ifs throttle register? on page 1495 00000000h 3800h 3803h ?tdbal: transmit descriptor base address low register? on page 1496 xxxxxxx0h 3804h 3807h ?tdbah: transmit descriptor base address high register? on page 1496 xxxxxxxxh 3808h 380bh ?tdlen: transmit descriptor length register? on page 1497 00000000h 3810h 3813h ?tdh: transmit descriptor head register? on page 1497 00000000h 3818h 381bh ?tdt: transmit descriptor tail register? on page 1498 00000000h 3820h 3823h ?tidv: transmit interrupt delay value register? on page 1499 00000000h 3828h 382bh ?txdctl: transmit descriptor control register? on page 1500 00000000h 382ch 382fh ?tadv: transmit absolute interrupt delay value register? on page 1502 00000000h 3830h 3833h ?tspmt: tcp segmentation pad and minimum threshold register? on page 1504 01000400h 4000h 4003h ?crcerrs: crc error count register? on page 1505 00000000h 4004h 4007h ?algnerrc: alignment error count register? on page 1506 00000000h 400ch 400fh ?rxerrc: receive error count register? on page 1506 00000000h 4010h 4013h ?mpc: missed packet count register? on page 1507 00000000h 4014h 4017h ?scc: single collision count register? on page 1507 0000h 4018h 401bh ?ecol: excessive collisions count register? on page 1508 00000000h 401ch 401fh ?mcc: multiple collision count register? on page 1508 00000000h 4020h 4023h ?latecol: late collisions count register? on page 1509 00000000h 4028h 402bh ?colc: collision count register? on page 1509 00000000h 4030h 4033h ?dc: defer count register? on page 1510 00000000h 4034h 4037h ?tncrs: transmit with no crs count register? on page 1510 00000000h 403ch 403fh ?cexterr: carrier extension error count register? on page 1511 00000000h 4040h 4043h ?rlec: receive length error count register? on page 1511 00000000h 4048h 404bh ?xonrxc: xon received count register? on page 1512 00000000h 404ch 404fh ?xontxc: xon transmitted count register? on page 1512 00000000h 4050h 4053h ?xoffrxc: xoff received count register? on page 1513 00000000h 4054h 4057h ?xofftxc: xoff transmitted count register? on page 1513 00000000h 4058h 405bh ?fcruc: fc received unsupported count register? on page 1514 00000000h 405ch 405fh ?prc64: good packets received count (64 bytes) register? on page 1514 00000000h 4060h 4063h ?prc127: good packets received count (65-127 bytes) register? on page 1515 00000000h 4064h 4067h ?prc255: good packets received count (128-255 bytes) register? on page 1515 00000000h 4068h 406bh ?prc511 - good packets received count (256-511 bytes) register? on page 1516 00000000h 406ch 406fh ?prc1023: good packets received count (512-1023 bytes) register? on page 1516 00000000h table 37-22. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 2 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1431 intel ? ep80579 integrated processor 4070h 4073h ?prc1522: good packets received count (1024 to max bytes) register? on page 1517 00000000h 4074h 4077h ?gprc: good packets received count (total) register? on page 1518 00000000h 4078h 407bh ?bprc: broadcast packets received count register? on page 1518 00000000h 407ch 407fh ?mprc: multicast packets received count register? on page 1519 00000000h 4080h 4083h ?gptc: good packets transmitted count register? on page 1519 00000000h 4088h 408ah ?gorcl: good octets received count low register? on page 1520 00000000h 408ch 408fh ?gorch: good octets received count high register? on page 1521 00000000h 4090h 4093h ?gotcl: good octets transmitted count low register? on page 1522 00000000h 4094h 4097h ?gotch: good octets transmitted count high register? on page 1522 00000000h 40a0h 40a3h ?rnbc: receive no buffers count register? on page 1523 00000000h 40a4h 40a7h ?ruc: receive undersize count register? on page 1523 00000000h 40a8h 40abh ?rfc: receive fragment count register? on page 1524 00000000h 40ach 40afh ?roc: receive oversize count register? on page 1524 00000000h 40b0h 40b3h ?rjc: receive jabber count register? on page 1525 00000000h 40c0h 40c3h ?torl: total octets received low register? on page 1526 00000000h 40c4h 40c7h ?torh: total octets received high register? on page 1526 00000000h 40c8h 40cfh ?totl: total octets transmitted low register? on page 1527 00000000h 40cch 40cfh ?toth: total octets transmitted high register? on page 1528 00000000h 40d0h 40d3h ?tpr: total packets received register? on page 1528 00000000h 40d4h 40d7h ?tpt: total packets transmitted register? on page 1529 00000000h 40d8h 40dbh ?ptc64 - packets transmitted count (64 bytes) register? on page 1529 00000000h 40e0h 40e3h ?ptc255: packets transmitted count (128-255 bytes) register? on page 1530 00000000h 40e4h 40e7h ?ptc511: packets transmitted count (256-511 bytes) register? on page 1530 00000000h 40e8h 40ebh ?ptc1023: packets transmitted count (512-1023 bytes) register? on page 1531 00000000h 40ech 40efh ?ptc1522: packets transmitted count (1024-1522 bytes) register? on page 1531 00000000h 40f0h 40f3h ?mptc: multicast packets transmitted count register? on page 1532 00000000h 40f4h 40f7h ?bptc: broadcast packets transmitted count register? on page 1532 00000000h 40f8h 40fbh ?tsctc: tcp segmentation context transmitted count register? on page 1533 00000000h 40fch 40ffh ?tsctfc: tcp segmentation context transmit fail count register? on page 1533 00000000h 5800h 5803h ?wuc - wake up control register (0x05800; rw)? on page 1534 00000000h 5808h 580bh ?wufc - wake up filter control register (0x05808; rw)? on page 1535 00000000h 5810h 5813h ?wus - wake up status register (0x05810; rw)? on page 1536 00000000h 5838h 583bh ?ipav - ip address valid register (0x05838; rw)? on page 1537 00000000h 5840h at 8h 5843h at 8h ?ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers? on page 1538 xxxxxxxxh 5880h 5883h ?ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4? on page 1539 xxxxxxxxh 05884h 5887h ?ipv6_addr0bytes_5_8 ? ipv6 address tabl e register, bytes 5 - 8? on page 1539 xxxxxxxxh 5888h 588bh ?ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12? on page 1540 xxxxxxxxh table 37-22. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 3 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1432 order number: 320066-003us 588ch 588fh ?ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16? on page 1541 xxxxxxxxh 5f00h at 8h 5f03h at 8h ?fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw)? on page 1542 00000000h 9000h at 8h 9003h at 8h ?ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1543 0000000xh 9800h at 8h 9803h at 8h ?ffvt[0-127]: flexible filter value table registers? on page 1544 xxxxxxxxh 0510h 0513h ?intbus_err_stat - internal bus error status register? on page 1544 00000000h 0900h 0903h ?mem_tst - memory error test register? on page 1546 00000000h 0904h 0907h ?mem_sts - memory error status register? on page 1547 007f0000h table 37-22. bus m, device 1, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 4 of 4) offset start offset end register id - description default value table 37-23. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 1 of 4) offset start offset end register id - description default value 0000h 0003h ?ctrl: device control register? on page 1438 00000a09h 0008h 000bh ?status: device status register? on page 1441 0000xxxxh 0018h 001bh ?ctrl_ext: extended device control register? on page 1442 00000000h 00e0h 00e3h ?ctrl_aux: auxiliary device control register? on page 1444 00000100h 0010h 0013h ?eeprom_ctrl - eeprom control register? on page 1446 00000x1xh 0014h 0017h ?eeprom_rr ? eeprom read register? on page 1448 xxxxxx00h 0028h 002bh ?fcal: flow control address low register? on page 1449 00c28001h 002ch 002fh ?fcah: flow control address high register? on page 1450 00000100h 0030h 0033h ?fct: flow control type register? on page 1451 00008808h 0038h 003bh ?vet: vlan ethertype register? on page 1452 00008100h 0170h 0173h ?fcttv: flow control transmit timer value register? on page 1452 00000000h 1000h 1003h ?pba: packet buffer allocation register? on page 1453 00100030h 00c0h 00c3h ?icr0: interrupt 0 cause read register? on page 1454 00000000h 00c4h 00c7h ?itr0: interrupt 0 throttling register? on page 1457 00000000h 00c8h 00cbh ?ics0: interrupt 0 cause set register? on page 1458 00000000h 00d0h 00d3h ?ims0: interrupt 0 mask set/read register? on page 1459 00000000h 00d8h 00dbh ?imc0: interrupt 0 mask clear register? on page 1460 00000000h 08c0h 08c3h ?icr1: interrupt 1cause read register? on page 1462 00000000h 08c8h 08cbh ?ics1: interrupt 0 cause set register? on page 1464 00000000h 08d0h 08d3h ?ims1: interrupt 1 mask set/read register? on page 1466 00000000h 08d8h 08dbh ?imc1: interrupt 1 mask clear register? on page 1467 00000000h 08e0h 08e3h ?icr2: error interrupt cause read register? on page 1469 00000000h 08e8h 08ebh ?ics2: error interrupt cause set register? on page 1471 00000000h 08f0h 08f3h ?ims2: error interrupt mask set/read register? on page 1472 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1433 intel ? ep80579 integrated processor 08f8h 08fbh ?imc2: error interrupt mask clear register? on page 1473 00000000h 0100h 0103h ?rctl: receive control register? on page 1474 00000000h 2160h 2163h ?fcrtl: flow control receive threshold low register? on page 1478 00000000h 2168h 216bh ?fcrth: flow control receive threshold high register? on page 1479 00000000h 2800h 2803h ?rdbal: receive descriptor base address low register? on page 1480 xxxxxxx0h 2804h 2807h ?rdbah: receive descriptor base address high register? on page 1480 xxxxxxxxh 2808h 280bh ?rdlen: receive descriptor length register? on page 1481 00000000h 2810h 2813h ?rdh: receive descriptor head register? on page 1481 00000000h 2818h 281bh ?rdt: receive descriptor tail register? on page 1482 00000000h 2820h 2823h ?rdtr: rx interrupt delay timer (packet timer) register? on page 1483 00000000h 2828h 282bh ?rxdctl: receive descriptor control register? on page 1483 00010000h 282ch 282fh ?radv: receive interrupt absolute delay timer register? on page 1485 00000000h 2c00h 2c03h ?rsrpd: receive small packet detect interrupt register? on page 1486 00000000h 5000h 5003h ?rxcsum: receive checksum control register? on page 1487 00000000h 5200h at 4h 5203h at 4h ?mta[0-127] ? 128 multicast table array registers? on page 1488 xxxx_xxxxh 5400h at 8h 5403h at 8h ?ral[0-15] - receive address low register? on page 1488 xxxxxxxxh 5404h at 8h 5407h at 8h ?rah[0-15] - receive address high register? on page 1489 000xxxxxh 5600h at 4h 5603h at 4h ?vfta[0-127] - 128 vlan filter table array registers? on page 1490 xxxxxxxxh 0400h 0403h ?tctl: transmit control register? on page 1491 00000008h 0410h 0413h ?tipg: transmit ipg register? on page 1493 00602008h 0458h 045bh ?ait: adaptive ifs throttle register? on page 1495 00000000h 3800h 3803h ?tdbal: transmit descriptor base address low register? on page 1496 xxxxxxx0h 3804h 3807h ?tdbah: transmit descriptor base address high register? on page 1496 xxxxxxxxh 3808h 380bh ?tdlen: transmit descriptor length register? on page 1497 00000000h 3810h 3813h ?tdh: transmit descriptor head register? on page 1497 00000000h 3818h 381bh ?tdt: transmit descriptor tail register? on page 1498 00000000h 3820h 3823h ?tidv: transmit interrupt delay value register? on page 1499 00000000h 3828h 382bh ?txdctl: transmit descriptor control register? on page 1500 00000000h 382ch 382fh ?tadv: transmit absolute interrupt delay value register? on page 1502 00000000h 3830h 3833h ?tspmt: tcp segmentation pad and minimum threshold register? on page 1504 01000400h 4000h 4003h ?crcerrs: crc error count register? on page 1505 00000000h 4004h 4007h ?algnerrc: alignment error count register? on page 1506 00000000h 400ch 400fh ?rxerrc: receive error count register? on page 1506 00000000h 4010h 4013h ?mpc: missed packet count register? on page 1507 00000000h 4014h 4017h ?scc: single collision count register? on page 1507 0000h 4018h 401bh ?ecol: excessive collisions count register? on page 1508 00000000h 401ch 401fh ?mcc: multiple collision count register? on page 1508 00000000h 4020h 4023h ?latecol: late collisions count register? on page 1509 00000000h 4028h 402bh ?colc: collision count register? on page 1509 00000000h table 37-23. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 2 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1434 order number: 320066-003us 4030h 4033h ?dc: defer count register? on page 1510 00000000h 4034h 4037h ?tncrs: transmit with no crs count register? on page 1510 00000000h 403ch 403fh ?cexterr: carrier extension error count register? on page 1511 00000000h 4040h 4043h ?rlec: receive length error count register? on page 1511 00000000h 4048h 404bh ?xonrxc: xon received count register? on page 1512 00000000h 404ch 404fh ?xontxc: xon transmitted count register? on page 1512 00000000h 4050h 4053h ?xoffrxc: xoff received count register? on page 1513 00000000h 4054h 4057h ?xofftxc: xoff transmitted count register? on page 1513 00000000h 4058h 405bh ?fcruc: fc received unsupported count register? on page 1514 00000000h 405ch 405fh ?prc64: good packets received count (64 bytes) register? on page 1514 00000000h 4060h 4063h ?prc127: good packets received count (65-127 bytes) register? on page 1515 00000000h 4064h 4067h ?prc255: good packets received count (128-255 bytes) register? on page 1515 00000000h 4068h 406bh ?prc511 - good packets received count (256-511 bytes) register? on page 1516 00000000h 406ch 406fh ?prc1023: good packets received count (512-1023 bytes) register? on page 1516 00000000h 4070h 4073h ?prc1522: good packets received count (1024 to max bytes) register? on page 1517 00000000h 4074h 4077h ?gprc: good packets received count (total) register? on page 1518 00000000h 4078h 407bh ?bprc: broadcast packets received count register? on page 1518 00000000h 407ch 407fh ?mprc: multicast packets received count register? on page 1519 00000000h 4080h 4083h ?gptc: good packets transmitted count register? on page 1519 00000000h 4088h 408ah ?gorcl: good octets received count low register? on page 1520 00000000h 408ch 408fh ?gorch: good octets received count high register? on page 1521 00000000h 4090h 4093h ?gotcl: good octets transmitted count low register? on page 1522 00000000h 4094h 4097h ?gotch: good octets transmitted count high register? on page 1522 00000000h 40a0h 40a3h ?rnbc: receive no buffers count register? on page 1523 00000000h 40a4h 40a7h ?ruc: receive undersize count register? on page 1523 00000000h 40a8h 40abh ?rfc: receive fragment count register? on page 1524 00000000h 40ach 40afh ?roc: receive oversize count register? on page 1524 00000000h 40b0h 40b3h ?rjc: receive jabber count register? on page 1525 00000000h 40c0h 40c3h ?torl: total octets received low register? on page 1526 00000000h 40c4h 40c7h ?torh: total octets received high register? on page 1526 00000000h 40c8h 40cfh ?totl: total octets transmitted low register? on page 1527 00000000h 40cch 40cfh ?toth: total octets transmitted high register? on page 1528 00000000h 40d0h 40d3h ?tpr: total packets received register? on page 1528 00000000h 40d4h 40d7h ?tpt: total packets transmitted register? on page 1529 00000000h 40d8h 40dbh ?ptc64 - packets transmitted count (64 bytes) register? on page 1529 00000000h 40e0h 40e3h ?ptc255: packets transmitted count (128-255 bytes) register? on page 1530 00000000h 40e4h 40e7h ?ptc511: packets transmitted count (256-511 bytes) register? on page 1530 00000000h 40e8h 40ebh ?ptc1023: packets transmitted count (512-1023 bytes) register? on page 1531 00000000h table 37-23. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 3 of 4) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1435 intel ? ep80579 integrated processor 40ech 40efh ?ptc1522: packets transmitted count (1024-1522 bytes) register? on page 1531 00000000h 40f0h 40f3h ?mptc: multicast packets transmitted count register? on page 1532 00000000h 40f4h 40f7h ?bptc: broadcast packets transmitted count register? on page 1532 00000000h 40f8h 40fbh ?tsctc: tcp segmentation context transmitted count register? on page 1533 00000000h 40fch 40ffh ?tsctfc: tcp segmentation context transmit fail count register? on page 1533 00000000h 5800h 5803h ?wuc - wake up control register (0x05800; rw)? on page 1534 00000000h 5808h 580bh ?wufc - wake up filter control register (0x05808; rw)? on page 1535 00000000h 5810h 5813h ?wus - wake up status register (0x05810; rw)? on page 1536 00000000h 5838h 583bh ?ipav - ip address valid register (0x05838; rw)? on page 1537 00000000h 5840h at 8h 5607h at 8h ?ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers? on page 1538 xxxxxxxxh 5880h 5883h ?ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4? on page 1539 xxxxxxxxh 05884h 0588fh ?ipv6_addr0bytes_5_8 ? ipv6 address tabl e register, bytes 5 - 8? on page 1539 xxxxxxxxh 5888h 588bh ?ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12? on page 1540 xxxxxxxxh 588ch 588fh ?ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16? on page 1541 xxxxxxxxh 5f00h at 8h 5f03h at 8h ?fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw)? on page 1542 00000000h 9000h at 8h 9003h at 8h ?ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw)? on page 1543 0000000xh 9800h at 8h 9803h at 8h ?ffvt[0-127]: flexible filter value table registers? on page 1544 xxxxxxxxh 0510h 0513h ?intbus_err_stat - internal bus error status register? on page 1544 00000000h 0900h 0903h ?mem_tst - memory error test register? on page 1546 00000000h 0904h 0907h ?mem_sts - memory error status register? on page 1547 007f0000h table 37-23. bus m, devices 2, function 0: summary of gigabit ethernet interface registers mapped through csrbar memory bar (sheet 4 of 4) offset start offset end register id - description default value
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1436 order number: 320066-003us 37.6.1.1 memory-mapped access to internal registers and memories the internal registers and memories may be accessed as direct memory-mapped offsets from the base address register. see section 37.6, ?gbe controller register summary? for the appropriate offset for each specific internal register. 37.6.1.2 i/o-mapped access to internal registers and memories to support pre-boot operation (prior to the allocation of physical memory base addresses), all internal registers and memories can be accessed using i/o operations. i/o accesses are supported only if an i/o base address is allocated and mapped, the bar contains a valid (non-zero value), and i/o address decoding is enabled in the pci/ pcix configuration. when an i/o bar is mapped, the i/o address range allocated opens a 32-byte ?window? in the system i/o address map. within this window, two i/o addressable register are implemented: ioaddr and io data. the ioaddr register is used to specify a reference to an internal register or memory and then the iodata register is used as a ?window? to the register or memory address specified by ioaddr: 37.6.1.2.1 ioaddr (i/o offset 0x00) the ioaddr register must always be written as a dword access (e.g. the pci_cbe_n[3:0] byte enables must all be enabled). writes that are less than 32 bits will be ignored. reads of any size will return a dword of data. however, the chipset or cpu may only return a subset of that dword. for software programmers, the in and out instructions must be used to cause i/o cycles to be used on the pci bus. because writes must be to a 32-bit quantity, the source register of the out instruction must be eax (the only 32-bit register supported by the out command). for reads, the in instruction can have any size target register, but it is recommended that the 32-bit eax register be used. because only a particular range is addressable, the upper bits of this register are hard coded to zero. bits 31 through 20 are not write-able and always read back as 0b. at hardware reset (lan_pwr _good) or pci reset, this register value resets to 0x00000000. once written, the value is retained until the next write or reset. 37.6.1.2.2 iodata (i/o offset 0x04) the iodata register must always be written as a dword access when the ioaddr register contains a value for the internal register and memories (e.g. 0x00000- 0x1fffc). in this case, writes that are less than 32 bits will be ignored. writes and reads to iodata when the ioaddr register value is in an undefined range (0x20000-0x7fffc) should not be performed. results are indeterministic. table 37-24. i/o mapped registers offset abbreviati on name r/w size 0x00 ioaddr internal register or internal memory location address. 0x00000-0x1ffff ? internal registers and memories 0x20000-0xfffff ? undefined rw 4 bytes 0x04 iodata data field for reads or writes to the internal register or internal memory location as identified by the current value in ioaddr. all 32 bits of this register are read/write-able. rw 4 bytes 0x08 ? 0x3f reserved reserved rw none
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1437 intel ? ep80579 integrated processor note: there are no special software timing requirements on accesses to ioaddr or iodata. all accesses will be immediate except when data is not readily available or acceptable. in this case, the mac will delay the results through normal bus methods. note: because a register/memory read or write takes two i/o cycles to complete, software must provide a guarantee that the two i/o cycles occur as an atomic operation. otherwise, results can be non-deterministic from the software viewpoint. 37.6.1.2.3 undefined i/o offsets i/o offsets 0x08 through 0x3f are considered to reserved offsets with the i/o window. writes within this address region may cause unpredictable behavior. reads within this address region may return indeterminate values. 37.6.1.3 register conventions all registers in the gbe are defined to be 32 bits and must be accessed with a dword transaction. ? reserved bit positions ? some registers contain certain bits that are marked as ?reserved?. these bits should never be written with anything other than their initial value by software (indicated in their individual descriptions). reads from registers containing reserved bits may return in determinate values in the reserved bit- positions unless read values are explicitly stated. when read, these reserved bits should be ignored by software. ? reserved and/or undefined addresses ? any register address not explicitly declared in this specification should be considered to be reserved, and should not be written. writing to reserved or undefined register addresses may cause indeterminate behavior. reads from reserved or undefined configuration register addresses may return indeterminate values unless read values are explicitly stated for specific addresses. ? initial values ? most registers define the initial hardware values prior to being programmed. in some cases, hardware initial values are undefined and will be listed as such via the text ?undefined?, ?unknown?, or ?x?. some such configuration values may need to be set by software in order for proper operation to occur; this need is dependent on the function of the bit. other registers may cite a hardware default which is overridden by a higher-precedence operation. operations which may supersede hardware defaults may include completion of a hardware operation (such as hardware auto-negotiation), or writing of a different register whose value is then reflected in another bit. for all registers, partial reads and writes may cause indeterminate behavior.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1438 order number: 320066-003us 37.6.2 general registers: detailed descriptions 37.6.2.1 ctrl ? device control register this register, as well as the extended device control register ( ctrl_ext ), controls the major operational modes for the device. while software write to this register to control device settings, several bits (such as fd and speed) may be overridden depending on other bit settings and the resultant link configuration determined by the auto- negotiation resolution with the phy. see ?physical layer auto-negotiation & link setup features? on page 1394 for a detailed explanation on the link configuration process. table 37-25. ctrl: device control register (sheet 1 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0000h 0003h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0000h 0003h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0000h 0003h size: 32 bits default: 00000a09h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 rsvd reserved 0h rv 30 vme vlan mode enable. 0 = vlan mode disabled. 1 = vlan mode enabled. all packets transmitted have an 802.1q header added to the packet. the contents of the header come from the transmit descriptor and from the vlan type register. on receive, vlan information is stripped from 802.1q packets. see ?802.1q vlan support? on page 1400 for more details. 0h rw 29 rsvd reserved 0h rv 28 tfce transmit flow control enable. 0 = transmit flow control disabled. 1 = transmit flow control enabled. flow control packets (xon & xoff frames) will be transmitted based on receiver fullness. if auto-negotiation is enabled, this bit is set to the negotiated duplex value. see ?physical layer auto-negotiation & link setup features? on page 1394 for more information about auto-negotiation. 0h rw 27 rfce receive flow control enable. 0 = receive flow control disabled. 1 = receive flow control enabled. indicates the device will respond to the reception of flow control packets. reception of flow control packets requires the correct loading of the fcah / fcal & fct registers. if auto- negotiation is enabled, this bit is set to the negotiated duplex value. see ?physical layer auto-negotiation & link setup features? on page 1394 for more information about auto-negotiation. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1439 intel ? ep80579 integrated processor 26 rst device reset, also referred to as a ?soft reset?. normally 0, writing 1 initiates the reset. this bit is self clearing. ctrl .rst may be used to globally reset the entire gbe hardware. this register is provided primarily as a last-ditch software mechanism to recover from an indeterminate or suspected hung hardware state. most registers (receive, transmit, interrupt, statistics, etc.), and state machines will be set to their power-on reset values, approximating the state following a power-on or unit reset. however, the packet buffer allocation register ( pba ) retains its value through a global reset. note: software must first disable both transmit & receive operation using the tctl .en and rctl .en register bits before asserting ctrl .rst. to ensure that the global device reset has fully completed and that the controller will respond to subsequent accesses, software must wait a minimum of 5 milliseconds after setting ctrl .rst before attempting to check if the bit has cleared or to access any other gbe device register. 0h rw 25 :21 rsvd reserved 0h rv 20 advd3wuc d3cold wakeup capability advertisement enable. when set, d3cold wakeup capability may be advertised based on whether the aux_pwr pin advertises presence of auxiliary power (see section 2.13.3 for details). when 0, d3cold wakeup capability will not be advertised even if aux_pwr presence is indicated. formerly used as sdp2 pin data value, initial value is eeprom-configurable *note that this bit is loaded from the eeprom, if present 0h rw 19 : 13 rsvd reserved 0h rv 12 frcdplx force duplex. 0 = mode is full-duplex, regardless of the fd setting. 1 = ctrl .fd bit sets duplex mode. 0h rw 11 frcspd force speed. 0 = default of 1gbps is used to set the mac speed. see ?physical layer auto-negotiation & link setup features? on page 1394 for more details. 1 = ctrl .speed bits set the mac speed. note: this bit is superseded by the ctrl_ext .spd_byps bit which has a similar function. note: *note that this bit is loaded from the eeprom, if present 1rw 10 rsvd reserved 0h rv table 37-25. ctrl: device control register (sheet 2 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0000h 0003h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0000h 0003h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0000h 0003h size: 32 bits default: 00000a09h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1440 order number: 320066-003us 09 : 08 speed speed selection. these bits are written by software (assuming, after reading the phy registers through the mdio interface) to set the mac speed configuration. see ?physical layer auto- negotiation & link setup features? on page 1394 for details. ? 00 => 10 mbps ? 01 => 100 mbps ? 10 => 1000 mbps ? 11 => reserved note: these bits affect the mac speed setting only if ctrl_ext .spd_byps or ctrl .frcspd are used. 10b rw 07 reserved reserved 0h rv 06 slu set link up. slu must be set to ?1? to enable the mac. this bit may also be initialized by the apme bit in the eeprom initialization control word3, if an eeprom is used. 0h rw 05 rsvd reserved. must be set to 0. 0h rw 04 rsvd reserved 0h rv 03 rsvd reserved 1rw 02 rsvd reserved 0h rv 01 rsvd reserved. must write ?0? to this bit. 1 = 0h rw 00 fd full duplex. controls the mac duplex setting. 0 = half duplex 1 = full duplex in half-duplex mode, ep80579?s gbe transmits carrier extended packets and can receive both carrier extended packets, and packets transmitted with bursting. *note that this bit is loaded from the eeprom, if present 1rw table 37-25. ctrl: device control register (sheet 3 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0000h 0003h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0000h 0003h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0000h 0003h size: 32 bits default: 00000a09h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1441 intel ? ep80579 integrated processor 37.6.2.2 status ? device status register this register reports the status of the major operational modes for the device. this is a read only register. table 37-26. status: device status register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0008h 000bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0008h 000bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0008h 000bh size: 32 bits default: 0000xxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 rsvd reserved 0h rv 09 : 08 reserved reserved xro 07 : 06 speed link speed setting: reflects speed setting of the mac. in gmii/mii mode, these bits reflect the software ctrl .speed setting ? 00 => 10 mbps ? 01 => 100 mbps ? 10 => 1000 mbps ? 11 => 1000 mbps xro 05 linkmode mode. based on ctrl_ext . link_mode. 0 = mac is operating in gmii/mii mode 1 = reserved xro 04 txoff transmission off. this bit indicates the state of the transmit function when symmetrical flow control has been enabled and negotiated with the link partner. 0 = symmetrical flow control is disabled, or transmission is not paused. 1 = symmetrical flow control is enabled, and the transmit function is paused due to the reception of an xoff frame. it is cleared upon expiration of the pause timer or the receipt of an xon frame. xro 03 : 02 rsvd reserved 0h rv 01 rsvd reserved xro 00 fd full duplex. this bit reflects the mac duplex configuration. normally, the duplex setting for the link, as it should reflect the duplex configuration negotiated between the phy and link partner (copper link) or mac and link partner (fiber link). 0 = half duplex mode 1 = full duplex mode xro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1442 order number: 320066-003us 37.6.2.3 ctrl_ext ? extended device control register this register provides extended control of device functionality beyond that provided by the device control register ( ctrl ). table 37-27. ctrl_ext: extended device control register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0018h 001bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0018h 001bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0018h 001bh size: 32 bit default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 25 rsvd reserved 0h rv 24 rmii_rx_mode rmii gasket receive mode select: 0 = for proper 100mbps receive operation, after assertion of the rmii crs_dv signal on gben_rxctl, the rmii gasket requires that a minimum of two di-bits of ?00? appear on gben_rxdata[1:0] before the preamble appears. 1 = for proper 100mbps receive operation, the rmii gasket requires that crs_dv be asserted on gben_rxctl synchronously with gbe_refclk_rmii and on the same cycle in which the first di-bit of the preamble appears on gben_rxdata[1:0]. 0 is the default value of this bit and makes the rmii gasket compatible with rmii phys that assert crs_dv as soon as the receive medium is non-idle, and subsequently drive ?00? on rxd[1:0] until proper receive signal decoding has been achieved (per the rmii specification, revision 1.2). setting this bit to a 1 makes the gasket compatible with rmii phys that assert crs_dv simultaneously with the start of the preamble driven on rxd[1:0]. while this crs_dv signalling mode does not scrictly conform to the rmii specification, it is provided to allow compatibility with phy devices that use this alternate method of asserting crs_dv at the start of the packet. this bit must be set to the proper state that corresponds to the crs_dv behavior of the attached rmii phy, otherwise 100mbps packets cannot be properly received by the gbe. this bit does not affect transmit operations. 0h rw 23 : 22 link_mode link mode. this controls which interface is used to talk to the link. ? 00 => gmii/mii mode ? 01 => reserved ? 10 => reserved ? 11 => reserved ? *note that this bit is loaded from the eeprom, if present 0h rw 21 : 16 rsvd reserved 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1443 intel ? ep80579 integrated processor 15 spd_byps speed select bypass. 0 = normal speed detection mechanisms are used to determine the speed of the mac. 1 = all speed detection mechanisms are bypassed and the mac is immediately set to the setting of ctrl .speed. note: ctrl_ext .spd_byps performs a function similar to ctrl .frcspd in that the device's speed settings are determined by the value software writes to the ctrl .speed bits. however, when using ctrl_ext .spd_byps the ctrl .speed setting takes effect immediately, when using ctrl .frcspd the ctrl .speed setting waits until after the device's clock switching circuitry performs the change. 0h rw 14 rsvd reserved 0h rv 13 ee_rst eeprom reset initiates a ?reset-like? event to the eeprom function. this causes the eeprom to be read as if a unit_reset had occurred. all device functions should be disabled prior to setting this bit. this bit is self-clearing. note: this will not cause the controller to detect the eeprom 0h rw 12 rsvd reserved 0h rv 11 : 00 rsvd reserved 0h rv table 37-27. ctrl_ext: extended device control register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0018h 001bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0018h 001bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0018h 001bh size: 32 bit default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1444 order number: 320066-003us 37.6.2.4 ctrl_aux ? auxiliary device control/status register this register provides extended control of device functionality beyond that provided by the device control register ( ctrl ) and extended device control register table 37-28. ctrl_aux: auxiliary device control register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00e0h 00e3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00e0h 00e3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00e0h 00e3h size: 32 bits default: 00000100h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 :18 rsvd reserved 0h ro 17 rmii_log_fix enable logic change to fix rmii 100mbps tx dropped packet data. to enable this mode of operation, set this bit to a ?1?. when enabled, the fix modifies the legacy new-packet signalling logic in the transmit path to prevent the first 8 bytes of packet data from being dropped when operating in rmii mode and a line speed of 100mbps. 0h rw 16 rmii_freq_fix disable dma frequency change to fix rmii 100mbps tx dropped packet data. this is the default mode of operation. to disable this mode of operation, set this bit to a ?1?. this must be disabled if fix2 is enabled. when enabled, sets the dma clock frequency to 50mhz when operating in rmii mode. this produces a favorable frequency ratio between dma and mac clocks that prevents the first 8 bytes of transmit packet data from being dropped when operating in rmii mode and a line speed of 100mbps. 0h rw 15 :12 rsvd reserved 0h ro 11 :10 end_sel selects whether the descriptor or packet data is controlled by endianness configuration. 00 - descriptor and packet transfers use ctrl_aux.endianess 01 - descriptor uses ctl_aux.endianess, packet uses default 10 - descriptor uses default, packet uses ctrl_aux.endianess 11 - all transfers use ctrl_aux.endianess 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1445 intel ? ep80579 integrated processor 09 : 08 endianess endianness: these bits control the endianness of the data in memory. these settings apply to all internal bus transactions, including packet data and descriptors ?00? - lw little--endian, byte big-endian ?01? - lw little-endian, byte little-endian (default) ?10? - lw big-endian, byte big-endian ?11? - lw big-endian, byte little-endian refer to section 37.5.14, ?endianness? for further details. 01h rw 07 : 01 rsvd reserved 0h ro 00 rgmii_rmii rgmii/rmii translation gasket select ??0? - rgmii ??1? - rmii 0h rw table 37-28. ctrl_aux: auxiliary device control register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00e0h 00e3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00e0h 00e3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00e0h 00e3h size: 32 bits default: 00000100h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1446 order number: 320066-003us 37.6.2.5 eeprom_ctrl ? eeprom control register table 37-29. eeprom_ctrl - eeprom control register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0010h 0013h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0010h 0013h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0010h 0013h size: 32 bits default: 00000x1xh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 rsvd reserved 0h ro 09 ee_size eeprom size . 0 reserved 1 4096-bit (256 word) nm93c66 compatible eeprom if an eeprom is present, this bit indicates its size, based on acknowledges seen during eeprom scans of different addresses. this bit is read-only. note: this bit will not be updated as a result of anything but a power up reset. xh ro 08 ee_pres eeprom present this bit attempts to indicate if an eeprom is present by monitoring the ee_do input for a active-low ?acknowledge? by the serial eeprom during initial eeprom scan. if no eeprom is present, the ee_do line will remain pulled-high and thus no acknowledge will be seen. 1=eeprom present; 0=no eeprom. note: this bit will not be set except as a result of eeprom detection during power up reset. xh ro 07 ee_gnt grant eeprom access when this bit is 1 the software can access the eeprom using the sk, cs, di, and do bits. 0h ro 06 ee_req request eeprom access the software must write a 1 to this bit to get direct eeprom access. it has access when ee_gnt is 1. when the software completes the access it must write a 0. 0h rw 05 : 04 rsvd reserved 01h ro 03 ee_do data output bit from the eeprom . the ee_do input signal is mapped directly to this bit in the register and contains the eeprom data output. this bit is read-only from the software perspective ? writes to this bit have no effect. xro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1447 intel ? ep80579 integrated processor this register provides software direct access to the eeprom. software can control the eeprom by successive writes to this register. data & address information is clocked into the eeprom by software toggling the eesk bit (2) of this register with eecs set to 1. data output from the eeprom is latched into bit 3 of this register via the internal 62.5mhz clock and may be accessed by software via reads of this register. 02 ee_di data input to the eeprom . when ee_gnt is 1, the ee_di output signal is mapped directly to this bit. software provides data input to the eeprom via writes to this bit. 0h rw 01 ee_cs chip select input to the eeprom . when ee_gnt is 1, the ee_cs output signal is mapped to the chip select of the eeprom device. software enables the eeprom by writing a 1 to this bit. 0h rw 00 ee_sk clock input to the eeprom . when ee_gnt is 1, the ee_sk output signal is mapped to this bit and provides the serial clock input to the eeprom. software clocks the eeprom via toggling this bit with successive writes. 0h rw table 37-29. eeprom_ctrl - eeprom control register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0010h 0013h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0010h 0013h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0010h 0013h size: 32 bits default: 00000x1xh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1448 order number: 320066-003us 37.6.2.6 eeprom_rr ? eeprom read register this registers is used by software to read individual words in the eeprom. to read a word, software writes the address to the read address field and simultaneously writes a 1 to the start read field. the gbe will read the word from the eeprom and place it in the read data field, setting the read done filed to 1. software can poll this register, looking for a 1 in the read done filed, and then using the value in the read data field. when this register is used to read a word from the eeprom, that word is not written to any of the mac's internal registers even if it is normally a hardware accessed word. note: if sw has requested direct pin control of the eeprom using the eec register, an access through the eerd register mechanism may stall until the eec control has been released. sw should ensure that eec.ee _req=0 and that eec.ee_gnt=0 as well before attempting to utilize eerd to access the eeprom. table 37-30. eeprom_rr ? eeprom read register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0014h 0017h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0014h 0017h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0014h 0017h size: 32 bits default: xxxxxx00h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 data read data data returned from the eeprom read. xro 15 : 08 addr read address this field is written by software along with start read to indicate the word to read. xrw 07 : 05 rsvd reserved reads as 0 0h rv 04 done read done set to 1 when the eeprom read completes. set to 0 when the eeprom read is in progress. writes by software are ignored. 0h ro 03 : 01 rsvd reserved reads as 0 0h rv 00 start start read writing a 1 to this bit causes the eeprom to read a (16-bit) word at the address stored in the ee_addr field, storing the result in the ee_data field. this bit is self-clearing 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1449 intel ? ep80579 integrated processor 37.6.2.7 fcal ? flow control address low register flow control packets are defined by 802.3x to be either a unique multicast address or the station address with the ethertype field indicating pause. the fcah and fcal registers provide the value hardware compares incoming packets against to determine that it should pause its output. this register contains the lower bits of the internal 48 bit flow control ethernet address. note: any packet matching the contents of { fcah , fcal , fct } when ctrl .rfce is set will be acted on by the ep80579?s gbe. whether flow control packets are passed to the software depends on the state of the rctl .dpf bit and whether the packet matches any of the normal filters. note: at the time of the original implementation, the flow control multicast address was not defined and thus hardware provided progra mmability. since then, the final release of the 802.3x standard has reserved the following multicast address for mac control frames: 01-80-c2-00-00-01. note: this register must be written by software with the appropriate value for the mac to behave properly. table 37-31. fcal: flow control address low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0028h 002bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0028h 002bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0028h 002bh size: 32 bits default: 00c28001h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 fcal this register must be programmed with 0x00c2_8001. 00c28001h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1450 order number: 320066-003us 37.6.2.8 fcah ? flow control address high register flow control packets are defined by 802.3x to be either a unique multicast address or the station address with the ethertype field indicating pause. the fcah and fcal registers provide the value hardware compares incoming packets against to determine that it should pause its output. this register contains the upper bits of the internal 48 bit flow control ethernet address. note: any packet matching the contents of { fcah , fcal , fct } when ctrl .rfce is set will be acted on by the ep80579?s gbe. whether flow control packets are passed to the software depends on the state of the rctl .dpf bit and whether the packet matches any of the normal filters. note: at the time of the original implementation, the flow control multicast address was not defined and thus hardware provided programmability. since then, the final release of the 802.3x standard has reserved the following multicast address for mac control frames: 01-80-c2-00-00-01. note: this register must be written by software with the appropriate value for the mac to behave properly. table 37-32. fcah: flow control address high register description: this register must be programmed with 0x00000100. view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 002ch 002fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 002ch 002fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 002ch 002fh size: 32 bits default: 00000100h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 16 rsvd reserved 0rv 15 : 00 fcah this register must be programmed with 0x00_00_01_00. 0100h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1451 intel ? ep80579 integrated processor 37.6.2.9 fct ? flow control type register flow control packets are defined by 802.3x to be either a unique multicast address or the station address with the ethertype field indicating pause. the fcah and fcal registers provide the value hardware compares incoming packets against to determine that it should pause its output. this register contains the type field hardware matches against to recognize a flow control packet. note: any packet matching the contents of { fcah , fcal , fct } when ctrl .rfce is set will be acted on by the ep80579?s gbe. whether flow control packets are passed to the software depends on the state of the rctl .dpf bit and whether the packet matches any of the normal filters. note: at the time of the original implementation, the flow control type field was not defined and thus hardware provided programmability. since then, the final release of the 802.3x standard has specified the type/length value for mac control frames as 88-08. table 37-33. fct: flow control type register description: this register must be programmed with 0x00_00_88_0 view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0030h 0033h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0030h 0033h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0030h 0033h size: 32 bits default: 00008808h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 16 rsvd reserved 0000h rv 15 : 00 fct this register must be programmed with 0x00_00_88_08. 8808h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1452 order number: 320066-003us 37.6.2.10 vet ? vlan ethertype register this register contains the type field hardware matches against to recognize an 802.1q (vlan) ethernet packet. 37.6.2.11 fcttv ? flow control transmit timer value register the register holds a 16-bit value in the ttv field that is inserted into a transmitted frame (either xoff frames or any pause frame value in any software transmitted packets). it counts in units of slot time, usually 64b. if software wishes to send an xon frame, it must set ttv to 0 prior to initiating the pause frame. note: the ep80579?s gbe uses a fixed slot time value of 64b times table 37-34. vet: vlan ethertype register description: to be compliant with the 802.3ac standard, this re gister must be programmed with the value 0x00_00_81_00 view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0038h 003bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0038h 003bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0038h 003bh size: 32 bits default: 00008100h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 16 rsvd reserved 0rv 15 : 00 vet to be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00. 8100h rw table 37-35. fcttv: flow control transmit timer value register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0170h 0173h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0170h 0173h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0170h 0173h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 ttv transmit timer value to be included in xoff frame. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1453 intel ? ep80579 integrated processor 37.6.2.12 pba ? packet buffer allocation register this register sets the gbe hardware receive and transmit storage allocation ratio. the tx allocation is calculated from the programmed rx allocation, assuming 64kb of total packet buffer memory. note: programming this register does not automatically re-load or initialize internal packet- buffer ram pointers. the software must reset both transmit and receive operation (using the global device reset ctrl .rst bit) after changing this register in order for it to take effect. the pba register itself will not be reset by assertion of the global reset, but will only be reset upon initial hardware power-on. table 37-36. pba: packet buffer allocation register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 1000h 1003h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 1000h 1003h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 1000h 1003h size: 32 bits default: 00100030h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 :22 rsvd reserved 0h ro 21 : 16 txa transmit packet buffer allocation in k bytes. pba .txa is read only and calculated based on pba .rxa. 0010h =>16kb 0010h ro 15 :6 rsvd reserved 0h ro 5: 00 rxa receive packet buffer allocation in k bytes. pba .rxa legal values must be 8k aligned. valid values are (decimal) 8, 16, 24, 32, 40, 48, 56. 0030h => 48kbh 0030h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1454 order number: 320066-003us 37.6.3 interrupt registers: detailed descriptions 37.6.3.1 icr0 ? interrupt 0 cause read register this register contains all interrupt conditions for the gbe. whenever an interrupt causing event occurs, the corresponding interrupt bit is set in this register. see ?ims0 ? interrupt 0 mask set/read register? on page 1459 for additional details. note: all register bits clear on read. thus, reading this register implicitly acknowledges all pending interrupt events. writing a 1 to any bit in the register will also clear that bit. writing a 0 to any bit will have no effect. table 37-37. icr0: interrupt 0 cause read register (sheet 1 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00c0h 00c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00c0h 00c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00c0h 00c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus internal bus error. this bit indicates that an error occurred during either a target or host transaction on the bus. refer to section 37.5.12, ?error handling? for complete details. the details of this error are reported in the intbus_err_stat register. 0h rcwc 27 err_stat statistic register ecc error. the statistic registers are implemented using a memory that uses a single-bit correct/multi-bit detect ecc parity algorithm to protect it. this bit indicates that a multi-bit error has occurred on a read from that memory. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst) 0h rcwc 26 err_mcfspf this bit indicates that either a multicast filter parity error, special packet filter parity error or a flex filter parity error occurred. these filters use parity protected srams for data buffers. this bit indicates that a parity error has occurred on a read from either of these data buffers. this error is considered non-fatal and will clear after a read of the mem_err_stat register . 0h rcwc 25 : 24 rsvd reserved 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1455 intel ? ep80579 integrated processor 23 err_pb dma packet buffer 2-bit ecc error. the 64kb dma packet buffer uses a single-bit correct/multi-bit detect ecc parity algorithm to protect the sram it uses for data. this bit indicates that a multi-bit error has occurred on a read from that sram. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst) 0h rcwc 22 rsvd reserved 0h rv 21 err_txds dma transmit descriptor 2-bit ecc error. the dma transmit descriptor buffer uses a single-bit correct/multi- bit detect ecc parity algorithm to protect the sram it uses for a data buffer. this bit indicates that a multi-bit error has occurred on a read from that data buffer. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst) 0h rcwc 20 err_rxds dma receive descriptor 2-bit ecc error. the dma receive descriptor buffer uses a single-bit correct/multi-bit detect ecc parity algorithm to protect the sram it uses for a data buffer. this bit indicates that a multi-bit error has occurred on a read from that data buffer. no indication of a single- bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst) 0h rcwc 19 : 17 rsvd reserved 0h rv 16 srpd small receive packet detected. indicates that a packet of size rsrpd.size register has been detected and transferred to host memory. the interrupt is only asserted if rsrpd.size register has a non-zero value 0h rcwc 15 txd_low transmit descriptor low threshold hit. indicates that the descriptor ring has reached the threshold specified in ?txdctl ? transmit descriptor control register? on page 1500 . 0h rcwc 14 : 8 rsvd reserved 0h rv 07 rxt0 receiver timer interrupt. set when the timers expire, see ?receive interrupts? on page 1360 for details. 0h rcwc 06 rxo receiver overrun. set on receive data fifo overrun. could be caused either because there are no available buffers or because internal bus receive bandwidth is inadequate. 0h rcwc table 37-37. icr0: interrupt 0 cause read register (sheet 2 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00c0h 00c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00c0h 00c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00c0h 00c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1456 order number: 320066-003us 05 rsvd reserved 0h rv 04 rxdmt0 receive descriptor minimum threshold hit. indicates that the minimum number of receive descriptors are available and software should load more receive descriptors. 0h rcwc 03 rsvd reserved 0h rcwc 02 rsvd reserved 0h rv 01 txqe transmit queue empty. set when the last descriptor block for a transmit queue has been used. 0h rcwc 00 txdw transmit descriptor written back. set when hardware processes a descriptor with its rs bit set. if using delayed interrupts (tdesc.ide is set in the transmit descriptor cmd), the interrupt is delayed until after one of the delayed-timers ( tidv or tadv ) expires. 0h rcwc table 37-37. icr0: interrupt 0 cause read register (sheet 3 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00c0h 00c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00c0h 00c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00c0h 00c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1457 intel ? ep80579 integrated processor 37.6.3.2 itr0 ? interrupt 0 throttling register software can use this register to pace (o r balance) the delivery of the functional interrupt signal to the host cpu. this register provides a guaranteed inter-interrupt delay between interrupts asserted by the network controller, regardless of network traffic conditions. table 37-38. itr0: interrupt 0 throttling register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00c4h 00c7h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00c4h 00c7h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00c4h 00c7h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 miii minimum inter-interrupt interval. ? in rgmii mode, the interval is specified in 256ns increments. ? in rmii mode, the interval is specified in 320ns increments ? zero disables interrupt throttling logic (the following example applies to rgmii mode) to independently validate configuration settings, software can use the following formula to convert the inter-interrupt interval value to the common 'interrupts/sec? performance metric: interrupts/sec = (256 x 10 -9 sec x inter-interrupt interval) - 1 inversely, inter-interrupt interval value can be calculated as: inter-interrupt interval = (256 x 10 -9 sec x interrupts/sec) - 1 for example, if the interval is programmed to 500d, the network controller guarantees the cpu will not be interrupted by the network controller for 128 usec from the last interrupt. the maximum observable interrupt rate from the adapter should never exceed 7813 interrupts/sec. the optimal performance setting for this register is system/configuration specific. a initial suggested range is 651-5580 (28bh - 15cch), or, more generally, between 700 and 6000 interrupts per second. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1458 order number: 320066-003us 37.6.3.3 ics0 ? interrupt 0 cause set register software uses this register to set an interrupt condition. assuming the interrupt mask is set, any bit written with a 1 triggers the corresponding interrupt, see ?ims0 ? interrupt 0 mask set/read register? on page 1459 and ?icr0 ? interrupt 0 cause read register? on page 1454 . table 37-39. ics0: interrupt 0 cause set register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00c8h 00cbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00c8h 00cbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00c8h 00cbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus triggers internal bus error 0h rw 27 err_stat triggers statistic register ecc error 0h rw 26 err_mcfspf triggers special packet filter parity error 0h rw 25 : 24 rsvd reserved 0h rv 23 err_pkbuf triggers dma packet buffer ecc error 0h rw 22 rsvd reserved 0h rv 21 err_txds triggers dma transmit descriptor buffer ecc error 0h rw 20 err_rxds triggers dma receive descriptor buffer ecc error 0h rw 19 : 17 rsvd reserved 0h rv 16 srpd triggers small receive packet detected and transferred 0h rw 15 txd_low triggers transmit descriptor low threshold hit 0h rw 14 : 8 rsvd reserved 0h rv 07 rxt0 triggers receiver timer interrupt 0h rw 06 rxo triggers receiver overrun. set on receive data fifo overrun 0h rw 05 rsvd reserved 0h rv 04 rxdmt0 triggers receive descriptor minimum threshold hit 0h rw 03 rsvd reserved 0h rw 02 rsvd reserved. must be written as ?0? 0h rv 0 1 tx q e tr i gg er s tra n sm i t q u e u e e mp ty 0 h r w 00 txdw triggers transmit descriptor written back 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1459 intel ? ep80579 integrated processor 37.6.3.4 ims0 ? interrupt 0 mask set/read register this register contains which interrupts are enabled. an interrupt is enabled if its corresponding mask bit is set to 1, and disabled if its corresponding mask bit is set to 0. an interrupt is generated whenever one of the bits in this register is set, and the corresponding interrupt condition occurs, see the ?icr0 ? interrupt 0 cause read register? on page 1454 for interrupt conditions. a particular interrupt may be enabled by writing a 1 to the corresponding mask bit in this register. any bits written with a 0, are unchanged. thus, if software desires to disable a particular interrupt condition that had been previously enabled, it must write to the interrupt mask clear register rather than writing a 0 to a bit in this register. table 37-40. ims0: interrupt 0 mask set/read register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00d0h 00d3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00d0h 00d3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00d0h 00d3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus enables internal bus error 0h rw 27 err_stat enables statistic register ecc error 0h rw 26 err_mcfspf enables special packet filter parity error 0h rw 25 : 24 rsvd reserved 0h rv 23 err_pkbuf enables dma packet buffer ecc error 0h rw 22 rsvd reserved 0h rv 21 err_txds enables dma transmit descriptor buffer ecc error 0h rw 20 err_rxds enables dma receive descriptor buffer ecc error 0h rw 19 : 17 rsvd reserved. must be written as ?0? 0h rv 16 srpd sets the mask for small receive packet detected and transferred 0h rw 15 txd_low sets the mask for transmit descriptor low threshold hit 0h rw 14 : 8 rsvd reserved 0h rv 07 rxt0 sets the mask for receiver timer interrupt 0h rw 06 rxo sets the mask for receiver overrun. set on receive data fifo overrun 0h rw 05 rsvd reserved 0h rv 04 rxdmt0 sets the mask for receive descriptor minimum threshold hit 0h rw 03 rsvd reserved 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1460 order number: 320066-003us 37.6.3.5 imc0 ? interrupt 0 mask clear register software uses this register to disable an interrupt condition that was previously enabled. interrupts are presented to the bus interface only when the mask bit is set and the interrupt condition is active. the status of the mask bit is reflected in the ?ims0 ? interrupt 0 mask set/read register? on page 1459 , and the status of the cause bit is reflected in the ?icr0 ? interrupt 0 cause read register? on page 1454 . software disables a given interrupt by writing a 1 to the corresponding bit in this register, a 0 is ignored. a read from this register will return the current value of the interrupt mask settings, returning the same value as a read of the ims register. 02 rsvd reserved. must be written as ?0? 0h rv 01 txqe sets the mask for transmit queue empty 0h rw 00 txdw sets the mask for transmit descriptor written back 0h rw table 37-40. ims0: interrupt 0 mask set/read register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00d0h 00d3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00d0h 00d3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00d0h 00d3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access table 37-41. imc0: interrupt 0 mask clear register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00d8h 00dbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00d8h 00dbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00d8h 00dbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus clears the mask for internal bus error 0h wo 27 err_stat clears the mask for statistic register ecc error 0h wo 26 err_mcfspf clears the mask for the filter memory errors 0h wo 25 : 24 rsvd reserved 0h rv 23 err_pkbuf clears the mask for dma packet buffer ecc error 0h wo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1461 intel ? ep80579 integrated processor 22 rsvd reserved 0h rv 21 err_txds clears the mask for dma transmit descriptor buffer ecc error 0h wo 20 err_rxds clears the mask for dma receive descriptor buffer ecc error 0h wo 19 : 17 rsvd reserved 0h rv 16 srpd clears the mask for small receive packet detected and transferred 0h wo 15 txd_low clears the mask for transmit descriptor low threshold hit 0h wo 14 : 8 rsvd reserved 0h rv 07 rxt0 clears the mask for receiver timer interrupt 0h wo 06 rxo clears the mask for receiver overrun. set on receive data fifo overrun 0h wo 05 rsvd reserved 0h rv 04 rxdmt0 clears the mask for receive descriptor minimum threshold hit 0h wo 03 rsvd reserved 0h wo 02 rsvd reserved. must be written as ?0? 0h rv 01 txqe clears the mask for transmit queue empty 0h wo 00 txdw clears the mask for transmit descriptor written back 0h wo table 37-41. imc0: interrupt 0 mask clear register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 00d8h 00dbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 00d8h 00dbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 00d8h 00dbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1462 order number: 320066-003us 37.6.3.6 icr1 ? interrupt 1 cause read register this register contains all interrupt conditions for the gbe. whenever an interrupt causing event occurs, the corresponding interrupt bit is set in this register. see ?ims0 ? interrupt 0 mask set/read register? on page 1459 for additional details. note: all register bits clear on read. thus, reading this register implicitly acknowledges all pending interrupt events. writing a 1 to any bit in the register will also clear that bit. writing a 0 to any bit will have no effect. table 37-42. icr1: interrupt 1cause read register (sheet 1 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08c0h 08c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08c0h 08c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08c0h 08c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus internal bus error. this bit indicates that an error occurred during either a target or host transaction on the bus. refer to section 37.5.12, ?error handling? for complete details. the details of this error are reported in the intbus_err_stat register. 0h rcwc 27 err_stat statistic register ecc error. the statistic registers are implemented using a memory that uses a single-bit correct/multi-bit detect ecc parity algorithm to protect it. this bit indicates that a multi-bit error has occurred on a read from that memory. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst) 0h rcwc 26 err_mcfspf multicast filter parity error/special packet filter parity error. the multicast filter and special packets filter use parity protected srams for data buffers. this bit indicates that a parity error has occurred on a read from either of these data buffers. this error is considered non- fatal and will clear after a read of the mem_err_stat register . 0h rcwc 25 : 24 rsvd reserved 0h rv 23 err_pb dma packet buffer 2-bit ecc error. the 64kb dma packet buffer uses a single-bit correct/multi-bit detect ecc parity algorithm to protect the sram it uses for data. this bit indicates that a multi-bit error has occurred on a read from that sram. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst). 0h rcwc 22 rsvd reserved 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1463 intel ? ep80579 integrated processor 21 err_txds dma transmit descriptor 2-bit ecc error. the dma transmit descriptor buffer uses a single-bit correct/multi- bit detect ecc parity algorithm to protect the sram it uses for a data buffer. this bit indicates that a multi-bit error has occurred on a read from that data buffer. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst). 0h rcwc 20 err_rxds dma receive descriptor 2-bit ecc error. the dma receive descriptor buffer uses a single-bit correct/multi-bit detect ecc parity algorithm to protect the sram it uses for a data buffer. this bit indicates that a multi-bit error has occurred on a read from that data buffer. no indication of a single- bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst). 0h rcwc 19 : 17 rsvd reserved 0h rv 16 srpd small receive packet detected. indicates that a packet of size rsrpd.size register has been detected and transferred to host memory. the interrupt is only asserted if rsrpd.size register has a non-zero value 0h rcwc 15 txd_low transmit descriptor low threshold hit. indicates that the descriptor ring has reached the threshold specified in ?txdctl ? transmit descriptor control register? on page 1500 . 0h rcwc 14 : 8 rsvd reserved 0h rv 07 rxt0 receiver timer interrupt. set when the timers expire, see ?receive interrupts? on page 1360 for details. 0h rcwc 06 rxo receiver overrun. set on receive data fifo overrun. could be caused either because there are no available buffers or because internal bus receive bandwidth is inadequate. 0h rcwc 05 rsvd reserved 0h rv 04 rxdmt0 receive descriptor minimum threshold hit. indicates that the minimum number of receive descriptors are available and software should load more receive descriptors. 0h rcwc 03 rsvd reserved 0h rcwc 02 rsvd reserved 0h rv table 37-42. icr1: interrupt 1cause read register (sheet 2 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08c0h 08c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08c0h 08c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08c0h 08c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1464 order number: 320066-003us 37.6.3.7 ics1 ? interrupt 1 cause set register software uses this register to set an interrupt condition. assuming the interrupt mask is set, any bit written with a 1 triggers the corresponding interrupt, see ?ims0 ? interrupt 0 mask set/read register? on page 1459 and ?icr0 ? interrupt 0 cause read register? on page 1454 . 01 txqe transmit queue empty. set when the last descriptor block for a transmit queue has been used. 0h rcwc 00 txdw transmit descriptor written back. set when hardware processes a descriptor with its rs bit set. if using delayed interrupts (tdesc.ide is set in the transmit descriptor cmd), the interrupt is delayed until after one of the delayed-timers ( tidv or tadv ) expires. 0h rcwc table 37-42. icr1: interrupt 1cause read register (sheet 3 of 3) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08c0h 08c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08c0h 08c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08c0h 08c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access table 37-43. ics1: interrupt 0 cause set register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08c8h 08cbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08c8h 08cbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08c8h 08cbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus triggers internal bus error 0h rw 27 err_stat triggers statistic register ecc error 0h rw 26 err_mcfspf triggers special packet filter parity error 0h rw 25 : 24 rsvd reserved 0h rv 23 err_pkbuf triggers dma packet buffer ecc error 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1465 intel ? ep80579 integrated processor 22 rsvd reserved 0h rv 21 err_txds triggers dma transmit descriptor buffer ecc error 0h rw 20 err_rxds triggers dma receive descriptor buffer ecc error 0h rw 19 : 17 rsvd reserved 0h rv 16 srpd triggers small receive packet detected and transferred 0h rw 15 txd_low triggers transmit descriptor low threshold hit 0h rw 14 : 8 rsvd reserved 0h rv 07 rxt0 triggers receiver timer interrupt 0h rw 06 rxo triggers receiver overrun. set on receive data fifo overrun 0h rw 05 rsvd reserved 0h rv 04 rxdmt0 triggers receive descriptor minimum threshold hit 0h rw 03 rsvd reserved 0h rv 02 rsvd reserved. must be written as ?0? 0h rv 01 txqe triggers transmit queue empty 0h rw 00 txdw triggers transmit descriptor written back 0h rw table 37-43. ics1: interrupt 0 cause set register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08c8h 08cbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08c8h 08cbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08c8h 08cbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1466 order number: 320066-003us 37.6.3.8 ims1 ? interrupt 1 mask set/read register this register contains which interrupts are enabled. an interrupt is enabled if its corresponding mask bit is set to 1, and disabled if its corresponding mask bit is set to 0. an interrupt is generated whenever one of the bits in this register is set, and the corresponding interrupt condition occurs, see the ?icr0 ? interrupt 0 cause read register? on page 1454 for interrupt conditions. a particular interrupt may be enabled by writing a 1 to the corresponding mask bit in this register. any bits written with a 0, are unchanged. thus, if software desires to disable a particular interrupt condition that had been previously enabled, it must write to the interrupt mask clear register rather than writing a 0 to a bit in this register. table 37-44. ims1: interrupt 1 mask set/read register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08d0h 08d3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08d0h 08d3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08d0h 08d3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus enables internal bus error rw 0h wo 27 err_stat enables statistic register ecc error rw 0h wo 26 err_mcfspf enables special packet filter parity error rw 0h wo 25 : 24 rsvd reserved rv 0h rv 23 err_pkbuf enables dma packet buffer ecc error rw 0h wo 22 rsvd reserved rv 0h rv 21 err_txds enables dma transmit descriptor buffer ecc error rw 0h wo 20 err_rxds enables dma receive descriptor buffer ecc error rw 0h wo 19 : 17 rsvd reserved 0h rv 16 srpd sets the mask for small receive packet detected and tra n sf e rr e d 0h rw 15 txd_low sets the mask for transmit descriptor low threshold hit 0h rw 14 : 8 rsvd reserved 0h rv 07 rxt0 sets the mask for receiver timer interrupt 0h rw 06 rxo sets the mask for receiver overrun. set on receive data fifo overrun 0h rw 05 rsvd reserved 0h rv 04 rxdmt0 sets the mask for receive descriptor minimum threshold hit 0h rw 03 rsvd reserved 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1467 intel ? ep80579 integrated processor 37.6.3.9 imc1 ? interrupt 1 mask clear register software uses this register to disable an interrupt condition that was previously enabled. interrupts are presented to the bus interface only when the mask bit is set and the interrupt condition is active. the status of the mask bit is reflected in the ?ims0 ? interrupt 0 mask set/read register? on page 1459 , and the status of the cause bit is reflected in the ?icr0 ? interrupt 0 cause read register? on page 1454 . software disables a given interrupt by writing a 1 to the corresponding bit in this register, a 0 is ignored. 02 rsvd reserved. must be written as ?0? 0h rw 01 txqe sets the mask for transmit queue empty 0h rw 00 txdw sets the mask for transmit descriptor written back 0h rw table 37-44. ims1: interrupt 1 mask set/read register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08d0h 08d3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08d0h 08d3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08d0h 08d3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access table 37-45. imc1: interrupt 1 mask clear register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08d8h 08dbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08d8h 08dbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08d8h 08dbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus clears the mask for internal bus error 0h wo 27 err_stat clears the mask for statistic register ecc error 0h wo 26 err_mcfspf clears the mask for the filter memory errors 0h wo 25 : 24 rsvd reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1468 order number: 320066-003us 23 err_pkbuf clears the mask for dma packet buffer ecc error 0h wo 22 rsvd reserved 0h rv 21 err_txds clears the mask for dma transmit descriptor buffer ecc error 0h wo 20 err_rxds clears the mask for dma receive descriptor buffer ecc error 0h wo 19 : 17 rsvd reserved 0h rv 16 srpd clears the mask for small receive packet detected and tra n sf e rr e d 0h wo 15 txd_low clears the mask for transmit descriptor low threshold hit 0h wo 14 : 8 rsvd reserved 0h rv 07 rxt0 clears the mask for receiver timer interrupt 0h wo 06 rxo clears the mask for receiver overrun. set on receive data fifo overrun 0h wo 05 rsvd reserved 0h rv 04 rxdmt0 clears the mask for receive descriptor minimum threshold hit 0h wo 03 rsvd reserved 0h wo 02 rsvd reserved 0h rv 01 txqe clears the mask for transmit queue empty 0h wo 00 txdw clears the mask for transmit descriptor written back 0h wo table 37-45. imc1: interrupt 1 mask clear register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08d8h 08dbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08d8h 08dbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08d8h 08dbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1469 intel ? ep80579 integrated processor 37.6.3.10 icr2 ? error interrupt cause read register this register contains all interrupt conditions for the gbe. whenever an interrupt causing event occurs, the corresponding interrupt bit is set in this register. see ?ims0 ? interrupt 0 mask set/read register? on page 1459 for additional details. note: all register bits clear on read. thus, reading this register implicitly acknowledges all pending interrupt events. writing a 1 to any bit in the register will also clear that bit. writing a 0 to any bit will have no effect. table 37-46. icr2: error interrupt cause read register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08e0h 08e3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08e0h 08e3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08e0h 08e3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus internal bus error. this bit indicates that an error occurred during either a target or host transaction on the bus. refer to section 37.5.12, ?error handling? for complete details. the details of this error are reported in the intbus_err_stat register. 0h rcwc 27 err_stat statistic register ecc error. the statistic registers are implemented using a memory that uses a single-bit correct/multi-bit detect ecc parity algorithm to protect it. this bit indicates that a multi-bit error has occurred on a read from that memory. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst) 0h rcwc 26 err_mcfspf multicast filter parity error/special packet filter parity error. the multicast filter and special packets filter use parity protected srams for data buffers. this bit indicates that a parity error has occurred on a read from either of these data buffers. 0h rcwc 25 : 24 rsvd reserved 0h rv 23 err_pb dma packet buffer 2-bit ecc error. the 64kb dma packet buffer uses a single-bit correct/multi-bit detect ecc parity algorithm to protect the sram it uses for data. this bit indicates that a multi-bit error has occurred on a read from that sram. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register (ctrl.rst). 0h rcwc 22 rsvd reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1470 order number: 320066-003us 21 err_txds dma transmit descriptor 2-bit ecc error. the dma transmit descriptor buffer uses a single-bit correct/multi- bit detect ecc parity algorithm to protect the sram it uses for a data buffer. this bit indicates that a multi-bit error has occurred on a read from that data buffer. no indication of a single-bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst). 0h rcwc 20 err_rxds dma receive descriptor 2-bit ecc error. the dma receive descriptor buffer uses a single-bit correct/multi-bit detect ecc parity algorithm to protect the sram it uses for a data buffer. this bit indicates that a multi-bit error has occurred on a read from that data buffer. no indication of a single- bit error correction will be given by hardware. note: if this interrupt asserts, further gbe dma reads and writes are blocked until software issues a soft reset to the gbe by writing the device control register ( ctrl .rst). 0h rcwc 19 : 00 rsvd reserved 0h rv table 37-46. icr2: error interrupt cause read register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08e0h 08e3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08e0h 08e3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08e0h 08e3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1471 intel ? ep80579 integrated processor 37.6.3.11 ics2 ? error interrupt cause set register software uses this register to set an interrupt condition. assuming the interrupt mask is set, any bit written with a 1 triggers the corresponding interrupt, see ?ims0 ? interrupt 0 mask set/read register? on page 1459 and ?icr0 ? interrupt 0 cause read register? on page 1454 . table 37-47. ics2: error interrupt cause set register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08e8h 08ebh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08e8h 08ebh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08e8h 08ebh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus triggers internal bus error 0h rw 27 err_stat triggers statistic register ecc error 0h rw 26 err_mcfspf triggers special packet filter parity error 0h rw 25 : 24 rsvd reserved 0h rv 23 err_pkbuf triggers dma packet buffer ecc error 0h rw 22 rsvd reserved 0h rv 21 err_txds triggers dma transmit descriptor buffer ecc error 0h rw 20 err_rxds triggers dma receive descriptor buffer ecc error 0h rw 19 : 00 rsvd reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1472 order number: 320066-003us 37.6.3.12 ims2 ? error interrupt mask set/read register this register contains which interrupts are enabled. an interrupt is enabled if its corresponding mask bit is set to 1, and disabled if its corresponding mask bit is set to 0. an interrupt is generated whenever one of the bits in this register is set, and the corresponding interrupt condition occurs, see the ?icr0 ? interrupt 0 cause read register? on page 1454 for interrupt conditions. a particular interrupt may be enabled by writing a 1 to the corresponding mask bit in this register. any bits written with a 0, are unchanged. thus, if software desires to disable a particular interrupt condition that had been previously enabled, it must write to the interrupt mask clear register rather than writing a 0 to a bit in this register. table 37-48. ims2: error interrupt mask set/read register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08f0h 08f3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08f0h 08f3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08f0h 08f3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus enables internal bus error 0h rw 27 err_stat enables statistic register ecc error 0h rw 26 err_mcfspf enables special packet filter parity error 0h rw 25 : 24 rsvd reserved 0h rv 23 err_pkbuf enables dma packet buffer ecc error 0h rw 22 rsvd reserved 0h rv 21 err_txds enables dma transmit descriptor buffer ecc error 0h rw 20 err_rxds enables dma receive descriptor buffer ecc error 0h rw 19 : 00 rsvd reserved 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1473 intel ? ep80579 integrated processor 37.6.3.13 imc2 ? error interrupt mask clear register software uses this register to disable an interrupt condition that was previously enabled. interrupts are presented to the bus interface only when the mask bit is set and the interrupt condition is active. the status of the mask bit is reflected in the ?ims0 ? interrupt 0 mask set/read register? on page 1459 , and the status of the cause bit is reflected in the ?icr0 ? interrupt 0 cause read register? on page 1454 . software disables a given interrupt by writing a 1 to the corresponding bit in this register, a 0 is ignored. table 37-49. imc2: error interrupt mask clear register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 08f8h 08fbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 08f8h 08fbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 08f8h 08fbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 29 rsvd reserved 0h rv 28 err_intbus clears the mask for internal bus error 0h wo 27 err_stat clears the mask for statistic register ecc error 0h wo 26 err_int clears the mask for internal memory error 0h wo 25 : 24 rsvd reserved 0h rv 23 err_pkbuf clears the mask for dma packet buffer ecc error 0h wo 22 rsvd reserved 0h rv 21 err_txds clears the mask for dma transmit descriptor buffer ecc error 0h wo 20 err_rxds clears the mask for dma receive descriptor buffer ecc error 0h wo 19 : 00 rsvd reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1474 order number: 320066-003us 37.6.4 receive registers: detailed descriptions 37.6.4.1 rctl ? receive control register this register controls the types and sizes of packets received, as well as any manipulation of those received packets. the size of the receive buffers where those packets reside before they are transferred to system memory is also controlled here. table 37-50. rctl: receive control register (sheet 1 of 4) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0100h 0103h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0100h 0103h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0100h 0103h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 27 rsvd reserved 0h rv 26 secrc strip ethernet crc. this bit controls whether the hardware strips the ethernet crc from the received packet. this stripping occurs prior to any checksum calculations. the stripped crc is not dma'd to host memory and is not included in the length reported in the descriptor. 0h rw 25 bsex buffer size extension. combined with rctl .bsize to program the receive buffer size. control of receive buffer size permits software to trade-off descriptor performance versus required storage space. buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes. rctl .bsex = 0 / rctl .bsize = 00 -> receive buffer size = 2048b rctl .bsex = 0 / rctl .bsize = 01 -> receive buffer size = 1024b rctl .bsex = 0 / rctl .bsize = 10 -> receive buffer size = 512b rctl .bsex = 0 / rctl .bsize = 11 -> receive buffer size = 256b rctl .bsex = 1 / rctl .bsize = 00 -> reserved rctl .bsex = 1 / rctl .bsize = 01 -> receive buffer size = 16384b rctl .bsex = 1 / rctl .bsize = 10 -> receive buffer size = 8192b rctl .bsex = 1 / rctl .bsize = 11 -> receive buffer size = 4096b 0h rw 24 rsvd reserved 0h rv 23 pmcf pass mac control frames. this bit controls the dma function of mac control frames (other than flow control). a mac control frame in this context must be addressed to either the mac control frame multicast address or the station address, it must match the type field and must not match the pause opcode of 0x0001. 0 = do not pass mac control frames 1 = pass any mac control frame (type field value of 0x8808) that does not contain the pause opcode of 0x0001. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1475 intel ? ep80579 integrated processor 22 dpf discard pause frames. this bit controls the dma function of flow control packets addressed to the station address ( rah / ral [0]). if a packet is a valid flow control packet and is addressed to the station address it will not be dma'd to host memory if rctl .dpf=1. 0 = incoming frames are subject to filter comparison 1 = incoming valid pause frames discarded even if they match any of the filter registers 0h rw 21 rsvd reserved 0h rv 20 cfi canonical form indicator. one of the three bits that control the vlan filter table. this bit may be compared to the cfi bit found in the 802.1q packet as part of the acceptance criteria. rctl .cfien and rctl .vfe determine whether or not this comparison takes place. 0h rw 19 cfien canonical form indicator enable. one of the three bits that control the vlan filter table. this bit enables using the cfi bit found in the 802.1q packet as part of the acceptance criteria. the next two are used to decide whether the cfi bit found in the.1q packet should be used as part of the acceptance criteria. 0 = cfi disabled: bit not compared to determine packet acceptance 1 = cfi from packet must match cfi field for acceptance of 802.1q packet 0h rw 18 vfe vlan filter enable. one of the three bits that control the vlan filter table. this bit determines whether the table participates in the packet acceptance criteria. 0 = disabled, filter table does not decide packet acceptance 1 = enabled, filter table decides acceptance of 802.1q packets 0h rw table 37-50. rctl: receive control register (sheet 2 of 4) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0100h 0103h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0100h 0103h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0100h 0103h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1476 order number: 320066-003us 17 : 16 bsize receive buffer size. combined with rctl .bsex to program the receive buffer size. control of receive buffer size permits software to trade-off descriptor performance versus required storage space. buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes. rctl .bsex = 0 / rctl .bsize = 00 -> receive buffer size = 2048b rctl .bsex = 0 / rctl .bsize = 01 -> receive buffer size = 1024b rctl .bsex = 0 / rctl .bsize = 10 -> receive buffer size = 512b rctl .bsex = 0 / rctl .bsize = 11 -> receive buffer size = 256b rctl .bsex = 1 / rctl .bsize = 00 -> reserved rctl .bsex = 1 / rctl .bsize = 01 -> receive buffer size = 16384b rctl .bsex = 1 / rctl .bsize = 10 -> receive buffer size = 8192b rctl .bsex = 1 / rctl .bsize = 11 -> receive buffer size = 4096b 00h rw 15 bam broadcast accept mode. 0 = ignore broadcast (unless it matches exact or imperfect filters) 1 = accept broadcast packets 0h rw 14 rsvd reserved 0h rv 13 : 12 mo multicast offset. this determines which bits of the incoming multicast address are used in looking up the bit vector. ? 00 = [47:36] ? 01 = [46:35] ? 10 = [45:34] ? 11 = [43:32] 0h rw 11 : 10 rsvd reserved 0h rv 09 : 08 rdmts receive descriptor minimum threshold size. these bits determines the threshold value for free receive descriptors. the corresponding interrupt is set whenever the fractional number of free descriptors becomes equal to rctl .rdmts. refer to ?rdlen ? receive descriptor length register? on page 1481 for further information. ? 00 = 1/2 ? 01 = 1/4 ? 10 = 1/8 ? 11 = reserved 00h rw table 37-50. rctl: receive control register (sheet 3 of 4) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0100h 0103h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0100h 0103h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0100h 0103h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1477 intel ? ep80579 integrated processor 07 : 06 lbm loopback mode. these bits enable the loopback function.when using a phy, a value of 00 should be used and the phy is configured for loopback through the mdio interface. ? 00 = normal operation (or phy loopback in gmii/mii mode) ? 01 = mac loopback enable (only supported for gmii/ mii mode) ? 10 = reserved ? 11 = reserved ? 11 = reserved note: phy devices require programming for loopback operation using mdio accesses. note: the gbe must be configured for full-duplex operation if mac loopback mode is enabled. 00h rw 05 lpe long packet enable. this bit controls whether long packet reception is permitted. 0 = disabled, hardware discards packets longer than 1522b 1 = enabled, 16384b is the maximum packet size that the gbe can receive 0h rw 04 mpe multicast promiscuous enable. 0 = disabled 1 = enabled 0h rw 03 upe unicast promiscuous enable. 0 = disabled 1 = enabled 0h rw 02 sbp store bad packets. 0 = disabled 1 = enabled 0h rw 01 en receiver enable. 0 = all incoming packets are immediately dropped and are not stored in the receive fifo. if a packet is already in-progress when disabled it will be finished. 1 = incoming packet reception is enabled. 0h rw 00 rsvd reserved 0h rv table 37-50. rctl: receive control register (sheet 4 of 4) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0100h 0103h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0100h 0103h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0100h 0103h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1478 order number: 320066-003us 37.6.4.2 fcrtl: flow control receive threshold low register this register contains the receive threshold used to determine when to send an xon packet, counting in units of bytes. the lower 3 bits must be programmed to 0 (8b granularity). whenever hardware crosses the receive high threshold (becoming more full), and then crosses the receive low threshold, then hardware will transmits an xon frame (if enabled with fcrtl .xone). note: flow control reception/transmission are negotiated capabilities by the auto-negotiation process. when the device is manually configured, flow control operation is determined by the ctrl .rfce & ctrl .tfce. table 37-51. fcrtl: flow control receive threshold low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2160h 2163h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2160h 2163h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2160h 2163h size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 xone xon enable 0b = disabled. 1b = enabled. when set, enables the ethernet controller to transmit xon packets based on receive fifo crosses fcrtl.rtl threshold value, or based on external pins xoff and xon. see section 37.6.4.3, ?fcrth ? flow control receive threshold high register? on page 1479 0h rw 30 : 16 rsvd reserved 0h rv 15 : 03 rtl receive threshold low. fifo low water mark for flow control transmission. 0h rw 02 : 00 0 writes are ignored, reads return 0. 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1479 intel ? ep80579 integrated processor 37.6.4.3 fcrth ? flow control receive threshold high register this register contains the receive threshold used to determine when to send an xoff packet. it counts in units of bytes. this value must be at least 8 bytes less than the maximum number of bytes allocated to the receive packet buffer ( pba , rxa), and the lower 3 bits must be programmed to 0 (8b granularity). whenever the receive fifo reaches the fullness indicated by fcrth .rth, hardware transmits a pause frame if the transmission of flow control frames is enabled. note: flow control reception/transmission are negotiated capabilities by the auto-negotiation process. when the device is manually configured, flow control operation is determined by the ctrl .rfce & ctrl .tfce. table 37-52. fcrth: flow control receive threshold high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2168h 216bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2168h 216bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2168h 216bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 xfce external flow control enabled 0b = disabled. 1b = enabled. allows the ethernet controller to send xoff and xon frames based on external pins xoff and xon. the transmission of pause frames must be also enabled through the ctrl.tfce control bit. when the xoff signal is asserted high, the ethernet controller transmits a single xoff frame. the assertion of xon (after deassertion of xoff) initiates an xon frame transmission, if enabled by fcrtl.xone. the assertion/deassertion of xon is required between assertions of xoff in order to send another xoff frame. this behavior also provides a built-in hysteresis mechanism. note: the ep80579 does not have external xon/xoff pins and therefore does not support external flow control enable. this bit must be set to 0 for correct operation. 0h rw 30 : 16 rsvd reserved 0h rv 15 : 03 rth receive threshold high. fifo high water mark for flow control transmission. 0h rw 02 : 00 0 writes are ignored, reads return 0. 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1480 order number: 320066-003us 37.6.4.4 rdbal ? receive descriptor base address low register this register contains the lower bits of the 64 bit descriptor base address. the receive descriptor base address must point to a 16b aligned block of data (i.e. the lower 4 bits are always 0). 37.6.4.5 rdbah ? receive descriptor base address high register this register contains the upper 32 bits of the 64 bit descriptor base address. table 37-53. rdbal: receive descriptor base address low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2800h 2803h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2800h 2803h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2800h 2803h size: 32 bits default: xxxxxxx0h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 rdbal receive descriptor base address low x rw 03 : 00 0 writes are ignored, reads return 0. 0h rv table 37-54. rdbah: receive descriptor base address high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2804h 2807h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2804h 2807h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2804h 2807h size: 32 bits default: xxxxxxxxh power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 rdbah receive descriptor base address. note: rdbah[31:0] must be set to 0. xrw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1481 intel ? ep80579 integrated processor 37.6.4.6 rdlen ? receive descriptor length register this register sets the number of bytes allocated for descriptors in the circular descriptor buffer. this value must be 128b aligned (i.e., the lower 7 bits are always 0). 37.6.4.7 rdh ? receive descriptor head register this register contains the head pointer for the receive descriptor buffer. the register points to a 16b datum. hardware controls the pointer. writing this register at any time will cause indeterminate behavior. table 37-55. rdlen: receive descriptor length register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2808h 280bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2808h 280bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2808h 280bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 rsvd reserved 0h rv 19 : 07 len descriptor length 0h rw 06 : 00 0 writes are ignored, reads return 0. 0h rv table 37-56. rdh: receive descriptor head register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2810h 2813h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2810h 2813h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2810h 2813h size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 rdh receive descriptor head 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1482 order number: 320066-003us 37.6.4.8 rdt ? receive descriptor tail register this register contains the tail pointers for the receive descriptor buffer. the register points to a 16b datum. software writes the tail register to add receive descriptors to the hardware free list for the ring. 37.6.4.9 rdtr ? rx interrupt delay timer (packet timer) register this register is used to delay interrupt notification for the receive descriptor ring by coalescing interrupts for multiple received packets. delaying interrupt notification helps maximize the number of receive packets serviced by a single interrupt. this feature operates by initiating a countdown timer upon successfully receiving each packet to system memory. if a subsequent packet is received before the timer expires, the timer is reinitialized to the programmed value and re-starts its countdown. if the timer expires due to not having received a subsequent packet within the programmed interval, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated. setting the value to 0b represents no delay from a receive packet to the interrupt notification, an results in immediate interrupt notification for each received packet. writing this register with fpd set initiates an immediate expiration of the timer, causing a writeback of any consumed receive descriptors pending writeback, and results in a receive timer interrupt in the icr. receive interrupts due to a receive absolute timer (radv) expiration cancels a pending rdtr interrupt. the rdtr countdown timer is reloaded but halted, so as to avoid generation of a spurious second interrupt after the radv has been noted, but might be restarted by a subsequent received packet. table 37-57. rdt: receive descriptor tail register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2818h 281bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2818h 281bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2818h 281bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 rdt receive descriptor tail 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1483 intel ? ep80579 integrated processor 37.6.4.10 rxdctl ? receive descriptor control register this register controls the fetching and write-back of receive descriptors. the three threshold values are used to determine when descriptors will be read from and written to host memory. the values may be in units of cache lines or 16b descriptors. table 37-58. rdtr: rx interrupt delay timer (packet timer) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2820h 2823h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2820h 2823h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2820h 2823h size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 fpd flush partial descriptor. writing this bit with 1 initiates an immediate expiration of the timer, causing a writeback of any consumed receive descriptors pending writeback, and results in a receive timer interrupt in the icr register. this bit is self clearing and always reads 0. 0h wo 30 : 16 rsvd reserved 0h rv 15 : 00 rpdt receive packet delay timer timer increments are rmii: 1.28 microseconds rgmii: 1.024 microseconds. see register description above 0h rw table 37-59. rxdctl: receive descriptor control register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2828h 282bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2828h 282bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2828h 282bh size: 32 bits default: 00010000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 25 rsvd reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1484 order number: 320066-003us 24 gran granularity of the thresholds in this register. 0 = threshold values are in units of cache lines, thresholds specified must not be greater than 31 descriptors (496b) or 15 32b cache lines. 1 = threshold values are in units of descriptors (16b each) 0h rw 23 : 22 rsvd reserved 0h rv 21 : 16 wthresh write-back threshold. this field controls the write-back of processed receive descriptors. this threshold refers to the number of receive descriptors in the gbe hardware buffer which are ready to be written back to host memory. in the absence of external events (explicit flushes), the write-back will occur only after more than wthresh descriptors are available for write-back. note: since the default value for this field is 1, the descriptors are normally written back as soon as one cache line is available. this field must contain a non-zero value to take advantage of the write- back bursting capabilities of the ep80579?s gbe. 01h rw 15 : 14 rsvd reserved 0h rv 13 : 08 hthresh host threshold. this field is used to control the fetching of descriptors from host memory. this threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched. 0h rw 07 : 06 rsvd reserved 0h rv 05 : 00 pthresh prefetch threshold. this field is used to control when a prefetch of descriptors will be considered. this threshold refers to the number of valid, unprocessed receive descriptors the chip has in its gbe hardware buffer. if this number drops below pthresh, the algorithm will consider pre-fetching descriptors from host memory. this fetch will not happen however unless there are at least hthresh valid descriptors in host memory to fetch. 0h rw table 37-59. rxdctl: receive descriptor control register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2828h 282bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2828h 282bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2828h 282bh size: 32 bits default: 00010000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1485 intel ? ep80579 integrated processor 37.6.4.11 radv ? receive interrupt absolute delay timer register table 37-60. radv: receive interrupt absolute delay timer register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 282ch 282fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 282ch 282fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 282ch 282fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 radt receive absolute delay timer receive absolute delay timer measured in increments of rmii: 1.28 microseconds rgmii: 1.024 microseconds. (0b =disabled) if the packet delay timer is used to coalesce receive interrupts, the ethernet controller ensures that when receive traffic abates, an interrupt is generated within a specified interval of no receives. during times when receive traffic is continuous, it may be necessary to ensure that no receive remains unnoticed for too long an interval. this register can be used to ensure that a receive interrupt occurs at some predefined interval after the first packet is received. when this timer is enabled, a separate absolute countdown timer is initiated upon successfully receiving each packet to system memory. when this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated. setting this register to 0b disables the absolute timer mechanism (the rdtr register should be used with a value of 0b to cause immediate interrupts for all receive packets). receive interrupts due to a receive packet timer (rdtr) expiration cancels a pending radv interrupt. if enabled, the radv countdown timer is reloaded but halted, so as to avoid generation of a spurious second interrupt after the rdtr has been noted. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1486 order number: 320066-003us 37.6.4.12 rsrpd ? receive small packet detect interrupt register this register will generate an interrupt condition when any received packet is less than or equal to the size programmed. table 37-61. rsrpd: receive small packet detect interrupt register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 2c00h 2c03h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 2c00h 2c03h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 2c00h 2c03h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 rsvd reserved 0h rv 11 : 00 size any packet received that is <= size will assert an interrupt condition (icr.srpd). this field is specified in bytes and includes the headers and the crc but not the vlan header in the size calculation. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1487 intel ? ep80579 integrated processor 37.6.4.13 rxcsum ? receive checksum control register this register controls the receive checksum off loading features. the gbe supports the off loading of three receive checksum calculations: the packet checksum, the ip header checksum, and the tcp/udp checksum. supported frame types are ethernet ii and ethernet snap. this register should only be written when the receiver is not enabled (i.e., only when rctl .en = 0). table 37-62. rxcsum: receive checksum control register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5000h 5003h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5000h 5003h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5000h 5003h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 rsvd reserved 0h rv 09 tuofl tcp/udp checksum off load enable. this bit is used to enable the tcp/udp checksum off-loading feature. 0 = tcp/udp checksum off load disabled 1 = hardware will calculate the tcp or udp checksum and indicate a pass/fail indication to software via the tcp/ udp checksum error bit (tcpe). 0h rw 08 ipofl ip checksum off load enable. this bit is used to enable the ip checksum off-loading feature. 0 = ip checksum off load disabled 1 = hardware will calculate the ip checksum and indicate a pass/fail indication to software via the ip checksum error bit (ipe) in the error field of the receive descriptor. 0h rw 07 : 00 pcss packet checksum start. this field controls the starting byte for the packet checksum calculation. the packet checksum is the one's complement over the receive packet, starting from the byte indicated by pcss (0 corresponds to the first byte of the packet), after stripping. for example, for an ethernet ii frame encapsulated as an 802.3ac vlan packet and with pcss set to 14, the packet checksum would include the entire encapsulated frame, excluding the 14-byte ethernet header (da, sa, type and length) and the 4-byte vlan tag. the packet checksum will not include the ethernet crc if the rctl.secrc bit is set. software must make the required offsetting computation (to back out the bytes that should not have been included and to include the pseudo-header) prior to comparing the packet checksum against the tcp checksum stored in the packet. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1488 order number: 320066-003us 37.6.4.14 mta[0-127] ? 128 multicast table array registers there is one register per 32 bits of the multicast address table for a total of 128 registers (thus the mta[127:0] designation). the size of the word array depends on the number of bits implemented in the multicast address table. software must mask to the desired bit on reads and supply a 32-bit word on writes. refer to ?receive initialization? on page 1348 for details on initialization and usage. 37.6.4.15 ral[0-15] ? receive address low register these registers contain the lower bits of the 48 bit ethernet address. table 37-63. mta[0-127] ? 128 multicast table array registers description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5200h at 4h 5203h at 4h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5200h at 4h 5203h at 4h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5200h at 4h 5203h at 4h size: 32 bits default: xxxx_xxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 vector 32b vector of multicast address filter table information. x rw table 37-64. ral[0-15] - receive address low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5400h at 8h 5403h at 8h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5400h at 8h 5403h at 8h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5400h at 8h 5403h at 8h size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/ 2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ral receive address low. the lower 32 bits of the 48 bit ethernet address. xrw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1489 intel ? ep80579 integrated processor 37.6.4.16 rah[0-15] ? receive address high register these registers contain the upper bits of the 48 bit ethernet address. the complete 48b address is { rah , ral }. the first receive address register (rar0) is also used for exact match pause frame checking (i.e. the destination address matches the first register). therefore rar0 should always be used to store the individual ethernet mac address of the adapter. table 37-65. rah[0-15] - receive address high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5404h at 8h 5407h at 8h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5404h at 8h 5407h at 8h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5404h at 8h 5407h at 8h size: 32 bits default: 000xxxxxh power well: gbe0: aux gbe1/ 2: core bit range bit acronym bit description sticky bit reset value bit access 31 av address valid. this bit determines whether this address is compared against the incoming packet. cleared after software reset or unit reset. 0 = no match on this address field 1 = match on this address field 0h rw 30 : 18 rsvd reserved 0h rv 17 : 16 asel address select. selects how the address is to be used when performing special filtering on receive packets. ? 00: destination address (must be set to this in normal mode) ? 01: source address ? 10: reserved ? 11: reserved xrw 15 : 00 rah receive address high. the upper 16 bits of the 48 bit ethernet address. xrw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1490 order number: 320066-003us 37.6.4.17 vfta[0-127] ? 128 vlan filter table array registers there is one register per 32 bits of the vlan filter table. the size of the word array depends on the number of bits implemented in the vlan filter table. software must mask to the desired bit on reads and supply a 32-bit word on writes. the algorithm for vlan filtering via the vfta is identical to that used for the multicast table array, refer to ?receive initialization? on page 1348 for details on initialization and usage. table 37-66. vfta[0-127] - 128 vlan filter table array registers description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5600h at 4h 5603h at 4h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5600h at 4h 5603h at 4h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5600h at 4h 5603h at 4h size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 vlan_vector 32b vector of vlan filter table information. x rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1491 intel ? ep80579 integrated processor 37.6.5 transmit registers: detailed descriptions 37.6.5.1 tctl ? transmit control register this register controls packet transmission. packet collision recovery, 64b data padding, and software xoff transmission are controlled here. table 37-67. tctl: transmit control register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0400h 0403h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0400h 0403h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0400h 0403h size: 32 bits default: 00000008h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 25 rsvd reserved 0h rv 24 rtlc re-transmit on late collision. this bit configures the hardware to perform retransmission of packets when a late collision is detected. note that the collision window is speed dependent: 64b for 10/100 mbps and 512b for 1gbps operation. if a late collision is detected when this bit is clear, the transmit function assumes the packet is successfully transmitted. note: this bit is ignored in full-duplex mode. 0h rw 23 pbe packet burst enable. the ep80579?s gbe does not support packet bursting for 1gbps half-duplex transmit operation. this bit must be set to 0. 0h rv 22 swxoff software xoff transmission. when set to a 1 the device will schedule the transmission of an xoff (pause) frame using the current value of the pause timer. this bit clears itself upon transmission of the xoff frame. note: while 802.3x flow control is only defined during full duplex operation, the sending of pause frames via the swxoff bit is not gated by the duplex settings within the device. software should not write a 1 to this bit while the device is configured for half duplex operation. 0h rw 21 : 12 cold collision distance. wire speeds of 1gbps result in a very short collision radius with traditional minimum packet sizes. this bit specifies the minimum number of bytes in the packet to satisfy the desired collision distance for proper csma/cd operation. it is important to note that the resulting packet has special characters appended to the end, not regular data characters. hardware strips special characters for packets that go from 1 gbps environments to 100 mbps environments. note: the hardware checks and pads to this value even in full-duplex operation. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1492 order number: 320066-003us 11 : 04 ct collision threshold. software may choose to abort packet transmission in less than the ethernet mandated 16 collisions. this field determines the number of attempts at retransmission prior to giving up on the packet (not including the first transmission attempt). the ethernet back-off algorithm is implemented and clamps to the maximum number of slot-times after 10 retries. this field only has meaning when in half-duplex operation. note: while this field can be varied, it should be set to a value of 15 in order to comply with the ieee specification requiring a total of 16 attempts. 0h rw 03 psp pad short packets to 64b with valid data characters, not padding symbols. 0 = do not pad short packets 1 = pad short packets note: this is not the same as the mini-mum collision distance. 1h rw 02 rsvd reserved. 0h rv 01 en enable. 0 = writing this bit to 0 will stop transmission after any in progress packets are sent. data remains in the transmit fifo until the device is re-enabled. software should combine this with reset if the packets in the fifo should be flushed. 1 = the transmitter is enabled. 0h rw 00 rsvd reserved. 0h rv table 37-67. tctl: transmit control register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0400h 0403h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0400h 0403h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0400h 0403h size: 32 bits default: 00000008h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1493 intel ? ep80579 integrated processor 37.6.5.2 tipg ? transmit ipg register this register controls the inter packet gap (ipg) timer. table 37-68. tipg: transmit ipg register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0410h 0413h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0410h 0413h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0410h 0413h size: 32 bits default: 00602008h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 30 rsvd reserved 0h rv 29 : 20 ipgr2 ipg receive time 2. specifies the total length of the ipg time for non back-to- back transmissions. measured in increments of the mac clock: ? 8 ns mac clock when operating @ 1 gbps (82544gc/ei only). ? 80 ns mac clock when operating @ 100 mbps ? 800 ns mac clock when operating @ 10 mbps. in order to calculate the actual ipg value, a value of six should be added to the ipgr2 value as six mac clocks are used by the mac for synchronization and internal engines. for the ieee 802.3 standard ipg value of 96-bit time, the value that should be programmed into ipgr2 is six (total ipg delay of 12 mac clock cycles) according to the ieee802.3 standard, ipgr1 should be 2/3 of ipgr2 value.ipgr2 is significant only in half-duplex mode of operation. 0x6h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1494 order number: 320066-003us 19 : 10 ipgr1 ipg receive time 1. specifies the length of the first part of the ipg time for non back-to- back transmissions. during this time, the internal ipg counter restarts if any carrier event occurs. once the time specified in ipgr1 has elapsed, carrier sense does not affect the ipg counter. according to the ieee802.3 standard, ipgr1 should be 2/3 of ipgr2 value. measured in increments of the mac clock: ? 8 ns mac clock when operating @ 1 gbps ? 80 ns mac clock when operating @ 100 mbps ? 800 ns mac clock when operating @ 10 mbps. for ieee 802.3 minimum ipg value of 96-bit time, the value that should be progra mmed into ipgr1 is eight. ipgr1 is significant only in half-duplex mode of operation. 0x8h rw 09 : 00 ipgt ipg transmit time specifies the ipg time for back-to-back packet transmissions measured in increments of the mac clock: ? 8 ns mac clock when operating @ 1 gbps. ? 80 ns mac clock when operating @ 100 mbps. ? 800 ns mac clock when operating @ 10 mbps. to calculate the ipg value for 10/100/1000base-t applications, a value of four should be added to the ipgt value as four clocks are used by the mac as internal overhead. the value that should be programmed into ipgt is 8. these values are recommended to assure that the minimum ipg gap is met under all synchronization conditions. 0x8h rw table 37-68. tipg: transmit ipg register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0410h 0413h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0410h 0413h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0410h 0413h size: 32 bits default: 00602008h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1495 intel ? ep80579 integrated processor 37.6.5.3 ait ? adaptive ifs throttle register adaptive ifs throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the csma/cd transmit function. this can be used to delay the transmission of back-to-back packets on the wire. normally, this register should be set to 0. however, if additional delay is desired between back-to-back transmits, then this register may be set with a value greater than zero. the adaptive ifs throttle timer provides a similar function to the ?tipg ? transmit ipg register? on page 1493 , however, adaptive ifs affects only the initial transmission timing, not re-transmission timing. table 37-69. ait: adaptive ifs throttle register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0458h 045bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0458h 045bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0458h 045bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 aifs adaptive ifs value adaptive ifs throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the csma/cd transmit function. normally, this register should be set to 0b. however, if additional delay is desired between back-to-back transmit packets, then this register can be set with a value greater than zero (0). this feature can be helpful in high collision half-duplex environments. in order for aifs to take effect it should be larger than the minimum ifs value defined in ieee 802.3 standard. aifs has no effect on transmissions that occur immediately after receives or transmissions that are not back-to-back. in addition, it has no effect on re-transmission timing (retransmission after collisions). the aifs value is additive to the tipg.ipgt value. this time unit for this value is speed dependent: 1000mbps is 8ns 100mbps is 80ns 10 mbps is 800ns 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1496 order number: 320066-003us 37.6.5.4 tdbal ? transmit descriptor base address low register this register contains the lower bits of the 64 bit descriptor base address. the transmit descriptor base address must point to a 16b aligned block of data (i.e. the lower 4 bits are always 0). 37.6.5.5 tdbah ? transmit descriptor base address high register this register contains the upper 32 bits of the 64 bit descriptor base address. table 37-70. tdbal: transmit descriptor base address low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3800h 3803h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3800h 3803h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3800h 3803h size: 32 bits default: xxxxxxx0h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 tdbal transmit descriptor base address low x rw 03 : 00 0 writes are ignored, reads return 0. 0h rv table 37-71. tdbah: transmit descriptor base address high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3804h 3807h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3804h 3807h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3804h 3807h size: 32 bits default: xxxxxxxxh power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 tdbah transmit descriptor base address note: tdbah[31:0] must be set to 0. xrw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1497 intel ? ep80579 integrated processor 37.6.5.6 tdlen ? transmit descriptor length register this register contains the descriptor length and must be 128b aligned (i.e. the lower 7 bits are always 0). 37.6.5.7 tdh ? transmit descriptor head register this register contains the head pointer for the transmit descriptor ring. it points to a 16b datum. hardware controls this pointer. the only time that software should write to this register is after a reset (hardware reset or ctrl .rst) and before enabling the transmit function ( tctl .en). writing this register while the transmit function is enabled will cause indeterminate behavior. table 37-72. tdlen: transmit descriptor length register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3808h 380bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3808h 380bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3808h 380bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 rsvd reserved 0h rv 19 : 07 len descriptor length 0h rw 06 : 00 0 writes are ignored, reads return 0. 0h rv table 37-73. tdh: transmit descriptor head register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3810h 3813h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3810h 3813h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3810h 3813h size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 tdh transmit descriptor head 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1498 order number: 320066-003us 37.6.5.8 tdt ? transmit descriptor tail register this register contains the tail pointer for the transmit descriptor ring. it points to a 16b datum. software writes the tail pointer to add more descriptors to the transmit ready queue. hardware attempts to transmit all packets referenced by descriptors between head and tail. table 37-74. tdt: transmit descriptor tail register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3818h 381bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3818h 381bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3818h 381bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 tdt transmit descriptor tail 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1499 intel ? ep80579 integrated processor 37.6.5.9 tidv ? transmit interrupt delay value register this register is used to delay interrupt notification for transmit operations by coalescing interrupts for multiple transmitted buffers. delaying interrupt notification helps maximize the amount of transmit buffers reclaimed by a single interrupt. this feature only applies to transmit descriptor operations where interrupt-based reporting is requested (rs set) and the use of the timer function is requested (ide is set). table 37-75. tidv: transmit interrupt delay value register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3820h 3823h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3820h 3823h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3820h 3823h size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 idv interrupt delay value. timer increments are rmii: 1.28 microseconds rgmii: 1.024 microseconds. ? this register is used to delay interrupt notification for transmit operations by coalescing interrupts for multiple transmitted buffers. delaying interrupt notification helps maximize the amount of transmit buffers reclaimed by a single interrupt. this feature only applies to transmit descriptor operations where (a) interrupt-based reporting is requested (rs set) and (b) the use of the timer function is requested (ide is set). ? this feature operates by initiating a countdown timer upon successfully transmitting the buffer. if a subsequent transmit delayed-interrupt is scheduled before the timer expires, the timer is re-initialized to the programmed value and re-starts its countdown. when the timer expires, a transmit-complete interrupt (icr.txdw) is generated. ? hardware always loads the transmit interrupt counter whenever it processes a descriptor with ide set even if it is already counting down due to a previous descriptor. ? setting the value to 0 is not allowed. if an immediate (non-scheduled) interrupt is desired for any transmit descriptor, the descriptor ide should be set to 0. ? the occurrence of either an immediate (non- scheduled) or absolute transmit timer interrupt will halt the tidv timer and eliminate any spurious second interrupts. ? transmit interrupts due to a transmit absolute timer (tadv) expiration or an immediate interrupt (rs =1, ide=0) will cancel a pending tidv interrupt. the tidv countdown timer is reloaded but halted, though it may be restarted by a processing a subsequent transmit descriptor. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1500 order number: 320066-003us 37.6.5.10 txdctl ? transmit descriptor control register this register controls the fetching and write-back of transmit descriptors. the three threshold values are used to determine when descriptors will be read from and written to host memory. the values may be in units of cache lines or 16b descriptors. table 37-76. txdctl: transmit descriptor control register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3828h 382bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3828h 382bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3828h 382bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 25 lwthresh transmit descriptor low threshold. this field controls the number of pre-fetched transmit descriptors at which a transmit descriptor-low interrupt is reported. asserting icr.txd_low only when the processing distance from the tdt register drops below lwthresh may allow software to operate more efficiently by maintaining a continuous addition of transmit work, interrupting only when the hardware nears completion of all submitted work. an interrupt condition is asserted when the number of descriptors available transitions from threshold_level + 1 -> threshold_level where lwthresh specifies a multiple of 8 descriptors, (i.e. threshold_level = 8*lwthresh). setting this value to 0 will cause this interrupt to be generated only when the transmit descriptor cache becomes completely empty. 0h rw 24 gran granularity of the thresholds in this register. 0 = cache lines 1 = descriptors (16b each) 0h rw 23 : 22 rsvd reserved 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1501 intel ? ep80579 integrated processor 21 : 16 wthresh write-back threshold. this field controls the write-back of processed transmit descriptors. this threshold refers to the number of transmit descriptors in the gbe hardware buffer which are ready to be written back to host memory. in the absence of external events (explicit flushes), the write-back will occur only after more than wthresh descriptors are available for write-back. since write-back notification of transmit descriptor completion is optional (under the control of the rs bit in the descriptor), not all processed descriptors are counted with respect to wthresh (any single transmit descriptor with rs=0 is consumed with no writeback notification performed). when wthresh is non-zero, processing a descriptor with rs=1 initiates accumulation of pending writebacks; accumulated writebacks will include even those descriptors with rs=0, in order to optimize writeback bursts. note: when wthresh value is set to 0, transmit descriptor writeback notification will be similar to the 82452 behavior. in accordance with wthresh=0, the writeback notification for a descriptor with rs=1 will occur as soon as the descriptor is processed. in addition, processed transmit descriptors are not written-back in entirety; only the descriptor status field is written back/ updated. this 82542-compatible mode is the default hw behavior. 0h rw 15 : 14 rsvd reserved 0h rv 13 : 08 hthresh host threshold. this field is used to control the fetching of descriptors from host memory. this threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched. 0h rw 07 : 06 rsvd reserved 0h rv 05 : 00 pthresh prefetch threshold. this field is used to control when a prefetch of descriptors will be considered. this threshold refers to the number of valid, unprocessed transmit descriptors the chip has in its gbe hardware buffer. if this number drops below pthresh, the algorithm will consider pre-fetching descriptors from host memory. this fetch will not happen however unless there are at least hthresh valid descriptors in host memory to fetch. 0h rw table 37-76. txdctl: transmit descriptor control register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3828h 382bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3828h 382bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3828h 382bh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1502 order number: 320066-003us 37.6.5.11 tadv ? transmit absolute interrupt delay value register the transmit absolute interrupt delay value register ( tadv ) may be used to coalesce transmit interrupts, however, it may be necessary to ensure that no completed transmission remains unnoticed for too long an interval in order ensure timely release of transmit buffers. this register may be used to ensure that a transmit interrupt occurs at some predefined interval after a transmit is completed. like the tidv , the absolute transmit timer only applies to transmit descriptor operations where interrupt- based reporting is requested (rs set) and the use of the timer function is requested (ide is set). table 37-77. tadv: transmit absolute interrupt delay value register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 382ch 382fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 382ch 382fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 382ch 382fh size: 32 bits default: 00000000h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved 0h rv 15 : 00 idv interrupt delay value. timer increments are rmii: 1.28 microseconds rgmii: 1.024 microseconds. the transmit interrupt delay timer (tidv) can be used to coalesce transmit interrupts. however, it might be necessary to ensure that no completed transmit remains unnoticed for too long an interval in order ensure timely release of transmit buffers. this register can be used to ensure that a transmit interrupt occurs at some predefined interval after a transmit is completed. like the delayed-transmit timer, the absolute transmit timer only applies to transmit descriptor operations where (a) interrupt-based reporting is requested (rs set) and (b) the use of the timer function is requested (ide is set). this feature operates by initiating a countdown timer upon successfully transmitting the buffer. when the timer expires, a transmit-complete interrupt (icr.txdw) is generated. the occurrence of either an immediate (non- scheduled) or delayed transmit timer (tidv) expiration interrupt halts the tadv timer and eliminates any spurious second interrupts. setting the value to 0b disables the transmit absolute delay function. if an immediate (nonscheduled) interrupt is desired for any transmit descriptor, the descriptor ide should be set to 0b. note: this timer only causes an interrupt. it does not cause a writeback 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1503 intel ? ep80579 integrated processor 37.6.5.12 tspmt ? tcp segmentation pad and minimum threshold register this register specifies fields affecting hardware behavior during tcp segmentation operations. for normal (non tcp segmentation) operations, the transmit dma never begins servicing an individual data descriptor unless the transmit packet buffer has sufficient room to accept all of the data associated with the descriptor. however, for tcp segmentation operations, it may be desirable to use a data descriptor which refers to a larger contiguous buffer in host memory than is actually allocated for the transmit packet buffer. for this case, the transmit dma must be able to initiate smaller transfers than the entire descriptor's data length field (i.e., during tcp segmentation, the transmit dma does not wait until the entire descriptor's data can fit in the packet buffer). when performing tcp segmentation, the packet prototype header initially transferred by dma is stored internally and updated as each packet of the tcp segmentation operation is composed. as data for subsequent tcp segments is dma'd into the controller, the frame header for each segment is dynamically inserted in front of the frame payload data stream prior to being wr itten to the packet buffer. in order to obtain the most efficient use of burst dma operations, the transmit dma will attempt to fetch as much data from a descriptor as possibl e, rather than limiting itself to bursting each data segment individually. however, to do this, sufficient packet-buffer space must be reserved to account for all headers which will be inserted into the fetched data stream, as the burst may span multiple data segments. the calculation of how much packet buffer space should be reserved is dependent on the mss being used in the packet header, the maximum-sized data buffer pointed to by a descriptor, and the current header size. such calculation cannot be easily calculated in hardware, and is left to software to pre-calculate for the worst-case usage. the transmit dma will further refrain from initiating service of a new data descriptor unless sufficient packet buffer space exists to at least fetch a full data segment or complete a partially-fetched segment. this a dditionally helps to reduce the number of small dma bursts and reducing the efficiency of the host interface.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1504 order number: 320066-003us table 37-78. tspmt: tcp segmentation pad and minimum threshold register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 3830h 3833h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 3830h 3833h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 3830h 3833h size: 32 bits default: 01000400h power well: gbe0: core gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 tspbp tcp segmentation packet buffer padding , value is in bytes. this field allows software configuration of packet buffer space which must be reserved as ?pad? for worst- case header insertion. to ensure that this value does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (maximum tcp hdrlen + maximum mss + tspmt.tmpbp + 80 bytes). 0x0100h rw 15 : 00 tsmt tcp segmentation minimum transfer , value is in bytes. the dma will attempt to issue burst fetches for as much data as possible, and it is possible for the transmit dma to cause the transmit packet buffer to approach fullness (less the pad specified). however, if the packet buffer empties slightly, the transmit dma could initiate a series of small transfers. to further optimize the efficiency of the transmit dma during tcp segmentation operation, the this tspmt.tsmt field allows software configuration of the minimum number of bytes which the dma should attempt to transfer in a single burst operation. the transmit dma will use this value to refrain from issuing a burst read until at least tspmt.tsmt bytes of data from the current data descriptor can be stored in the packet buffer. this check will be ignored if, after a series of dma operations, the descriptor contains a smaller number of unfetched data bytes. to ensure that this minimum threshold does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (tspmt.tsmt + tspmt.tspbp + 80 bytes). 0x0400h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1505 intel ? ep80579 integrated processor 37.6.6 statistical registers: detailed descriptions the statistics registers generally assume the presence of a system host driver which has enabled transmit and receive operations between the gbe controller and host memory. throughout the descriptions of specific statistics registers, many require the driver to have enabled transmits enabled ( tctl .en=1) or receives enabled ( rctl .en=1). some of the registers provide an indication of link activity even when the driver has transmits or receives disabled. all statistics registers are cleared when read. it is the responsibility of software to maintain incremental count variables if statistics are intended to be monitored regularly for extended periods of time. all registers ?stick? at a maximum value of 0xffffffff when reached (until cleared by reset or a read) - if accurate statistics are required, it is expected that software will query statistics at sufficient intervals to avoid reaching maximum values and failing to count values unexpectedly. note: for the receive statistics it should be noted that a packet is indicated as ?received? if it passes the device's filters and is directed towards receive packet buffer memory. a packet does not have to be received all the way to the driver in order to be counted as ?received?. note: due to divergent paths between interrupt-generation and logging of relevant statistics counts, it may be possible to generate an interrupt to the system for a noteworthy event prior to the associated statistics count actually being incremented. this is extremely unlikely due to expected delays associated with the system interrupt- collection and isr delay, but might be observed as an interrupt for which statistics values do not quite make sense. hardware guarantees that any event noteworthy of inclusion in a statistics count will be reflected in the appropriate count within 1 usec; a small time-delay prior to read of statistics may be necessary to avoid the potential for receiving an interrupt and observing an inconsistent statistics count as part of the isr. 37.6.6.1 crcerrs ? crc error count register this register counts the number of receive packets with crc errors. in order for a packet to be counted in this register, it must pass mac address filtering (broadcast or individual-address/multicast match) and must be 64b or greater (from through , inclusively) in length. table 37-79. crcerrs: crc error count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4000h 4003h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4000h 4003h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4000h 4003h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 crcerrs crc error count 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1506 order number: 320066-003us 37.6.6.2 algnerrc ? alignment error count register this register counts the number of receive packets with alignment errors (i.e. the packet is not an integer number of bytes in length). in order for a packet to be counted in this register, it must pass mac address filtering (broadcast or individual-address/ multicast match) and must be 64b or grea ter (from through , inclusively) in length. this register is valid only in gmii/mii mode, during 10/ 100 mbps operation. 37.6.6.3 rxerrc ? receive error count register this register counts the number of packets received in which rx_er was asserted by the phy. in order for a packet to be counted in this register, it must pass mac address filtering (broadcast or individual-address/mu lticast match) and must be 64bor greater (from through , inclusively) in length. table 37-80. algnerrc: alignment error count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4004h 4007h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4004h 4007h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4004h 4007h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 algnerrc alignment error count 0h rc table 37-81. rxerrc: receive error count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 400ch 400fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 400ch 400fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 400ch 400fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 rxerrc rx error count 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1507 intel ? ep80579 integrated processor 37.6.6.4 mpc ? missed packet count register this register counts the number of missed packets. packets are missed when the receive fifo has insufficient space to store the incoming packet. this could be caused because of too few buffers allocated, or be cause there is insufficient bandwidth on the internal bus. events setting this counter cause the receiver overrun interrupt condition ( icr .rxo) to be set. this register does not count packets dropped due to the receiver being disabled. note: missed packets will be included/counted in the ?tpr ? total packets received register? on page 1528 as well as in the total octets received counter of the ?torl ? total octets received low register? on page 1525 and the ?torh ? total octets received high register? on page 1526 . 37.6.6.5 scc ? single collision count register this register counts the number of times that a successfully transmitted packet encountered a single collision. this register will only increment if transmits are enabled and the device is in half-duplex mode. table 37-82. mpc: missed packet count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4010h 4013h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4010h 4013h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4010h 4013h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 mpc missed packets count 0h rc table 37-83. scc: single collision count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4014h 4017h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4014h 4017h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4014h 4017h size: 32 bits default: 0000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 scc number of times a transmit encountered a single collision. 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1508 order number: 320066-003us 37.6.6.6 ecol ? excessive collisions count register when 16 or more collisions have occurred on a packet, this register increments, regardless of the value of collision threshold. if collision threshold is set below 16, this counter won't increment. this register will only increment if transmits are enabled and the device is in half-duplex mode. 37.6.6.7 mcc ? multiple collision count register this register counts the number of times that a transmit encountered more than one collision but less than 16. this register will only increment if transmits are enabled and the device is in half-duplex mode. table 37-84. ecol: excessive collisions count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4018h 401bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4018h 401bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4018h 401bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ecol number of packets with more than 16 collisions 0h rc table 37-85. mcc: multiple collision count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 401ch 401fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 401ch 401fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 401ch 401fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 mcc number of times a successful transmit encountered multiple collisions. 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1509 intel ? ep80579 integrated processor 37.6.6.8 latecol ? late collisions count register late collisions are collisions that occur after one slot time. this register will only increment if transmits are enabled and the device is in half-duplex mode. 37.6.6.9 colc ? collision count register this register counts the total number of collisions seen by the transmitter. this register will only increment if transmits are enabled and the device is in half-duplex mode. this register applies to clear as well as secure traffic. table 37-86. latecol: late collisions count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4020h 4023h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4020h 4023h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4020h 4023h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 latecol number of packets with late collisions 0h rc table 37-87. colc: collision count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4028h 402bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4028h 402bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4028h 402bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 colc total number of collisions experienced by the transmitter 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1510 order number: 320066-003us 37.6.6.10 dc ? defer count register this register counts defer events. a defer event occurs when the transmitter cannot immediately send a packet due to the medium busy either because another device is transmitting, half-duplex deferral events, or reception of xoff frames. this register will only increment if transmits are enabled. 37.6.6.11 tncrs ? transmit with no crs count register this register counts the number of successful packet transmission in which the crs signal from the phy was not asserted within one slot time of start of transmission from the mac. start of transmission is defined as the assertion of tx_en to the phy. the phy should assert crs during every transmission. failure to do so may indicate that the link has failed, or the phy has an incorrect link configuration. this register will only increment if transmits are enabled and is only valid when the device is operating at half duplex. table 37-88. dc: defer count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4030h 4033h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4030h 4033h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4030h 4033h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 dc number of defer events. 0h rc table 37-89. tncrs: transmit with no crs count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4034h 4037h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4034h 4037h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4034h 4037h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 tncrs number of transmissions without a crs assertion from the phy. 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1511 intel ? ep80579 integrated processor 37.6.6.12 cexterr ? carrier extension error count register this register counts the number of packets received in which a carrier extension error was signaled by the phy (by the encoding of 0x1f on the receive data inputs while rx_er is asserted to the mac) during the carrier extended time of a packet reception. this register will only increment when the dr iver has receives enabled and the device is operating at 1000mb/s. this counter is non-functional as the receiver doesn?t detect carrier-extend errors. 37.6.6.13 rlec ? receive length error count register this register counts receive length error events. a length error occurs if an incoming packet passes the mac address filtering (broadcast or individual-address/multicast match) but is undersized or oversized. packets less than 64b are deemed as undersized; packets over 1522b are deemed oversized if rctl .lpe=0. if rctl .lpe=1, then an incoming packet is only considered oversized if it exceeds 16384b. table 37-90. cexterr: carrier extension error count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 403ch 403fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 403ch 403fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 403ch 403fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 cexterr number of packets received with a carrier extension error. 0h rc table 37-91. rlec: receive length error count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4040h 4043h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4040h 4043h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4040h 4043h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 rlec number of packets with receive length errors. 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1512 order number: 320066-003us 37.6.6.14 xonrxc ? xon received count register this register counts the number of xon packets received. xon packets can use the global address or the station address. this register will only increment if the driver has receives enabled. 37.6.6.15 xontxc ? xon transmitted count register this register counts the number of xon packets transmitted. these packets can be either hardware-initiated due to queue room availability or due to software-initiated action (using tctl .swxoff). this register will only increment if transmits are enabled. table 37-92. xonrxc: xon received count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4048h 404bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4048h 404bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4048h 404bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 xonrxc number of xon packets received. 0h rc table 37-93. xontxc: xon transmitted count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 404ch 404fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 404ch 404fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 404ch 404fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 xontxc number of xon packets transmitted. 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1513 intel ? ep80579 integrated processor 37.6.6.16 xoffrxc ? xoff received count register this register counts the number of xoff packets received. xoff packets can use the global address or the station address. this register will only increment if the driver has receives enabled. 37.6.6.17 xofftxc ? xoff transmitted count register this register counts the number of xoff packets transmitted. these packets can be either hardware-initiated due to queue fullness, or due to software-initiated action (using tctl .swxoff). this register will only increment if transmits are enabled. table 37-94. xoffrxc: xoff received count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4050h 4053h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4050h 4053h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4050h 4053h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 xoffrxc number of xoff packets received. 0h rc table 37-95. xofftxc: xoff transmitted count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4054h 4057h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4054h 4057h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4054h 4057h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 xofftxc number of xoff packets transmitted. 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1514 order number: 320066-003us 37.6.6.18 fcruc ? fc received unsupported count register this register counts the number of unsupported flow control frames that are received. this counter is incremented when a packet is received which matches either the reserved flow control multicast address (in fcah / fcal ) or the mac station address, has a matching flow control type field match (to the value in fct ), but has an incorrect opcode field. this register will only increment if the driver has receives enabled. 37.6.6.19 prc64 ? good packets received count (64 bytes) register this register counts the number of good packets (no link or crc error) received that are exactly 64b (from through , inclusively) in length. hardware flow-control packets are not included in this count. this register includes good regular packets received to the receive packet buffer. packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). table 37-96. fcruc: fc received unsupported count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4058h 405bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4058h 405bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4058h 405bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 fcruc number of unsupported flow control frames received 0h rc table 37-97. prc64: good packets received count (64 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 405ch 405fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 405ch 405fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 405ch 405fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 prc64 number of good packets received exactly 64 bytes in length. 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1515 intel ? ep80579 integrated processor 37.6.6.20 prc127 ? good packets received count (65-127 bytes) register this register counts the number of good packets (no link or crc error) received that are from 65b-127b (from through , inclusively) in length. this register includes good regular packets received to the receive packet buffer. packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). 37.6.6.21 prc255 ? good packets received count (128-255 bytes) register this register counts the number of good packets (no link or crc error) received that are from 128b-255b (from through , inclusively) in length. this register includes good regular packets received to the receive packet buffer. packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). table 37-98. prc127: good packets received count (65-127 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4060h 4063h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4060h 4063h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4060h 4063h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 prc127 number of good packets received, (65-127) bytes in length 0h rc table 37-99. prc255: good packets received count (128-255 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4064h 4067h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4064h 4067h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4064h 4067h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 prc255 number of good packets received, (128-255) bytes in length. 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1516 order number: 320066-003us 37.6.6.22 prc511 ? good packets received count (256-511 bytes) register this register counts the number of good packets (no link or crc error) received that are from 256b-511b (from through , inclusively) in length. this register includes good regular packets received to the receive packet buffer. packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). 37.6.6.23 prc1023 ? good packets received count (512-1023 bytes) register this register counts the number of good packets (no link or crc error) received that are from 512b-1023b (from through , inclusively) in length. this register includes good regular packets received to the receive packet buffer. packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). table 37-100.prc511 - good packets received count (256-511 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4068h 406bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4068h 406bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4068h 406bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 prc511 number of good packets received, (256-511) bytes in length 0h rc table 37-101.prc1023: good packets received count (512-1023 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 406ch 406fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 406ch 406fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 406ch 406fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 prc1023 number of good packets received, (512-1023) bytes in length 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1517 intel ? ep80579 integrated processor 37.6.6.24 prc1522 ? good packets received count (1024 to max bytes) register this register counts the number of good packets (no link or crc error) received that are from 1024b-(max) bytes (from through , inclusively) in length. the value (max) is dependent on the current receiver configuration (i.e., rctl .lpe, etc.) and the type of packet being received. this register includes good regular packets received to the receive packet buffer. packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). regular packets identified as oversized packets (larger than max) are also not included in this count (refer to the ?roc ? receive oversize count register? on page 1524 ). note: due to changes in the standard for maximum frame size for vlan tagged frames in 802.3, the nominal value for (max) is 1522b length. table 37-102.prc1522: good packets received count (1024 to max bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4070h 4073h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4070h 4073h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4070h 4073h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 prc1522 number of good packets received, (1024-max) bytes in length 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1518 order number: 320066-003us 37.6.6.25 gprc ? good packets received count (total) register this register counts the number of good packets (no link or crc error) received that are of any legal length. this register incl udes good regular packets received to the receive packet buffer. regular packets identified as missed packets due to receive packet buffer overruns are not included in this count (refer to the ?mpc ? missed packet count register? on page 1507 ). this register should represent the sum of the good packets received (size=n) counts, and when the driver is enabled, should normally represent the total number of packets received to the driver. 37.6.6.26 bprc ? broadcast packets received count register this register counts the number of good (non-erred) broadcast packets received. this register does not count broadcast packets rece ived when the broadcast address filter is disabled. table 37-103.gprc: good packets received count (total) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4074h 4077h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4074h 4077h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4074h 4077h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gprc number of good packets received (total of all lengths) 0h rc table 37-104.bprc: broadcast packets received count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4078h 407bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4078h 407bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4078h 407bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 bprc number of broadcast packets received 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1519 intel ? ep80579 integrated processor 37.6.6.27 mprc ? multicast packets received count register this register counts the number of good (non-erred) multicast packets received. this register does not count multicast packets received that fail to pass the multicast address filtering, nor does it count received flow control packets. this register does not count packets counted by the ?mpc ? missed packet count register? on page 1507 . 37.6.6.28 gptc ? good packets transmitted count register this register counts the number of good (valid) packets transmitted without error (collision, etc.). a good packet is considered one that is 64b or more in length (from through , inclusively). this count does not include flow control packets transmitted. this register will only increment when transmits are enabled by the driver. table 37-105.mprc: multicast packets received count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 407ch 407fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 407ch 407fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 407ch 407fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 mprc number of multicast packets received 0h rc table 37-106.gptc: good packets transmitted count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4080h 4083h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4080h 4083h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4080h 4083h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gptc number of good packets transmitted 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1520 order number: 320066-003us 37.6.6.29 gorcl ? good octets received count low register this is the low 32b of a register that counts the number of octets received which are associated with good packets (no link or crc errors, no flow-control packets). this counter is incremented for each good regular packet received to the receive packet buffer. regular packets dropped due to receive packet buffer overruns or due to the driver's receiver being disabled ar e not included in this count. { gorch , gorcl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( gorch ) is read. the register sticks at 0xffff_ffff_ffff_ffff. table 37-107.gorcl: good octets received count low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4088h 408ah view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4088h 408ah view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4088h 408ah size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gorcl number of good octets received - lower 4 bytes 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1521 intel ? ep80579 integrated processor 37.6.6.30 gorch ? good octets received count high register this is the high 32b of a register that counts the number of octets received which are associated with good packets (no link or crc errors, no flow-control packets). this counter is incremented for each good regular packet received to the receive packet buffer. regular packets dropped due to receive packet buffer overruns or due to the driver's receiver being disabled are not included in this count. { gorch , gorcl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( gorch ) is read. the register sticks at 0xffff_ffff_ffff_ffff. 37.6.6.31 gotcl ? good octets transmitted count low register this is the low 32b of a register that counts the number of octets transmitted as good packets. good packets are considered those which are 64b or more in length (from through , inclusively), and do not encounter an error (collision, etc.) during transmission. this count does not include octets transmitted in flow control packets. this register will only increment when transmits are enabled by the driver. octets from the field through the field are included in this count. { gotch , gotcl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( gotch ) is read. the register sticks at 0xffff_ffff_ffff_ffff. table 37-108.gorch: good octets received count high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 408ch 408fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 408ch 408fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 408ch 408fh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gorch number of good octets received - upper 4 bytes 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1522 order number: 320066-003us 37.6.6.32 gotch ? good octets transmitted count high register this is the high 32b of a register that counts the number of octets transmitted as good packets. good packets are considered thos e which are 64b or more in length (from through , inclusively), and do not encounter an error (collision, etc.) during transmission. this count does not include octets transmitted in flow control packets. this register will only increment when transmits are enabled by the driver. octets from the field through the field are included in this count. { gotch , gotcl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( gotch ) is read. the register sticks at 0xffff_ffff_ffff_ffff. table 37-109.gotcl: good octets transmitted count low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4090h 4093h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4090h 4093h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4090h 4093h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gotcl number of good octets transmitted - lower 4 bytes 0h rc table 37-110.gotch: good octets transmitted count high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 4094h 4097h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 4094h 4097h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 4094h 4097h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 gotch number of good octets transmitted - upper 4 bytes 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1523 intel ? ep80579 integrated processor 37.6.6.33 rnbc ? receive no buffers count register this register counts the number of times that frames were received when there were no available buffers in host memory to store those frames (receive descriptor head and tail pointers were equal). the packet will still be received if there is space in the fifo. this register does not increment when flow control packets are received. this register will only increment if receives are enabled. 37.6.6.34 ruc ? receive undersize count register this register counts the number of received frames that passed address filtering, and were less than minimum size (64b from through , inclusively), and had a valid crc. this register will only increment if receives are enabled. table 37-111.rnbc: receive no buffers count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40a0h 40a3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40a0h 40a3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40a0h 40a3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 rnbc number of receive no buffer conditions 0h rc table 37-112.ruc: receive undersize count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40a4h 40a7h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40a4h 40a7h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40a4h 40a7h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ruc number of receive undersize errors 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1524 order number: 320066-003us 37.6.6.35 rfc ? receive fragment count register this register counts the number of received frames that passed address filtering, and were less than minimum size (64b from through , inclusively), but had a bad crc (this is slightly different from the ?ruc ? receive undersize count register? on page 1523 ). this register will only increment if receives are enabled. 37.6.6.36 roc ? receive oversize count register this register counts the number of received frames that passed address filtering, and were greater than maximum size. packets over 1522 bytes are oversized if longpacketenable is clear (i.e. rctl .lpe=0). if longpacketenable is set, then an incoming, packet is considered oversized if it exceeds 16384 bytes. if receives are not enabled, this register will not increment. these lengths are based on bytes in the received packet from through , inclusively. table 37-113.rfc: receive fragment count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40a8h 40abh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40a8h 40abh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40a8h 40abh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 rfc number of receive fragment errors 0h rc table 37-114.roc: receive oversize count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40ach 40afh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40ach 40afh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40ach 40afh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 roc number of receive oversize errors 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1525 intel ? ep80579 integrated processor 37.6.6.37 rjc ? receive jabber count register this register counts the number of received frames that passed address filtering, and were greater than maximum size and had a bad crc (this is slightly different from the ?roc ? receive oversize count register? on page 1524 ). packets over 1522b are oversized if longpacketenable is 0. if longpacketenable (lpe) is 1, then an incoming packet is considered oversized if it exceeds 16384 bytes. if receives are not enabled, this register will not increment. these lengths are based on bytes in the received packet from through , inclusively. 37.6.6.38 torl ? total octets received low register this is the low 32b of a register that counts the total number of octets received, including octets from both good and bad packets. packets must first pass the mac address filtering (broadcast or individual-address/multicast match) - packets not for this mac are not included. octets will be counted for all packets regardless of their length, whether they encountered errors, whether they are detected as regular packets or flow control packets, and regardless of whether they are stored successfully versus dropped from a receive fifo (receive packet buffer). bytes from the field through the field (inclusively) are counted. { torh , torl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( torh ) is read. the register sticks at 0xffff_ffff_ffff_ffff. table 37-115.rjc: receive jabber count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40b0h 40b3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40b0h 40b3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40b0h 40b3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 rjc number of receive jabber errors 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1526 order number: 320066-003us 37.6.6.39 torh ? total octets received high register this is the high 32b of a register that counts the total number of octets received, including octets from both good and bad packets. packets must first pass the mac address filtering (broadcast or individual-address/multicast match) - packets not for this mac are not included. octets will be counted for all packets regardless of their length, whether they encountered errors, whether they are detected as regular packets or flow control packets, and regardless of whether they are stored successfully versus dropped from a receive fifo (receive packet buffer). bytes from the field through the field (inclusively) are counted. { torh , torl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( torh ) is read. the register sticks at 0xffff_ffff_ffff_ffff. table 37-116.torl: total octets received low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40c0h 40c3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40c0h 40c3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40c0h 40c3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 torl number of total octets received - lower 4 bytes 0h rc table 37-117.torh: total octets received high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40c4h 40c7h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40c4h 40c7h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40c4h 40c7h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 torh number of total octets received - upper 4 bytes 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1527 intel ? ep80579 integrated processor 37.6.6.40 totl ? total octets transmitted low register this the low 32b of a 64b register that counts the total number of octets in successfully transmitted packets. octets transmitted as part of partial packet transmission (e.g. collisions in half-duplex mode) are not included. octets will be counted for all packets regardless of their length and regardless of whether regular packets or flow-control packets. octets from the field through the field are included in this count. { toth , totl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( toth ) is read. the register sticks at 0xffff_ffff_ffff_ffff. 37.6.6.41 toth ? total octets transmitted high register this the high 32b of a 64b register that counts the total number of octets in successfully transmitted packets. octets transmitted as part of partial packet transmission (e.g. collisions in half-duplex mode) are not included. octets will be counted for all packets regardless of their length and regardless of whether regular packets or flow-control packets. octets from the field through the field are included in this count. { toth , totl } together make up a logical 64-bit register. each half must be accessed independently using separate 32-bit accesses. both registers are reset when the upper 32-bit value ( toth ) is read. the register sticks at 0xffff_ffff_ffff_ffff. table 37-118.totl: total octets transmitted low register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40c8h 40cfh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40c8h 40cfh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40c8h 40cfh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 totl number of total octets transmitted - lower 4 bytes 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1528 order number: 320066-003us 37.6.6.42 tpr ? total packets received register this register counts the total number of all packets received by the node (must pass the mac address filtering - broadcast or individual-address/multicast match). all packets received by the mac will be counted in this register, regardless of their length, whether they encountered errors, and regardless of whether they are detected as regular packets or flow control packets. table 37-119.toth: total octets transmitted high register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40cch 40cfh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40cch 40cfh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40cch 40cfh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 toth number of total octets transmitted - upper 4 bytes 0h rc table 37-120.tpr: total packets received register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40d0h 40d3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40d0h 40d3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40d0h 40d3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 tpr total of all packets received 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1529 intel ? ep80579 integrated processor 37.6.6.43 tpt ? total packets transmitted register these registers count the total number of successfully transmitted packets. partial packet transmissions (e.g. collisions in half-duplex mode) are not included in this count. all packets will be counted regardless of their length and regardless of whether regular packets or flow-control packets. 37.6.6.44 ptc64 ? packets transmitted count (64 bytes) register this register counts the number of packets successfully transmitted that are exactly 64b (from through , inclusively) in length. partial packet transmissions (e.g. collisions in half-duplex mode) are not included in this count. packet transmissions shorter than 64 bytes which may be generated due to having short-frame padding (psp) disabled are not included. this register also does not include any flow control packets transmitted. table 37-121.tpt: total packets transmitted register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40d4h 40d7h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40d4h 40d7h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40d4h 40d7h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 tpt number of all packets transmitted 0h rc table 37-122.ptc64 - packets transmitted count (64 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40d8h 40dbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40d8h 40dbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40d8h 40dbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ptc64 number of all packets transmitted that are 64 bytes in length 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1530 order number: 320066-003us 37.6.6.45 ptc127 ? packets transmitted count (65-127 bytes) register this register counts the number of packets successfully transmitted that are 65b-127b (from through , inclusively) in length. partial packet transmissions (e.g. collisions in half-duplex mode) are not included in this count. 37.6.6.46 ptc255 ? packets transmitted count (128-255 bytes) register this register counts the number of packets successfully transmitted that are 128b- 255b (from through , inclusively) in length. partial packet transmissions (e.g. collisions in half-duplex mode) are not included in this count. 37.6.6.47 ptc511 ? packets transmitted count (256-511 bytes) register this register counts the number of packets successfully transmitted that are 256b- 511b (from through , inclusively) in length. partial packet transmissions (e.g. collisions in half-duplex mode) are not included in this count. table 37-123.ptc255: packets transmitted count (128-255 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40e0h 40e3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40e0h 40e3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40e0h 40e3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ptc255 number of packets transmitted that are 128-255 bytes in length 0h rc table 37-124.ptc511: packets transmitted count (256-511 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40e4h 40e7h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40e4h 40e7h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40e4h 40e7h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ptc511 number of packets transmitted that are 256-511 bytes in length 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1531 intel ? ep80579 integrated processor 37.6.6.48 ptc1023 ? packets transmitted count (512-1023 bytes) register this register counts the number of packets successfully transmitted that are 512b- 1023b (from through , inclusively) in length. partial packet transmissions (e.g. collisions in half-duplex mode) are not included in this count. 37.6.6.49 ptc1522: packets transmitted count (1024-1522 bytes) register this register counts the number of packets successfully transmitted that are 1024b or longer (from through , inclusively) in length. partial packet transmissions (e.g., collisions in half-duplex mode) are not included in this count. table 37-125.ptc1023: packets transmitted count (512-1023 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40e8h 40ebh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40e8h 40ebh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40e8h 40ebh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ptc1023 number of packets transmitted that are 512-1023 bytes in length 0h rc table 37-126.ptc1522: packets transmitted count (1024-1522 bytes) register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40ech 40efh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40ech 40efh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40ech 40efh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ptc1522 number of packets transmitted that are 1024 or more bytes in length 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1532 order number: 320066-003us 37.6.6.50 mptc ? multicast packets transmitted count register this register counts the number of multicast packets transmitted. this register does not include flow control packets and increments only if transmits are enabled. 37.6.6.51 bptc ? broadcast packets transmitted count register this register counts the number of broadcast packets transmitted. this register will only increment if transmits are enabled. table 37-127.mptc: multicast packets transmitted count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40f0h 40f3h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40f0h 40f3h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40f0h 40f3h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 mptc number of multicast packets transmitted 0h rc table 37-128.bptc: broadcast packets transmitted count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40f4h 40f7h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40f4h 40f7h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40f4h 40f7h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 bptc number of broadcast packets transmitted count 0h rc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1533 intel ? ep80579 integrated processor 37.6.6.52 tsctc ? tcp segmentation context transmitted count register this register counts the number of tcp segmentation off load transmissions and increments once the last portion of the tcp segmentation context payload is segmented and loaded as a packet into the gb e hardware transmit buffer. note that it is not a measurement of the number of packets sent out (covered by other registers). this register will only increment if transmits and tcp segmentation off load are enabled. 37.6.6.53 tsctfc ? tcp segmentation context transmit fail count register this register counts the number of tcp segmentation off load requests to the hardware that failed to transmit all data in the tcp segmentation context payload (due to the context specifying less data than the data descriptors reference). tcp segmentation requires the context's length specification to match the total length of the supplied data descriptors, however. therefore, this count should always be zero if tcp segmentation is properly used. table 37-129.tsctc: tcp segmentation context transmitted count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40f8h 40fbh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40f8h 40fbh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40f8h 40fbh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 tsctc number of tcp segmentation contexts transmitted count 0h rc table 37-130.tsctfc: tcp segmentation context transmit fail count register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 40fch 40ffh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 40fch 40ffh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 40fch 40ffh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 tsctfc number of tcp segmentation contexts where the device failed to transmit the entire data payload 0h rc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1534 order number: 320066-003us 37.6.7 management register descriptions 37.6.7.1 wuc ? wake up control register (0x05800; rw) note: the pme_en and pme_status bits are reset when pwr_good is 0. when aux_pwr_present=0, this register is also reset by the deassertion (rising edge) of reset_n and the transition from d3 to d0. the other bits are reset on the standard internal resets. table 37-131.wuc - wake up control register (0x05800; rw) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5800h 5803h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5800h 5803h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5800h 5803h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 rsvd reserved 0h ro 03 apmpme assert pme on apm wakeup ? if it is 1, the gbe will set the pme_status bit in the power management control / status register (pmcsr) and assert gbe_pme_wake when apm wakeup is enabled and the gbe receives a matching magic packet. *note that this bit is loaded from the eeprom, if present 0h rw 02 pme_status pme_status this bit is set when the gbe receives a wakeup event. it is the same as the pme_status bit in the power management control / status register (pmcsr). writing a ?1? to this bit will clear it and clear the pme_status bit in the pmcsr. 0h rwc 01 pme_en pme_en this read/write bit is used by the driver to access the pme_en bit of the power management control / status register (pmcsr) without writing to pci configuration space. 0h rw 00 apme advance power management enable - if ?1?, apm wakeup is enabled. *note that this bit is loaded from the eeprom, if present 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1535 intel ? ep80579 integrated processor 37.6.7.2 wufc ? wake up filter control register (0x05808; rw) this register is used to enable/disable ea ch of the pre-defined and flexible filters affecting wake up support. for most bits, a value of 1 means a wakeup for the specific event is enabled, and a value of 0 means the wakeup is disabled. for example, when mc=1, a packet containing an ia which matches the directed multicast filter will generate a wakeup event. table 37-132.wufc - wake up filter control register (0x05808; rw) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5808h 580bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5808h 580bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5808h 580bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 rsvd reserved. should be set to 0. 0h rv 19 flx3 flexible filter 3 enable 0h rw 18 flx2 flexible filter 2 enable 0h rw 17 flx1 flexible filter 1 enable 0h rw 16 flx0 flexible filter 0 enable 0h rw 15 rsvd reserved. should be set to 0. 0h rw 14 : 08 rsvd reserved. should be set to 0. 0h rv 07 ipv6 directed ipv6 packet wake up enable 0h rw 06 ipv4 directed ipv4 packet wake up enable 0h rw 05 arp arp/ipv4 request packet wake up enable 0h rw 04 bc broadcast wake up enable 0h rw 03 mc directed multicast wake up enable 0h rw 02 ex directed exact wake up enable 0h rw 01 mag magic packet wake up enable 0h rw 00 rsvd reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1536 order number: 320066-003us 37.6.7.3 wus ? wake up status register (0x05810; rw) this register is used to record statistics about all wake up packets received. if a packet matches multiple criteria than multiple bits could be set. writing a 1 to any bit will clear that bit. this register will not be cleared when reset_n is asserted. it will only be cleared when pwr_ok is deasserted or when cleared by the driver. prior to re-entering a wakeup-enabled sleep state, this register should be explicitly cleared by writing with all 1's. table 37-133.wus - wake up status register (0x05810; rw) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5810h 5813h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5810h 5813h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5810h 5813h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 20 rsvd reserved. should be set to 0. 0h rv 19 flx3 flexible filter 3 match 0h rwc 18 flx2 flexible filter 2 match 0h rwc 17 flx1 flexible filter 1 match 0h rwc 16 flx0 flexible filter 0 match 0h rwc 15 : 08 reserved reserved. 0h rv 07 ipv6 directed ipv6 packet wake up packet received 0h rwc 06 ipv4 directed ipv4 packet wake up packet received 0h rwc 05 arp arp/ipv4 request packet wake up packet received 0h rwc 04 bc broadcast wake up packet received 0h rwc 03 mc directed multicast wake up packet received the packet was a multicast packet whose hashed to a value that corresponded to a 1 bit in the multicast table array note: if the mac has been configured for promiscuous mode, a multicast wakeup will occur if a broadcast packet is received. this is because a broadcast message is a special type of multicast message. refer to 802.3. 0h rwc 02 ex directed exact wake up packet received the packet's address matched one of the 16 pre- programmed exact values in the receive address registers 0h rwc 01 mag magic packet wake up packet received 0h rwc 00 rsvd reserved. must be written as ?0? 0h rv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1537 intel ? ep80579 integrated processor 37.6.7.4 ipav ? ip address valid register (0x05838; rw) the ip address valid indicates whether the ip addresses in the ip address table are valid: table 37-134.ipav - ip address valid register (0x05838; rw) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5838h 583bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5838h 583bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5838h 583bh size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 17 rsvd reserved. should be set to 0. 0h rv 16 v60 ipv6 address 0 valid 0h rw 15 : 04 rsvd reserved. should be set to 0. 0h rv 03 v43 ipv4 address 3 valid 0h rw 02 v42 ipv4 address 2 valid 0h rw 01 v41 ipv4 address 1 valid 0h rw 00 v40 ipv4 address 0 valid the initial value is loaded from the ip address valid bit of the eeprom's management control register 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1538 order number: 320066-003us 37.6.7.5 ip4at[0-3] - (0x5840 - 0x5858; rw) ? ipv4 address table registers the ipv4 address table is used to store the four ipv4 addresses for arp/ipv4 request packet and directed ipv4 packet wake up. it has the following format: ? address 0x5840: ipv4 addr0 ? address 0x5848: ipv4 addr1 ? address 0x5850: ipv4 addr2 ? address 0x5858: ipv4 addr3 * note: the first entry is loaded from the eeprom if the ip address valid field of the eeprom's management control word is 1 and the ip address type field is 0 (ipv4). otherwise, the value of this register is undefined after reset 37.6.7.6 ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4 the ipv6 address table is used to store the ipv6 addresses for arp/ipv6 request packet and directed ipv6 packet wake up and it has the following format ? address 0x5880: ipv6 addr0, bytes 1 - 4 ( table 37-136 ) ? address 0x5884: ipv6 addr0, bytes 5 - 8 ( table 37-137 ) ? address 0x5888: ipv6 addr0, bytes 9 - 12 ( ta bl e 3 7 - 1 3 8 ) ? address 0x588f: ipv6 addr0, bytes 13 - 16 ( table 37-139 ) table 37-135.ip4at (0x5840 - 0x5858; rw)[0-3]: ipv4 address table registers description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5840h at 8h 5843h at 8h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5840h at 8h 5843h at 8h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5840h at 8h 5607h at 8h size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ipv4addrx ipv4 address xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1539 intel ? ep80579 integrated processor 37.6.7.7 ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8 the ipv6 address table is used to store the ipv6 addresses for arp/ipv6 request packet and directed ipv6 packet wake up and it has the following format ? address 0x5880: ipv6 addr0, bytes 1 - 4 ( ta bl e 3 7 - 1 3 6 ) ? address 0x5884: ipv6 addr0, bytes 5 - 8 ( ta bl e 3 7 - 1 3 7 ) ? address 0x5888: ipv6 addr0, bytes 9 - 12 ( ta b l e 3 7 - 1 3 8 ) ? address 0x588f: ipv6 addr0, bytes 13 - 16 ( table 37-139 ) table 37-136.ipv6_addr0bytes_1_4 ? ipv6 address table register (0x5880), bytes 1 - 4 description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5880h 5883h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5880h 5883h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5880h 5883h size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ipv6addr0 ipv6 address0, bytes 1 - 4 xh rw table 37-137.ipv6_addr0bytes_5_8 ? ipv6 address table register, bytes 5 - 8 description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 05884h 5887h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 05884h 5887h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 05884h 0588fh size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ipv6addr1 ipv6 address, bytes 5 - 8 x rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1540 order number: 320066-003us 37.6.7.8 ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12 the ipv6 address table is used to store the ipv6 addresses for arp/ipv6 request packet and directed ipv6 packet wake up and it has the following format ? address 0x5880: ipv6 addr0, bytes 1 - 4 ( table 37-136 ) ? address 0x5884: ipv6 addr0, bytes 5 - 8 ( table 37-137 ) ? address 0x5888: ipv6 addr0, bytes 9 - 12 ( ta bl e 3 7 - 1 3 8 ) ? address 0x588f: ipv6 addr0, bytes 13 - 16 ( table 37-139 ) 37.6.7.9 ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16 the ipv6 address table is used to store the ipv6 addresses for arp/ipv6 request packet and directed ipv6 packet wake up and it has the following format ? address 0x5880: ipv6 addr0, bytes 1 - 4 ( table 37-136 ) ? address 0x5884: ipv6 addr0, bytes 5 - 8 ( table 37-137 ) ? address 0x5888: ipv6 addr0, bytes 9 - 12 ( ta bl e 3 7 - 1 3 8 ) ? address 0x588c: ipv6 addr0, bytes 13 - 16 ( table 37-139 ) table 37-138.ipv6_addr0bytes_9_12 ? ipv6 address table register, bytes 9 - 12 description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5888h 588bh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5888h 588bh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5888h 588bh size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ipv6addr2 ipv6 address, bytes 9 - 12 x rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1541 intel ? ep80579 integrated processor note: this table is loaded from the eeprom if the ip address valid field of the eeprom's management control word is 1 and the ip address type field is 1(ipv6). otherwise, the value of this table is undefined after reset. 37.6.7.10 fflt[0-3] ? flexible filter length table registers (0x5f00 - 0x5f18; rw) the flexible filter length table stores the minimum packet lengths required to pass each of the flexible filters. any packets that are shorter than the programmed length won't pass that filter. each flexible filter will consider a packet that doesn't have any mismatches up to that point to have passed the flexible filter when it reaches the required length. it will not check any bytes past that point: ? address 0x5f00: fflt_len0 ? address 0x5f04: reserved ? address 0x5f08: fflt_len1 ? address 0x5f0c: reserved ? address 0x5f10 fflt_len2 ? address 0x5f14: reserved ? address 0x5f18: fflt_len3 ? address 0x5f1c: reserved table 37-139.ipv6_addr0bytes_13_16 ? ipv6 address table register, bytes 13 - 16 description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 588ch 588fh view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 588ch 588fh view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 588ch 588fh size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 ipv6ddr3 ipv6 address, bytes 13 - 16 x rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1542 order number: 320066-003us note: before writing to the flexible filter length table the driver must first disable the flexible filters by writing 0's to the flexible filter enable bits of the wake up filter control register (wufc.flxn) 37.6.7.11 ffmt[0-127] ? flexible filter mask table registers (0x9000 - 0x93f8; rw) the flexible filter mask and table is used to store the four 1-bit masks for each of the first 128 data bytes in a packet, one for each flexible filter. if the mask bit is 1, the corresponding flexible filter will compare the incoming data byte at the index of the mask bit to the data byte stored in the flexible filter value table: table 37-140.fflt[0-3] - flexible filter length table registers (0x5f00 - 0x5f18; rw) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 5f00h at 8h 5f03h at 8h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 5f00h at 8h 5f03h at 8h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 5f00h at 8h 5f03h at 8h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 11 rsvd reserved 0h rv 10 : 00 fflt_lenx flexible filter length for filter x 0h rw table 37-141.flexible filter mask table address content address content 0x9000 byte 0 mask 0x9004 reserved 0x9008 byte 1 mask 0x900c reserved 0x9010 byte 2 mask 0x9014 reserved ... byte 3 - 126 mask ... reserved 0x93f8 byte 127mask 0x93fc reserved
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1543 intel ? ep80579 integrated processor note: before writing to the flexible filter length table the driver must first disable the flexible filters by writing 0's to the flexible filter enable bits of the wake up filter control register (wufc.flxn) 37.6.7.12 ffvt[0-127] ? flexible filter value table registers the flexible filter value and table is used to store the one value for each byte location in a packet for each flexible filter. if the corresponding mask bit is 1, the flexible filter will compare the incoming data byte to the values stored in this table. table 37-142.ffmt[0-127] - flexible filter mask table registers (0x9000 - 0x93f8; rw) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 9000h at 8h 9003h at 8h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 9000h at 8h 9003h at 8h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 9000h at 8h 9003h at 8h size: 32 bits default: 0000000xh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 04 rsvd reserved 0h rv 03 : 00 mask_x byte mask for byte xx xh rw table 37-143.flexible filter mask table address content address content 0x9800 byte 0 values 0x9804 reserved 0x9808 byte 1 values 0x980c reserved 0x9810 byte 2 values 0x9814 reserved ... byte 3 - 126 values ... reserved 0x9bf8 byte 127 values 0x9bfc reserved
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1544 order number: 320066-003us note: before writing to the flexible filter length table the driver must first disable the flexible filters by writing 0's to the flexible filter enable bits of the wake up filter control register (wufc.flxn) 37.6.8 error register descriptions 37.6.8.1 intbus_err_stat ? internal bus error status register this register captures status information about errors that occur on the internal bus. table 37-144.ffvt[0-127]: flexible filter value table registers description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 9800h at 8h 9803h at 8h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 9800h at 8h 9803h at 8h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 9800h at 8h 9803h at 8h size: 32 bits default: xxxxxxxxh power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 24 val3 byte x compare value 3 x rw 23 : 16 val2 byte x compare value 2 x rw 15 : 08 val1 byte x compare value 1 x rw 07 : 00 val0 byte x compare value 0 x rw table 37-145.intbus_err_stat - internal bus error status register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0510h 0513h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0510h 0513h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0510h 0513h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 13 rsvd reserved 0h rv 12 intbus_err_h _dis 0 - internal bus errors will halt further gbe transmit/ receive operation. 1 - internal bus errors will no t halt further gbe operation. 0rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1545 intel ? ep80579 integrated processor 37.6.8.2 mem_tst ? memory error test register for software testability (in order to generate an ecc or parity error in hardware), this register can be used to generate a hardware ecc or parity error in the gbe memories. the selected ecc or parity error is continuously written in to the selected memory as long as the memory is selected, at any address currently in use. the ?select? field allows selection of the memory that the errored data should be written to. the ?mask? field provides an xor mask for the ecc or parity bits of that register. although a 16 bit mask is provided, not all registers use all bits of the mask field. refer to the register description below. the ecc or parity error will not occur until the errored location has been read. note : 11 : 06 rsvd reserved 0h rv 05 : 04 type internal bus error type: ? 00 = unsupported internal bus transaction targeted at gbe ? 01 = pull data error detected during a target write transaction ? 10 = gbe received a internal bus data error response while mastering a dma transaction ? 11 = master pull data error occurred as a result of an internal memory error 0h ro 03 :02 rsvd reserved 0h rv 01 merr indicates whether one or more than one internal bus errors have occurred before intbus_err_stat .cerr was cleared 0 = one internal bus error 1 = more than one internal bus error 0h rwc 00 cerr internal bus error: asserts when internal bus error status and address registers are valid 0 = no error has been logged 1 = internal bus error status and address registers have logged an error if error handling is enabled (intbus_err_h_dis = 0) then this bit can only be cleared by a reset. 0h rwc table 37-145.intbus_err_stat - internal bus error status register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0510h 0513h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0510h 0513h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0510h 0513h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1546 order number: 320066-003us ? single bit errors will be corrected in all but types 010 and 011, with no error indication. ? multiple bit errors will cause a gbe error response for all other memory types. ? a multiple bit error is caused by forcing multiple mask bits [15:8] and/or multiple bits of [7:0] for types 100, 101, 110. forcing one bit in [15:8] and one bit in [7:0] will not create a multiple bit error (and will therefore not produce a gbe error response). 37.6.8.3 mem_sts ? memory error status register this register reports ecc or parity errors, for each of the memories with ecc or parity coverage. errors will be reported in this register, regardless of whether they were induced by the met logic or through actual hardware errors. host write dma transactions issued after these fatal memory errors are encountered will result in a data error asserted for every internal bus transaction. csr target transactions, including transactions to the errored memory, will complete without error, however the memory errors will still be logged in the mes register. if the mem_errh_dis bit is set (error handling is disabled), the individual memory errors can be cleared with a write to the appropriate memory error bit in this register, however the errored memory is likely to produce unexpected gbe functionality. table 37-146.mem_tst - memory error test register description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0900h 0903h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0900h 0903h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0900h 0903h size: 32 bits default: 00000000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 : 19 rsvd reserved 0h rv 18 : 16 select selects the memory where the error mask is applied: 000 : none - no errors injected 001 : statistics registers 010 : multicast filter memory 011 : special packet filter memory 100 : tx descriptor buffer 101 : rx descriptor buffer 110 : packet buffer 111 : flexible filter memory 0h rw 15 : 00 mask ecc/parity check bit xor mask the valid mask bits are selected according to the select field, as follows: 001 : 15:8 reserved; 7:0 ecc mask 010 : 15:4 reserved; 3:0 parity bit mask 011 : 15:4 reserved; 3:0 parity bit mask 100 : 15:0 ecc mask 101 : 15:0 ecc mask 110 : 15:0 ecc mask 111 : 15:0 reserved; 3:0 parity bit mask 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1547 intel ? ep80579 integrated processor if the mem_errh_dis bit is not set (error handling is enabled) then the error bits will only be cleared by a soft reset. table 37-147.mem_sts - memory error status register (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0904h 0907h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0904h 0907h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0904h 0907h size: 32 bits default: 007f0000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access 31 23 rsvd reserved. 0h rv 22 22 err_flex_dis flex filter parity error disable 0: error trapping enabled 1: error trapping disabled 1h rw 21 21 err_stat_dis statistics register ecc error disable 0: error trapping enabled 1: error trapping disabled 1h rw 20 20 err_pkbuf_di s packet buffer ecc error disable 0: error trapping enabled 1: error trapping disabled 1h rw 19 19 err_txds_dis transmit descriptor ecc error disable 0: error trapping enabled 1: error trapping disabled 1h rw 18 18 err_rxds_dis receive descriptor ecc error disable 0: error trapping enabled 1: error trapping disabled 1h rw 17 17 err_spf_dis special packets filter parity error disable 0: error trapping enabled 1: error trapping disabled 1h rw 16 16 err_mf_dis multicast filter parity error disable 0: error trapping enabled 1: error trapping disabled 1h rw 15 13 rsvd reserved 0h rv 12 12 mem_errh_di s memory error handling disable: indicates, for the following error types, whether gbe tx/ rx operation will be halted: err_stat err_pkbuf err_rxds err_txds 0: memory errors will halt further gbe tx/rx operation and a soft-reset is required to restore operation 1: memory errors will be logged, but will not halt further gbe tx/rx operation 0h rw 11 7 rsvd reserved. 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1548 order number: 320066-003us 6 6 err_flex flex filter parity error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc. 0h ro/rwc 55 err_stat statistics register ecc error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc 0h ro/rwc 44 err_pkbuf packet buffer ecc 2-bit error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc. 0h ro/rwc 33 err_txds transmit descriptor ecc 2-bit error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc. 0h ro/rwc 22 err_rxds receive descriptor ecc 2-bit error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc. 0h ro/rwc 11 err_spf special packets filter parity error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc 0h ro/rwc 00 err_mf multicast filter parity error 0: no error occurred 1: error occurred when mem_errh_dis is clear then this bit is ro. when mem_errh_dis is set then this bit is rwc 0h ro/rwc table 37-147.mem_sts - memory error status register (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:0:0 offset start: offset end: 0904h 0907h view: pci 2 bar: csrbar bus:device:function: m:1:0 offset start: offset end: 0904h 0907h view: pci 3 bar: csrbar bus:device:function: m:2:0 offset start: offset end: 0904h 0907h size: 32 bits default: 007f0000h power well: gbe0: aux gbe1/2: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1549 intel ? ep80579 integrated processor 37.7 power management note: power management may be disabled via bits in the initialization control word which is loaded from the eeprom during power-up reset. even when disabled, the power management register set is still present. the following power management related features are supported: ? power states of d0 & d3hot ? support of optional d3cold for gbe0 ? power(d3) < power(d0) ?wake-up 37.7.1 assumptions the following assumptions apply: ? prior to transition from d0 to the d3 state, the os will ensure the device driver has been disabled and all pending bus transactions are complete or terminated cleanly. ? per the pci power management specification (revision 1.1, section 5.4), software ?will need to perform a full re-initialization of the function including its pci configuration space.? on a transition from d3 to d0u state, all of the pci configuration space is reset. ? the driver will set up the wake up filters prior to the system transitioning the gbe to d3 state. ? no wakeup capability, except apm wakeup if enabled in the eeprom, is required after the system puts the mac in d3 state and then returns the mac to d0. ? if the apmpme bit in the wake up control register (wuc.apmpme) bit is 1, it is permissible to assert gbe_pme_wake even when pme_en is 0. ? no wakeup capability, except apm wakeup if enabled in the eeprom, is required after the system asserts, then deasserts reset_n. ? the deassertion (rising) edge of reset_n will put the controller in d0u state. ? the system will never deactivate the internal bus clock without asserting reset_n. ? any time pwr_ok is asserted all power supplies are stable and reset_n is stable. 37.7.2 d3cold support if the d3cold wake up capability advertisement enable bit of the device control register (ctrl.advd3wuc) is set to '1', the d3cold capability may be advertised (if 0, the capability will not be advertised). when 1, the ep80579 will then use the aux_pwr_present input as an indication of whether auxiliary power is available to the gbe controller, and if aux_pwr_present=1 will advertise d3cold wake up support in the pci capabilities list for that gbe controller. if d3cold is supported, the pme_en and pme_status bits of the power management control/status register (pmcsr), as well as shadow bits in the wake up control register (wuc), are not reset by unit_reset. however, if d3cold wake up is not supported they will always be reset on the deassertion (falling edge) of unit_reset. note that aux_pwr_present is level sensitive and is sampled at assertion of aux_pwr_good from the eedi pin. eedi must be pulled high to indicate that aux_pwr_present is a ?1?. eedi must be pulled low to indicate that aux_pwr_present is a ?0?. eedi must be either pulled up or down. aux_pwr_present may not be left indeterminate.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1550 order number: 320066-003us besides the reset change and capability advertisement, the ep80579 d3cold behavior is identical to d3hot behavior (i.e. operates the same regardless of whether power is supplied from main vs. auxiliary power supplies). 37.7.3 power states the gbe controller supports d0 and d3 power states defined in the pci power management specification. in addition, d0 is divided into two sub-states: d0u, and d0a. in addition, it supports a dr state that is entered when unit_reset is asserted. figure 37-50 shows the power states and what causes a transition between them. 37.7.3.1 dr on initial boot-up, once pwr_good is asserted the gbe controller will enter the dr state and read the eeprom. if the apm enable bit in the eeprom's initialization control word 2 is set then apm wake up will be enabled. internally, the controller treats the dr reset state equivalently to d3. any wakeup filter settings that were enabled before enteri ng this reset state will be maintained. the deassertion (falling edge) of unit_reset will cause a transition to d0u. figure 37-50.power state transitions dr* d0u d0a d3 pwr_good assertion unit_reset deassertion unit_reset assertion enable memory/io access set power state to d0 set power state to d3 unit_reset assertion unit_reset assertion * equivalent to d3
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1551 intel ? ep80579 integrated processor 37.7.3.2 d0u state the d0u state is a low-power state used after unit_reset is deasserted, or when coming out of d3, but before the gbe controller is initialized. when entering d0u the gbe controller will disable wake ups, assert reset to the phy for between 24s and 1ms, and re-read the eeprom. if the apm mode bit in the eeprom's initialization control word 2 is set then apm wake up will be enabled. on a transition from d3 to d0u state, all of the pci configuration space is reset. per the pci power management specification (revision 1.1, section 5.4), software ?will need to perform a full reinitialization of the function including its pci configuration space.? internally, d0u is treated like d3 and some internal clocks and registers are shut down. as in the dr state, the phy power state depends on whether phy power-management and wakeup are enabled. the d0u state is exited when the system enables memory space access to the controller by writing a 1 to the memory access enable bit of the pci command register. 37.7.3.3 d0a once memory space is enabled all internal clocks are activated and the controller enters an active state. it can transmit and receive packets if properly configured by the driver. any apm wakeup previously active will remain active. the driver can deactivate apm wakeup by writing to the wake up control register (wuc), or activate other wake up filters by writing to the wake up filter control register (wufc). 37.7.3.4 d3 prior to transition from d0 to the d3 state, the driver must ensure that controller transmit and receive operation has been disa bled and all pending bus transactions are complete or terminated cleanly. if wake up capability is needed the driver should set up the appropriate wake up registers and the system should write a 1 to the pme_en bit of the power management control / status register (pmcsr) prior to the transition to d3. when the system writes a '11 to the powerstate field of the power management control/status register (pmcsr) the gbe controller will transition to d3. any wakeup filter settings that were enabled before entering this reset state will be maintained. upon transitioning to d3 the controller will clear the memory access enable bit of the pci command register, which will disable memory access decode. for power savings, the gbe controller shuts down some internal clocks and registers in d3 state. to transition back to d0u, the system writes a 00 to the power state field of the power management control/status register (pmcsr). 37.7.4 timing of power-state transitions the following sections give detailed timing for the state transitions. in the diagrams the dotted connecting lines represent the macs? requirements, while the solid connecting lines represent the macs? guarantees. the timing diagrams are not to scale. the clocks edges are shown to indicate running clocks only are not used to indicate the actual number of cycles for any operation.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1552 order number: 320066-003us 37.7.4.1 power up (off to dr to d0u to d0a) figure 37-51.reset deasserted after 1st eeprom read completes power pwr_ok clk reset dstate d0u reading eeprom read eeprom read eeprom d0a memory access enable 1 wakeup enabled 4 6 dr 5 2 10 4 apm apm t ppg t rpg t pgee t ee t pgprst t clkpr t ee tprmem 11 t pree 7 note 1 pwr_ok must not be asserted until all power supplies are good 2 an eeprom read is started on the rising edge of pwr_ok and reset. 4 apm wakeup may be enabled based on what is read from the eeprom. 5 the system can delay an arbitrary time before deasserting reset. 7 the deassertion edge of reset will cause the eeprom to be re-read and wake up disabled. 10 the system can delay an arbitrary time before enabling memory access. 11 writing a 1 to the memory access enable bit in the pci command register will transition the mac from d0u to d0 state
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1553 intel ? ep80579 integrated processor figure 37-52.reset deasserted after before eeprom read completes power pwr_ok clk reset dstate d0u reading eeprom read eeprom d0a memory access enable 1 wakeup enabled 4 dr 5 2 10 apm t ppg t rpg t pgee t ee t pgprst tprmem 11 note 1 pwr_ok must not be asserted until all power supplies are good 2 an eeprom read is started on the rising edge of pwr_ok and reset. 4 apm wakeups may be enabled based on what is read from the eeprom. 5 the system can delay an arbitrary time before deasserting reset. 10 the system can delay an arbitrary time before enabling memory access. 11 writing a 1 to the memory access enable bit in the pci command register will transition the mac from d0u to d0 state
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1554 order number: 320066-003us 37.7.4.2 transition from d0a to d3 and back without reset figure 37-53.transition from d0a to d3 and back without reset clk reset reading eeprom read eeprom 11 dstate d3 d0u d0 wakeup enabled memory access enable d3 write apm any mode d0 write d0a 3 1 t d0ee 2 4 t ee td0mem 6 7 note 1 writing a 11 to the power state field of the power management control/status register (pmcsr) will transition the power state to d3. 2 the system can delay an arbitrary amount of time between setting d3 mode and asserting reset. 4 upon assertion of reset the mac will go to ?dr? state. 6 the deassertion edge of reset will case the eeprom to be re-read and wake up disabled. 10 the system can delay an arbitrary time before enabling memory access. 11 writing a 1 to the memory access enable bit in the pci command register will transition the mac from d0u to d0 state
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1555 intel ? ep80579 integrated processor 37.7.4.3 transition from d0a to d3 and back with reset figure 37-54.transition from d0a to d3 and back with reset clk reset dstate d0u reading eeprom read eeprom d0a memory access enable wakeup enabled dr 8 any mode apm tprclk t ee t prwdis tprmem t pree d0a 9 1 2 3 4 tclkpr1 7 note 1 writing a 11 to the power state field of the power management control/status register (pmcsr) will transition the mac to d3. 2 the system can delay an arbitrary amount of time between setting d3 mode and asserting reset. 4 upon assertion of reset the mac will go to ?dr? state. 6 the deassertion edge of reset will case the eeprom to be re-read and wake up disabled. 10 the system can delay an arbitrary time before enabling memory access. 11 writing a 1 to the memory access enable bit in the pci command register will transition the mac from d0u to d0 state.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1556 order number: 320066-003us 37.7.4.4 reset without transition to d3 37.7.4.5 timing requirements the mac requires the following start-up or power state transition related timing figure 37-55.reset without transition to d3 clk reset dstate d0u reading eeprom read eeprom d0a memory access enable wakeup enabled dr any mode apm wakeup t ee t prwdis tprmem t pree d0a 8 2 4 9 note 2 upon assertion of reset the mac will go to ?dr? state. 4 the deassertion edge of reset will case the eeprom to be re-read, and wake up disabled. 8 the system can delay an arbitrary time before enabling memory access. 9 writing a 1 to the memory access enable bit in the pci command register will transition the mac from d0u to d0 state. table 37-148.mac timing parameter description min max. notes tppg power to pwr_ok 0 - trpg reset stable to pwr_ok 0 - tpgrst pwr_ok assertion to reset deassertion. 0- tprmem reset deassertion to memory access enable 10ms - the power management specification permits access in 10ms after exiting d3 cold. pci 2.2 gives 225 cycles. tclkpr1 clk stopped to reset deassertion. 0ns the reset must be asserted before the rising edge of the last cycle before the clock is stopped.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1557 intel ? ep80579 integrated processor 37.7.4.6 timing guarantees the gbe guarantees the following start-up or power state transition related timing parameters. 37.7.5 power management extended capabilities registers power management registers are part of the capabilities linked list pointed to by the capabilities pointer (cap_ptr) in the pci configuration space. all fields are reset by pwr_good. all of the fields except pme_en and pme_status are reset by the deassertion (rising edge) of unit_reset. if aux_pwr_present=0, the pme_en and pme_status fields also reset by the deassertion (rising edge) of unit_reset. refer to section 35.6.1.17, ?offset dch: pcid ? power management capability id register? on page 1251 , section 35.6.1.18, ?offset ddh: pcp ? power management next capability pointer register? on page 1251 , section 35.6.1.19, ?offset deh: pmcap ? power management capability register? on page 1252 , and section 35.6.1.20, ?offset e0h: pmcs ? power management control and status register? on page 1253 for register details. table 37-149.gbe timing guarantees parame ter description min max. notes tpgee pwr_ok assertion to start of eeprom read. 01s tpree reset deassertion to start of eeprom read 0 10s tee eeprom read duration 24s 10ms the mac must attempt to read the eeprom to determine if an eeprom is present, so this applies even if no eeprom is connected. td3ps d3 write to power reduction. 0 500ns
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1558 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1559 intel ? ep80579 integrated processor 38.0 global configuration unit 38.1 overview the global configuration unit (gcu) implements the configuration space registers for system-level, ep80579 features. this unit also implements an mdio interface to support the ethernet interfaces. 38.2 feature list the following is a list of features/register sets implemented in the global configuration unit: ?mdio interface ? command and status registers ? mdio drive strength register ? mdc drive strength register ? rcomp registers ? local expansion bus (leb) ? gbe (one set for all three interfaces) ? drive strength registers ? ssp signal group drive strength register ? tdm outputs ? can (one for both) 38.3 usage model all configuration writes and reads are word accesses. addresses to configuration reads and writes are word aligned. 38.3.1 rcomp the rcomp circuitry dynamically compensates the io output drivers for variations in operating conditions due to process, temperature, voltage and pcb layout. these variations are measured through a resistive mechanism in two special io pads. the resistive mechanism on those io pads reference external resistors the user provides to match output driver strength to. thus the output driver impedance can be tuned specifically to the application pcb characteristics for nominal signal transfer into the transmission lines formed by the pcb traces. the rcomp design is nominally set to operate at 50ohms, but the user is free to set the impedance in the range 45ohms to 55ohms.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1560 order number: 320066-003us two rcomp pins are provided to establish th e output driver impedance, one to control the drive high strength, and one to control the drive low strength. these rcomp outputs drive into the external resistors provided by the customer. the drivers form a resistor divider and the voltages developed in these dividers are compared to a reference voltage. the rcomp state machine independently adjusts the strength of the drivers making them stronger or weaker until the comparator signals that the voltage is greater than or less than the reference. the state machine will continue making adjustments causing the comparators to oscillate between two strength settings just above and just below the comparator trip point. logic in the rcomp state machine recognizes when this "dithering" between the two values has begun, and holds the strength output for the outputs fixed at one of the two settings. note this algorithm is independently and concurrently applied to the drive high strength and to the drive low strength. 38.3.1.1 gbe the gbe rcomp controller starts operation when the gbe_aux_pwr_good input is asserted. this condition indicates the power supply's are stable and it also indicates that the gbe_refclk input is being driven with a 125 mhz clock. refer to section 37.0, ?gigabit ethernet controller? on page 1341 for details on the gbe operation. the gbe_refclk input is divided by either 4 or 16 and then used to drive the rcomp state machine. also present are software accessible registers that provide options to monitor/overwrite internal bias and comparator output for sv needs. see section 38.4.1.5, ?offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register? on page 1564 and section 38.4.1.6, ?offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register? on page 1564 . 38.3.1.2 leb the leb rcomp controller starts operation when the leb comes out of reset. the rcomp logic is clocked by the externally provided expansion bus clock. refer to section 42.0, ?local expansion bus controller? on page 1671 for details on the leb operation. also present are software accessible registers that provide options to monitor/overwrite internal bias and comparator output for sv needs. see section 38.4.1.7, ?offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register? on page 1565 and section 38.4.1.8, ?offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register? on page 1566
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1561 intel ? ep80579 integrated processor 38.4 register summary writes to unused address space have no affect. reads from unused address space may return indeterminate data. neither reads nor writes cause detrimental effects on device operation unless specifically documented. reserved bits within registers must be written with their reset value unless otherwise stated. for more information on the conventions the following register summaries adopt, see section 7.1, ?overview of register descriptions and summaries? on page 183 . note: any programming order dependencies on configuration write values must be handled by the os. the global configuration unit registers materialize in the pci space. table 38-1. bus m, device 3, function 0: summary of gcu registers mapped through csrbar memory bar offset start offset end register id - description default value 00000010h 00000013h ?offset 0x00000010h: mdio_status - mdio status register? on page 1562 00000000h 00000014h 00000017h ?offset 0x00000014h: mdio_command - mdio command register? on page 1562 00000000h 00000018h 0000001bh ?offset 0x00000018h: mdio_drive - mdio drive register? on page 1563 03030107h 00000020h 00000023h ?offset 0x00000020h: mdc_drive - mdc drive register? on page 1563 0303030fh 00000024h 00000027h ?offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register? on page 1564 0031f31fh 00000044h 00000047h ?offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register? on page 1564 00000000h 00000050h 00000053h ?offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register? on page 1565 63000300h 00000054h 00000057h ?offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register? on page 1566 000030f301h 00000060h 00000063h ?offset 0x00000060h: ssp_drive - ssp drive register? on page 1566 02000200h 00000064h 00000067h ?offset 0x00000064h: tdm_drive_3 - tdm drive register for tdm ports 3? on page 1567 02000200h 00000068h 0000006bh ?offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2? on page 1567 02000200h 00000028h 0000002bh ?offset 0x00000028h: can_drive - can drive register? on page 1568 02000200h table 38-2. register-table legend attribute legend rv reserved ro read only rw read/write wo write only rs set automatically when read rc cleared automatically when read wc write to clear. see individual bit description for more details.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1562 order number: 320066-003us 38.4.1 detailed register descriptions 38.4.1.1 offset 0x00000010h: mdio_status - mdio status register 38.4.1.2 offset 0x00000014h: mdio_command - mdio command register table 38-3. offset 0x00000010h: mdio_status - mdio status register description: status register for communicating with mdio devices. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000010h 00000013h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 mdio_status 0 = successfully read 1 = read error 0b ro 30 :16 rsvd reserved 0000h ro 15 :00 mdio_read_d ata read data 0000h ro table 38-4. offset 0x00000014h: mdio_command - mdio command register description: command register for communicating with mdio devices. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000014h 00000017h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 mdio_go application logic sets this to ?1? to start the mdio access. this bit remains ?1? during the access. when the access is finished, this bit is reset to ?0?. 0b rw 30 :27 rsvd reserved for future use. 0h rv 26 mdio_oper 1 = mdio write access 0 = mdio read access note: once the transaction completes (as indicated by mdio_go returning ?0?), this bit is also reset to ?0?. 0b rw 25 :21 mdio_phy_ad dr physical address of the phy to be accessed. 0h rw 20 :16 mdio_phy_re g register number of the phy register to be accessed. note: once the transaction completes (as indicated by mdio_go returning ?0?), this field is also reset to ?0?. 00h rw 15 :00 mdio_write_ data write data on mdio write accesses. note: once the transaction completes (as indicated by mdio_go returning ?0?), this field is also reset to ?0?. 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1563 intel ? ep80579 integrated processor 38.4.1.3 offset 0x00000018h: mdio_drive - mdio drive register 38.4.1.4 offset 0x00000020h: mdc_drive - mdc drive register table 38-5. offset 0x00000018h: mdio_drive - mdio drive register description: drive control of mdio output bits. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000018h 0000001bh size: 32 bit default: 03030107h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 rsvd reserved 00h rv 27 :24 mdio_nchan_5x drive strength for n-channel at 5x ratio 03h rw 23 :16 mdio_nchan_1x drive strength for n-channel at 1x ratio 03h rw 15 :12 rsvd reserved 00h rv 11 :08 mdio_pchan_5x drive strength for p-channel at 5x ratio 01h rw 07 :00 mdio_pchan_1x drive strength for p-channel at 1x ratio 07h rw table 38-6. offset 0x00000020h: mdc_drive - mdc drive register description: drive control of mdc outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000020h 00000023h size: 32 bit default: 0303030fh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 rsvd reserved 00h rv 27 :24 mdio_nchan_5x drive strength for n-channel at 5x ratio 03h rw 23 :16 mdio_nchan_1x drive strength for n-channel at 1x ratio 03h rw 15 :12 rsvd reserved 00h rv 11 :08 mdio_pchan_5x drive strength for p-channel at 5x ratio 03h rw 07 :00 mdio_pchan_1x drive strength for p-channel at 1x ratio 0fh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1564 order number: 320066-003us 38.4.1.5 offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register 38.4.1.6 offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register table 38-7. offset 0x00000024h: gcu_gbe_rc_ctrl - gcu gbe rcomp control register description: rcomp control for gbe bus outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000024h 00000027h size: 32 bit default: 0031f31fh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 en on-die termination disabled. 0 - enabled 1 - not enabled 0h rw 30 ovr_wr overwrite rcomp engine strength outputs with dn_tst and up_tst and apply to output pads 0h rw 29 rsvd reserved 0h rv 28 rsvd reserved 0h rv 27 rsvd reserved 0h rv 26 mntr monitor. disable the update lowpass filter. allow new strength values to be output to the rcomp pads as soon as they are calculated. 0h rw 25 stop stop sending new strength values to the rcomp pads. mntr has precedence over stop 0h rw 24 div_bps when set, rcomp engine runs at gbe_refclk / 4. when clear, rcomp engine runs at gbe_refclk/16 0h rw 23 :20 dn_tst_11_8 pull down strength bits [11:8]. each bit enables 5 unit pull-down drivers in the output pad. 3h rw 19 :12 dn_tst_7_0 pull down strength bits [7:0]. each bit enables 1 unit pull-down driver in the output pad. 1fh rw 11 :08 up_tst_11_8 pull up strength bits [11:8]. each bit enables 5 unit pull- up drivers in the output pad. 3h rw 7 :00 up_tst_7_0 pull up strength bits [7:0]. each bit enables 1 unit pull- up driver in the output pad. 1fh rw table 38-8. offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register description: rcomp status of local expansion bus outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000044h 00000047h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 ready ready from the rcomp controller 0h ro 30 pmos_comp pmos comparator output (input to controller) 0h ro 29 nmos_comp nmos comparator output (input to controller) 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1565 intel ? ep80579 integrated processor 38.4.1.7 offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register 28 rsvd reserved 0h ro 27 :16 nmos_ctrl nmos strength control output to pads 0h ro 15 :12 rsvd reserved 0h ro 11 :00 pmos_ctrl pmos strength control output to pads 0h ro table 38-9. offset 0x00000050h: gcu_leb_rc_stat - gcu local expansion bus rcomp status register description: rcomp status of local expansion bus outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000050h 00000053h size: 32 bit default: 63000300h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 ready ready from the rcomp controller 0h ro 30 pmos_comp pmos comparator output (input to controller) 1h ro 29 nmos_comp nmos comparator output (input to controller) 1h ro 28 rsvd reserved 0h ro 27 :16 nmos_ctrl nmos strength control output to pads 300h ro 15 :12 rsvd reserved 0h ro 11 :00 pmos_ctrl pmos strength control output to pads 300h ro table 38-8. offset 0x00000044h: gcu_gbe_rc_stat - gcu gbe rcomp status register description: rcomp status of local expansion bus outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000044h 00000047h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1566 order number: 320066-003us 38.4.1.8 offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register 38.4.1.9 offset 0x00000060h: ssp_drive - ssp drive register table 38-10. offset 0x00000054h: gcu_leb_rc_ctrl - gcu local expansion bus rcomp control register description: rcomp control for gbe bus outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000054h 00000057h size: 32 bit default: 000030f301h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 sw_rst software reset write ?1? to reset. write ?0? to enable operation 0h rw 30 ovr_wr overwrite output bus values from special register 0h rw 29 cmp for overwrite comparator output 0h rw 28 cmpo_wr for overwrite comparator output (select) 0h rw 27 cmpo_rd for test comparator output 0h rw 26 mntr bypass the update logic system 0h rw 25 stop "freeze" output bus, but circuit operation continue 0h rw 24 div_bps bypass internal clock divider 0h rw 23 :20 dn_tst_11_8 pull down strength bits [11:8]. each bit enables 5 unit pull-down drivers in the output pad. 3h rw 19 12 dn_tst_7_0 pull down strength bits [7:0]. each bit enables 1 unit pull-down driver in the output pad. 0fh rw 11 8 up_tst_11_8 pull up strength bits [11:8]. each bit enables 5 unit pull- up drivers in the output pad. 3h rw 7 0 up_tst_7_0 pull up strength bits [7:0]. each bit enables 1 unit pull- up driver in the output pad. 01h rw table 38-11. offset 0x00000060h: ssp_drive - ssp drive register description: drive control of ssp outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000060h 00000063h size: 32 bit default: 02000200h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :30 rsvd reserved 0h rv 29 :28 rsvd reserved 0h rv 27 :24 mdio_nchan_5x drive strength for n-channel at 5x ratio 02h rw 23 :16 mdio_nchan_1x drive strength for n-channel at 1x ratio 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1567 intel ? ep80579 integrated processor 38.4.1.10 offset 0x00000064h: tdm_drive_3 - tdm drive register for tdm port 3 38.4.1.11 offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2 15 :12 rsvd reserved 0h rv 11 :8 mdio_pchan_5x drive strength for p-channel at 5x ratio 02h rw 07 :00 mdio_pchan_1x drive strength for p-channel at 1x ratio 0h rw table 38-12. offset 0x00000064h: tdm_drive_3 - tdm drive register for tdm ports 3 description: drive control of tdm port 3outputs view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000064h 00000067h size: 32 bit default: 02000200h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 rsvd reserved 0h rv 27 :24 mdio_nchan_5x drive strength for n-channel at 5x ratio 02h rw 23 :16 mdio_nchan_1x drive strength for n-channel at 1x ratio 0h rw 15 :12 rsvd reserved 0h rv 11 :8 mdio_pchan_5x drive strength for p-channel at 5x ratio 02h rw 07 :00 mdio_pchan_1x drive strength for p-channel at 1x ratio 0h rw table 38-13. offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2 description: drive control of tdm port 1 & 2outputs view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000068h 0000006bh size: 32 bit default: 02000200h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 rsvd reserved 0h rv 27 :24 mdio_nchan_5x drive strength for n-channel at 5x ratio 02h rw table 38-11. offset 0x00000060h: ssp_drive - ssp drive register description: drive control of ssp outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000060h 00000063h size: 32 bit default: 02000200h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1568 order number: 320066-003us 38.4.1.12 offset 0x00000028h: can_drive - can drive register 23 :16 mdio_nchan_1x drive strength for n-channel at 1x ratio 0h rw 15 :12 rsvd reserved 0h rv 11 :08 mdio_pchan_5x drive strength for p-channel at 5x ratio 02h rw 07 :00 mdio_pchan_1x drive strength for p-channel at 1x ratio 0h rw table 38-14. offset 0x00000028h: can_drive - can drive register description: drive control of both can controller outputs. view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000028h 0000002bh size: 32 bit default: 02000200h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :28 rsvd reserved 0h rv 27 :24 mdio_nchan_5x drive strength for n-channel at 5x ratio 02h rw 23 :16 mdio_nchan_1x drive strength for n-channel at 1x ratio 0h rw 15 :12 rsvd reserved 0h rv 11 :8 mdio_pchan_5x drive strength for p-channel at 5x ratio 02h rw 07 :00 mdio_pchan_1x drive strength for p-channel at 1x ratio 0h rw table 38-13. offset 0x00000068h: tdm_drive_12 - tdm drive register for tdm ports 1 & 2 description: drive control of tdm port 1 & 2outputs view: pci bar: csrbar bus:device:function: m:3:0 offset start: offset end: 00000068h 0000006bh size: 32 bit default: 02000200h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1569 intel ? ep80579 integrated processor 39.0 controller area network - can 39.1 overview controller area network (can) is a serial bus system used in a broad range of embedded and automation control systems. the can usually links two or more microcontroller-based physical devices (nodes). can protocol is based on a broadcast co mmunication mechanism. this broadcast communication is achieved by using a message-oriented transmission protocol. in this protocol, node-addresses are not defined, only messages are defined. these messages are identified by a message identifier. the message identifier has to be unique within the network and it defines not only the content, but also the priority of the message. a high degree of system and configuration flexibility is achieved as a result of the content-oriented addressing scheme.this content-oriented addressing scheme allows for a high degree of system and configuration flexibility. it is easy to add stations to an existing can network without making any hardware or software modifications to the existing stations, as long as the new stations are purely receivers. this allows for modularization of the components and also permits multiple reception and the synchronization of distributed processes: data needed as information by several stations can be transmitted via the network in such a way that it is unnecessary for each station to know who the producer of the data is. this allows easy servicing and upgrading of networks, as data transmission is not based on the availability of specific types of stations. 39.2 feature list key features are listed below: ? conforms to iso 11898-1(high-speed can). ? full can 2.0b compliance. ? supports can 2.0a. ? supports 11-bit identifier and 29-bit identifier. ? bit rates up to 1mbps. ? 16 receive buffers: ? each buffer has its own message filter. ? message filter covers: id, ide, rtr, data byte (1 and 2). ? message buffers can be linked together to build a larger message array. ? automatic rtr response handler. ?transmit path: ? 8 transmit message holding registers with programmable priority arbitration. ? message abort command. ? test and debugging support:
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1570 order number: 320066-003us ? listen only mode. ? sram-based message buffer: ? 1odd/even parity generation and checking. ? parity error reporting and parity test mode. 39.3 functional block diagram the block diagram for the can unit and its interface to other major blocks on the ep80579 is shown in figure 39-1 . the figure shows only one instance of the can unit. there are two instances of the same can unit. figure 39-1. can block diagram ep80579 can unit internal bus coupler memory arbiter can framer int ctrl status & configuration control & command rx message handler tx message handler sram 32bits x 160deep 4 bits for parity internal bus can io pads
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1571 intel ? ep80579 integrated processor 39.4 usage model 39.4.1 can basics can is an asynchronous serial bus system. the bus structure is open and linear, with equal bus nodes. a can bus typically consists of two or more nodes. nodes can be added to the can network dynamically without interrupting the communication of other nodes. that makes it easy to add or take off bus nodes (e.g. for adding functionality to the system, error recovery or monitoring). the can bus is a ?wired-and? mechanism, where recessive bits (high) are overwritten by dominant bits (low). if no nodes are driving a dominant bit, the bus stays in the recessive state (idle). the node that first drives a dominant bit becomes the master and owns the bus. one of the cheapest and most common mediums is a twisted differential wire pair. the two lines are ?can_h? and can_l?, which can be connected directly to the nodes via a connector. the maximum speed for the can bus is 1mbps up to 40m. for bus length beyond 40 m, the bus speed must be reduced. up to 30 nodes can be connected without extra equipment. can is insensitive to emi because a differential pair will be affected in the same way. the bit stream in a message is coded according on the non-return-to-zero (nrz) method, which means the signal level remains constant over the bit time and thus one time slot is required to represent a bit. to guarantee proper synchronization of all bus nodes, bit stuffing must be used. if five consecutive bits of the same polarity have been driven by the master, the sixth bit will be of opposite polarity, then the master will continue to transmit. every receiver on the bus will check for the amount of bits with the same polarity, and will destuff (the sixth bit) the message. 39.4.2 addressing and bus arbitration the can protocol uses csma/cd with nda (carrier sense multiple access/collision detection with non-destructive arbitration) for bus arbitration. a node that wants to transmit a message onto the network must first check if the can bus is in the ?idle? state (carrier sense). the node then becomes the master by transmitting its message. every other node will switch to receive mode during the start of frame bit, see figure 39-2 . after receiving a message with no errors, all nodes sends an acknowledge, and store the message if required. if message storage is not required, the message is discarded. if multiple nodes start their transmission simultaneously (multiple access), collision is avoided by the use of bitwise arbitration (collision detection/non-destructive arbitration), and the ?wired-and? mechanism. the node that sends out a recessive bit in its identifier field (msb first), but reads back a dominant bit, loses arbitration and switches to receive mode. the competitive node won arbitration because it had a higher priority. this way, nodes with higher priority do not have to waste time re- sending their message. the nodes that lose arbitration will automatically attempt to re- send their message after the bus becomes ?idle?. note: different nodes cannot have similar identifiers on the same network. standard can (can2.0a) has an 11 bit identifier field, see figure 39-2 , allowing a total of 2048 identifiers. this limitation has been improved by the extended can (can2.0b), which has either a 11 and/or a 29 bit identifier field, resulting in a total of 536 million identifiers. see figure 39-2 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1572 order number: 320066-003us 39.4.3 frame types the can protocol is defined and controlled by four different frame types: ? data frame - data frame from a transmitting node to receiving nodes. ? remote frame - receiving node requesting the data frame with equal identifier. ? error frame - transmitted by any node that detected an error. ? overload frame - a node can generate an overload frame under two conditions: ? if the node detects a dominant bit during the interframe space (intermission). ? the node is not yet ready to receive another data frame (wait states). nodes are not allowed to generate more than 2 consecutive overload frames to delay the next transfer. ? the can unit will not generate an overload frame but will respond to it if it sees one on the bus. 39.4.3.1 data frame a standard can data frame is composed of seven fields, as shown in figure 39-2 . ? start of frame: one dominant bit marks the beginning of data frames and remote frames. the purpose is hard synchronization for all nodes. ? arbitration field, consisting of: ? 11 bit identifier ? 1 rtr bit. this bit is used to distinguish between a data frame (dominant) and a remote frame (recessive). figure 39-2. standard can data frame 11111 4 0...64 15 1 1 1 7 3 standard data frame start of frame identifier ide bit (d) reserved (d) rtr bit (d) dlc data field crc sequence crc delimiter ack slot ack delimiter end of frame intermission bus idle bus idle arbitration field control field crc field acknowledge field recessive level dominant level 1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1573 intel ? ep80579 integrated processor ? control field, consisting of: ? data length code, which is 4 bits wide ? 2 reserved bits for future expansion ? data field, consisting of the data to be transmitted. the data field can be from 0 to 8 bytes. (msb transferred first). ? crc field, consisting of: ? crc sequence, which is the remainder of a polynomial division. this is a 15 bit value. ? crc delimiter which is one recessive bit. ? ack field, containing: ?a one bit ack slot a transmitting node drives this bit with a recessive value. all receiving nodes with comparable crc values acknowledge with a dominant bit. ?a one bit ack delimiter this will always be a recessive bit. ? end of frame, which consists of seven recessive bits. between any frame the can bus must stay ?idle? for at least three bit times(intermission). if no nodes wish to send a frame, the bus stays ?idle?. the extended can data frame is illustrated in figure 39-3 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1574 order number: 320066-003us note: to to use both extended and standard frames on the same network, it is necessary to split the 29 bit extended identifier into one 11 bit (most significant) and one 18 bit (least significant) section. by doing this, the ide bit can remain in the same bit position in both standard and extended frames. ? start of frame: one dominant bit marks the beginning of both data frames and remote frames. this is for hard synchronization with all nodes. ? arbitration field, consisting of: ? 11 bit identifier (most significant) ? srr bit, recessive ? ide bit, recessive to denote an extended can frame ? extended identifier, 18 bits ? 1 rtr bit. this bit is used to distinguish between a data frame(dominant) and a remote frame (recessive). ? control field, consisting of: ?two dominant bits ? data length code, which is 4 bits wide the remaining fields are similar to standard data frame. figure 39-3. extended can data frame 11111 18 12 4 0...64 15 111 7 3 extended data frame start of frame identifier srr bit (r) ide bit (r) extended identifier rtr bi t (d) (2 reserved (d)) dlc data field crc sequence crc del i mi ter ack slot ack delimiter end of frame intermission bus idle bus idle arbitration field (without ide bit) control field (plus ide bit) crc fi el d acknowledge field recessive level dominant level
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1575 intel ? ep80579 integrated processor 39.4.3.2 remote frame in the can protocol, it is also possible for a destination node to request data from a source. this can be done by transmitting a remote frame with an identifier that matches the identifier of the required data frame. this request results in a response from the source with the matching identifier, including the data frame. if a node were to transmit a data frame at the same time as a node were to send a remote frame with the same identifier, the data frame would win arbitration due to the dominant rtr bit. the format of an extended remote frame is shown in figure 39-5 . figure 39-4. standard can remote frame 11111 4 15 111 7 3 standard remote frame start of frame identifier ide bit (d) reserved (d) rtr bit (r) dlc crc sequence crc delimiter ack slot ack delimiter end of frame intermission bus idle bus idle arbitration field control field crc field acknowledge field recessive level dominant level 1
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1576 order number: 320066-003us 39.4.3.3 error frames can, as a message-oriented protocol, uses e rror signaling. each network node checks each message that is transmitted on the bus for errors. when a transmitting or receiving network node detects an error, the node signals all other nodes by transmitting an error message (error frame). the error frame contains a six bit combination with the same polarity, normally as a dominant bit sequence (active error flag). all network nodes detect the error signal and cancel the segments of a message already received. consistent data is thus ensured for all nodes of the network. an error frame consists of two fields: ? error flag field: ? an active error flag consists of six consecutive dominant bits. this violates the can protocol bit stuffing rule, and in turn all nodes on the network will generate error frames. the error frame field will then vary from a minimum of 6 to maximum of 12 consecutive dominant bits. ? a passive error flag consists of six consecutive recessive bits, unless overwritten by dominant bits from other nodes. unless the bus master transmits the passive error flag, the passive error flag will not affect any other node on the network. ? error delimiter field: consists of eight recessive bits and terminates the error frame. figure 39-5. extended can remote frame 11111 18 12 4 15 1 1 1 7 3 extended remote frame start of frame identifier srr bit (r) ide bit (r) extended identifier rtr bit (r) (2 reserved (d)) dlc crc sequence crc delimiter ack slot ack delimiter end of frame intermission bus idle bus idle arbitration field (without ide bit) control field (plus ide bit) crc field acknowledge field recessive level dominant level
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1577 intel ? ep80579 integrated processor when a transmitting node has transmitted an error frame to completion or has received one, it immediately attempts to transmit the previously transmitted message again with another bus arbitration process. the error signaling mechanism ensures that the message transfer with all nodes of a network is error-free and consistent. because error signaling takes place immediately after an error is detected, short error recovery times are guaranteed. note: the can protocol also provides a self-monitoring mechanism that prevents one dysfunctional node from holding the network down. the assessment of a node?s statistical error rate may result in deactivation of the node. 39.4.3.4 overload frames an overload frame has the same format as an active error frame. the difference is when the overload frame is transmitted and its purpose: an overload frame is only permitted to transmit during interframe space (intermission). two conditions lead to the generation of an overload frame: ? if a node is not yet ready for any data (insert wait state). ? a node detects a dominant bit during intermission. a node may generate at most 2 consecutive overload frames, to dela y the next data or remote frame. overload frames consist of two fields: ? the overload flag has the same format as an active error frame. ? the overload delimiter consists of eight recessive bits. note: the can controller will not generate overload frames. however, it will respond to overload frames when it sees one on the bus. 39.4.4 can bit timing 39.4.4.1 introduction the can network is configured based on the bit rate. the nominal bit rate is the number of bits per second passing through the network in the absence of re synchronization. each member of this network can implement the required timing parameters for a given bit rate using different values as long as the chosen values meet the synchronization requirements. oscillator drift and other issues could make the nominal configured bit rate to vary but the can protocol provides a mechanism to re synchronize the messages. the nominal bit rate is made up of the following non-overlapping segments: ? synchronization segment: this is the start of the frame segment of the bit being transmitted. it is used primarily to synchronize nodes on the bus. the synchronization segment is always fixed to 1 time quanta. ? propagation segment: the is the time required for signals to travel in the can network. it includes the time required to travel from one end of the system to the other and back again. it also accounts for the can components to react. ? phase buffer segment 1 & 2: these phase buffers exists to compensate for timing problems created by the oscillator drift and other issues. these 2 segments are adjusted in units called the synchronization jump width. ? sample point: the sample point always occurs between the phase 1 and phase 2 segments. it can be set to be either single or multiple.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1578 order number: 320066-003us each member of can network can use different timing parameters to achieve the same bit rate. as shown in figure 39-6 each segment is defined in terms of time quantum (tq). the time quantum value is the basic unit of the bit time and is determined by the can controller system clock frequency and the bit scaler. tq = bit_scaler / can clock frequency. for a given bit rate that the can requires, the bit_scaler can be changed to meet the recommended values of phase buffer segments and synchronization jump width. the cia (can in automation) draft standard 102 version 2.0 defines the content of the physical layer and the basic characteristics of the physical medium, for communication according to the controller area network protocol specification (can) between different types of electronic modules in general industrial applications. figure 39-6. can timing parameters synchronization segment propagation delay segment phase buffer segment 1 phase buffer segment 2 time quanta sample point bit time 1 table 39-1. cia recommended bit rate and timing parameters (sheet 1 of 2) bit rate (kbits/s) bus length (m) nominal bit time tb (us) number of time quanta per bit length of time quantum tq (us) location of sample point wrt tq location of sample point (us) comments 1000 25 1 8 0.125 6 tq 0.75 max 40m 800 50 1.25 10 0.125 8 tq 1 500 100 2 16 0.125 14 tq 1.75 250 250 4 16 0.250 14 tq 3.5 125 500 8 16 0.500 14 tq 7 50 1000 20 16 1.25 14 tq 17.5 max 1km 20 2500 50 16 3.125 14 tq 43.75 has to be supported by all modules
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1579 intel ? ep80579 integrated processor the cia recommended timing parameters for each bit rate is show in figure 39-7 . 39.4.4.2 setting proper bit rate, tseg1 and tseg2 the can controller unit provides the following programmable timing parameters, which can be used to achieve cia recommended bit rates: ? cfg_tseg1 (propagation delay segment + phase buffer segment 1): this is used to compensate for edge phase errors but also consists of a propagation segment, which is used to compensate fo r signal delays in the network. ? cfg_tseg2 (phase buffer segment 2): this is also used for compensation of edge phase errors. ? cfg_sjw (synchronization jump width): this defines how far the re-synchronization may move the sample point inside the limits defined by the phase buffer segments to compensate for edge phase errors. as shown in figure 39-7 , the sample point separates tseg1 and tseg 2, this is the point in time where the bus level is read and interpreted. the can unit in the ep80579 operates at a frequency of 40mhz. based on this frequency, the recommended timing parameter values are as show in table 39-2 . 10 5000 100 16 6.25 14 tq 87.5 minimum bit rate sampling mode = single synchronization mode = reccessive to dominant edges only synchronization jump width = 1 * tq phase segment 2 = 2 * tq table 39-1. cia recommended bit rate an d timing parameters (sheet 2 of 2) bit rate (kbits/s) bus length (m) nominal bit time tb (us) number of time quanta per bit length of time quantum tq (us) location of sample point wrt tq location of sample point (us) comments figure 39-7. bit rate and time settings 1 tseg1 + 1 tseg2 + 1 sample point bit time time quanta (tq) bittime = ( 1 + ( tseg1 + 1 ) + ( tseg2 + 1 ) ) * timequanta timequanta = bitrate + 1 f clk
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1580 order number: 320066-003us 39.5 theory of operation 39.5.1 modes of operation the can unit can be used in different operating modes. by disabling transmitting data, it is possible to use the can in listen-only mode, enabling features such as automatic bit rate detection. the two units can be used in an on-chip loop-back mode. before starting the can controller, all can configuration registers must be set according to the target application. 39.5.2 error handling the can protocol provides sophisticated erro r detection mechanisms. the following list of errors can be detected: ? cyclic redundancy check (crc) error - the received crc sequence did not match the calculated result. ? acknowledge error - the transmitter did not detect a dominant bit during ack slot. ? form error - one or more illegal bits in a fixed-form bit field. ? bit error - the monitored bit value is different from the bit value sent. ? stuff error - between start of frame and crc delimiter, 6 consecutive bits with the same polarity are detected. an interrupt will be generated if an error is enabled and detected, see ?offset 00000000h: int_status - interrupt status register? . table 39-2. can recommended bit rate and timing parameters bit rate (kbs/s) nominal bit time (us) number of time quanta per bit nominal bit time / can controller frequency ? time quantum (us) bit rate scaler required for 40mhz can clock cfg_tseg1 (tseg - 1) cfg_bitrate 1000 1 8 40 0.125 5 4 4 800 1.25 10 50 0.125 5 6 4 500 2 16 80 0.125 5 12 4 250 4 16 160 0.250 10 12 9 125 8 16 320 0.500 20 12 19 50 20 16 800 1.250 50 12 49 20 50 16 2000 3.125 125 12 124 10 100 16 4000 6.250 250 12 249 the bit rate scaler is chosen such that this is an integer value. can clock frequency = 40mhz cfg_tseg2 = 1 cfg_sjw = 0 single sampling mode synchronization mode: recessive to dominant only
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1581 intel ? ep80579 integrated processor note: the errors are always detected and registered in the interrupt status register. the interrupt enable register determines whether or not it gets propagated. for more information please refer to ?offset 00000000h: int_status - interrupt status register? and ?offset 00000004h: int_ebl - interrupt enable register? 39.5.3 send/receive procedure 39.5.3.1 send procedure use the following procedure to send a message: 1. write a message into one of the transmit message holding buffers. an empty buffer is indicated by a txreq that equals zero. 2. request transmission by setting the respective txreq flag to ?1?. 3. the txreq flag remains set as long as the message transmit request is pending. the content of the message buffer must not change while the txreq flag is set. 4. the internal message priority arbiter selects the message according to the chosen arbitration scheme. 5. once the message is transmitted, the txreq flag is set to zero and the txmsg interrupt status is asserted. a message can be removed from a transmit holding buffer by setting the txabort flag. use the following procedure to remove the contents of a particular txmessage buffer: 1. set txabort to ?1? to request the message removal. 2. the txabort flag remains set as long as the message abort request is pending. the flag is cleared when either the message wins arbitration (txmsg interrupt active) or the message is removed (txmsg interrupt inactive). 39.5.3.2 receive procedures the can unit supports 16 individual receive message buffers. each one has its own message filter mask. automatic reply to rtr messages is supported. if a message is accepted in a receive buffer, its msgav flag is set. the message remains valid as long as msgav flag is set. the host cpu has to reset the msgav flag to enable receipt of a new message. figure 39-8. receive message handler rxmessage 0 rxmessage 1 rxmessage 2 rxmessage 15 inican rxmessage handler 1 2 3 16 canbus canmodule-iii
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1582 order number: 320066-003us 39.5.3.3 rx message processing after receipt of a new message, the rxmessagehandler searches all receive buffers starting from rxmessage0 until it finds a valid buffer. a valid buffer is indicated by: ? receive buffer is enabled indicated by rxbufferebl = ?1?. ? acceptance filter of receive buffer matches incoming message. if the rxmessagehandler finds a valid buffer that is empty, then the message is stored and the msgav flag is set to ?1?. if the rxintebl flag is set, then the rxmsg flag of the interrupt controller is set. if the receive buffer already contains a message indicated by msgav = ?1? and the link flag is not set, then a rxmsgloss interrupt flag is set. if an incoming message has its rtr flag set and the rtrreply flag is set, then the message is not stored but an rtr auto-reply is issued. see ?offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control? for more details. 39.5.3.4 acceptance filter each receive buffer has its own acceptance filter that is used to filter incoming messages. an acceptance filter consists of an acceptance mask register (amr) and acceptance code register (acr) pair. the amr defines which bits of the incoming can message have to match the respective acr bits. the following message fields are covered: ?id ?ide ?rtr ? data byte 1 and data byte 2 (data[63:56]) note: some can high level protocols such as sds or device net carry additional protocol related information in the first or first two data bytes that are used for message acceptance and selection. the capability to filter on these fields provides a more efficient implementation of the protocol stack running on the cpu. the acceptance mask register (amr) defines whether the incoming bit is checked against the acceptance code register (acr). ?amr: ? ?0?: the incoming bit is checked against the respective acr. the message is not accepted when the incoming bit doesn?t match the respective acr flag. ? ?1?: the incoming bit is ?don?t care?. example: the following example shows the acceptance register settings used to support receipt of a canopen tpd01 (transmit process data object) message. in canopen, a widely used can higher level protocol (hlp), the id bits are used to select the message type. the bit assignment is shown in the following table:
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1583 intel ? ep80579 integrated processor identifier fields: ? function code: the function code for a tdpo1 message is 3h. ? node-id: the example uses 02h as the node id. ? ide = ?0?: canopen uses the short format message. ? rtr = ?0?:identifies a regular message. to accept this message, the acceptance filter settings would look like the following: ?amr settings: id[28:18] = 0 id[17:0] = all ones ide = 0 rtr = 0 data[63:56] = all ones ?acr settings: id[28:18] = 182h id[17:0] = don't care ide = 0 rtr = 0 data[63:56] = don?t care 39.5.3.5 rtr auto-reply the can unit supports fully automatic answering of rtr message requests. all 16 receive buffers support this feature. if an rtr message is accepted in a receive buffer, where the rtrreply flag is set, then this buffer automatically replies to this message with the content of this receive buffer. the rtrreply_pending flag is set when the rtr message request is received. the flag is reset when the message was sent or when the message buffer is disabled. to abort a pe nding rtrreply message, use the rtrabort command. 39.5.3.6 rxbuffer linking several receive buffers may be linked together to form a receive buffer array which acts like a receiver fifo. the requirements are as follows: ? all buffers of the same array must have the same message filter setting (amr and acr are identical). ? the last buffer of an array may not have its link flag set. when a receive buffer already contains a message (msgav=?1?) and a new message arrives for this buffer, then this message would be discarded (rxmsgloss interrupt). to avoid this situation, several receive buffers can be linked together. when the can unit receives a new message, the rxmessage handler searches for a valid receive buffer. if table 39-3. can higher level protocol (hlp) bit assignment canopen identifier 109 8765432 1 0 function code node-id
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1584 order number: 320066-003us one is found that is already full (msgav=?1?) and the link flag is set (bufferlink=?1?), the search for a valid receive buffer is continued. if no other buffer is found, then the rxmsgloss interrupt is set anyway. it is possible to build several message arrays. each of these arrays must use the same amr and acr. 39.5.4 txmessage registers eight transmit message holding buffers are provided. an internal priority arbiter selects the message according to the chosen arbitration scheme. upon transmission of a message or message arbitration loss, the priority arbiter re-evaluates the message priority of the next message. the priority arbiter supports round robin and fixed priority arbitration. the arbitration mode is selected using the configuration register. ? round robin - buffers are served in a de fined order: 0-1-2..7-0-1... a particular buffer is only selected if its txreq flag is set. this scheme guarantees that all buffers receive the same probability to send a message. ? fixed priority - buffer 0 has the highest priority. with this mode, it is possible to designate buffer 0 as the buffer for error messages and it is guaranteed that they are sent first. note: rtr message requests are served before txmessage buffers are handled (e.g. rtrreq0, ... rtrreq15, txmessage0, txmessage0, txmessage1, ... txmessage7). see the description of the configuration register in the txmessage0 buffer in ?offset 00000020h: txmessagecontrol[0-7] - transmit message control and command? for information about how to select these modes. figure 39-9. message arbitration internal bus coupler priority arbiter txmessage0 txmessage7 txmessage1 rxmessage0 rxmessage15 inican rtrreq rtrreq canbus internal bus txreq txreq txreq
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1585 intel ? ep80579 integrated processor 39.6 register summary the default value for all registers is 0h, unless otherwise noted. all registers starting at 20h are implemented in sram without guaranteed reset values. it is the responsibility of either bios or sw to initialize these to 0. for more information on the conventions the following register summaries adopt, see section 7.1, ?overview of register descriptions and summaries? on page 183 . the can registers materialize in the pcispace. ta bl e 3 9 - 4 and ta bl e 3 9 - 5 summarize the can interface #0 and #1 materializations from the pci perspective. table 39-4. bus m, device 4, function 0: summary of can registers mapped through csrbar memory bar offset start offset end register id - description default value 00000000h 00000003h ?offset 00000000h: int_status - interrupt status register? on page 1587 00000000h 00000004h 00000007h ?offset 00000004h: int_ebl - interrupt enable register? on page 1588 00000000h 00000008h 0000000ah ?offset 00000008h: buffer status indicators? on page 1589 00000000h 0000000ch 0000000fh ?offset 0000000ch: errorstatus - error status indicators? on page 1590 00000000h 00000010h 00000013h ?offset 00000010h: command - operating modes? on page 1591 00000000h 00000014h 00000017h ?offset 00000014h: config - can configuration register? on page 1592 00000000h 00000020h at 10h 00000023h at 10h ?offset 00000020h: txmessagecontrol[0-7] - transmit message control and command? on page 1593 xxxxxxxxh 00000024h at 10h 00000027h at 10h ?offset 00000024h: txmessageid[0-7] - transmit message id? on page 1595 xxxxxxxxh 00000028h at 10h 0000002ah at 10h ?offset 00000028h: txmessagedatahigh[0-7] - transmit message data high? on page 1596 xxxxxxxxh 0000002ch at 10h 0000002fh at 10h ?offset 0000002ch: txmessagedatalow[0-7] - transmit message data low? on page 1597 xxxxxxxxh 000000a0h at 20h 000000a3h at 20h ?offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control? on page 1598 xxxxxxxxh 000000a4h at 20h 000000a7h at 20h ?offset 000000a4h: rxmessageid[0-15] - receive message id? on page 1600 xxxxxxxxh 000000a8h at 20h 000000abh at 20h ?offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high? on page 1600 xxxxxxxxh 000000ach at 20h 000000afh at 20h ?offset 000000ach: rxmessagedatalow[0-15] - receive message data low? on page 1601 xxxxxxxxh 000000b0h at 20h 000000b3h at 20h ?offset 000000b0h: rxmessageamr[0-15] - receive message amr? on page 1601 xxxxxxxh 000000b4h at 20h 000000b7h at 20h ?offset 000000b4h: rxmessageacr[0-15] - receive message acr? on page 1602 xxxxxxxxh 000000b8h at 20h 000000bbh at 20h ?offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data? on page 1603 xxxxxxxxh 000000bch at 20h 000000bfh at 20h ?offset 000000bch: rxmessageacr_data[0-15] - receive message acr data? on page 1604 xxxxxxxxh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1586 order number: 320066-003us table 39-5. bus m, device 5, function 0: summary of can registers mapped through csrbar memory bar offset start offset end register id - description default value 00000000h 00000003h ?offset 00000000h: int_status - interrupt status register? on page 1587 00000000h 00000004h 00000007h ?offset 00000004h: int_ebl - interrupt enable register? on page 1588 00000000h 00000008h 0000000ah ?offset 00000008h: buffer status indicators? on page 1589 00000000h 0000000ch 0000000fh ?offset 0000000ch: errorstatus - error status indicators? on page 1590 00000000h 00000010h 00000013h ?offset 00000010h: command - operating modes? on page 1591 00000000h 00000014h 00000017h ?offset 00000014h: config - can configuration register? on page 1592 00000000h 00000020h at 10h 00000023h at 10h ?offset 00000020h: txmessagecontrol[0-7] - transmit message control and command? on page 1593 xxxxxxxxh 00000024h at 10h 00000027h at 10h ?offset 00000024h: txmessageid[0-7] - transmit message id? on page 1595 xxxxxxxxh 00000028h at 10h 0000002ah at 10h ?offset 00000028h: txmessagedatahigh[0-7] - transmit message data high? on page 1596 xxxxxxxxh 0000002ch at 10h 0000002fh at 10h ?offset 0000002ch: txmessagedatalow[0-7] - transmit message data low? on page 1597 xxxxxxxxh 000000a0h at 20h 000000a3h at 20h ?offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control? on page 1598 xxxxxxxxh 000000a4h at 20h 000000a7h at 20h ?offset 000000a4h: rxmessageid[0-15] - receive message id? on page 1600 xxxxxxxxh 000000a8h at 20h 000000abh at 20h ?offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high? on page 1600 xxxxxxxxh 000000ach at 20h 000000afh at 20h ?offset 000000ach: rxmessagedatalow[0-15] - receive message data low? on page 1601 xxxxxxxxh 000000b0h at 20h 000000b3h at 20h ?offset 000000b0h: rxmessageamr[0-15] - receive message amr? on page 1601 xxxxxxxh 000000b4h at 20h 000000b7h at 20h ?offset 000000b4h: rxmessageacr[0-15] - receive message acr? on page 1602 xxxxxxxxh 000000b8h at 20h 000000bbh at 20h ?offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data? on page 1603 xxxxxxxxh 000000bch at 20h 000000bfh at 20h ?offset 000000bch: rxmessageacr_data[0-15] - receive message acr data? on page 1604 xxxxxxxxh
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1587 intel ? ep80579 integrated processor 39.6.1 detailed register descriptions this section shows all internal registers and describes how the can unit can be used and programmed. 39.6.1.1 offset 00000000h: int_status - interrupt status register the interrupt controller contains an interrupt status and an interrupt enable register. the interrupt status register stores internal interrupt events. once a bit is set, it remains set until it is cleared by writing a '1' to it. the interrupt enable register has no effect on the interrupt status register. the interrupt enable register controls which particular bits from the interrupt status register are used to assert the interrupt output int_n. int_n is asserted if a particular interrupt status bit and the respective enable bit are set. table 39-6. offset 00000000h: int_status - interrupt status register description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000000h 00000003h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000000h 00000003h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :13 reserved reserved n 0h ro 12 rx_msg indicates that a message was received. n 0b rwc 11 tx_msg indicates that a message was sent. n 0b rwc 10 rx_msg_loss is set when a new message arrives but the rxmessage flag msgav is set n0b rwc 09 bus_off the can has reached the bus off state n 0b rwc 08 crc_err an crc error occured while receiving or transmitting data n 0b rwc 07 form_err a form error occured while receiving or transmitting data. n 0b rwc 06 ack_err an acknowledge error occured while transmitting data n 0b rwc 05 stuff_err a stuff error occured while transmitting data n 0b rwc 04 bit_err a bit error occured while receiving or transmitting data n 0b rwc 03 ovr_load an overload condition has occured n 0b rwc 02 ar_loss the arbitration was lost while sending a message n 0b rwc 01 :00 reserved reserved n 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1588 order number: 320066-003us 39.6.1.2 offset 00000004h: int_ebl - interrupt enable register table 39-7. offset 00000004h: int_ebl - interrupt enable register description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000004h 00000007h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000004h 00000007h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :13 rsvd reserved, these bits are always 0 0h rw 12 rx_msg indicates that a message was received. 0h rw 11 tx_msg indicates that a message was sent. 0b rw 10 rx_msg_loss is set when a new message arrives but the rxmessage flag msgav is set 0b rw 09 bus_off the can has reached the bus off state 0b rw 08 crc_err a crc error occured while receiving or transmitting data 0b rw 07 form_err a form error occured while receiving or transmitting data. 0b rw 06 ack_err an acknowledge error occured while transmitting data 0b rw 05 stuff_err a stuff error occured while transmitting data 0b rw 04 bit_err a bit error occured while receiving or transmitting data 0b rw 03 ovr_load an overload condition has occured 0b rw 02 ar_loss the arbitration was lost while sending a message 0b rw 01 rsvd reserved 0b rw 00 int_ebl int_ebl, global interrupt enable flag. 0 = all interrupts are disabled 1 = enabled interrupt sources are available 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1589 intel ? ep80579 integrated processor 39.6.1.3 offset 00000008h: buffer status - buffer status indicators these status indicators bundle the respective flags from all rxmessage and txmessage buffers. note: all flags are read only (e.g. to acknowledg e a msgav flag, the cpu has to write to the respective rxmessage buffer). table 39-8. offset 00000008h: buffer status indicators description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000008h 0000000ah view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000008h 0000000ah size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rsvd reserved, these bits are always 0 0h ro 23 :16 txmsg_7_0 txreq pending (bits [7:0]) 0b ro 15 :00 rxmsg_15_0 msgav (bits [15:0]) 0b ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1590 order number: 320066-003us 39.6.1.4 offset 0000000ch: errorstatus - error status indicators status indicators are provided to report the can controller error state, receive error count and transmit error count. special flags to report error counter values equal to or in excess of 96 errors are available to indicate heavily disturbed bus situations. table 39-9. offset 0000000ch: errorstatus - error status indicators description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 0000000ch 0000000fh view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 0000000ch 0000000fh size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :20 rsvd reserved, these bits are always 0 0h ro 19 rxgte96 the receiver error counter is greater or equal 96(dec) 0b ro 18 txgte96 the transmitter error counter is greater or equal 96(dec) 0b ro 17 :16 error_stat_1_0 the error state of the can node (bits[1:0]): ?00? = error active (normal operation) ?01? = error passive ?1x? = bus off 0h ro 15 :8 rx_err_cnt_7_0 the receiver error counter (bits [7:0]) according to the bosch can 2.0 specification. when in bus off (inactive), this counter is used to count the idle states 0b ro 07 :00 tx_err_cnt_7_0 the transmitter error counter (bits [7:0]) according to the bosch* can 2.0 specification. when it is greater than 255(dec), it is fixed at 255. 0b ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1591 intel ? ep80579 integrated processor 39.6.1.5 offset 00000010h: command - operating modes the can unit can be used in different operating modes. by disabling transmitting data, it is possible to use the can in listen-only mode. this allows for features such as automatic bit rate detection. before starting the can controller, all can controller registers have to be set according to the target application. note: the run/stop bit [00] can not be written from run mode to stop mode while a message is pending in the tx buffer. the stalled packet can be dequeued first using the abort bit in the buffer prior to setting the mode to stop. if the requirement is to retain the tx packet in the buffer, transitioning to listen mode first by setting bit [1] will allow the controller to then transition to stop mode. the packet will then remain in the buffer if the controller is transitioned back to run mode. table 39-10. offset 00000010h: command - operating modes description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000010h 00000013h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000010h 00000013h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :02 rsvd reserved, these bits are always 0 0h ro 01 listen listen mode: ?0? = active ?1? = can listen only: the output is held at ?r? level. the can is only listening 0b rw 00 run_stop run/stop mode: ?0? = sets the can controller into stop mode. read ?0? when stopped. ?1? = sets the can controller into run mode. read ?1? when running 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1592 order number: 320066-003us 39.6.1.6 offset 00000014h: config - can configuration register the can unit must be configured prior to its use. the following registers define the effective can data rate, can data synchronization, and message buffer arbitration. note: additional information on the can data rate settings using time segment1(tseg1), time segment2(tseg2), and the bit rate are given in section 39.4.4, ?can bit timing? on page 1577 . table 39-11. offset 00000014h: config - can configuration register description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000014h 00000017h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000014h 00000017h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved, these bits are always 0 0b ro 30 :16 cfg_bitrate_14_ 0 prescaler (bits[14:0]) for generating the time quantum which defines the tq: ?0?: one time quantum equals 1 clock cycle ?1?: one time quantum equals 2 clock cycles 32767: one time quantum equals 32768 clock cycles 0h rw 15 :13 rsvd reserved. 0h rw 12 cfg_arbiter transmit buffer arbiter ?0?: round robin: txmessage0-1-2-3 etc. ?1?: fixed priority: txmessage0 is highest, txmessage2 is lowest 0b rw 11 :08 cfg_tseg1 time segment 1. length of the first time segment: tseg1 = cfg_tseg1 +1 time segment 1 includes the propagation time. cfg_tseg1 = 0 and cfg_tseg1 =1 are not allowed. 0h rw 7:05 cfg_tseg2 time segment 2. length of the second time segment: tseg2 = cfg_tseg2 +1 time segment 2 includes the propagation time. cfg_tseg1 = 0 and cfg_tseg1 =1 are not allowed. 0h rw 4auto_restart ?0?: after bus off, the can must be started ?by hand?. ?1?: after bus off, the can is restarting automatically after 128 groups of 11 recessive bits 0b rw 03 :02 cfg_sjw synchronization jump width - 1 sjw <= tseg1 and sjw <= tseg2 0h rw 1 sampling_mode can bus bit sampling ?0?: one sampling point is used in the receiver path ?1?: 3 sampling points with majority decision are used 0b rw 0 edge_mode can bus synchronization logic ?0?: edge from ?r? to ?d? is used for synchronization ?1?: both edges are used 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1593 intel ? ep80579 integrated processor 39.6.1.7 offset 00000020h: txmessagecontrol[0-7] - transmit message control and command note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-12. offset 00000020h: txmessagecontrol[0-7] - transmit message control and command (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000020h at 10h 00000023h at 10h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000020h at 10h 00000023h at 10h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rsvd reserved. xh rw 23 wpn_21_16 write protect not. using the wpn flag enables simple retransmission of the same message by only having to set the trx flag without taking care of the special flags. ?0?: bit [21:16] remain unchanged. ?1?: bit [21:16] are modified, default. note: the readback state of this bit is undefined. xh rw 22 rsvd reserved. xh rw 21 rtr remote bit ?0?: this is a standard message ?1?: this is an rtr message xh rw 20 ide extended identifier bit. ?0?: this is a standard format message ?1?: this is an extended format message xh rw 19 :16 dlc data length code. invalid values are transmitted as they are, but only the number of data bytes is limited to eight. 0: message has 0 data byte, data[63:0] is not used 1: message has 1 data byte, data [63:56] is used .... 8: message has 8 data bytes, data [63:0] is used 9-15: message has 8 data bytes xh rw 15 :04 rsvd reserved. xh rw 03 wpn_2 message control: wpn: write protect not ?0?: bit [2] remain unchanged. ?1?: bit [2] is modified, default. note: the readback state of this bit is undefined. xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1594 order number: 320066-003us 02 txintebl tx interrupt enable ?0?: interrupt disabled. ?1?: interrupt enabled, successful message transmission set the txmsg flag in the interrupt controller. xh rw 01 txabort transmit abort request ?0?: idle ?1?: requests removal of a pending message. the message is removed the next time an arbitration loss happened. the flag is cleared when the message was removed or when the message won arbitration. the txreq flag is released at the same time. xh rw 00 txreq transmit request write: ?0?: idle. ?1?: message transmit request. the tx message buffer must not be changed while txreq is ?1?. read: ?0?: txreq completed. ?1?: txreq pending. xh rw table 39-12. offset 00000020h: txmessagecontrol[0-7] - transmit message control and command (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000020h at 10h 00000023h at 10h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000020h at 10h 00000023h at 10h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1595 intel ? ep80579 integrated processor 39.6.1.8 offset 00000024h: txmessageid[0-7] - transmit message id note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-13. offset 00000024h: txmessageid[0-7] - transmit message id description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000024h at 10h 00000027h at 10h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000024h at 10h 00000027h at 10h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :03 id_28_0 identifier (bits [28:0]) xh rw 02 :00 rsvd reserved. xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1596 order number: 320066-003us 39.6.1.9 offset 00000028h: txmessagedatahigh[0-7] - transmit message data high note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-14. offset 00000028h: txmessagedatahigh[0-7] - transmit message data high description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 00000028h at 10h 0000002ah at 10h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 00000028h at 10h 0000002ah at 10h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 datahigh txmessage0 buffer. data [63:32]. byte 1 is data[63:56], byte 2 is data[55:48] etc. xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1597 intel ? ep80579 integrated processor 39.6.1.10 offset 0000002ch: txmessagedatalow[0-7] - transmit message data low note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-15. offset 0000002ch: txmessagedatalow[0-7] - transmit message data low description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 0000002ch at 10h 0000002fh at 10h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 0000002ch at 10h 0000002fh at 10h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 datalow txmessage0 buffer. data [31:0]. xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1598 order number: 320066-003us 39.6.1.11 offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-16. offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control (sheet 1 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000a0h at 20h 000000a3h at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000a0h at 20h 000000a3h at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rsvd reserved. xh rw 23 wpn_21_16 rxmessage control: write protect not high. ?0?: [21:16] remain unchanged ?1?: [21:16] are modified, default. this bit is always zero for readback xh rw 22 rsvd reserved. xh rw 21 rtr remote bit xh rw 20 ide extended identifier bit xh rw 19 :16 dlc data length code. invalid values are shown as received. xh rw 15 :08 rsvd reserved. xh rw 07 wpn_6_3 rxmessage control: write protect low ?0?: [6:3] remain unchanged ?1?: [6:3] are modified, default. this bit is always zero for readback xh rw 06 lf link flag ?0?: this buffer is not linked, or it is the last one of an array ?1?: this buffer is linked with other buffers xh rw 05 rxintebl receive interrupt enable ?0?: interrupt is disabled ?1?: interrupt is enabled xh rw 04 rtrreply automatic message reply to rtr messages ?0?: automatic rtr disabled ?1?: automatic rtr enabled xh rw 03 be buffer enable ?0?: buffer is disabled ?1?: buffer is enabled xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1599 intel ? ep80579 integrated processor 02 rtrabort rtr abort request ?0?: idle ?1?: request removal of a pending rtr message reply. the flag is cleared when the message was removed or when the message won arbitration. the txreq flag is released at the same time xh rw 01 rtrreply_pendi ng reply pending ?0?: no rtr reply request pending ?1?: rtr reply request pending xh rw 00 msgav message available read: ?0?: no new message available 1?: new message available write: ?0?: idle ?1?: acknowledges receipt of new message. acknowledging a message clears the msgav flag. before acknowledging receipt of a new message, the message content must be copied into system memory. acknowledging a message clears the msgav flag. xh rw table 39-16. offset 000000a0h: rxmessagecontrol[0-15] - receive message command and control (sheet 2 of 2) description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000a0h at 20h 000000a3h at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000a0h at 20h 000000a3h at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1600 order number: 320066-003us 39.6.1.12 offset 000000a4h: rxmessageid[0-15] - receive message id note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. 39.6.1.13 offset 000000a8h: rxmessagedatahigh[0-15] - receive message data high note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-17. offset 000000a4h: rxmessageid[0-15] - receive message id description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000a4h at 20h 000000a7h at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000a4h at 20h 000000a7h at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :03 rx_id_28_0 identifier (bits [28:0]) xh rw 02 :00 rsvd reserved xh rw table 39-18. offset 000000a8h: rxmessagedata high[0-15] - receive message data high description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000a8h at 20h 000000abh at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000a8h at 20h 000000abh at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 rxdatahigh rxmessage0 buffer. data [63:32]. xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1601 intel ? ep80579 integrated processor 39.6.1.14 offset 000000ach: rxmessagedatalow[0-15] - receive message data low note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. 39.6.1.15 offset 000000b0h: rxmessageamr[0-15] - receive message amr note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-19. offset 000000ach: rxmessagedatalow[0-15] - receive message data low description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000ach at 20h 000000afh at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000ach at 20h 000000afh at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :00 rxdatalow rxmessage0 buffer. data [31:0]. xh rw table 39-20. offset 000000b0h: rxmessageamr[0-15] - receive message amr description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000b0h at 20h 000000b3h at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000b0h at 20h 000000b3h at 20h size: 32 bit default: xxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :03 identifier identifier xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1602 order number: 320066-003us 39.6.1.16 offset 000000b4h: rxmessageacr[0-15] - receive message acr note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. 02 ide extended identifier bit xh rw 01 rtr remote bit xh rw 00 rsvd reserved xh rw table 39-20. offset 000000b0h: rxmessageamr[0-15] - receive message amr description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000b0h at 20h 000000b3h at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000b0h at 20h 000000b3h at 20h size: 32 bit default: xxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access table 39-21. offset 000000b4h: rxmessageacr[0-15] - receive message acr description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000b4h at 20h 000000b7h at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000b4h at 20h 000000b7h at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :03 identifier identifier xh rw 02 ide extended identifier bit xh rw 01 rtr remote bit xh rw 00 rsvd reserved xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1603 intel ? ep80579 integrated processor 39.6.1.17 offset 000000b8h: rxmessageamr_data[0-15] - receive message amr data note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. 39.6.1.18 offset 000000bch: rxmessageacr_data[0-15] - receive message acr data note: these registers are implemented in the sram which does not have the capability to mask writes to reserved bits. therefore, reserved bits in this csr will be rw. software should treat these bits as reserved and not change the reset value of these bits. note: these registers are implemented in sram which is not initialized at power-up or upon reset. so before enabling the can, software needs to update these csr?s with the reset values. table 39-22. offset 000000b8h: rxmessageamr_d ata[0-15] - receive message amr data description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000b8h at 20h 000000bbh at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000b8h at 20h 000000bbh at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 rsvd reserved xh rw 15 :00 data_63_48 data (bits [63:48]) xh rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1604 order number: 320066-003us table 39-23. offset 000000bch: rxmessageac r_data[0-15] - receive message acr data description: view: pci 1 bar: csrbar bus:device:function: m:4:0 offset start: offset end: 000000bch at 20h 000000bfh at 20h view: pci 2 bar: csrbar bus:device:function: m:5:0 offset start: offset end: 000000bch at 20h 000000bfh at 20h size: 32 bit default: xxxxxxxxh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 rsvd reserved. xh rw 15 :00 data_63_48 data (bits [63:48]) xh rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1605 intel ? ep80579 integrated processor 40.0 ssp serial port 40.1 overview the ssp (synchronous serial port) is a full-duplex synchronous serial interface. the ssp can connect to a variety of external analog-to-digital (a/d) converters, audio and telecom codecs, and many other devices that use serial protocols for transferring data. it supports national microwire*, texas instruments* synchronous serial protocol (ssp), and motorola* serial peripheral interface (spi) protocol. the ssp operates in master mode (the attached peripheral functions as a slave), and supports serial bit rates from 7.2 kbps to 1.84 mbps. serial data formats may range from 4 to 16 bits in length. two on-chip re gister blocks function as independent fifos for data, one for each direction. the buffers are 16 entries deep x 16 bits wide. this section describes the signal definitions and operations of the ssp functional block. 40.2 feature list a list of features is presented below: ? supports national microwire format. ? supports texas instruments synchronous serial protocol (ssp). ? supports motorola serial peripheral interface (spi). ? supports serial data rates from 7.2 kbps to 1.84 mbps. ? provides 32 byte fifos for both receive and transmit data. 40.3 theory of operation 40.3.1 endianness the ssp uses only bits 15:0 of the internal data bus, the host must format the data into the two least significant bytes of the 32 bit internal bus transfer. the two high order bytes are ignored. the ssp unit is accessed only using dword accesses. 40.3.2 error handling no error handling is defined for this unit beyond the functional receiver overrun status bit (ror) (see section 40.4.3.7 ) in the ssp status register (see section 40.4.3 ). this error condition causes the unit?s interrupt to be asserted and is non-maskable.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1606 order number: 320066-003us 40.4 register summary there are five registers in the ssp block: two control, one data, one status register, and one test register. ? control registers are used to program th e baud rate, data length, frame format, data transfer mechanism, and port enabling. in addition, they permit setting the fifo ?fullness? threshold that will trigger an interrupt. ? the data register is mapped as one 32-bit location, which physically points to either of two 32-bit registers. one register is for writes, and transfers data to the transmit fifo; the other is for reads, and takes data from the receive fifo. a write cycle, will load successive words into the ssp write register, from the lower half 2 bytes of a 32-bit word to the transmit fifo. a read cycle, will similarly take data from the ssp read register, and the receive fifo will reload it with available data bits it has stored. the fifos are independent buffers that allow full duplex operation. ? the status register signals the state of the fifo buffers: whether the programmable threshold has been passed (transmit/receive buffer service request), and a value showing the actual ?fullness? of the fifo. there are flag bits to indicate when the ssp is actively transmitting data, when the transmit buffer is not full, and when the receive buffer is not empty. error bits signal overrun errors. the ssp registers materialize in the pci space. ta b l e 4 0 - 1 summarizes the ssp materialization from the pci perspective. table 40-1. bus m, device 6, function 0: summary of ssp csrs offset start offset end register id - description default value 00h 03h ?offset 00h: sscr0 - ssp control register 0 details? on page 1607 00000000h 04h 07h ?offset 04h: sscr1 - ssp control register 1 details? on page 1610 00000000h 08h 0bh ?offset 08h: sssr - ssp status register details? on page 1614 0000f004h 0ch 0fh ?offset 0ch: ssitr - ssp interrupt test register details? on page 1617 00000000 10h 13h ?offset 10h: ssdr - ssp data register details? on page 1618 00000000h
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1607 intel ? ep80579 integrated processor 40.4.1 ssp control register 0 40.4.1.1 offset 00h: sscr0 - ssp control register 0 details the ssp control register 0 (sscr0) contains fi ve different bit fields that control various functions within the ssp. register name: sscr0 block base address: n/a offset address 00 reset value 00000000 register description: ssc control register 0 access: (see below.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved scr sse ecs frf srs table 40-2. offset 00h: sscr0 - ssp control register 0 details (sheet 1 of 2) description: ssp control register 0 view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 00 h 03h size: 32 bit default: 00000000 h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved 0h rv 15 :08 scr serial clock rate selection value (0 to 255) used to generate transmission rate of ssp. bit rate = clk/ (2 x (scr + 1)) where scr is a decimal integer clk may be the internally provided clock of 3.7 mhz (2.777mhz for low-power sku) or the externally provided clock. 0h rw 7sse synchronous serial port enable bit. 0 = ssp operation disabled 1 = ssp operation enabled 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1608 order number: 320066-003us 6ecs external clock select bit. 0 = on-chip clock used to produce the ssp?s serial clock ( ssp_sclk ). 1 = ssp_extclk is used to create the ssp?s ssp_sclk . 0b rw 05 :04 frf this field specifies the frame format. 00 - motorola* serial peripheral interface (spi) 01 - texas instruments* synchronous serial protocol (ssp) 10 - national microwire* 11 - reserved, undefined operation 0h rw 03 :00 dss this field specifies the data size selection. 0000 - reserved, undefined operation 0001 - reserved, undefined operation 0010 - reserved, undefined operation 0011 - 4-bit data 0100 - 5-bit data 0101 - 6-bit data 0110 - 7-bit data 0111 - 8-bit data 1000 - 9-bit data 1001 - 10-bit data 1010 - 11-bit data 1011 - 12-bit data 1100 - 13-bit data 1101 - 14-bit data 1110 - 15-bit data 1111 - 16-bit data 0h rw table 40-2. offset 00h: sscr0 - ssp control register 0 details (sheet 2 of 2) description: ssp control register 0 view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 00 h 03h size: 32 bit default: 00000000 h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1609 intel ? ep80579 integrated processor 40.4.1.2 data size select (dss) the 4-bit data size select (dss) field is used to select the size of the data transmitted and received by the ssp. data can be 4 to 16 bits in length. when data is programmed to be less than 16 bits, received data is automatically right-justified and the upper bits in the receive fifo are zero-filled by receive logic. transmit data should not be left- justified by the user before being placed in the transmit fifo; transmit logic in the ssp will automatically left-justify the data sample according to the value of dss before the sample is transmitted on ssp_txd . although it is possible to program data sizes of 1, 2, and 3 bits, these sizes are reserved and produce unpredictable results in the ssp. when national microwire frame format is selected, this bit field selects the size of the received data. note that the size of the transmitted data is always 8 bits in this mode. 40.4.1.3 frame format (frf) the 2-bit frame format (frf) field is used to select which frame format to use: motorola spi (frf=00), texas instruments synchronous serial (frf=01), or national microwire (frf=10). note that frf=11 is reserved and the ssp will produce unpredictable results if this value is used. 40.4.1.4 external clock select (ecs) the external clock select (ecs) bit selects whether the on-chip 3.6864-mhz (2.777mhz for low-power sku) clock is used by the ssp or if an off-chip clock is supplied via ssp_extclk . when ecs=0, the ssp uses the on-chip 3.6864-mhz clock (2.777mhz for low-power sku) to produce a range of serial transmission rates. when ecs=1, the ssp uses ssp_extclk to input a clock supplied from off-chip. the frequency of the off-chip clock can be any value up to 3.6864 mhz (2.777mhz for low-power sku). this off-chip clock is useful when a serial transmission rate, which is not an even multiple of the internal clock, is required for synchronization with the target off-chip slave device. 40.4.1.5 synchronous serial port enable (sse) the ssp enable (sse) bit is used to enable and disable all ssp operations. when sse=0, the ssp is disabled; when sse=1, it is enabled. when the ssp is disabled, all of its clocks are powered down to minimize power consumption. note that the sse is the only control bit within the ssp that is reset to a known state. it is cleared to zero to ensure the ssp is disabled following a reset. when the sse bit is cleared during active operation, the ssp is disabled immediately, causing the current frame being transmitted to be terminated. clearing sse resets the ssp?s fifos. however the ssp?s control and status registers are not reset. the user must ensure these registers are properly reconfigured before re-enabling the ssp. 40.4.1.6 serial clock rate (scr) the 8-bit serial clock rate (scr) bit-field is used to select the baud, or bit rate, of the ssp. the serial clock generator can be configured to use the internally provided 3.6864- mhz (2.777mhz for low-power sku) clock produced by the on-chip pll or the externally provided clock. the source clock is divided by a fixed value of 2, and then divided by the programmable scr value (0 to 255) plus 1 to generate the serial clock ( ssp_sclk ). when configured to use the internal clock, a total of 256 different bit rates can be selected. the resultant clock is driven on the ssp_sclk pin and is used by the ssp?s transmit logic to drive data on the ssp_txd pin, and to latch data on the ssp_rxd pin. depending on the frame format selected, each transmitted bit is driven on either the rising or falling edge of ssp_sclk , and is sampled on the opposite clock edge.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1610 order number: 320066-003us note that the sse bit is the only control bit that is reset to a known state, to ensure the ssp is disabled following a reset. the reset state of all other control bits is unknown and must be initialized before enabling the ssp. 40.4.2 ssp control register 1 40.4.2.1 offset 04h: sscr1 - ssp control register 1 details the ssp control register 1 (sscr1) contains nine bit fields that control various ssp functions. register name: sscr1 block base address: n/a offset address 0x04 reset value 00000000 register description: ssc control register 1 access: (see below.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved strf efwr rft tft mwds sph spo lbm tie rie table 40-3. offset 04h: sscr1 - ssp control register 1 details (sheet 1 of 2) description: view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 04 h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved 0h rv 15 strf select fifo for efwr: 0 = transmit fifo is selected for ?enable fifo write/ read? 1 = receive fifo is selected for ?enable fifo write/read? 0b rw 14 efwr enable fifo write/read: 0 = fifo write/read function is disabled 1 = fifo write/read function is enabled 0b rw 13 :10 rft receive fifo threshold. sets threshold level at which receive fifo asserts interrupt. this level should be set to the threshold value minus 1. 0h rw 09 :06 tft transmit fifo threshold. sets threshold level at which transmit fifo asserts interrupt. this level should be set to the threshold value minus 1. 0h rw 05 mwds national microwire* data size 0 = 8 bit microwire format 1 = 16 bits microwire format 0b rw 04 sph motorola* spi ssp_sclk phase setting: 0 = ssp_sclk is inactive one full cycle at the start of a frame and 1/2 cycle at the end of a frame. 1 = ssp_sclk is inactive 1/2 cycle at the start of a frame and one full cycle at the end of a frame. 0b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1611 intel ? ep80579 integrated processor 40.4.2.2 receive fifo interrupt enable (rie) the receive fifo interrupt enable (rie) bit is used to mask or enable the receive fifo service request interrupt. when rie=0, the interrupt is masked and the state of the receive fifo service request (rfs) bit within the ssp status register is ignored by the interrupt controller. when rie=1, the interrupt is enabled and whenever rfs is set to one, an interrupt request is made to the interrupt controller. note that programming rie=0 does not affect the current state of rfs or the receive fifo logic?s ability to set and clear rfs, it only blocks the generation of the interrupt request. 40.4.2.3 transmit fifo interrupt enable (tie) the transmit fifo interrupt enable (tie) bit is used to mask or enable the transmit fifo service request interrupt. when tie=0, the interrupt is masked and the state of the transmit fifo service request (tfs) bit within the ssp status register is ignored by the interrupt controller. when tie=1, the interrupt is enabled, and whenever tfs is set to one an interrupt request is made to the interrupt controller. note that programming tie=0 does not affect the current state of tfs or the transmit fifo logic?s ability to set and clear tfs, it only blocks the generation of the interrupt request. 40.4.2.4 loop back mode (lbm) the loop back mode (lbm) bit is used to enable and disable the ability of the ssp transmit and receive logic to communicate. when lbm=0, the ssp operates normally. the transmit and receive data paths are independent and communicate via their respective pins. when lbm=1, the output of the transmit serial shifter is directly connected to the input of the receive serial shifter internally. loop back mode is only valid for ssp and spi modes, microwire mode does not support loop back mode testing because the bus protocol is half-duplex. note: while in loopback mode, the data will continue to be driven on the transmit pins. 03 spo motorola spi ssp_sclk polarity setting: 0 = the inactive or idle state of ssp_sclk is low. 1 = the inactive or idle state of ssp_sclk is high. 0b rw 02 lbm loop bank mode enable bit. 0 = normal serial port operation enabled 1 = output of transmit serial shifter connected to input of receive serial shifter, internally 0b rw 01 tie transmit fifo interrupt enable 0 = transmit fifo level interrupt is disabled 1 = transmit fifo level interrupt is enabled 0b rw 00 rie receive fifo interrupt enable 0 = receive fifo level interrupt is disabled 1 = receive fifo level interrupt is enabled 0b rw table 40-3. offset 04h: sscr1 - ssp control register 1 details (sheet 2 of 2) description: view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 04 h 07h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1612 order number: 320066-003us 40.4.2.5 serial clock polarity (spo) the serial clock ( ssp_sclk ) polarity bit (spo) selects the polarity of the inactive state of the ssp_sclk pin when motorola spi format is selected (frf=00). for spo=0, the ssp_sclk is held low in the inactive or idle state when the ssp is not transmitting/ receiving data. for spo=1, the ssp_sclk is held high during the inactive/idle state. the programmed setting of the spo alone does not determine which ssp_sclk edge is used to transmit or receive data. the spo setting in combination with the ssp_sclk phase bit (sph) determines this. note that the spo is ignored for all data frame formats except for the motorola spi format (frf=00). 40.4.2.6 serial clock phase (sph) the serial clock ( ssp_sclk ) phase bit (sph) determines the phase relationship between the ssp_sclk and the serial frame ( ssp_sfrm ) pins when the motorola spi format is selected (frf=00). when sph=0, ssp_sclk remains in its inactive/idle state (as determined by the spo setting) for one full cycle after ssp_sfrm is asserted low at the beginning of a frame. ssp_sclk continues to transition for the rest of the frame and is then held in its inactive state for one-half of an ssp_sclk period before ssp_sfrm is de-asserted high at the end of the frame. when sph=1, ssp_sclk remains in its inactive/idle state (as determined by the spo setting) for one-half cycle after ssp_sfrm is asserted low at the beginning of a frame. ssp_sclk continues to transition for the rest of the frame and is then held in its inactive state for one full ssp_sclk period before ssp_sfrm is de-asserted high at the end of the frame. the combination of the spo and sph settings determines when ssp_sclk is active during the assertion of ssp_sfrm and which ssp_sclk edge is used to transmit and receive data on the ssp_txd and ssp_rxd pins. when spo and sph are programmed to the same value (both 0 or both 1), transmit data is driven on the falling edge of ssp_sclk and receive data is latched on the rising edge of ssp_sclk . when spo and sph are programmed to opposite values (one 0 and the other 1), transmit date is driven on the rising edge of ssp_sclk and receive data is latched on the falling edge of ssp_sclk . note that the sph is ignored for all data frame formats except for the motorola spi format (frf=00). ta b l e 4 0 - 4 shows the pin timing for all four programming combinations of spo and sph. note that spo inverts the polarity of the ssp_sclk signal and sph determines the phase relationship between ssp_sclk and ssp_sfrm , shifting the ssp_sclk signal one-half phase to the left or right during the assertion of ssp_sfrm .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1613 intel ? ep80579 integrated processor 40.4.2.7 national microwire* data size (mwds) this bit sets the size of data in the microwire format. if ?1?, a 16 bits data size is chosen for the microwire format, otherwise, an 8-bit data size. 40.4.2.8 transmit fifo interrupt threshold (tft) this 4-bit value sets the level at or below which the fifo controller triggers a service interrupt. 40.4.2.9 receive fifo interrupt threshold (rft) this 4-bit value sets the level at or above which the fifo controller triggers a service interrupt. 40.4.2.10 enable fifo write/read function (efwr) this bit enables a special functional mode for the ssp. when efwr = 0, the ssp operates in the normal mode described in this document. when efwr = 1, the ssp enters a mode in which whenever the cpu reads or writes to the ssp data register, it actually reads and writes exclusively to either the transmit fifo or the receive fifo depending on the programmed state of the select fifo for efwr (strf) bit. in this special mode, data will not be transmitted on the txd pin and data input on the rxd table 40-4. motorola * spi frame formats for spo and sph programming ssp_sc lk spo=0 ... ssp_sc lk spo=1 ... ssp_sf rm ... ssp_tx d4 bit bit ... bit<1> bit<0> ssp_rx d4 bit bit ... bit<1> bit<0> msb 4 to 16 bits lsb sph = 0 ssp_sc lk spo=0 ... ssp_sc lk spo=1 ... ssp_sf rm ... ssp_tx d4 bit bit ... bit<1> bit<0> ssp_rx d4 bit bit ... bit<1> bit<0> msb 4 to 16 bits lsb sph = 1
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1614 order number: 320066-003us pin will not be stored. this mode can be used to test, through software, whether or not the transmit fifo or the receive fifo operates properly as a first-in-first-out memory stack. note: when this mode is enabled, a write followed immediately by a read to the rx or tx fifos may not return the correct read data. since this is a test mode, a delay should be inserted between the write and read transactions so that the data is guaranteed to be read back correctly. 40.4.2.11 select fifo for enable fifo write/read (strf) this bit selects whether the transmit or receive fifo is enabled for write/read. 40.4.3 ssp status register 40.4.3.1 offset 08h: sssr - ssp status register details the ssp status register (sssr) contains bits that signal overrun errors as well as the transmit and receive fifo service requests. each of these hardware-detected events signal an interrupt request to the interrupt controller. the status register also contains flags that indicate when the ssp is actively transmitting characters, when the transmit fifo is not full, and when the receive fifo is not empty (no interrupt generated). bits that cause an interrupt will signal the request as long as the bit is set. once the bit is cleared, the interrupt is cleared. read/write bits are called status bits, read-only bits are called flags. status bits are referred to as ?sticky? (once set by hardware, must be cleared by software). writing a 1 to a sticky status bit clears it, writing a 0 has no effect. read-only flags are set and cleared by hardware; writes have no effect. additionally some bits that cause interrupts have corresponding mask bits in the control registers and are indicated in the section headings that follow. register name: sssr block base address: n/a offset address 08h reset value 0000f024 register description: ssp status register access: (see below.) 313029282726252423222120191817161514131211109876543210 reserved rfl tfl ror rfs tfs bsy rne tnf rsvd. table 40-5. offset 08h: sssr - ssp status register details (sheet 1 of 2) description: view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 08 h 0bh size: 32 bit default: 0000f004h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved 0h rv 15 :12 rfl receive fifo level: number of entries in receive fifo fh ro 11 :08 tfl transmit fifo level: number of entries in transmit fifo 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1615 intel ? ep80579 integrated processor 40.4.3.2 transmit fifo not full flag (tnf) (read-only, non-interruptible) the transmit fifo not full flag (tnf) is a read-only bit that is set whenever the transmit fifo contains one or more entries that do not contain valid data. tnf is cleared when the fifo is completely full. this bit can be polled when using programmed i/o to fill the transmit fifo over its half-way mark. this bit does not request an interrupt. 40.4.3.3 receive fifo not empty flag (rne) (read-only, non-interruptible) the receive fifo not empty flag (rne) is a read-only bit that is set whenever the receive fifo contains one or more entries of valid data and is cleared when it no longer contains any valid data. this bit can be polled when using programmed i/o to remove remaining bytes of data from the receive fifo since cpu interrupt requests are only made when the receive fifo threshold has been met or exceeded. this bit does not request an interrupt. 40.4.3.4 ssp busy flag (bsy) (read-only, non-interruptible) the ssp busy (bsy) flag is a read-only bit that is set when the ssp is actively transmitting and/or receiving data and is cleared when the ssp is idle or disabled (sse=0). this bit does not request an interrupt. 07 ror receive fifo overrun: 0 = receive fifo has not experienced an overrun 1 = attempted data write to full receive fifo, request interrupt y0b rwc 06 rfs receive fifo service request: 0 = receive fifo level is below rft threshold, or ssp disabled. 1 = receive fifo level is at or above rfl threshold, request interrupt 0b ro 05 tfs transmit fifo service request: 0 - transmit fifo level exceeds tft threshold, or ssp disabled 1 - transmit fifo level is at or below tfl threshold, request interrupt 0b ro 04 bsy ssp is busy 0 = ssp is idle or disabled 1 = ssp currently transmitting or receiving a frame 0b ro 03 rne receive fifo not empty. 0 - receive fifo is empty 1 - receive fifo is not empty 0b ro 02 tnf transmit fifo not full. 0 = transmit fifo is full 1 = transmit fifo is not full 1b ro 01 :00 reserved reserved 0h rv table 40-5. offset 08h: sssr - ssp status register details (sheet 2 of 2) description: view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 08 h 0bh size: 32 bit default: 0000f004h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1616 order number: 320066-003us 40.4.3.5 transmit fifo service request flag (tfs) (read-only, maskable interrupt) the transmit fifo service request flag (tfs) is a read-only bit that is set when the transmit fifo is nearly empty and requires service to prevent an underrun. tfs is set any time the transmit fifo has the same or fewer entries of valid data than indicated by the transmit fifo threshold and it is cleared when it has more entries of valid data than the threshold value. when the tfs bit is set, an interrupt request is made unless the transmit fifo interrupt request enable (tie) bit is cleared. after the cpu fills the fifo such that it exceeds the threshold, the tfs flag (and the service request and/or interrupt) is automatically cleared. 40.4.3.6 receive fifo service request flag (rfs) (read-only, maskable interrupt) the receive fifo service request flag (rfs) is a read-only bit that is set when the receive fifo is nearly filled and requires service to prevent an overrun. rfs is set any time the receive fifo has the same or more entries of valid data than indicated by the receive fifo threshold and it is cleared when it has fewer entries than the threshold value. when the rfs bit is set, an interrupt request is made unless the receive fifo interrupt request enable (rie) bit is cleared. after the cpu reads the fifo such that it has fewer entries than the rft value, the rfs flag (and the service request and/or interrupt) is automatically cleared. 40.4.3.7 receiver overrun status (ror) (read/write, non-maskable interrupt) the receiver overrun status bit (ror) is a read/write bit that is set when the receive logic attempts to place data into the receive fifo after it has been completely filled. each time a new piece of data is received, the set signal to the ror bit is asserted and the newly received data is discarded. this process is repeated for each new piece of data received until at least one empty fifo entry exists. when the ror bit is set, an interrupt request is made. writing 1 to this bit resets ror status and its interrupt request. 40.4.3.8 transmit fifo level this 4-bit value shows how many valid entries are currently in the transmit fifo. 40.4.3.9 receive fifo level this 4-bit value shows how many valid entries are currently in the receive fifo. the following bit table shows the bit locations corresponding to the status and flag bits within the ssp status register. all bits are read-only except ror, which is read/write. writes to tnf, rne, bsy, tfs, and rfs have no effect. the reset state of ror is unknown and must be initialized before enabling the ssp. note that writes to reserved bits are ignored and reads to those bits return zeros. 40.4.4 ssp interrupt test register 40.4.4.1 offset 0ch: ssitr - ssp interrupt test register details writing ?1? to the corresponding bit position to the ssp interrupt test register generates an interrupt strobe signal to the interrupt controller for test purposes. note: ssitr functionality is available even when the ssp is disabled.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1617 intel ? ep80579 integrated processor 40.4.5 ssp data register 40.4.5.1 offset 10h: ssdr - ssp data register details the ssp data register (ssdr) is a block of 32-bit locations that can be accessed by 32- bit data transfers. transfers can be from 1 to 8 words. the ssdr represents two physical registers: the first is temporary storage for data on its way out through the transmit fifo, the other is temporary storage for data coming in through the receive fifo. as the register is accessed by the system, fifo control logic transfers data automatically between register and fifo as fast as the system moves it. data in the fifo shifts up or down to accommodate the new word (unless it?s an attempted write to a full transmit fifo). status bits are available to show the system whether either buffer is full, above/below a programmable threshold, or empty. for outbound data transfers (write from system to ssp peripheral), the register may be loaded (written) by the system processor anytime the register is empty. when a data size of less than 16-bits is selected, the user should not left-justify data written to the transmit fifo. transmit logic left-justifies the data and ignores any unused bits. received data less than 16-bits is automatically right-justified in the receive buffer. when the ssp is programmed for national microwire frame format, the default size for transmit data is 8-bits (the most significant byte is ignored), the receive data size is controlled by the programmer using the dss field in sscr0. the following table shows the location of the ssp data register. note that both fifos are cleared when the block is reset or by writing a zero to sse (ssp disabled). register name: ssitr block base address: n/a offset address 0x0c reset value 00000000 register description: ssp interrupt test register access: (see below.) 313029282726252423222120191817161514131211109876543210 reserved tror trfs ttfs reserved table 40-6. offset 0ch: ssitr - ssp interrupt test register details description: view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 0ch 0fh size: 32 bit default: 00000000 power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :08 reserved reserved 0h rv 07 tror test receive fifo overrun (ror) 0b rw 06 trfs test receive fifo service request (rfs) 0b rw 0 5 tt fs tes t tra n sm i t f if o s er v i ce r e qu e st ( t fs ) 0 b r w 04 :00 reserved reserved 0h rv
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1618 order number: 320066-003us register name: ssdr block base address: n/a offset address 0x10 reset value 00000000 register description: ssp data register access: (see below.) 313029282726252423222120191817161514131211109876543210 reserved data table 40-7. offset 10h: ssdr - ssp data register details description: view: pci bar: csrbar bus:device:function: m:6:0 offset start: offset end: 10 h 13h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :16 reserved reserved 0h rv 15 :00 data data (low word): when written, the data will be written to the transmit fifo. when read, data from the receive fifo is returned. 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1619 intel ? ep80579 integrated processor 41.0 ieee 1588 time synchronization hardware assist 41.1 overview this document describes the hardware-assist logic developed to achieve time synchronization on ethernet and can. in a distributed control system containing multiple clocks, individual clocks tend to drift apart. some kind of correction mechanism is necessary to synchronize the individual clocks to maintain global time, which is accurate to some requisite clock resolution. for this purpose, you can use the ieee 1588 standard, which defines a precision clock synchronization protocol for networked measurement and control systems. the ieee standard defines several messages that you can use to exchange timing information. the hardware assist logic, required to achieve precision clock synchronization using the ieee 1588 standard, is left to the implementation. the time synchronization logic monitors the internal mii and gmii signals on the gigabit ethernet controller. only gigabit port 0 and port 1 are supported. the interrupt signals from can will also be monitored to allow can traffic to be time-stamped as well. an interrupt signal to the host processor is generated by the 1588 time sync block when any of the following conditions occur and are enabled: ?target time expiration ? auxiliary target time expiration ? auxiliary master mode snapshot is taken ? auxiliary slave mode snapshot is taken ? pulse per second signal assertion the system time, target time and aux target time registers are all 64 bits wide. when the system time is greater than or equal to the target time, the target time expiration condition will set. an interrupt enable mask must be set to allow the target time interrupt to pass to the core.the aux target time register works the same as the target time register. 41.2 feature list a list of features is presented below: ? supports ieee1588-2008. ? supports user-defined messages. ? supports detection of ieee 1588 messages for both receive and transmit directions. ? supports ethernet mii and gmii. ? supports can 2.0b. ? provides external signals to signify if a snapshot was taken. ? provides external control over taking snapshots.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1620 order number: 320066-003us ? supports 15 ns resolution on the 1066 mhz and 1200 mhz skus. ? supports 20 ns resolution on the 600mhz skus. ? provides a pulse per second output. 41.2.1 signal descriptions ? auxiliary slave mode snapshot ? an active high level on this input causes a snapshot of system time to be captured in the asms register. refer to ?auxiliary snapshots? on page 4765 for usage and restrictions. ? auxiliary master mode snapshot ? an active high level on this input causes a snapshot of system time to be captured in the amms register. refer to ?auxiliary snapshots? on page 4765 for usage and restrictions. ? test mode data ? this signal will reflect bits of the internal system timer depending on the setting of internal control bits in the ts_test register. ? pulse per second output - this signal is asserted high when a match occurs between the compare register and lower 32 bits of system time. clearing of this signal is under firmware control. the register and pin can be used to create a pulse per second event. ? snapshot taken outputs ? these 2 signals will each pulse high for eight (8) pclks whenever a timestamp has been taken on the selected channel. (either tx or rx). the channel that is monitored is determined by the control bits in the ts_test register. 41.3 functional block diagram a programming model is shown in figure 41-1 , showing registers and interconnections. note: if the functional block is the master, the xmit snapshot holds the ?sync? message time and the recv snapshot holds the delay? message time. if the unit is the slave, the xmit snapshot holds the ?delay? message time and the recv snapshot holds the ?sync? message time. note: ?take snapshot? = synch, edge detect, and lock, until reset by writing a ?1? to the corresponding bit in the event register.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1621 intel ? ep80579 integrated processor figure 41-1. programming model event - 32 bit system time clock - 64bit (low word always read/written 1st) addend - 32 bit (frequency scaling value) accumulator - 32 bit + = carry increment target time - 64bit auxiliary master mode snapshot - 64bit auxiliary slave mode snapshot - 64bit > = = ethernet xmit snapshot - 64bit sync/delay message detect ethernet mii / gmii system bus control/status - 32 bit ethernet recv snapshot - 64bit recv message source uuid ? 48bit sequence id ? 16bit take snapshot 2 locked locked system time clock is > or = target time interrupt to host processor, if enabled in control/store channel event - 32 bit channel control - 32 bit repeat for each ethernet channel repeat for each can channel can snapshot - 64bit can message detect can channel status - 32 bit can take snapshot 2 take snapshot 2 take snapshot 2 take snapshot 2 asmssig ammssig
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1622 order number: 320066-003us 41.4 usage model 41.4.1 channel mapping ten channels are supported which are mapped to the ethernet and can interfaces as shown in the table below: 41.5 functional description 41.5.1 ieee 1588 overview a simplified view of an example 1588 network topology is shown in figure 41-2, ?example network topology? on page 1623 . each device in an ieee 1588 enabled network may have one or more ports each of which is defined to be a master or a slave port. each slave synchronizes it?s internal clock to that of the master. each master- enabled port may also act as a slave. the specific hierarchy of the network is determined dynamically. there are five basic types of precision time protocol (ptp) devices: ? ordinary clock. ? boundary clock. ? end-to-end transparent clock. ? peer-to-peer transparent clock. ? management node. an ordinary clock communicates with the network via a single physical port. this interface is used to send and receive ptp messages, which are time stamped based on the value of the local clock. the ordinary clock can be the grandmaster clock in a system or it can be a slave clock in the master-slave hierarchy. the boundary clock typically has several physical ports. each port of a boundary clock is similar to the port of an ordinary clock, but the local clock is now common to all the ports. each port of the boundary clock terminates all messages related to synchronization and establishing the master-slave hierarchy. table 41-1. channel mapping to interfaces channel interface being monitored notes ethernet channel 0 n/a reserved for future use ethernet channel 1 n/a reserved for future use ethernet channel 2 n/a reserved for future use ethernet channel 3 gbe 0 gmii/mii both gmii and mii modes supported ethernet channel 4 gbe 1 gmii/mii both gmii and mii modes supported ethernet channel 5 n/a reserved for future use ethernet channel 6 n/a reserved for future use ethernet channel 7 n/a reserved for future use can channel 0 can 0 supports simple timestamping of packets can channel 1 can 1 supports simple timestamping of packets
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1623 intel ? ep80579 integrated processor the end-to-end transparent clock forwards all messages just as a normal switch, router or repeater. however for ptp-event messages, the time the message takes to traverse the switch is measured and appended to the forwarded event messages. the peer-to-peer transparent clock is similar to the end-to-end transparent clock however, it also measures peer-to-peer link delays in addition to the internal message traversal time. a management node is a ptp device that is physically connected to the network and provides an user interface to the ptp mana gement messages. it will not be discussed further here the operation of a ptp enabled network is divided into two stages, initialization and time synchronization. 41.5.1.1 initialization at the initialization stage every master enabled node starts by sending sync packets that include the clock parameters of its clock. these parameters include the source of the clock, the accuracy of the clock, it?s variance, etc. upon reception of a sync packet, a node compares the received clock parameters to its own and if the received parameters are better, then this node moves to slave state and stops sending sync packets. when in slave state the node continuously compares the incoming packet to its currently chosen master and if the new cl ock parameters are better then the master selection is transferred to this master clock. eventually the best master clock is chosen. every node has a defined time-out interval in which if no sync packet was received from its chosen master clock it moves back to master state and starts sending sync packets until a new best master clock (bmc) is chosen. 41.5.1.2 time synchronization the time synchronization stage is different to master and slave nodes. if a node is at master state it should periodically send a sync packet which is time stamped by hardware on the tx path (as close as possible to the phy). after the sync packet is sent, a follow_up packet is sent which includes the value of the timestamp captured from the sync packet. in addition the master should timestamp delay_req packets on its rx path and return to the slave that sent it the timestamp value using a delay_response packet. a node in slave state should timestamp every incoming sync packet and if it came from its selected master keep this value for time offset calculation. in addition it should periodically send delay_req packets in order to figure 41-2. example network topology
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1624 order number: 320066-003us calculate the path delay from its master. every sent delay_req packet sent by the slave is time stamped and kept. with the value received from the master with delay_response packet the slave can now calculate the path delay from the master to the slave. the implementation of this protocol is typically distributed between hardware and software. the hw responsibilities are: ? identify the packets that require time stamping. ? time stamp the packets on both rx and tx paths. ? store the time stamp value for sw. ? keep the system time in hw and give a time adjustment service to the sw. ? maintain auxiliary features related to the system time. the sw responsibilities are: ? bmc protocol execution which means defining the node state (master or slave) and selection of the master clock if in slave state. ? read time stamps from hw and generate ptp packets. ? calculate the time offset and adjust the system time using hw mechanism for that. ? enable configuration and usage of the auxiliary features. 41.5.1.2.1 protocol for ordinary and boundary clocks the synchronization protocol flow and the offset calculation for an ordinary or boundary clock model are described in figure 41-3 .
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1625 intel ? ep80579 integrated processor figure 41-3. clock synchronization s y n c f o l l o w _ u p ( t 1 ) d e l a y _ r e q d e l a y _ r e s p o n s e ( t 4 ) master slave t1 t2 t3 t4 timestamp timestamp timestamp timestamp table 41-2. clock synchronization protocol flow action responsibility node type generate a sync packet sw master timestamp the sync packet and store the value in registers (t1) hw master timestamp the incoming sync packet; store the value in a register (t2); and record the sourceid and sequenceid in registers hw slave read the timestamp register (t1) and put the value in a follow_up packet and send it. sw master note the timestamp (t1) from the received follow-up message sw slave generate a delay_req packet and send it sw slave timestamp the outgoing delay_req packet and store in register (t3) hw slave timestamp incoming delay_req message; store value (t4); record sourceid and sequenceid in registers hw master read timestamp (t4) from register and send back to slave using a delay_response packet sw master note the timestamp (t4) from received delay_resp packet and calculate the time offset using t1, t2, t3, and t4 sw slave
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1626 order number: 320066-003us 41.5.1.2.2 protocol for transparent switches the synchronization protocol flow through a transparent switch is described in figure 41-4 . table 41-3. transparent clock synchronization protocol flow action responsibility node type sync packet generate a sync packet sw master timestamp the sync packet and store the value in registers (t1) hw master timestamp the incoming sync packet; store the value in a register (t2); and record the sourceid and sequenceid in registers hw transparent switch forward the received sync packet to the slave sw transparent switch timestamp the sync packet and store the value in registers (t2a) hw transparent switch timestamp the incoming sync packet; store the value in a register (t3); and record the sourceid and sequenceid in registers hw slave follow_up packet read the timestamp register (t1) and put the value in a follow_up packet and send it. sw master forward the received follow_up packet, first appending the residence time (rc2) of the previous sync packet. rc2 being the delay between receiving the sync packet (t2) and transmitting the sync packet (t2a) sw transparent switch note the timestamp (t1) and the residence time (rc2) from the received follow-up message sw slave delay_req packet generate a delay_req packet and send it sw slave timestamp the outgoing delay_req packet and store in register (t4) hw slave timestamp incoming delay_req message; store value (t5); record sourceid and sequenceid in registers hw transparent switch forward the received delay_req packet to the master sw transparent switch timestamp the outgoing delay_req packet and store the value in registers (t5a) hw transparent switch timestamp incoming delay_req message; store value (t6); record sourceid and sequenceid in registers hw master delay_response packet read timestamp (t6) from register and send back to slave using a delay_response packet sw master forward the received delay_response packet, first appending the residence time (rc5) of the previous delay_req packet. rc5 being the delay between receiving the delay_req packet (t5) and transmitting the delay_req packet (t5a) sw transparent switch note the timestamp (t6) and the residence time rc5 from received delay_resp packet and calculate the time offset using t1, rc2, t3, t4, rc5 and t6 sw slave
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1627 intel ? ep80579 integrated processor figure 41-4. transparent clock switch protocol flow s y n c f o l l o w _ u p ( t 1 ) d e l a y _ r e q d e l a y _ r e s p o n s e ( t 6 ) master slave t1 t2 t5 t6 s y n c f o l l o w _u p( t 1 , r c 2 ) d el a y _ r e q d e l a y _ r e s p o n s e ( t 6 , r c 5 ) t2a t3 t4 t5a transparent switch
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1628 order number: 320066-003us 41.5.1.3 ptp message formats the time sync implementation supports both ieee1588 v1 and ieee1588-2008 ptp messages. formats the format for each of these is shown in ta bl e 4 1 - 4 . when a ptp message containing packet is recognized, the ptp version is checked. if it is v1 ptp message then the control field contains the message type. the message type decoding is shown in ta b l e 4 1 - 5 and ta bl e 4 1 - 6 . table 41-4. ieee1588 version 1 and ieee1588-2008 ptp message formats offset in bytes v1 fields ieee1588-2008 fields 0 versionptp transport specific/messageid 1 reserved (4 bits)/versionptp(4 bits) 2 versionnetwork messagelength 3 4 subdomain subdomainnumber 5 reserved 6 flags 7 8 correctionns 9 10 11 12 13 14 correctionsubns 15 16 reserved 17 18 19 20 messagetype reserved 21 source communication technology source communication technology 22 sourceuuid sourceuuid 23 24 25 26 27 28 sourceportid sourceportid 29 30 sequenceid sequenceid 31
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1629 intel ? ep80579 integrated processor 41.5.2 time stamping operation time stamping means that the current value in the system time register is captured in a second register, generally called a snapshot register. the time stamping will occur when the appropriate conditions exist such as an auxiliary input is received or when a particular type of message is transmitted or received by the channel. once a timestamp of system time is taken and locked, a unique indication for the snapshot is set in the appropriate event register. no further timestamps of that 32 control control 33 reserved 34 flags logmessageperiod 35 table 41-4. ieee1588 version 1 and ieee1588-2008 ptp message formats offset in bytes v1 fields ieee1588-2008 fields table 41-5. message decoding for v1 enumeration value note ptp_sync_message 0 time stamp ptp_delay_req_message 1 time stamp ptp_followup_message 2 ptp_delay_resp_message 3 ptp_management_message 4 reserved 5-255 table 41-6. message decoding for ieee1588-2008 messageid message type value (hex) note ptp_sync_message event 0 time stamp ptp_delay_req_message event 1 time stamp ptp_path_delay_req_message event 2 time stamp ptp_path_delay_resp_message event 3 time stamp unused 4-7 ptp_followup_message general 8 ptp_delay_resp_message general 9 ptp_path_delay_followup_message general a ptp_announce_message general b ptp_signalling_message general c ptp_management_message general d unused e-f
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1630 order number: 320066-003us type can be received until the snapshot indication is cleared by firmware. thus, the setting of the indication is a lockout of further snapshots of a particular type until firmware takes action (unless the traffic analyzer lock inhibit feature is enabled). 41.5.2.1 sync messages the sw for the master channel sends a sync message periodically over the network at 1-, 2-, 8-, 16-, or 64-second intervals. if the channel is a master, the time sync logic will monitor the interface and detect when a sync message has been transmitted. when a sync message is detected and the xmit_snapshot is not locked out, the message is time stamped and the current system time is captured in the xmit_snapshot register. if the message is transmitted with no errors, the xmit_snapshot is locked. if the channel is a slave, the time sync logic will monitor the interface and detect when a sync message has been received. when the sync message is detected and the recv_snapshot is not locked out, the message is time stamped and the current system time is captured in the recv_snapshot register. if the message is received with no errors, the recv_snapshot is locked. when the snapshot of the sync message has occurred, an indication asserts in the ts_channel_event register and remains set unti l firmware explicitly writes a ?1? back to that bit. until the sync message snapshot indication is cleared, no further sync messages will be time stamped. locking can be inhibited by setting the ts_channel_control register appropriately. 41.5.2.2 follow-up messages the time sync logic performs no action related to follow-up messages. it is the responsibility of the sw for the master to read the xmit_snapshot register and send the follow-up message containing this timestamp. 41.5.2.3 delay_req message slave channels transmit a delay_req message to the master in response to receiving a sync message. if the channel is a master, the time sync logic will monitor the interface and detect when a delay_req message has been received. when the message is detected and the recv_snapshot is not locked out, the message is time stamped and the current system time is captured in the recv_snapshot register. if the message is received with no errors, the recv_snapshot is locked. if the channel is a slave, the time sync logic will monitor the interface and detect when a delay_req message has been transmitted. when the message is detected and the xmit_snapshot is not locked out, the message is time stamped and the current system time is captured in the xmit_snapshot register. if the message is transmitted with no errors, the xmit_snapshot is locked. when the snapshot for the delay_req message has occurred, an indication asserts in the ts_channel_event register and remains set until firmware explicitly writes a ?1? back to that bit. until the delay_req message snapshot indication is cleared, no further delay_req messages will be time stamped. this is important to note since multiple slave channels may try to send delay_req messages simultaneously. locking can be inhibited by setting the ts_channel_control register appropriately.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1631 intel ? ep80579 integrated processor 41.5.2.4 delay_response messages the time sync logic performs no action related to delay_response messages. it is the responsibility of the sw for the master to read the recv_snapshot register and send the delay_response message containing this timestamp. 41.5.2.5 error handling the time synchronization hardware depends on software for filtering appropriate ieee- 1588 packets. when the software receives a sync or delay request message, it interrogates the 1588 hardware for time snapshot information. however before using this data, the software must do several reasonableness checks on the data. this is due to the possibility of lost messages, the limited 1588 queue size of 1 entry, the possibility of multiple domains (the 1588 hardware only supports 1 domain), the asynchronous nature of the software clearing the timestamp lock with respect to possible incoming messages, and other similar events. therefore the hardware includes some mechanisms to assist the software filtering, such as the capture of the uuid and sequence count. when a time sync message is received by software that is expected to have an associated timestamp, the software should perform the following checks: 1. compare snapshot uuid to uuid in received 1588 packet. 2. compare snapshot sequence count to sequence count in received 1588 packet. 3. verify that timestamp is different than last timestamp. if any of these tests fail, the software should clear the lock and discard the information. 41.5.3 ieee1588 over ethernet 41.5.3.1 timestamping mechanism per the 1588 specification, synchronized time is referenced to the end of the ?start of frame delimiter? (sfd) as shown figure 41-5 . the time sync hardware captures the system time immediately upon detection of the sfd. the timestamp point is immediately after the sfd. this timestamp is stored in the snapshot register and is frozen in the snapshot register when the last nibble of the frame crc is transmitted or received and the overall message is detected with no errors. if an errored frame is detected (tx_err or rx_err are asserted) then the frame/message will be ignored. due to phy and synchronization delays, the actual timestamp will be slightly later than the desired reference point. however, allowing for 1 pclk synchronization jitter, this is a fixed delay, easily nulled out in the software portion of the algorithm. this fixed delay is dependent on the 10/100/1000 mhz selection at the phy. therefore, a constant can be subtracted from the snapshot to compensate for phy and synchronization delays to arrive at the ieee-1588 specified time stamp point.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1632 order number: 320066-003us 41.5.3.2 ptp message detection in ethernet frames ieee1588 ptp messages may be detected within three types of ethernet frames. ? l4 udp frames where the port is of the type ?eventport? ? l2 ethernet frames where the ethertype is defined to be ?ieee1588? ? a user defined frame in which configurable offsets, masks and compare values can be defined by the user via registers. this mode is provided to facilitate usage with a custom or otherwise non-ieee1588 compliant system. the specific decoding to identify a ptp containing frame is shown in ta bl e 4 1 - 7 . figure 41-5. time stamp reference point ethernet start of frame delimiter preamble octet first octet following start of frame 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 bit time message timestamp point table 41-7. ptp frame identification field field size l4 l2 user defined ethernet header dest mac address 6 x x x source mac address 6 x x x ethertype 2 0x0800 --- or --- 0x8100 (indicates tagged frame) programmable value (default = 0x88f7 ieee1588) --- or --- 0x8100 for tagged frame programmable mask and value vlan header vlan tag control (only present if ethertype = 0x8100) 2 ignore if present ignore if present not present ethertype (only present in tagged frame) 2 if tagged frame then test against programmed value (default = 0x88f7) ip header
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1633 intel ? ep80579 integrated processor 41.5.3.3 modes of operation the specific message detection mode for each channel can be configured. ta b l e 4 1 - 8 documents the supported modes of operation. version 1 0x45 (ipv4) not present not present tos 1 x length 2 x id 2 x flags/frag offset 2 x ttl 1 x protocol 1 0x11 (udp) header checksum 2 x source address 4 x dest address 4 x upd header source port 2 0x013f (eventport type) not present not present dest port 2 x length 2 x checksum 2 x ptp header see table 41-4, ?ieee1588 version 1 and ieee1588-2008 ptp message formats? on page 1628 user defined match programmable location against a programmable value to determine to timestamp table 41-7. ptp frame identification field field size l4 l2 user defined table 41-8. timestamping configurations ?offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel)? on page 1656 behavior version [31] mode [20:16 ] mm [0] ta [1] l2 l4 ptp version 1 ptp version 2 messages locked 0ignore0 0noyes yes no sync (rx only) delay_req (tx only) yes 0ignore1 0noyes yes no sync (tx only) delay_req (rx only) yes 0 ignore ignore 1 no yes yes no sync delay_req no 1 0 ignore ignore no yes yes no sync delay_req yes 1 1 ignore ignore no yes yes no all messages no
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1634 order number: 320066-003us when the mode of operation is ?locked?, the timestamp taken after the sfd is frozen in the snapshot registers and will not be updated until the software reset it. when the mode of operation is not ?locked?, each message is time stamped at the reception of a start of frame delimiter (sfd), however the snapshot registers will be overwritten with the arrival of a subsequent ptp message. 41.5.4 ieee1588 over can the time synchronization logic supports a hardware assist implementation for a can network (e.g. devicenet). the 1588 protocol operates over a can network in much the same way as it does over ethernet, using the same time synchronization messages identified earlier. however, the can protocol requires that these relatively lengthy messages are broken into much smaller frames. this fragmentation prevents one device from utilizing excessive bandwidth and maintains real time access to the network for all devices. since the can protocol breaks up 1588 messages into small frames and the frames do not carry 1588 specific identifiers, it is not practical to identify the 1588 sync and delay request messages in hardware. therefore, the hardware merely captures a timestamp into a holding register at the appropriat e point in each and every frame that is transmitted or received. the software has the responsibility to log the captured timestamp as part of each frame, as the software processes the transmit done interrupt (at the completion of a sent frame) or the received frame ready interrupt (at the availability of a received frame). this hardware assisted approach eliminates the potential for variable software interrupt service times from introducing jitter in the time snapshot and provides improved accuracy over a software-only approach. however, it does require significant software support. for example, when using 1588 hardware support for can, the multiple message buffers and screeners of the normal can block cannot be used in a continually over-writing updating mode without processor intervention. this is due to the fact that the software must read and save the time snapshot before the next message is sent or received. therefore, when 1588 hardware support is used, software will only be able to effectively use 1 screener/buffer and must guarantee that all can frame interrupts are 1 2 ignore ignore yes yes yes yes all event sync delay_req path_delay_req path delay_resp yes 1 3 ignore ignore yes yes yes yes all messages no 17:4 reserved 1 8 ignore ignore ignor e ignor e ignore ignore user-defined mode yes table 41-8. timestamping configurations ?offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel)? on page 1656 behavior version [31] mode [20:16 ] mm [0] ta [1] l2 l4 ptp version 1 ptp version 2 messages locked
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1635 intel ? ep80579 integrated processor serviced, which may come as often as the minimum frame size. these requirements should be easily met since can is a half duplex protocol operating at a relatively low baud rate. when a can packet is received or transmitted, the interrupt signal from the can device will assert and cause a snapshot of system time to be captured in the ts_cansnaplo and ts_cansnaphi registers. the ts_cansnaplo register contains the lower 32 bits of the time value, and the ts_cansnaphi register contains the upper 32 bits. the interrupt signal from the can must be enabled to assert on receive and transmit completion of each packet in order to capture snapshots for can packets. it is up to the firmware to assemble the packets into messages and determine which packet's snapshot is the appropriate one for the entire message. there is one pair of can snapshot registers (low and high) for each can device. therefore, for each can device, the assertion of the can interrupt signal when a frame transmit or receive is completed will capture the system time in a 64-bit snapshot register for that can device. each frame that is received or transmitted will have a snapshot taken. firmware will process the frames as part of the overall message evaluation, identify valid time sync messages, and determine the appropriate snapshot to utilize. two can channels are currently supported. note: in order to timestamp can activity the following assumptions must be valid. ? the can interrupts from the can controller must be serviced by software before the next can frame is detected. the initial assertion of the interrupt signal will initiate a time snapshot of the first frame but no further snapshots will be taken and no 1588 overflow will be set on any subsequent frames. however, this condition is detected, not by the 1588 block but by the can controller itself. the primary detection of a missed can interrupt is still (and always was) an overrun condition in the can controller. ? in1588 mode, it is expected that only one of the 16 available can receive buffers will be enabled and used. the relatively slow speed of the can channel makes this an acceptable trade-off between hardware and performance. when a frame is received, the can controller sets the buffer's msgav bit. if another frame is received and no receive buffers are available (as would be the case if only one buffer was enabled and its msgav bit was set from a previous frame not yet serviced), the rxmsglost flag is set in the can ip. thus the software would recognize this overflow condition by the rxmsglost flag when it finally got around to servicing the interrupt. 41.5.5 auxiliary snapshots time stamps may also be taken based on externally provided signals (asmssig and/or ammssig). these time stamps are recorded in the auxiliary snapshot registers. when the signal is asserted the hardware will take a timestamp and set the lock. software may then be notified via interrupt (if so configured) and it will read the appropriate register. if the software clears the lock before the signal is de-asserted, then a second, redundant snapshot event will be generated. note: hardware filtering and edge-detection were considered but not implemented because the signal quality from the master could be bad enough to cause spurious locks. for example, cables to a gps could be a kilometer or more in length and the type of cable could be a factor as well. the firmware handles the filtering and must not clear the lock until after the master has negated the snapshot input.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1636 order number: 320066-003us 41.5.6 target time expiration a system time that is greater than or equal to the target time sets the target time expiration condition and generates an interrupt if enabled. two independent target times are supported. refer to section 41.6.1.11, ?offset 0028h: ts_trgtlo - target time low register? and section 41.6.1.12, ?offset 002ch: ts_trgthi - target time high register? . also, section 41.6.1.28, ?offset 01f0h: ts_aux_trgtlo - auxiliary target time low register? and section 41.6.1.29, ?offset 01f4h: ts_aux_trgthi -auxiliary target time high register? 41.5.7 system time the system timer is derived from the source clock through a frequency divider. the frequency divider is based on the value in the addend register. once every system clock cycle the value in the addend register is added to the value in the accumulator register. when the accumulator register rolls over, the system timer is incremented. a single sourceclock is provided from which the desired systemclock can be derived via a frequency divider. the frequency divider is implemented by using the addend register. once every sourceclock cycle the value in the addend register is added to the value in the accumulator register. when the accumulator register rolls over, the system timer is incremented. thus, the system timer is incremented once every systemclock period. the value in the addend register represents the frequency compensation value. this value is determined as follows: freqdivisionratio = freqoscillator / freqclock the equation for the frequency compensation value utilizes the precision of the accumulator and the freqdivisionratio. since the accumulator is 32 bits, the following equation applies: freqcompensationvalue = 2 32 / freqdivisionratio the hexadecimal representation of the freqcompensationvalue is the value that is written to the addend register. the following table gives examples of addend values based on a 66.67 mhz freqoscillator: table 41-9. addend values freqoscillator 1 freqclock freqdivisionratio freqcompensationvalue 66.67 mhz 40 mhz 1.67 0x994b1d20 66.67 mhz 50 mhz 1.33 0xc07b301e 66.67 mhz 60 mhz 1.11 0xe6a17102 1. 50 mhz for 600 mhz ia-32 core and 66.67 mhz for 1066 mhz/1200 mhz ia-32 core.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1637 intel ? ep80579 integrated processor 41.5.8 interrupts an level sensitive interrupt signal to the processor is generated when any of the following conditions occur and are enabled: ? auxiliary master mode snapshot is taken ? auxiliary slave mode snapshot is taken ? target time expiration. ? auxiliary target time expiration ? pulse per second assertion an interrupt enable mask must be set to allow any of the interrupts to pass to the core. 41.5.9 reset there are two types of reset: ?power-on reset ? mmr write to soft reset register to initiate a channel each channel may be independently reset by sw by writing to the channel?s control register. if the gmii interface changes clock speeds (1000mbps down to 100/10 mbps), sw must initiate a soft reset to the corresponding channel. 41.6 register summary writes to unused address space will have no affect. reads to unused address space may return indeterminate data. neither situation should cause detrimental effects on device operation unless specifically documented. reserved bits within registers must be written with their reset value unless otherwise stated. for more information on the conventions the following register summaries adopt, see section 7.1, ?overview of register descriptions and summaries? on page 183 . the ieee 1588 hardware assist registers materialize in the pci space table 41-10 summarizes the ieee 1588 tsync materialization from the pci perspective. table 41-10. bus m, device 7, function 0: summary of ieee 1588 tsync csrs (sheet 1 of 2) offset start offset end register id - description default value 00000000h 00000003h ?offset 0000h: ts_control register? on page 1639 00000000h 00000004h 00000007h ?offset 0004h: ts_event register? on page 1641 0022h 00000008h 0000000bh ?offset 0008h: ts_addend register? on page 1643 0000h 0000000ch 0000000fh ?offset 000ch: ts_accum register? on page 1643 0000h 00000010h 00000013h ?offset 0010h: ts_test register? on page 1644 0000h 00000014h 00000017h ?offset 0014h: ts_pps_compare register? on page 1646 ffffffffh
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1638 order number: 320066-003us 00000018h 0000001bh ?offset 0018h: ts_rsystimelo register? on page 1647 0000h 0000001ch 0000001fh ?offset 001ch: ts_rsystimehi register? on page 1648 0000h 00000020h 00000023h ?offset 0020h: ts_systimelo register? on page 1649 0000h 00000024h 00000027h ?offset 0024h: ts_systimehi register? on page 1650 0000h 00000028h 0000002bh ?offset 0028h: ts_trgtlo register? on page 1650 0000h 0000002ch 0000002fh ?offset 002ch: ts_trgthi register? on page 1651 0000h 00000030h 00000033h ?offset 0030h: ts_asmslo register? on page 1652 0000h 00000034h 00000037h ?offset 0034h: ts_asmshi register? on page 1653 0000h 00000038h 0000003bh ?offset 0038h: ts_ammslo register? on page 1654 0000h 0000003ch 0000003fh ?offset 003ch: ts_ammshi register? on page 1655 0000h 0040h at 20h 0043h at 20h ?offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel)? on page 1656 0000h 0044h at 20h 0047h at 20h ?offset 0044h: ts_ch_event[0-7] - time synchronization channel event register per ethernet channel)? on page 1658 0000h 0048h at 20h 004bh at 20h ?offset 0048h: ts_txsnaplo[0-7] - transmit snapshot low register (per ethernet channel)? on page 1659 0000h 004ch at 20h 004fh at 20h ?offset 004ch: ts_txsnaphi[0-7] - transmit snapshot high register (per ethernet channel)? on page 1660 0000h 0050h at 20h 0053h at 20h ?offset 0050h: ts_rxsnaplo[0-7] - receive snapshot low register (per ethernet channel)? on page 1661 0000h 0054h at 20h 0057h at 20h ?offset 0054h: ts_rxsnaphi[0-7] - receive snapshot high register (per ethernet channel)? on page 1662 0000h 0058h at 20h 005bh at 20h ?offset 0058h: ts_srcuuidlo[0-7] - source uuid0 low register (per ethernet channel)? on page 1663 0000h 005ch at 20h 005fh at 20h ?offset 005ch: ts_srcuuidhi[0-7] - sequenceid/sourceuuid high register (per ethernet channel)? on page 1664 0000h 0140h at 10h 0143h at 10h ?offset 0140h: ts_canx_status[0-1] - time synchronization channel event register (per can channel)? on page 1665 0000h 0144h at 10h 0147h at 10h ?offset 0144h: ts_cansnaplo[0-1] - transmit snapshot low register (per can channel)? on page 1666 0000h 0148h at 10h 014bh at 10h ?offset 0148h: ts_cansnaphi[0-1] - transmit snapshot high register (per can channel)? on page 1667 0000h 000001f0h 000001f3h ?offset 01f0h: ts_aux_trgtlo register? on page 1668 0000h 000001f4h 000001f7h ?offset 01f4h: ts_aux_trgthi register? on page 1668 0000h 00000200h 00000203h ?offset 0200h: l2 ethertype register? on page 1669 000088f7h 0000204h 0000207h ?offset 0204h: user defined ethertype register? on page 1669 00000000h 00000208h 0000020bh ?offset 0208h:user defined header offset register? on page 1670 00000000h 0000020ch 0000020fh ?offset 020ch:user defined header register? on page 1670 00000000h table 41-10. bus m, device 7, function 0: summary of ieee 1588 tsync csrs (sheet 2 of 2) offset start offset end register id - description default value
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1639 intel ? ep80579 integrated processor 41.6.1 detailed register descriptions 41.6.1.1 offset 0000h: ts_control - time sync control register register name ts_control access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 (reserved) atm ppsm amm asm ttm rst table 41-11. offset 0000h: ts_control register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000000h 00000003h size: 32 bits default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 6 rsvd reserved for future use. must be written as ?0? 0ro 5: 5 atm auxiliary target time interrupt mask. the auxiliarytarget time interrupt mask controls whether the auxiliary target time interrupt is passed to the host processor. when this bit is set, the interrupt to the host is enabled. when cleared, the auxiliary target time interrupt to the host is disabled. 0h rw 4: 4 ppsm pps interrupt mask. the pps interrupt mask controls whether the 1 pps compare register match indication, which is the pps bit in the time sync event register, should interrupt the host processor. when this bit is set, the interrupt to the host is enabled. when cleared, the pps interrupt to the host is disabled. 0h rw 3: 3 amm amms interrupt mask. controls whether the auxiliary master mode snapshot indication, which is the snm bit in the time sync event register, should interrupt the host processor. ? when this bit is set, the interrupt to the host is enabled. ? when cleared, the amms interrupt to the host is disabled. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1640 order number: 320066-003us 2: 2 asm asms interrupt mask. controls whether the indication that an auxiliary slave mode snapshot, which is the sns bit in the time sync event register, has been taken should interrupt the host processor. ? when this bit is set, the interrupt to the host is enabled. ? when cleared, the asms interrupt to the host is disabled. 0h rw 1 : 1 ttm target time interrupt mask. controls whether the target time interrupt is passed to the host processor. ? when this bit is set, the interrupt to the host is enabled. ? when cleared, the target time interrupt to the host is disabled. 0h rw 0: 0 rst reset. ? when a ?1? is written to this bit, all logic is returned to the same default state as when a power-on reset occurs. ? after writing a ?1? to this bit to reset the logic, the firmware must write a ?0? to the bit to indicate the end of the reset. 0h rw table 41-11. offset 0000h: ts_control register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000000h 00000003h size: 32 bits default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1641 intel ? ep80579 integrated processor 41.6.1.2 offset 0004h: ts_event - time sync event register register name ts_event access (see below.) reset value 0x0000_0022 313029282726252423222120191817161514131211109876543210 (reserved) gbe1_mode gbe0_mode (reserved) atp pps snm sns ttipend rsvd table 41-12. offset 0004h: ts_event register (sheet 1 of 2) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000004h 00000007h size: 32 bits default: 0022h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 10 rsvd reserved for future use. x ro 9 : 9 gbe1_mode gbe1_mii_mode status: ?1? indicates the gbe 1 port is running in mii mode ?0? indicates the gbe 1 port is running in gmii mode 0h ro 8 : 8 gbe0_mode gbe0_mii_mode status: ?1? indicates the gbe 1 port is running in mii mode ?0? indicates the gbe 1 port is running in gmii mode 0h ro 7 : 6 rsvd reserved for future use. 0h ro 5: 5 atp auxiliary target time interrupt pending. this bit is the auxiliary target time interrupt pending indication. when this bit is set, it indicates that the auxiliary target time interrupt condition has occurred, which means that the system time value has reached the 64-bit auxiliary target time register value. if atm in the time sync control register is set, the interrupt will be passed to the host processor. to clear this condition and also the interrupt to the host if no other sources are driving it, the firmware must write a ?1? to the atp bit. to prevent an immediate reoccurrence of the auxiliary target time interrupt, the processor should first write a new value to the auxiliary target time register and then clear the condition. this bit is set at power-up since both the system time and the auxiliary target time are reset at power-up to 0x0000000000000000. 1rwc 4: 4 pps pps match. this event bit sets when the lower 32 bits of the system time register is equal to the 1pps compare register. when this signal is asserted high, an interrupt will be generated to the host on the ts_intreq if the ppsm bit in the time sync control register is also set. this signal also drives the ts_pps output pin of the timesync block. the user will clear pps by writing a '1' to it. 0h rwc 3: 3 snm amms snapshot. this event bit sets when the system time register value is captured in the auxiliary master mode snapshot register upon an active high level on a general purpose input, ammssig. ? when this signal is asserted high, an interrupt will be generated to the host on the ts_intreq if the amm bit in the time sync control register is also set. ? to clear snm, write a ?1? to it. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1642 order number: 320066-003us 2: 2 sns asms snapshot. this event bit sets when the system time register value is captured in the auxiliary slave mode snapshot register upon detection of a active high level on a general purpose input, asmssig. ? when this signal is asserted high, an interrupt will be generated to the host on the shared interrupt signal (ts_ntreq) if the asm bit in the time sync control register is set. ? to clear the sns bit, write a ?1? to it. 0h rwc 1 : 1 ttipend target time interrupt pending. this bit is the target time interrupt pending indication. when this bit is set, it indicates that the target time interrupt condition has occurred, which means that the system time value has reached the 64-bit target time register value. ? if ttm in the time sync control register is set, the interrupt will be passed to the host processor. ? to clear this condition, the firmware must write a ?1? to the ttipend bit. to prevent an immediate reoccurrence of the target time interrupt, the processor should first write a new value to the target time register and then clear the condition. this bit is set at power-up since both the system time and the target time are reset at power-up to 0. 1rwc 0 : 0 rsvd reserved for future use. 0h ro table 41-12. offset 0004h: ts_event register (sheet 2 of 2) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000004h 00000007h size: 32 bits default: 0022h power well: core bit range bit acronym bit description sticky bit reset value bit access
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1643 intel ? ep80579 integrated processor 41.6.1.3 offset 0008h: ts_addend - addend register 41.6.1.4 offset 000ch: ts_accum - accumulator register register name ts_addend access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 addend[31:0] table 41-13. offset 0008h: ts_addend register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000008h 0000000bh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 addend the addend register contains the frequency scaling value used by a firmware algorithm to achieve time synchronization in the module. the value in this register is added to the value in the accumulator. when the accumulator rolls over, an overflow pulse is asserted and increments system time. because the addend register is cleared at reset, it must be written with a non-zero value to allow system time to increment. 0h rw register name ts_accum access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 accumulator[31:0] table 41-14. offset 000ch: ts_accum register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0000000ch 0000000fh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 accumulator the accumulator register serves as the frequency divider in the time synchronization logic. firmware calculates a frequency scaling value to be written to the addend register. the data in the accumulator register is added to the value in the addend register once every period of the system clock. when the accumulator rolls over, an overflow pulse is asserted which increments the value in the system timer. this register is not read or written to in normal operation. 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1644 order number: 320066-003us 41.6.1.5 offset 0010h: ts_test - time sync test register register name ts_test access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 (reserved) rx_snap_cfg tx_snap_cfg tenb tm table 41-15. offset 0010h: ts_test register (sheet 1 of 2) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000010h 00000013h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 12 rsvd reserved for future use. x rv 11 : 8 rx_snap_cfg determines which rx channel activity is reflected on ts_rx_snap_taken 0000 -- channel 0 rx snapshot activity monitored 0001 -- channel 1 rx snapshot activity monitored 0010 -- channel 2 rx snapshot activity monitored 0011 -- channel 3 rx snapshot activity monitored 0100 -- channel 4 rx snapshot activity monitored 0101 -- reserved for channel 5 rx snapshot activity monitored 0110 -- reserved for channel 6 rx snapshot activity monitored 0111 -- reserved for channel 7 rx snapshot activity monitored 1000 -- can 0 snapshot activity monitored 1001 -- can 1 snapshot activity monitored 1010 -1111 -- reserved note: the ts_rx_snap_taken signal is non-zero when the tm bit is set and will be a pulse that is eight pclk cycles wide. 0000h rw 7: 4 tx_snap_cfg determines which tx channel activity is reflected on ts_tx_snap_taken 0000 -- channel 0 tx snapshot activity monitored 0001 -- channel 1 tx snapshot activity monitored 0010 -- channel 2 tx snapshot activity monitored 0011 -- channel 3 tx snapshot activity monitored 0100 -- channel 4 tx snapshot activity monitored 0101 -- reserved for channel 5 tx snapshot activity monitored 0110 -- reserved for channel 6 tx snapshot activity monitored 0111 -- reserved for channel 7 tx snapshot activity monitored 1000 -- can 0 snapshot activity monitored 1001 -- can 1 snapshot activity monitored 1010 -1111 -- reserved note: the ts_tx_snap_taken signal is non-zero when the tm bit is set and will be a pulse that is eight pclk cycles wide. 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1645 intel ? ep80579 integrated processor 3: 1 tenb test enable. these bits define what signals drive the ts_testmode_data pin when the tm bit in this register is set. the target time interrupt pending signal (readable in the ts_event register) is driven if tenb[2:0] is ?000? to support future applications. specific system timer bits drive ts_testmode_data for the remaining settings of tenb[2:0]. tenb[2:0] ts_testmode_data source 000 ts_event.ttipend 001 ts_systimelo[10] 010 ts_systimelo[12] 101 ts_systimelo[14] 100 ts_event.auxttipend 101-111 reserved 000h rw 0: 0 tm test mode. this bit, which defaults to ?0? at reset, is the test mode bit. ? when this bit is set, the ieee1588 hardware assist logic outputs one of four possible signals on the ts_testmode_data pin. the tenb[2:0] bits select the data. this data appears on the ts_testmode_data pin 0h rw table 41-15. offset 0010h: ts_test register (sheet 2 of 2) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000010h 00000013h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1646 order number: 320066-003us 41.6.1.6 offset 0014h: ts_pps - pps compare register register name ts_pps_compare access (see below.) reset value 0xffff_ffff 313029282726252423222120191817161514131211109876543210 pps_compare value[31:0] table 41-16. offset 0014h: ts_pps_compare register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000014h 00000017h size: 32 bits default: ffffffffh power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 ts_pps_compa re the pps compare register is a 32-bit register that contains a value that will be compared against the lower 32 bits of system time. the value placed in this register defines the value of the lower 32 bits of system time required to generate a 1 pulse per second signal to an external scope. when the two values are equal, the pin ts_pps is asserted concurrently, the state of the signal is visible as the pps bit in the ts_event register. the pps signal can also interrupt the host if the ppsm bit in the ts_channel register is set. it is the firmware's responsibility to calculate the new compare value for the next pulse per second and update this register accordingly. the bits of this register are set at reset in order to prevent ts_pps from asserting right after reset. ffffffffh rw note: the pps output controlled by this compare register is independent of the tm bit in the ts_test register
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1647 intel ? ep80579 integrated processor 41.6.1.7 offset 0018h: ts_tsystimelo - raw system time low register register name ts_rsystimelo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 rawsystemtime_low[31:0] table 41-17. offset 0018h: ts_rsystimelo register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000018h 0000001bh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 rawsystemtime _low this system time register is a read-only register of the raw system time. it is, therefore, not loadable and reflects the local time in the module. ? the lower 32 bits of the 64-bit system time are read in this register. ? the upper 32 bits are read in the rawsystemtime_high register. when a user reads system time with this pair of registers, no latching of system time occurs, which means that the system time could increment between the reading of the lower 32 bits in this register and the upper 32 bits in the rawsystemtime_high register. the user must account for this and deal with possible increments between reads of the two registers in firmware. 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1648 order number: 320066-003us 41.6.1.8 offset 001ch: ts_rsystimehi - raw system time high register register name ts_rsystimehi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 rawsystemtime_high[31:0] table 41-18. offset 001ch: ts_rsystimehi register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0000001ch 0000001fh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 rawsystemtime _high this register contains the upper 32 bits of system time. when you want to read or write the system time, this register typically first accesses the rawsystemtime_low register. this register pair contains the raw system timer value, and no latching of system time occurs when the lower half is read. time could increment between the reading of the lower 32 bits in the rawsystemtime_low register and the reading of this register. 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1649 intel ? ep80579 integrated processor 41.6.1.9 offset 0020h: ts_systimelo - system time low register register name ts_systimelo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 systemtime_low[31:0] table 41-19. offset 0020h: ts_systimelo register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000020h 00000023h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 systemtime_lo w the system timer is a loadable up-counter, and reflects the local time in the module. while the system timer is 64 bits wide, the lower 32 bits reside in this register. the system timer is clocked by the module system clock and incremented when the accumulator register rolls over. to read the entire system time value, the user must read this location first. reading this location captures the upper 32 bits of the system time in a temporary register, which is accessed when the user reads the systemtime_high register next. likewise, the systemtime_low register must be written first when the user wants to write a new 64-bit value to system time. the data written to this register is captured in a holding register. when the user writes to the systemtime_high register, all 64 bits are then written to the system timer. updating the system time with a direct write has precedence over increments to the system time based on an accumulator rollover. 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1650 order number: 320066-003us 41.6.1.10 offset 0024h: ts_systimehi - system time high register 41.6.1.11 offset 0028h: ts_trgtlo - target time low register register name ts_systimehi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 systemtime_high[31:0] table 41-20. offset 0024h: ts_systimehi register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000024h 00000027h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 systemtime_hi gh this register contains the upper 32 bits of system time. when the user wants to read or write the system time, this register must first access the systemtime_low register. see ?syste m time low register? on page 4784 for more details. 0000h rw register name ts_trgtlo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 targettime_low[31:0] table 41-21. offset 0028h: ts_trgtlo register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000028h 0000002bh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 targettime_low the target time register set contains 64 bits of a time value. when the system time is greater than or equal to the target time value, an interrupt is generated to the host on the ts_intreq signal if the ttm bit in the time sync control register is set. for more information about the target time interrupt, see ?time sync control register? on page 4775 . 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1651 intel ? ep80579 integrated processor 41.6.1.12 offset 002ch: ts_trgthi - target time high register register name ts_trgthi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 targettime_low[31:0] table 41-22. offset 002ch: ts_trgthi register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0000002ch 0000002fh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 ta r g e t t i m e _ h i g h the target time register set contains 64 bits of a time value. when the system time is greater than or equal to the target time value, an interrupt is generated to the host on the ts_intreq signal if the ttm bit in the time sync control register is set. for more information about the target time interrupt, see section 102.8.2.1, ?time sync control register? on page 4775 . 0000h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1652 order number: 320066-003us 41.6.1.13 offset 0030h: ts_asmlo - auxiliary slave mode snapshot low register register name ts_asmslo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 asms_low[31:0] table 41-23. offset 0030h: ts_asmslo register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000030h 00000033h size: 32 bits default: 0000 h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 asms_low when the board is operating in slave mode, the active high level of a general-purpose input, asmssig , triggers a snapshot of system time into the asms_low and asms_high registers. note: the processor can configure the gpio bit as an output, but it will always be input-only to the time sync block. when the asms snapshot occurs, the sns indication in the time sync event register is set. writing a logic 1 to that bit clears the snapshot indication and allows a new snapshot to occur on the next active high level of asmssig . 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1653 intel ? ep80579 integrated processor 41.6.1.14 offset 0034h: ts_asmhi - auxiliary slave mode snapshot high register register name ts_asmshi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 asms_high[31:0] table 41-24. offset 0034h: ts_asmshi register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000034h 00000037h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 asms_high when the board is operating in slave mode, the active high level of a general-purpose input, asmssig, triggers a snapshot of system time into the asms_low and asms_high registers. the general-purpose input is synchronized by the time sync logic before it is used. note: the processor can configure the gpio bit as an output, but it will always be input-only to the time sync block. when the asms snapshot occurs, the sns indication in the time sync event register is set. writing a logic 1 to that bit clears the snapshot indication and allows a new snapshot to occur on the next active high level of asmssig . 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1654 order number: 320066-003us 41.6.1.15 offset 0038h: ts_ammslo - auxiliary master mode snapshot low register register name ts_ammslo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 amms_low[31:0] table 41-25. offset 0038h: ts_ammslo register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000038h 0000003bh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 amms_low when the board is operating in master mode, it receives a general-purpose input signal for synchronization of snapshots and time. this general-purpose input, ammssig , is synchronized by the system clock in the time sync logic before it is used. note: the processor can configure the gpio as an output, but it will always be an input-only to the time sync block. when the amms snapshot occurs, the snm indication in the time sync event register is asserted. no new snapshots in the amms register pair are captured until the firmware writes a ?1? back to the snm bit to clear the snapshot indication. 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1655 intel ? ep80579 integrated processor 41.6.1.16 offset 003ch: ts_ammshi - auxiliary master mode snapshot high register register name ts_ammshi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 amms_high table 41-26. offset 003ch: ts_ammshi register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0000003ch 0000003fh size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 amms_high when the board is operating in master mode, it receives a general-purpose input signal for synchronization of snapshots and time. this general-purpose input, ammssig , is synchronized by the system clock in the time sync logic before it is used. note: the processor can configure the gpio as an output, but it will always be an input-only to the time sync block. when the amms snapshot occurs, the snm indication in the time sync event register is asserted. no new snapshots in the amms register pair are captured until the firmware writes a ?1? back to the snm bit to clear the snapshot indication. 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1656 order number: 320066-003us 41.6.1.17 offset 0040h: ts_ch_control [0-7] - time synchronization channel control register (per ethernet channel) register name ts_ch_control access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 reserved crst ta mm *address offsets per channel? channel 0 = 0x040 channel 1 = 0x060 channel 2 = 0x080 channel 3 = 0x0a0 channel 4 = 0x0c0 channel 5 = 0x0e0 channel 6 = 0x100 channel 7 = 0x120 table 41-27. offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0040h at 20h 0043h at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 version enables ieee1588-2008 support ? ?0? - ieee1588 v1 only (bits 20:16 ignored) ? ?1? - ieee1588 v1 and ieee1588-2008 (bit 1 ignored) 0rw 30 21 rsvd reserved for future use. must be written as ?0?. 0rw 20 16 mode selects timestamping configuration: ? ?0? - timestamp ptp version 1 sync and delay _req messages only. only ieee1588 l4 frames are decoded. timestamps are locked. ? ?1? - timestamp all ptp version 1 messages. when channel is ethernet, then decode for only ieee1588 l4 frames. timestamps are not locked. ? ?2 - timestamp ptp version 1 and 2 event messages only. when channel is ethernet, then decode for both l4 and l2 ieee1588 frames. timestamps are locked. ? ?3? - timestamp all ptp version 1 and 2 messages. when channel is ethernet, then decode for both l4 and l2 ieee1588 frames.timestamps are not locked. ? ?8? - timestamp user defined messages. timestamps are locked. refer to table 41-8, ?timestamping configurations? on page 1633 note: these settings are ignored for the can channels 0rw 15 3 rsvd reserved for future use. must be written as ?0?. 0rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1657 intel ? ep80579 integrated processor 2: 2 crst channel reset . when a '1' is written to this bit, the channel is returned to the same default state as when a power-on reset occurs. after writing a '1' to this bit to reset the logic, the firmware must write a '0' to the bit to indicate the end of the reset. 0h rw 1: 1 ta timestamp all messages. ? when this bit is set, the locking of the time snapshot registers is inhibited. each message is timestamped at the reception of a start of frame delimiter (sfd), regardless of whether the message is a sync or delay request message. the timestamp is captured by the snapshot register which is never locked and therefore must be read before the next sfd is received. ? when this bit is cleared, the timestamp taken after the sfd is frozen or locked when a valid sync or delay request message is detected, until the software resets it. 0h rw 0: 0 mm master mode. ? when this bit is set, it indicates that this channel is a time master on the network. ? when cleared, this bit indicates that this channel is in slave mode. the default after reset is slave mode. 0h rw table 41-27. offset 0040h: ts_ch_control[0-7] - time synchronization channel control register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0040h at 20h 0043h at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1658 order number: 320066-003us 41.6.1.18 offset 0044h: ts_ch_event[0-7] - time synchronization channel event register (per ethernet channel) register name ts_ch_event access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 reserved rxs txs *address offsets per channel? channel 0 = 0x044 channel 1 = 0x064 channel 2 = 0x084 channel 3 = 0x0a4 channel 4 = 0x0c4 channel 5 = 0x0e4 channel 6 = 0x104 channel 7 = 0x124 table 41-28. offset 0044h: ts_ch_event[0-7] - time synchronization channel event register per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0044h at 20h 0047h at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 2 reserved reserved for future use. 0h rv 1: 1 rxs receive snapshot locked. this bit is automatically set when a delay_req message in master mode, or a sync message in slave mode, is received and the ta bit in the corresponding ts_channel_control register is clear. it indicates that the current system time value has been captured in the recv_snapshot register and that further changes to the recv_snapshot are now locked out. to clear this bit, write a ?1? to it. 0h rwc 0: 0 txs transmit snapshot locked. this bit is automatically set when a sync message in master mode, or a delay_req message in slave mode, is transmitted and the ta bit in the corresponding ts_channel_control register is clear. it indicates that the current system time value has been captured in the xmit_snapshot register and that further changes to the xmit_snapshot are now locked out. to clear this bit, write a ?1? to it. 0h rwc
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1659 intel ? ep80579 integrated processor 41.6.1.19 offset 0048h: ts_txsnaplo[0-7] - transmit snapshot low register (per ethernet channel) register name ts_txsnaplo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 xmit_snapshot_low[31:0] *address offsets per channel? channel 0 = 0x048 channel 1 = 0x068 channel 2 = 0x088 channel 3 = 0x0a8 channel 4 = 0x0c8 channel 5 = 0x0e8 channel 6 = 0x108 channel 7 = 0x128 table 41-29. offset 0048h: ts_txsnaplo[0-7] - transmit snapshot low register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0048h at 20h 004bh at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 xmit_ snapshot_ low when a sync message in master mode, or a delay_req message in slave mode, is transmitted, the current system time is captured in this xmit_snapshot register. ? the xmit_snapshot_low register contains the lower 32 bits of the time value. ? the xmit_snapshot_high register contains the upper 32 bits. after a xmit_snapshot has occurred, the txs indication in the ts_channel_event register does not clear until the user writes a ?1? to that bit in that register. therefore, the firmware should read the xmit_snapshot_low and xmit_snapshot_high registers before it writes a ?1? to the txs bit to clear the snapshot indication. in this way, the snapshot value cannot change between reads of the high and low locations. 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1660 order number: 320066-003us 41.6.1.20 offset 004ch: ts_txsnaphi[0-7] - transmit snapshot high register (per ethernet channel) register name ts_txsnaphi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 xmit_snapshot_high[31:0] *address offsets per channel? channel 0 = 0x04c channel 1 = 0x06c channel 2 = 0x08c channel 3 = 0x0ac channel 4 = 0x0cc channel 5 = 0x0ec channel 6 = 0x10c channel 7 = 0x12c table 41-30. offset 004ch: ts_txsnaphi[0-7] - transmit snapshot high register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 004ch at 20h 004fh at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 xmit_ snapshot_ high when a sync message in master mode, or a delay_req message in slave mode, is transmitted, the current system time is captured in this xmit_snapshot register. ? the xmit_snapshot_low register contains the lower 32 bits of the time value. ? the xmit_snapshot_high register contains the upper 32 bits. after a xmit_snapshot has occurred, the txs indication in the ts_channel_event register does not clear until the user writes a ?1? to that bit in that register. therefore, the firmware should read the xmit_snapshot_low and xmit_snapshot_high registers before it writes a ?1? to the txs bit to clear the snapshot indication. in this way, the snapshot value cannot change between reads of the high and low locations. 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1661 intel ? ep80579 integrated processor 41.6.1.21 offset 0050h: ts_rxsnaplo[0-7] - receive snapshot low register (per ethernet channel) register name ts_rxsnaplo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 recv_snapshot_low[31:0] *address offsets per channel? channel 0 = 0x050 channel 1 = 0x070 channel 2 = 0x090 channel 3 = 0x0b0 channel 4 = 0x0d0 channel 5 = 0x0f0 channel 6 = 0x110 channel 7 = 0x130 table 41-31. offset 0050h: ts_rxsnaplo[0-7] - receive snapshot low register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0050h at 20h 0053h at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 recv_ snapshot_ low when a delay_req message in master mode, or a sync message in slave mode, is received, the current system time is captured in this recv_snapshot register. ? the recv_snapshot_low register contains the lower 32 bits of the time value. ? the recv_snapshot_high register contains the upper 32 bits. after a recv_snapshot has occurred, the rxs indication in the ts_channel_event register does not clear until the user writes a ?1? to that bit in that register. therefore, the firmware should read the recv_snapshot_low and recv_snapshot_high registers before it writes a ?1? to the rxs bit to clear the snapshot indication. in this way, the snapshot value cannot change between reads of the high and low locations. 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1662 order number: 320066-003us 41.6.1.22 offset 0054h: ts_rxsnaphi[0-7] - receive snapshot high register (per ethernet channel) register name ts_rxsnaphi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 recv_snapshot_high[31:0] *address offsets per channel? channel 0 = 0x054 channel 1 = 0x074 channel 2 = 0x094 channel 3 = 0x0b4 channel 4 = 0x0d4 channel 5 = 0x0f4 channel 6 = 0x114 channel 7 = 0x134 table 41-32. offset 0054h: ts_rxsnaphi[0-7] - receive snapshot high register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0054h at 20h 0057h at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 recv_ snapshot_ high when a delay_req message in master mode, or a sync message in slave mode, is received, the current system time is captured in this recv_snapshot register. ? the recv_snapshot_low register contains the lower 32 bits of the time value. ? the recv_snapshot_high register contains the upper 32 bits. after a recv_snapshot has occurred, the rxs indication in the ts_channel_event register does not clear until the user writes a ?1? to that bit in that register. therefore, the firmware should read the recv_snapshot_low and recv_snapshot_high registers before it writes a ?1? to the rxs bit to clear the snapshot indication. in this way, the snapshot value cannot change between reads of the high and low locations. 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1663 intel ? ep80579 integrated processor 41.6.1.23 offset 0058h: ts_srcuuidlo[0-7] - source uuid0 low register (per ethernet channel) register name ts_srcuuid0lo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 sourceuuid0_low[31:0] *address offsets per channel? channel 0 = 0x058 channel 1 = 0x078 channel 2 = 0x098 channel 3 = 0x0b8 channel 4 = 0x0d8 channel 5 = 0x0f8 channel 6 = 0x118 channel 7 = 0x138 table 41-33. offset 0058h: ts_srcuuidlo[0-7] - source uuid0 low register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0058h at 20h 005bh at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 sourceuuid0_l ow when a delay_req message in master mode, or a sync message in slave mode, is received with no errors, the source uuid of the message is captured. the source uuid is located in bytes 64 through 69 of the ethernet message, and this register contains the lower 32 bits of the source uuid. this register is read-only. at reset, the value in the register is 0, which is not a valid source uuid value. 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1664 order number: 320066-003us 41.6.1.24 offset 005ch: ts_srcuuidhi[0-7] - sequenceid/sourceuuid high register (per ethernet channel) when a delay_req message in master mode, or a sync message in slave mode, is received with no errors, the source uuid and the sequence id of the message are captured. register name ts_srcuuidhi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 sequenceid[15:0] sourceuuid_high[47:32] *address offsets per channel? channel 0 = 0x05c channel 1 = 0x07c channel 2 = 0x09c channel 3 = 0x0bc channel 4 = 0x0dc channel 5 = 0x0fc channel 6 = 0x11c channel 7 = 0x13c table 41-34. offset 005ch: ts_srcuuidhi[0-7] - sequenceid/sourceuuid high register (per ethernet channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 005ch at 20h 005fh at 20h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 sequenceid the sequence id is located in bytes 72 and 73 of the ethernet message, and is captured in this register in bit locations [31:16]. 0000h ro 15 : 0 sourceuuid_hi gh this register contains the upper 16 bits (bits 47:32) of the source uuid in bit locations [15:0]. 0000h ro note: this register has no meaning and is not used for the can interfaces.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1665 intel ? ep80579 integrated processor 41.6.1.25 offset 0140h: ts_canx_status[0-1] - time synchronization channel event register (per can channel) register name ts_canx_status access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 reserved valid ovr *address offsets per channel? can 0 = 0x140 can 1 = 0x150 table 41-35. offset 0140h: ts_canx_status[0-1] - time synchronization channel event register (per can channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0140h at 10h 0143h at 10h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 02 reserved reserved for future use. 0h rv 1 : 1 valid snapshot valid. this bit is automatically set when a can interrupt has caused a snapshot to be taken. it indicates that the current system time value has been captured in the can_snapshot register t. this bit remains set until the firmware writes a '1' to this bit location. 0h rwc 0: 0 ovr snapshot overrun. if a second snapshot is taken while the valid flag is still set, then the overrun error bit (ovr) in this register is set to a '1'. this indication notifies the firmware that a previous snapshot was overwritten by the current snapshot and never read. to clear this bit, write a ?1? to it. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1666 order number: 320066-003us 41.6.1.26 offset 0144h: ts_cansnaplo[0-1] - transmit snapshot low register (per can channel) register name ts_cansnaplo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 can_snapshot_low[31:0] *address offsets per channel? channel 0 = 0x144 channel 1 = 0x154 table 41-36. offset 0144h: ts_cansnaplo[0-1] - transmit snapshot low register (per can channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0144h at 10h 0147h at 10h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 can_ snapshot_ low when a can packet is transmitted or received, the current system time is captured in this can_snapshot register. ? the can_snapshot_low register contains the lower 32 bits of the time value. ? the can_snapshot_high register contains the upper 32 bits. after a can_snapshot has occurred, the valid indication in the ts_can_status register does not clear until the user writes a ?1? to that bit in that register. the firmware should check the state of the valid bit in the can_status register before reading can_snapshot_low. because the snapshot value could change between reads of the low and high snapshot registers, the firmware should check the state of the overrun bit before and after the read of the can_snapshot_high register. after reading the can_snapshot_high register, the firmware should write a '1' to the valid bit and the overrun bit if applicable. 0000h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1667 intel ? ep80579 integrated processor 41.6.1.27 offset 0148h: ts_cansnaphi[0-1] - transmit snapshot high register (per can channel) register name ts_cansnaphi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 can_snapshot_high[31:0] *address offsets per channel? can channel 0 = 0x148 can channel 1 = 0x158 table 41-37. offset 0148h: ts_cansnaphi[0-1] - transmit snapshot high register (per can channel) description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0148h at 10h 014bh at 10h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 00 can_ snapshot_ high when a can packet is transmitted or received, the current system time is captured in this can_snapshot register. ? the can_snapshot_low register contains the lower 32 bits of the time value. ? the can_snapshot_high register contains the upper 32 bits. after a can_snapshot has occurred, the valid indication in the ts_can_status register does not clear until the user writes a ?1? to that bit in that register. the firmware should check the state of the valid bit in the can_status register before reading can_snapshot_low. because the snapshot value could change between reads of the low and high snapshot registers, the firmware should check the state of the overrun bit before and after the read of the can_snapshot_high register. after reading the can_snapshot_high register, the firmware should write a '1' to the valid bit and the overrun bit if applicable. 0000h ro
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1668 order number: 320066-003us 41.6.1.28 offset 01f0h: ts_aux_trgtlo - auxiliary target time low register 41.6.1.29 offset 01f4h: ts_aux_trgthi -auxiliary target time high register register name ts_aux_trgtlo access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 auxtargettime_low[31:0] table 41-38. offset 01f0h: ts_aux_trgtlo register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 000001f0h 000001f3h size: 32 bits default: 0000 h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 aux_targettime _low the auxiliary target time register set contains 64 bits of a time value. when the system time is greater than or equal to the auxiliary target time value, an interrupt is generated to the host on the ts_intreq signal if the atm bit in the time sync control register is set. for more information about the auxiliary target time interrupt, see section 102.8.2.1, ?time sync control register? on page 4775 . 0000h rw register name ts_aux_trgthi access (see below.) reset value 0x0000_0000 313029282726252423222120191817161514131211109876543210 targettime_low[31:0] table 41-39. offset 01f4h: ts_aux_trgthi register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 000001f4h 000001f7h size: 32 bits default: 0000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 0 aux_targettime _high the auxiliary target time register set contains 64 bits of a time value. when the system time is greater than or equal to the auxiliary target time value, an interrupt is generated to the host on the ts_intreq signal if the atm bit in the time sync control register is set. for more information about the auxiliary target time interrupt, see section 102.8.2.1, ?time sync control register? on page 4775 . 0000h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1669 intel ? ep80579 integrated processor 41.6.1.30 offset 0200h: l2_ethertype - l2 ethertype register 02 41.6.1.31 offset 0204h: ud_ethertype - user defined ethertype register register name l2_ethertype access (see below.) reset value x0000_88f7 313029282726252423222120191817161514131211109876543210 (reserved) ethertype table 41-40. offset 0200h: l2 ethertype register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000200h 00000203h size: 32 bits default: 000088f7h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 rsvd reserved for future use. must be written as ?0? 0ro 15 : 0 ethertype ethertype compare value (default = 0x88f7). the user may optionally supply a different ethertype compare value for l2 ieee1588 detection 88f7h rw register name ud_ethertype access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 mask ud_ethertype table 41-41. offset 0204h: user defined ethertype register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0000204h 0000207h size: 32 bits default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 mask mask for compare value 0h rw 15 : 0 ud_ethertype user defined compare value for ethertype field. used in conjunction with mask, above. 0h rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1670 order number: 320066-003us 41.6.1.32 offset 0208h: ud_header_offset - user defined header offset register 41.6.1.33 offset 020ch: ud_header - user defined header register register name ud_header_offset access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 (reserved) ud_offset table 41-42. offset 0208h:user defined header offset register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 00000208h 0000020bh size: 32 bits default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 8 rsvd reserved. must be written as ?0? 0h rw 7 : 0 ud_offset user defined offset for header 0h rw register name ud_header access (see below.) reset value x0000_0000 313029282726252423222120191817161514131211109876543210 mask ud_header table 41-43. offset 020ch:user defined header register description: view: pci bar: csrbar bus:device:function: m:7:0 offset start: offset end: 0000020ch 0000020fh size: 32 bits default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 16 mask mask for compare value 0h rw 15 : 0 ud_header user defined compare value for header 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1671 intel ? ep80579 integrated processor 42.0 local expansion bus controller 42.1 overview the expansion bus controller provides an interface from to external expansion target devices. the expansion bus controller includes a 25-bit address bus and a 16-bit wide data path. the expansion bus supports intel multiplexed, intel non-multiplexed, intel strataflash ? technology, intel strataflash ? synchronous memory, micron* flow- through zbt, motorola* multiplexed, motorola non-multiplexed, and texas instruments* host port interface (hpi) target devices. byte-wide devices may also be used by programming the channel connection for 8-bit operation. for ti dsps that support an internal bus width of 32 bits, the multiplexed hpi-8 or hpi-16 interface can be used to complete these transfers. 42.2 feature list ? outbound transfers (the ep80579 integrated processor is the master to an external target device). ? eight programmable target chip selects. ? twenty five bits of address; sixteen bits of data. ? supports intel mode and motorola* mode bus cycles. ?supports intel strataflash ? technology. ? supports 66-mhz intel strataflash ? synchronous memory (16-bit only). ? supports 16-bit micron flow-through zbt (zero bus turnaround) srams. ? supports 8-bit and 16-bit texas instruments hpi specifications. ? multiplexed or non-multiplexed address / data buses for intel/motorola*/hpi bus cycles. ? supports even and odd parity generation and calculation for intel/motorola*/ micron* zbt modes. ? maximum clock input frequency of 80 mhz. ? minimum input clock frequency of 33mhz.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1672 order number: 320066-003us 42.3 block diagram 42.4 theory of operation the expansion bus controller supports outbound transfers that are initiated by the ep80579 that target expansion bus slaves. the expansion data bus is 16 bits wide and the address bus is 25 bits wide. since the expansion bus controller has only 1 outbound transaction queue, outbound accesses all complete in order. 42.4.1 outbound transfers for outbound data transfers, the expansion bus controller occupies up to 256 mbytes of address space in the ep80579?s memory map (refer to signal ex_addr [24:0] in table 48-24, ?expansion bus signals? ) and contains a 1-deep address queue, an 8- word write data fifo, and an 8-word read data fifo. eight chip selects are supported to allow up to eight independent external devices to be connected. the address space for each chip select is up to 32 mbytes. an external clock input, ex_clk, is required to operate the expansion interface. the maximum clock frequency supported by the expansion bus controller is 80 mhz. the clock input is provided to allow a wide variety of different peripherals to be connected to the expansion interface.to provide a glue-less interface to a wide variety of devices, the expansion bus controller supplies eight chips selects to a 16-bit wide external bus, which can be configured as intel, synchronous intel, micron zbt, motorola, or hpi-style controls. the signaling characteristics and timing for each chip select is individually programmable. figure 42-1. expansion bus controller interface
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1673 intel ? ep80579 integrated processor for synchronous intel strataflash memory, the expansion bus controller only supports single word asynchronous page-mode read and synchronous burst-mode read (1-8 words). it does not support page mode read mode or single word latched asynchronous read mode. when configuring a synchronous intel strataflash memory, wait polarity must be programmed to active low, data hold programmed to one clock, wait delay be deasserted with valid data and clock edge programmed to rising edge. for 16-bit synchronous intel devices, the burst length must be programmed to 16-word bursts. the latency count must be programmed to the appropriate value that is defined in the specific synchronous intel strataflash memory specification. the expansion bus interface signals need to be connected based upon the device type (intel, synchronous intel, micron zbt, motorola, or hpi-style control signals) and a sample mapping of the pins are shown in table 42-1 . the ex_iowait_n signal is available to be shared by the devices attached to chip 0 through 7, when the chip selects are configured in intel or motorola mode of operation. the ex_iowait_n signal allows an external device to hold off completion of the read or write phase of a transaction until the external device is ready to complete the transaction. similarly, ex_rdy[3:0] are provided for chip selects 7 through 4, respectively. the ex_rdy[3:0] signals are used to hold off data transfers when chip selects 7 through 4 are configured in hpi mode. for example when chip select 5 is configured in hpi mode of operation, chip select 5 will no longer respond to the ex_iowait_n signal and will only respond to the ex_rdy_n[1]. all other chip selects will respond to the ex_iowait_n signal. chip selects 7 through 4 are the only chip selects that can be configured in hpi mode of operation. 42.4.1.1 chip select address allocation the expansion bus controller occupies up to 256 mbytes of address space in the ep80579 memory map. the expansion bus controller uses bits 27:0, from the internal bus, to determine how to translate the internal bus address to the expansion bus address. if there are no 32 mbyte devices programmed (i.e., all eight exp_timing_cs registers bit 9 equal 0), the lower 24 bits of the internal bus address are translated to the lower 24 bits of the expansion bus address, ex_addr [23:0]. ex_addr[24] will always be zero. bits 26:24 of the internal bus are used to decode one of eight chip- table 42-1. example expansion bus pin mappings to target devices pin intel strataflash ? 28f128j3a synchronous intel strataflash 28f256k3 motorola* mcm6946 micron* zbt mt55l128l36 f1 ti* hpi tms320uc540 9 ex_ale open adv# open adv/ld# open ex_addr[24:0] a[23:0] a[24:1] a[18:0] sa hcsel,hcntl,h bil ex_be_n[1:0] open open open bw[d:a]# open ex_cs_n[7:0] ce# ce# en ce# hcs ex_data[15:0] d[15:0] d[15:0] dq[7:0] dq hd[7:0] ex_iowait_n open open open open open ex_parity[1:0] open open open dq open ex_rd_n oe# oe# g_n oe# hr_w_n ex_rdy_n[3:0] open open open open hrdy ex_wr_n we# we# w_n r/w# hds1_n
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1674 order number: 320066-003us select regions implemented by the expansion bus, each region being 16 mbytes. address bit 27 is not used and will currently alias each chip select region as shown on the left side of figure 42-2 . the right side of figure 42-2 shows the implementation of bit 13:10 of the each timing and control (exp_timing_cs) register. a timing and control (exp_timing_cs) register is implemented for each of the eight chip selects. each chip select defines a base region size of 512 bytes with the actual size of the region given by the formula shown in figure 42-3 . if the address is outside of the programmed region, the expansion bus controller responds with an error. figure 42-2. chip select address allocati on when there are no 32-mbyte devices programmed cs_n[7] 128 mbytes cs_n[0] cs_n[1] cs_n[2] cs_n[3] cs_n[4] cs_n[5] cs_n[6] mmbar + 0x1000000 mmbar + 0x2000000 mmbar + 0x3000000 mmbar + 0x4000000 mmbar + 0x5000000 mmbar + 0x6000000 mmbar + 0x7000000 mmbar + 0x0000000 16 mb cnfg[4:0] = 0b11110 size = 16 mbytes 0b11100 : 8 mbytes 0b11010 : 4 mbytes 0b11000 : 2 mbytes 0b10110 : 1 mbytes cs_n[x] mmbar + 0x8000000 0b00000 : 512 bytes cs_n[7] (alias) cs_n[0] (alias) ... ... mmbar + 0xf000000 mmbar + 0xfffffff 128 mbytes figure 42-3. expansion bus memory sizing region size = 2 (9+cnfg[4:1] + 16*cnfg[0]) for examples of how to use this feature: if bits 13:9 of timing and control (exp_timing_cs0) register 0 = ?00000? an address space of 2 9 = 512 bytes is defined for chip select 0 (ex_cs0_n). if bits 13:9 of timing and control (exp_timing_cs1) register 1 = ?10000? an address space of 2 17 = 128kbytes is defined for chip select 1 (ex_cs1_n). if bits 13:9 of timing and control (exp_timing_cs2) register 2 = ?11110? an address space of 2 24 = 16mbytes is defined for chip select 2 (ex_cs2_n). if bits 13:9 of timing and control (exp_timing_cs7) register 7 = ?00001? an address space of 2 25 = 32mbytes is defined for chip select 7 (ex_cs7_n).
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1675 intel ? ep80579 integrated processor if there is a 32-mbyte device programmed in any of the eight exp_cs_timing registers, a different memory map is used as shown in figure 42-4 . the lower 25 bits of the internal bus address are translated to the lower 25 bits of the expansion bus address, ex_addr [24:0]. bits 27:25 of the internal bus are used to decode one of eight chip-select regions implemented by the expansion bus, each region being 32 mbyte. if a design has 16-mbyte or smaller devices on all of the chip selects, one of the exp_cs_timing register could be programmed to a 32-mbyte device so the expansion bus address mapping will not change if that design switches to 32-mbyte device sometime in the future. the expansion bus controller will still work with the smaller device, however an error response will not be generated if there is an access outside the device window for that device. 42.4.1.2 address and data byte steering ta bl e 4 2 - 2 shows the address and data mapping from the internal bus to the expansion bus. this table applies to intel, synchronous intel, micron zbt and motorola defined cycles only. for 32-bit read operations to a byte/halfword wide interface, multiple bytes are collected and then transferred as a complete 32-bit word. this pattern occurs as shown below for any allowable sub-length re ad access. four and eight word reads are also supported and generate multiple accesses to the target device. four and eight word reads to synchronous intel, only generate one burst access to the device. byte enables are generated for both reads and writes and are valid the same cycles (t1-t4 phases) as ex_addr is valid. byte write devices (devices that need ex_be_n asserted in the same exact cycles that ex_wr_n is asserted) are not supported. the internal bus is always big endian format; the expansio n bus is big endian as well. the data byte steering for each cycle type is showing in ta bl e 4 2 - 2 . for 8-bit devices, ex_data[31:8] must not toggle to conserve power. similarly, for 16- bit devices, ex_data[31:16] must not toggle. for sub-word writes to 32-bit devices, ex_data must not toggle for byte enables not asserted. figure 42-4. chip select address allocation when a 32 mbyte device is programmed cs_n[7] 256 mbytes cs_n[0] cs_n[1] cs_n[2] cs_n[3] cs_n[4] cs_n[5] cs_n[6] mmbar + 0x2000000 mmbar + 0x4000000 mmbar + 0x6000000 mmbar + 0x8000000 mmbar + 0xa000000 mmbar + 0xc000000 mmbar + 0xe000000 mmbar + 0x0000000 32 mb cnfg[4:0] = 0b00001 size = 32 mbytes 0b11100 : 8 mbytes 0b11010 : 4 mbytes 0b11000 : 2 mbytes 0b10110 : 1 mbytes cs_n[x] mmbar + 0xfffffff 0b11110 : 16 mbytes 0b00000 : 512 bytes
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1676 order number: 320066-003us 42.4.1.3 expansion bus interface configuration table 42-2. expansion bus address and data byte steering (sheet 1 of 2) internal bus cycle device width connected to expansion bus (8-bit or 16- bit) internal address value (internal _addr[1:0]) expansion bus address value (ex_addr[1:0] ) data location translation between expansion data bus and internal data bus byte write 8-bit 00 00 internal data bus [31:24] = expansion data bus [7:0], ex_be_n = 0x2 01 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 10 internal data bus [15:8] = expansion data bus [7:0], ex_be_n = 0x2 11 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 word write 16-bit 00 00 internal data bus [31:16] = expansion data bus [15:0], ex_be_n = 0x0 10 internal data bus [15:0] = expansion data bus [15:0], ex_be_n = 0x0 byte read 8-bit 00 00 internal data bus [31:24] = expansion data bus [7:0], ex_be_n = 0x2 01 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 10 internal data bus [15:8] = expansion data bus [7:0], ex_be_n = 0x2 11 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 word read 16-bit 00 00 internal data bus [31:16] = expansion data bus [15:0], ex_be_n = 0x0 10 internal data bus [15:0] = expansion data bus [15:0], x_be_n = 0x0 byte read 8-bit 0x 00 internal data bus [31:24] = expansion data bus [7:0], ex_be_n = 0x2 01 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 byte read 8-bit 1x 10 internal data bus [15:8] = expansion data bus [7:0], ex_be_n = 0x2 11 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 word read 16-bit 0x 00 internal data bus [31:16] = expansion data bus [15:0], ex_be_n = 0x0 word read 16-bit 1x 10 internal data bus [15:0] = expansion data bus [15:0], ex_be_n = 0x0 byte write 8-bit 0x 00 internal data bus [31:24] = expansion data bus [7:0], ex_be_n = 0x2 01 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 byte write 8-bit 1x 10 internal data bus [15:8] = expansion data bus [7:0], ex_be_n = 0x2 11 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 word write 16-bit 0x 00 internal data bus [31:16] = expansion data bus [15:0], ex_be_n = 0x0
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1677 intel ? ep80579 integrated processor there are eight registers called the timing and control (exp_timing_cs) registers that define the operating mode for each chip select. when designing with the expansion bus interface, placing the devices on the correct chip selects is required. chip select 0 through 7 can be configured to operate with devices that require an intel, synchronous intel, micron zbt or motorola micro-processor style bus accesses. these chip selects can be configured to operate in a multiplexed or a simplex mode of operation for either intel- or motorola-style bus accesses. additionally, chip select 4 through 7 can be configured to generate texas instruments hpi-style bus accesses. the mode of operation (intel, motorola, ti hpi, or synchronous intel, micron zbt) is set by bits 15,14, and 8 of each timing and control (exp_timing_cs) register. table 42-6 on page 1698 shows the possible settings for the cycle type selection using bits 15, 14, and 8 of the timing and control (exp_timing_cs) register. word write 16-bit 1x 10 internal data bus [15:0] = expansion data bus [15:0], ex_be_n = 0x0 byte read 8-bit 00 00 internal data bus [31:24] = expansion data bus [7:0], ex_be_n = 0x2 byte read 8-bit 01 01 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 byte read 8-bit 10 10 internal data bus [15:8] = expansion data bus [7:0], ex_be_n = 0x2 byte read 8-bit 11 11 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 word read 16-bit 00 00 internal data bus [31:24] = expansion data bus [15:8], ex_be_n = 0x1 word read 16-bit 01 00 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 word read 16-bit 10 10 internal data bus [15:8] = expansion data bus [15:8], ex_be_n = 0x1 word read 16-bit 11 10 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 byte write 8-bit 00 00 internal data bus [31:24] = expansion data bus [7:0], ex_be_n = 0x2 byte write 8-bit 01 01 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 byte write 8-bit 10 10 internal data bus [15:8] = expansion data bus [7:0], ex_be_n = 0x2 byte write 8-bit 11 11 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 word write 16-bit 00 00 internal data bus [31:24] = expansion data bus [15:8], ex_be_n = 0x1 wordwrite 16-bit 01 00 internal data bus [23:16] = expansion data bus [7:0], ex_be_n = 0x2 word write 16-bit 10 10 internal data bus [15:8] = expansion data bus [15:8], ex_be_n = 0x1 word write 16-bit 11 10 internal data bus [7:0] = expansion data bus [7:0], ex_be_n = 0x2 table 42-2. expansion bus address and data byte steering (sheet 2 of 2) internal bus cycle device width connected to expansion bus (8-bit or 16- bit) internal address value (internal _addr[1:0]) expansion bus address value (ex_addr[1:0] ) data location translation between expansion data bus and internal data bus
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1678 order number: 320066-003us once the cycle type has been determined, the mode of operation must be set. there are two configurable modes of operation for each chip select, multiplexed and non- multiplexed. bit 4 of the timing and control (exp_timing_cs) registers is used to select this mode. if bit 4 of the timing and control (exp_timing_cs) register is set to logic 1, the access mode for that chip select is multiplexed. likewise, if bit 4 of the timing and control (exp_timing_cs) register is cleared to logic 0, the access mode for that chip select is non-multiplexed. for synchronous intel, micron zbt memories bit 4 must be programmed to logic 0. multiplexed and non-multiplexed can imply different operations depending upon the cycle type that is selected. the size of the data bus for each device connected to the expansion bus must be configured. the data bus size is selected on a per-chip-select basis, allowing the most flexibility when connecting devices to the expansion bus. there are two valid selections that can be configured for each data bus size, 8-bit or 16-bit. bit 0 f each timing and control (exp_timing_cs) register is used to select the data bus size on a per-chip- select basis. each chip select can be independently enabled or disabled by setting a value in bit 31 of each timing and control (exp_timing_cs) register. clearing bit 31 of the timing and control (exp_timing_cs) register to logic 0 disables the corresponding chip select. setting bit 31 of the timing and control (exp_timing_cs) register to logic 1 enables the corresponding chip select. accesses to chip selects that are disabled result in an error response. split transfers are supported for all read transfer types and controlled by setting bit 3 (splt_en) of the timing and control (exp_timing_cs) register. setting bit 3 of each timing and control (exp_timing_cs) register to logic 1 enables split transfers for accesses to the corresponding chip select. clearing bit 3 of each timing and control (exp_timing_cs) register to logic 0 disables split transfers for accesses to the corresponding chip select. enabling split transactions allows for more efficient utilization of the internal bus, especially for slow external expansion bus devices. for higher performance devices with low read latencies, disabling split transactions may provide better performance. each chip select region has the ability to be write-protected by setting bit 1 of each timing and control (exp_timing_cs) register. when bit 1 of timing and control (exp_timing_cs) register is cleared to logic 0, writes to a specified chip select region results in an error response. when bit 1 of timing and control (exp_timing_cs) register is set to logic 1, writes are allowed to a specified chip select region. chip select 0 will be write-protected after reset. for chip selects 4 through 7 configured in hpi mode of operation, there is an associated ready bit (ex_rdy [3:0]). the ready bit is only used when the mode of operation is set to texas instruments hpi mode. the ready bits are used to hold off the host processor when the given dsp is not ready to complete the transfer. however, the polarity of this ready bit can vary based upon the dsp that is selected. bit 5 of each timing and control (exp_timing_cs) register allows the polarity used by each ready bit to be independently set. when bit 5 of the timing and control (exp_timing_cs) register is cleared to logic 0, the ready bit is cleared to respond to an active low signal (logic 0). when bit 5 of the timing and control (exp_timing_cs) register is set to logic 1, the ready bit is set to respond to an active high signal (logic 1). one final set of parameters that may be set prior to using expansion bus interface chip select 1 through chip select 8. after boot up, these parameters may be adjusted for chip select 0 as well. these five parameters are the timing extension parameters for each phase of an expansion bus access. there are five phases to every expansion bus access: ? t1 ? address timing ? t2 ? setup/chip select timing
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1679 intel ? ep80579 integrated processor ? t3 ? strobe timing ? t4 ? hold timing ? t5 ? recovery phase for synchronous intel mode, the t1,t2, t3, t4, t5 timing parameters are only used for writes. for synchronous intel reads, the expansion bus controller uses the count value programmed in the exp_syncintel_count register to determine how many cycles before data is valid (based on the timing parameters for a specific device) for micron zbt devices, the timing parameters must be programmed to all zero since reads and writes are synchronous. the expansion-bus address is used to presen t the 25 bits of the address [24:0] used for the expansion bus access accompanied by an address latch enable output signal, ex_ale for multiplexed devices. the address phase normally lasts two clock cycles in multiplexed mode. the address phase may be extended by one to three clock cycles using the t1 - address timing parameter, bits 29:28 in the timing and control (exp_timing_cs) register for the particular chip select. when the address phase t1 is extended, the ale pulse is extended and always deasserts one cycle prior to the end of the t1 phase. the lower address bits are placed onto the data bus (i.e for a 16 bit data bus, ex_data contains ex_addr[15:0]) along with ex_addr[24:0] signals during the first cycle of the address phase. during the second cycle of the address phase, the data bus now will output data when attempting to complete a write or tri- state when attempting to complete a read. th e address signals will retain their state. for synchronous intel and micron zbt devices, ex_ale acts as the address valid signal (adv#) and is logic 0 during the address phase and logic 1 during the continuation of a burst or idle cycle. due to the fact that, in hpi mode of operation, it is possible to begin an access to a busy device (ex_rdy is false), special consideration must be taken with programming the t1 ? address timing parameter when using the chip select in hpi mode. the t1 ? address timing parameter must be set to a minimum of two additional cycles (t1 must equal to 0x2). programming the t1 ? address timing parameter to this value ensures that the asynchronous ex_rdy input is sampled and available to the controlling hardware logic before beginning the new hpi access over the expansion bus. the chip-select signal is presented for one expansion bus phase before the strobe phase. the chip select will be presented for the remainder of the expansion bus cycles (setup, strobe, and hold phases). the setup/chip select timing phase may also be extended by one to three clock cycles, using bits 27:26 of the timing and control (exp_timing_cs) register, t2 ? setup/chip select timing parameter. in hpi mode of operation, t2 is defined as the time required by the external dsp device to drive ex_rdy false for the current access plus the time required by the expansion bus controller to sample and synchronize the ex_rdy signal. the t2 ? setup/chip select timing parameter must have a minimum value of two additional cycles (t2 >= 0x2). programming the t2 ? setup/chip select timing parameter to be three clock cycles in length ensures that when the strobe phase, t3, begins, the strobe phase will be able to sample the ex_rdy signal and exit the strobe phase at the proper time. the strobe phase of an expansion-bus access is when the read or write strobe is applied. the 25 expansion bus interface address bits are maintained in non- multiplexed mode or the expansion bus interface data bus is switched from address to data when configured in multiplexed mode during the strobe phase. the strobe phase may be extended from one to 15 clock cycles, as defined by programming bits 25:22 of the timing and control (exp_timing_cs) register, t3 ? strobe timing parameter. in hpi mode of operation, the t3 ? strobe timing parameter
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1680 order number: 320066-003us must have a minimum value of one additional cycle (t3 >= 0x1). programming the t3 ? strobe timing parameter to be two clock cycles in length ensures that any data sent to the dsp is captured regardless of when the ex_rdy signal is asserted by the dsp. the hold phase of an expansion-bus access is provided to allow a hold time for data to remain valid after the data strobe has transitioned to an invalid state. during a write access, the hold phase provides hold time for data written to an external device on the expansion bus, after the strobe pulse has completed. during a read access, the hold phase allows an external device time to release the bus after driving data back to the controller. the hold phase may be extended one to three clock cycles, using bits 21:20 of the timing and control (exp_timing_cs) register, t4 ? hold timing parameter. in hpi mode of operation, the hold phase is defined the same as described for the intel and motorola modes of operation, but must be set to a minimum value of one additional cycle (t4 >= 0x1). after the address and chip select is de-asserted, the expansion bus controller can be programmed to wait a number of clocks before starting the next expansion bus access. this action is referred to as the recovery phase. the recovery phase is may be extended one to 15 clock cycles using bits 19:16 of the timing and control (exp_timing_cs) register, t5 ? recovery timing parameter. in hpi mode of operation, the recovery phase is defined the same as described for the intel and motorola modes of operation. 42.4.1.4 using i/o wait the ex_iowait_n signal is available to be shared by devices attached to chip selects 0 through chip select 7, when configured in intel or motorola modes of operation. the shared device will assert ex_iowait_n in the t2 phase of a read or write transaction. during idle cycles, the board is responsible for ensuring that ex_iowait_n is pulled- up. additionally, ex_iowait_n must always be pulled high during micron zbt, intel synchronous mode, and hpi cycles. the expansion bus controller will ignore ex_iowait_n for synchronous intel mode transfers and use the exp_syncintel_count register for the wait state generation. when an external device asserts ex_iowait_n before the first cycle of a strobe phase of a read or write transaction, the expansion bus controller will hold in the strobe phase until the ex_iowait_n signal returns to an inactive state. since there is a synchronizer cell on ex_iowait_n, the external device must assert ex_iowait_n three cycles before the deassertion of ex_wr_n/ex_rd_n. this implies that the value programmed in the t2 and t3 phase cannot both be equal to zero. after ex_iowait_n is deasserted the expansion bus controller will only transition to the t4 - hold state after the t3 counter reaches zero. operation of ex_rdy signals is the same as the ex_iowait_n signal, but is defined primarily for the ?c54xx family of dsps. in addition, the ex_rdy signals will hold the current access in the address phase if detected during that phase. this event can happen if a busy dsp memory access is started before the previous access completes. figure 42-5 shows the operation of the ex_iowait_n signal. notice that the access is an intel style simplex read access. the data strobe phase is set to a value to last three clock cycles. the data is returned from the peripheral device prior to the three clocks and the peripheral device de-asserts ex_iowait_n. the data strobe phase terminates after two clocks even though the strobe phase was configured to pulse for three clocks.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1681 intel ? ep80579 integrated processor 42.4.1.5 parity the expansion bus controller generates even or odd parity for each byte written to ex_data and compares parity for each byte read on ex_data, if par_en is set in each exp_timing_cs register. ex_parity is transferred in the same clock cycle in which ex_data is transferred. if a read transfer results in a parity mismatch on ex_parity, the target address is logged in the exp_parity_status and outerrorsts is set. exp_parity_error will be asserted by the expansion bus controller during a parity error and an interrupt will be generated if enabled in the interrupt controller. exp_parity_error will remain asserted until software clears exp_parity_status register. even parity is defined as the number of 1?s on ex_data[7:0] and ex_parity[0] must be an even number. for example, if ex_data[7:0] = 0x25, ex_parity[0] must be 1, since there are 3 bits set on 0x25 and there needs to be an even number of 1s. parity for the second byte of ex_data is generated on ex_parity[1]. if par_en is cleared for a particular device, the expansion bus controller doesn?t generate or compare parity and ex_parity should not toggle to conserve power. odd parity can be enabled by setting oddpar in the exp_mst_control register and is equivalent to the inverted value of even parity. 42.4.1.6 special design knowledge for using hpi mode the expansion bus controller supports a number of the 8-bit and 16-bit versions of the texas instruments host port interface* (hpi) standards. this flexibility allows the tms320c54xx family of digital signals processors (dsp) to seamlessly interface to the expansion bus. figure 42-5. expansion bus i/o wait operation ex_addr valid address ex_clk ex_cs_n t1 (1cycle) t2 (1 cycle) ex_iowait_n t3 (3 cycles) t4 (1 cycle) t5 (1 cycle) ex_rd_n ex_data valid data
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1682 order number: 320066-003us however, there are some special things to note when using the expansion bus in hpi mode of operation. these features are shown in the following tables. there are also some restrictions on the timing parameters and these are outlined in section 42.4.1.3, ?expansion bus interface configuration? on page 1676 . the expansion-bus address-pins bits 0, 1, 2, 22, and 23 are multiplexed with special function signal pins for hpi as shown in ta b l e 4 2 - 3 . the byte identification signal, ex_hbil, is used to determine the byte transfer order. (ex_hbil is driven low for the first byte of the transfer and driven high for the second byte.) the byte order bit (bob) in the hpic register (contained in the dsp) ? within the hpi device ? is used to determine the placement for the two bytes of the transfer. please consult the datasheet of the specific dsp being connected to determine the order of the transferred bytes. when operating in hpi mode, bits 13:10 in the timing and control (exp_timing_cs) registers are ignored. when operating in hpi-16, non-multiplexed mode, the expansion bus address bus provides direct accesses to the dsp memory space. the data associated with this address will be read or written from the location specified by the value contained on the expansion bus address bits.the signals ex_hcntl [1:0] are multiplexed onto the ex_addr [2:1] pins. when communicating to a multiplexed hpi interface, the ex_hcntl [1:0] signals are used to select one of four internal registers used for interfacing to the dsp. the ex_hcntl [1:0] mapping is described in the table 42-4 . 42.4.1.7 expansion bus outbound timing diagrams the state signal that is shown in some of the following timing diagrams is the internal state of the expansion bus controller. table 42-3. multiplexed output pins for hpi operation hpi control signal output signal pin ex_hbil ex_addr [0] ex_hcntl [1:0] ex_addr [2:1] ex_hcsel [1:0] ex_addr [23:22] table 42-4. hpi hcntl control signal decoding hcntl[1:0] required access 00 read / write control register (hpic) 01 read / write data register (hpid) hpi-8: post-increment hpia on reads, pre-increment on writes. hpi-16: post-increment hpia on reads and writes 10 read / write address register (hpia) 11 read / write data register (hpid)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1683 intel ? ep80579 integrated processor 42.4.1.7.1 intel, multiplexed-mode write access 42.4.1.7.2 intel, multiplexed-mode read access figure 42-6. expansion-bus write (intel, multiplexed mode) figure 42-7. expansion-bus read (intel, multiplexed mode) t5 (1-16 cycles) ex_addr valid address ex_ale ex_wr_n output data ex_data ex_clk ex_cs_n address t1 (2-5 cycles) ale extended multi p lexed address / t2 (1-4 cycles) t3 (1- 16 c y cles) t4 (1-4 cycles) t5 (1-16 cycles) ex_addr valid address ex_ale ex_clk ex_cs_n t1 (2-5 cycles) ale extended ex_rd_n input data ex_data address t2 (1-4 cycles) t3 (1-16 cycles) t4 (1-4 cycles)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1684 order number: 320066-003us 42.4.1.7.3 intel-simplex-mode and synchronous intel write access 42.4.1.7.4 intel, simplex-mode read access figure 42-8. expansion-bus write (intel-simplex mode, synchronous intel) figure 42-9. expansion-bus read (intel, simplex mode) ex_addr ex_wr_n output data ex_data ex_clk ex_cs_n t1 (1-4 cycles) t2 (1-4 cycles) t3 (1- 16 c y cles) t4 (1-4 cycles) t5 (1-16 cycles) ex_addr valid address ex_clk ex_cs_n t1 (1-4 cycles) ex_rd_n input data ex_data t2 (1-4 cycles) t3 (1-16 cycles) t4 (1-4 cycles) t5 (1-16 cycles)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1685 intel ? ep80579 integrated processor 42.4.1.7.5 synchronous intel 8-word read access the above timing diagram shows an 8-word read to a synchronous intel device such as synchronous intel strataflash. depending on the ex_clk period, the latency count bits in the intel synchronous device read configuration register needs to be programmed appropriately based on the timing parameters for the specific device. the expansion bus controller will always wait in cycles 1 and 2, regardless of ex_iowait_n. the device will then assert ex_iowait_n for several cycles and deassert ex_iowait_n when its ready to transfer data. after the device deasserts ex_iowait_n, it will transfer the remaining words until all 8 words are transferred. the expansion bus controller and synchronous intel device both support wrapping for 8-word reads, therefore addr0 is not always aligned to an 8-word boundary. the state signal shows the internal expansion bus state. figure 42-10.intel synchronous 8-word read intel synchronous 8-word read ex_clk -0 - -1 - -2 - - 3 - - 4 - - 5 - - 8 - - 9 - ex _cs_n ex_addr ex_ale ex_rd_n ex_wr_n ex_be_n ex_iowait _n ex _data ex_parity state - 10 - addr0 data0 data 0_hi par0_hi data1 address idle data 0_ lo data 7_hi data 7_ lo par 0_hi par7 _hi data6 data7 par7 _lo idle wait wait
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1686 order number: 320066-003us 42.4.1.7.6 synchronous intel 1-word read access figure 42-11.intel synchronous one-word read intel synchronous 1-word read state data_hi idle address idle wait wait data_lo data_lo ex_clk -0 - -1 - -2 - - 3 - - 4 - - 5 - - 6 - ex_cs_n ex_addr ex_ale ex_rd_n ex_wr_n ex_be_n ex_iowait _n ex_data ex_parity addr0 data_hi par_hi par_ lo
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1687 intel ? ep80579 integrated processor 42.4.1.7.7 micron* zbt write/read/write access figure 42-12 shows a write to a micron zbt device followed by a read and then followed by another read. the device will never assert ex_iowait_n for this mode. figure 42-12.micron* zbt write/read/write micron zbt write/read/write state data0 address data0 address idle address data0 idle ex_clk -0 - -1 - -2 - -3 --4 --5 --6 --7 --8 - ex _cs_n ex_addr ex_ale ex_rd_n ex_wr_n ex_be_n ex_iowait _n ex _data ex_parity addrx datax parx bex addry addrz bez dataz parz datay pary
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1688 order number: 320066-003us 42.4.1.7.8 motorola*, multiplexed-mode write access figure 42-13.expansion-bus write (motorola*, multiplexed mode) ex_addr valid address ex_ale ex_rd_n (exp_mot_rnw) output data ex_data ex_clk ex_cs_n address t1 (2-5 cycles) ale extended multi p lexed address / t2 (1-4 cycles) t3 (1-16 cycles) t4 (1-4 cycles) t5 (1-16 cycles) ex_wr_n (exp_mot_ds_n)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1689 intel ? ep80579 integrated processor 42.4.1.7.9 motorola*, multiplexed-mode read access figure 42-14.expansion-bus read (motorola*, multiplexed mode) ex_addr valid address ex_ale ex_clk ex_cs_n t1 (2-5 cycles) ale extended ex_wr_n (exp_mot_ds_n) input data ex_data address t2 (1-4 cycles) t3 (1-16 cycles) t4 (1-4 cycles) t5 (1-16 cycles) ex_rd_n (exp_mot_rnw)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1690 order number: 320066-003us 42.4.1.7.10 motorola*, simplex-mode write access 42.4.1.7.11 motorola*, simplex-mode read access figure 42-15.expansion-bus write (motorola*, simplex mode) figure 42-16.expansion-bus re ad (motorola*, simplex mode) ex_addr valid address ex_rd_n (exp_mot_rnw) output data ex_data ex_clk ex_cs_n t2 (1-4 cycles) t3 (1-16 cycles) t4 (1-4 cycles) t5 (1-16 cycles) ex_wr_n (exp_mot_ds_n) t1 (1-4 cycles) ex_addr valid address ex_clk ex_cs_n ex_wr_n (exp_mot_ds_n) input data ex_data t2 (1-4 cycles) t3 (1-16 cycles) t4 (1-4 cycles) t5 (1-16 cycles) ex_rd_n (exp_mot_rnw) t1 (1-4 cycles)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1691 intel ? ep80579 integrated processor 42.4.1.7.12 ti* hpi-8 write access figure 42-17.expansion-bus write (ti* hpi-8 mode) ex_ addr [2:1] (hcntl) ex_ addr [0] ( hbil) ex_rdy_n (hrdy) data ex_ data (hdin) ex_cs_n (hcs_n) ex_ wr_n ( hds1_n) ex_ rd_n (hr_w_n) valid data valid ex_ clk t1 t3 t4 t3 t2 t4 t5 t1 t2 t5 tadd _setup t cs2 h d s1 va l thds 1_ pulse tdata _setup tdata _ hold trecov hpi-8 write
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1692 order number: 320066-003us 42.4.1.7.13 ti* hpi-8 read access figure 42-18.expansion-bus read (ti* hpi-8 mode) revision 001 hpi-8 read t 1 t 3 t 2 t 4 t 5 t 2 t 1 ex_clk ex_cs_n (hcs_n) ex_addr[2:1] (hcnt) ex_rd_n (hr_w_n) ex_addr[0] (hbit ) ex_wr_n (hds_n) ex_rdy_n (hrdy) ex_data (hdout) t add_setup trecov valid tcs2hds1va thds1_pulse tdata_setup byte 1 byte 2 valid
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1693 intel ? ep80579 integrated processor 42.4.1.7.14 ti* hpi-16, multiplexed-mode write access figure 42-19.expansion-bus write (ti* hpi-16, multiplexed mode) data valid data valid t1 t3 t4 t3 t2 t4 t1 t2 t5 ex_ addr [2:1] (hcntl) ex_ rdy_n (hrdy) ex_ data ( hdin) ex_cs_n (hcs_n) ex_ wr_n (hds1_n) ex_rd_n (hr_w_n) ex_ clk tadd _ setup thds1_pulse tcs2 hds1val tdata_setup tdata_ hold trecov hpi-16 mux write
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1694 order number: 320066-003us 42.4.1.7.15 ti* hpi-16, multiplexed-mode read access figure 42-20.expansion-bus read (ti* hpi-16, multiplexed mode) ` b-01 valid valid data valid data t1 t3 t4 t3 t2 t4 t5 t1 t2 t5 ex_ addr [2:1] (hcntl) ex_rdy_n (hrdy) ex_ data ( hdout) ex_ cs_n (hcs_n) ex_wr_n ( hds1_n) ex_ rd_n (hr_w_n) ex_clk tadd_setup trecov thds1_pulse tdata_setup tcs2hds1val hpi-16 mux read
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1695 intel ? ep80579 integrated processor 42.4.1.7.16 ti* hpi-16, simplex-mode write access figure 42-21.expansion-bus write (ti* hpi-16, simplex mode) data valid data valid t1 t3 t4 t3 t2 t4 t1 t2 t5 b-01 ex_addr[23:0] (ha) ex_rdy_n (hrdy) ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup trecov thds1_pulse tcs2hds1val tdata_setup tdata_hold hpi-16 simplex write
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1696 order number: 320066-003us 42.4.1.7.17 ti* hpi-16, simplex-mode read access 42.5 register summary accesses to expansion bus registers are only via 32-bit transfers. other sized accesses result in unpredictable operation. accesses to all reserved bits must be written with zero unless otherwise specified. all reserved address spaces must not be read. all writes to reserved address spaces results in unpredictable operation. for more information on the conventions the following register summaries adopt, see section 7.1, ?overview of register descriptions and summaries? on page 183 . the local expansion bus registers materialize in the pci space. ta b l e 4 2 - 5 summarizes the local expansion bus materialization from the pci perspective. figure 42-22.expansion-bus read (ti* hpi-16, simplex mode) b-01 valid valid data valid data valid t1 t3 t4 t3 t2 t1 t2 t5 ex_addr[23:0] (ha) ex_rdy_n (hrdy) ex_data (hdout) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup tdata_setup thds1_pulse tcs2hds1val trecov hpi-16 simplex read
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1697 intel ? ep80579 integrated processor table 42-5. bus m, device 8, function 0: summary of local expansion bus registers mapped through csrbar pci memory bar" offset start offset end register id - description default value 00000000h 00000003h ?exp_timing_cs0 - expansion bus timing register? on page 1698 bfff3c40h 00000004h at 4h 00000007h at 4h ?exp_timing_cs[1-7] - expansion bus timing registers? on page 1700 00000000h 00000020h 00000020h ?exp_cnfg0 -configuration register 0? on page 1702 00000040h 00000120h 00000123h ?exp_parity_status - expansion bus parity status register? on page 1703 00000000h
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1698 order number: 320066-003us 42.5.1 timing and control registers 42.5.1.1 exp_timing_cs0 - expansion bus timing register the exp_timing_cs registers may only be written if there is not an outstanding expansion bus transaction. software must ensure that all outstanding expansion bus transfers are complete before changing the exp_timing_cs registers. table 42-6. exp_timing_cs0 - expansion bus timing register description: timing and control registers view: pci bar: csrbar bus:device:function: m:8:0 offset start: offset end: 00000000h 00000003h size: 32 bit default: bfff3c40h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 csx_en 0 = chip select x disabled 1 = chip select x enabled 1b rw 30 par_en 0 = parity is not generated or compared 1 = parity is generated and compared parity is only supported for intel, motorola, and micron zbt modes. 0b rw 29 : 28 t1_addr_tm t1 ? address timing 00 = generate normal address phase timing 01 - 11 = extend address phase by 1 - 3 clocks 11b rw 27 :26 t2_su_cs_tm t2 ? setup / chip select timing 00 = generate normal setup phase timing 01 - 11 = extend setup phase by 1 - 3 clocks 11b rw 25 : 22 t3_strb_tm t3 ? strobe timing 0000 = generate normal strobe phase timing 0001-1111 = extend strobe phase by 1 - 15 clocks 1111b rw 21 : 20 t4_hold_tm t4 ? hold timing 00 = generate normal hold phase timing 01 - 11 = extend hold phase by 1 - 3 clocks 11b rw 19 : 16 t5_rcvry_tm 0000 = generate normal recovery phase timing 0001-1111 = extend recovery phase by 1 - 15 clocks 1111b rw 15 :14 cyc_type 00 = configures the expansion bus for intel cycles. 01 = configures the expansion bus for motorola cycles. 10 = configures the expansion bus for hpi cycles. (hpi reserved for chip selects [7:4] only) 11 = configures the expansion bus for micron zbt cycles 00b rw 13 : 09 cnfg_4_0 device configuration size. calculated using the formula: size of addr space = 2 (9+cnfg[4:1]+16*cnfg[0]) for example: 00000 = address space of 2 9 = 512 bytes 00010 = address space of 2 10 = 1024 bytes ? 10000 = address space of 2 17 = 128 kbytes ? 11100 = address space of 2 23 = 8 mbytes 11110 = address space of 2 24 = 16 mbytes xxxx1 = address space of 2 25 = 32mbytes 11110b rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1699 intel ? ep80579 integrated processor 08 sync_intel synchronous intel strataflash ? select. this bit must be 0 if cyc_type is not programmed to intel cycles. 0 = target device is not a synchronous intel strataflash 1 = target device is a synchronous intel strataflash 0b rw 07 exp_chip 0 = target device is not an ep80579 1 = target device is an ep80579. this bit must only be set to 1 when cyc_type is configured to be intel cycles and sync_intel is set to 0. 0b rw 06 byte_rd16 byte read access to half word device 0 = byte access disabled. 1 = byte access enabled. 1b rw 05 hrdy_pol hpi hrdy polarity (reserved for exp_cs_n[7:4] only) 0 = polarity low true. 1 = polarity high true. 0b rw 04 mux_en 0 = separate address and data buses. 1 = multiplexed address / data on data bus. 0b rw 03 splt_en 0 = internal bus split transfers disabled. 1 = internal bus split transfers enabled. 0b rw 02 reserved reserved. this bit must be written with a ?0?. writing a ?1? will result in unpredictable behavior. 0b rw 01 wr_en 0 = writes to cs region are disabled. 1 = writes to cs region are enabled. 0b rw 00 byte_en 0 = expansion bus uses 16-bit-wide data bus 1 = expansion bus uses only 8-bit data bus 0b rw table 42-6. exp_timing_cs0 - expansion bus timing register description: timing and control registers view: pci bar: csrbar bus:device:function: m:8:0 offset start: offset end: 00000000h 00000003h size: 32 bit default: bfff3c40h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1700 order number: 320066-003us 42.5.1.2 exp_timing_cs[1-7] - expansion bus timing registers the exp_timing_cs registers may only be written if there is not an outstanding expansion bus transaction. software must ensure that all outstanding expansion bus transfers are complete before changing the exp_timing_cs registers. table 42-7. exp_timing_cs[1-7] - expansion bus timing registers (sheet 1 of 2) description: timing and control registers view: pci bar: csrbar bus:device:function: m:8:0 offset start: offset end: 00000004h at 4h 00000007h at 4h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 csx_en 0 = chip select x disabled 1 = chip select x enabled 0h rw 30 par_en 0 = parity is not generated or compared 1 = parity is generated and compared parity is only supported for intel, motorola, and micron zbt modes. 0h rw 29 : 28 t1_addr_tm t1 ? address timing 00 = generate normal address phase timing 01 - 11 = extend address phase by 1 - 3 clocks 0h rw 27 :26 t2_su_cs_tm t2 ? setup / chip select timing 00 = generate normal setup phase timing 01 - 11 = extend setup phase by 1 - 3 clocks 0h rw 25 : 22 t3_strb_tm t3 ? strobe timing 0000 = generate normal strobe phase timing 0001-1111 = extend strobe phase by 1 - 15 clocks 0h rw 21 : 20 t4_hold_tm t4 ? hold timing 00 = generate normal hold phase timing 01 - 11 = extend hold phase by 1 - 3 clocks 0h rw 19 : 16 t5_rcvry_tm t5 ? recovery timing 0000 = generate normal recovery phase timing 0001-1111 = extend recovery phase by 1 - 15 clocks 0h rw 15 :14 cyc_type 00 = configures the expansion bus for intel cycles. 01 = configures the expansion bus for motorola cycles. 10 = configures the expansion bus for hpi cycles. (hpi reserved for chip selects [7:4] only) 11 = configures the expansion bus for micron zbt cycles 0h rw 13 : 09 cnfg_4_0 device configuration size. calculated using the formula: size of addr space = 2 (9+cnfg[4:1]+16*cnfg[0]) for example: 00000 = address space of 2 9 = 512 bytes 00010 = address space of 2 10 = 1024 bytes ? 10000 = address space of 2 17 = 128 kbytes ? 11100 = address space of 2 23 = 8 mbytes 11110 = address space of 2 24 = 16 mbytes xxxx1 = address space of 2 25 = 32mbytes 0h rw
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1701 intel ? ep80579 integrated processor note: the seven exp_timing_cs[1-7] registers have following starting offsets: 00000004h - exp_timing_cs1 00000008h - exp_timing_cs2 0000000ch - exp_timing_cs3 00000010h - exp_timing_cs4 00000014h - exp_timing_cs5 00000018h - exp_timing_cs6 0000001ch - exp_timing_cs7 08 sync_intel synchronous intel strataflash ? select. this bit must be 0 if cyc_type is not programmed to intel cycles. 0 = target device is not a synchronous intel strataflash 1 = target device is a synchronous intel strataflash 0h rw 07 exp_chip 0 = target device is not an ep80579 1 = target device is an ep80579. this bit must only be set to 1 when cyc_type is configured to be intel cycles and sync_intel is set to 0. 0h rw 06 byte_rd16 byte read access to word device 0 = byte access disabled. 1 = byte access enabled. 0h rw 05 hrdy_pol hpi hrdy polarity (reserved for exp_cs_n[7:4] only) 0 = polarity low true. 1 = polarity high true. 0h rw 04 mux_en 0 = separate address and data buses. 1 = multiplexed address / data on data bus. 0h rw 03 splt_en 0 = internal bus split transfers disabled. 1 = internal bus split transfers enabled. 0h rw 02 reserved reserved. this bit must be written with a ?0?. writing a ?1? will result in unpredictable behavior. 0h rw 01 wr_en 0 = writes to cs region are disabled. 1 = writes to cs region are enabled. 0h rw 00 byte_en 0 = expansion bus uses 16-bit-wide data bus 1 = expansion bus uses only 8-bit data bus 0h rw table 42-7. exp_timing_cs[1-7] - expansion bus timing registers (sheet 2 of 2) description: timing and control registers view: pci bar: csrbar bus:device:function: m:8:0 offset start: offset end: 00000004h at 4h 00000007h at 4h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1702 order number: 320066-003us 42.5.2 configuration and status registers 42.5.2.1 exp_cnfg0 - configuration register 0 at power up or whenever reset_in_n is asserted, the expansion-bus address outputs are switched to inputs and the states of the bits are captured and stored in configuration register 0. this occurs when reset_out_n is deasserted. only bits ex_addr[23:21] are used. these configuration bits are made available to the system as outputs from the expansion bus controller block. the bits are read-only. table 42-8. exp_cnfg0 -configuration register 0 description: defines the reset-time configuration straps. view: pci bar: csrbar bus:device:function: m:8:0 offset start: offset end: 00000020h 00000020h size: 32 bit default: 00000040h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 :24 rsvd reserved 0h ro 23 :21 leb_size these bits are initialized from ex_addr[23:21] at reset using the reset-time strapping mechanism described above. this field always contains the value read from the straps at reset and is not updated in the event bios over- rides the value of leb_size. the effect of these bits is defined in table 35-159, ?mmbar addr field behavior? on page 1325 xro 20 :11 rsvd reserved 0h ro 10 exiow 1 = ex_iowait_n is sampled during the read/write expansion bus cycles as defined in section 42.4.1.4, ?using i/o wait? on page 1680 for chip select 0. 0 = ex_iowait_n is ignored for read and write cycles to chip select 0 if exp_timing_cs0 is configured to intel mode. typically, iowait_cs0 must be pulled down to vss when attaching a synchronous intel strataflash on chip select 0 since the default mode for exp_timing_cs0 is intel mode and ex_iowait_n is an unknown value for synchronous intel strataflash. if the board does not connect the synchronous intel strataflash wait pin to ex_wait_n (and the board guarantees ex_iowait_n is pulled up), the value of iowait_cs0 is a don?t care since ex_iowait_n will not be asserted. when exp_timing_cs0 is reconfigured to intel synchronous mode during boot-up (for synchronous intel chips), the expansion bus controller ignores ex_iowait_n during read and write cycles since the wait functionality is determined from the exp_syncintel_count and exp_timing_cs registers. 0h ro 9 :7 rsvd reserved 0h ro 6 rsvd reserved 1h ro 5 rsvd reserved 0h ro 4 rsvd reserved 0h rw 3 :0 rsvd reserved 0h ro
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1703 intel ? ep80579 integrated processor 42.5.2.2 exp_parity_status - expansion bus parity status register outerrorsts is generated to forms exp_parity_error which is routed to the interrupt controller and can generate interrupts to the processor core. in the event of multiple outbound parity errors, there is a race condition between when software performs a write to clear the exp_parity_status register and setting the inerrorsts/outerrorsts error bit in hardware. if the software clears the error bit before another parity error, the exp_parity_status register will be set again. however if softwa re clears the error bit on or after another parity error, the exp_parity_sta tus register will be cleared. 42.6 performance estimation the bandwidth that can be supported on the expansion bus depends on the latencies through the system and the nature of the protocol on the expansion bus. all latencies are dependent on whether the transaction is read or write. table 42-9. exp_parity_status - expansion bus parity status register description: specifies the parity error status. view: pci bar: csrbar bus:device:function: m:8:0 offset start: offset end: 00000120 h 00000123h size: 32 bit default: 00000000h power well: core bit range bit acronym bit description sticky bit reset value bit access 31 : 02 erroraddr address corresponding to the parity error for outbound transactions, the derivation of this address is as follows: ? erroraddr = internal_bus_addr[31:5] & ex_addr[4:2] internal_businternal_businternal_businternal_busif multiple parity errors occur (eg- multiple parity errors within a multi-word transfer/burst; or additional parity errors detected on subsequent transactions), then erroraddr contains the address of the first parity error. after receiving a parity error, the erroraddr is locked until outerrorsts is cleared by software. if another parity error occurs prior to the interrupt and exp_parity_status being cleared, then the subsequent parity errors will not be trapped nor will the address be logged. as a result, only the first errored transaction will be dropped, but the subsequent (errored) transaction(s) will be completed. note: erroraddr will not be unlocked until the current transaction is complete. 0h ro 01 rsvd reserved 0h rwc 00 outerrorsts a parity error occurred on an outbound read. this bit will not get set unless par_en is set in the exp_timing_cs for which the parity error has occurred. 0h rwc
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1704 order number: 320066-003us each specific protocol supported by the expansion has it?s own set of timing parameters as described by the number cycles required for t1, t2, t3, t4 and t5. the reader is referred to section 42.4, ?theory of operation? for explanation of these parameters. additionally, the number of wait states required contributes additional cycles required for a given transaction and will reduce the bandwidth. estimated system latencies expressed in terms of expansion bus clock cycles are shown in table 42-10 . the estimated bandwidth for a given platform configuration is determined as: bw (mbit/s) = transactionsize * leb_freq / totallatency where: ? transactionsize is size of the transaction expressed in bits ? leb_freq is the frequency of the external clock being used to clock the expansion bus ? totallatency is the sum of: ? sytemlatency + t1 + t2 + t3 + t4 + t5 + wait states note: the appropriate values for these latencies must be used dependending on whether the transaction is a read or a write. note: this estimate applies to a single, serialized request at the entry to the aioc (pci-to- pci bus m bridge) onto the expansion bus note: note: the system is assumed to be otherwise quiescent. no competing traffic on the internal buses is considered. note: these latencies comprehend only those from the time an ia initiated transaction is received at the aioc to the time the aioc completes the transaction. no ia, fsb, mch, software, etc latencies are included. ta b l e 4 2 - 1 1 provides example estimates for various platform configurations. table 42-10. leb performance calculation - estimated aioc latencies aioc internal bus (mhz) leb (mhz) aioc latency read (leb cycles) aioc latency write (leb cycles) 400 80 31 27 533 80 24 21 800 80 22 19 400 66 26 22 533 66 19 17 800 66 17 15
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1705 intel ? ep80579 integrated processor note: these examples assume 0 wait states introduced by the external leb device. the latency of the attached device must be taken into account for specific applications. table 42-11. outbound performance estimation examples example a write example a read example b write example b read example c write example c read expansion bus (mhz) 80 80 80 80 80 80 aioc internal bus (mhz) 400 400 533 533 800 800 transaction size(bits) 32 32 32 32 32 32 aioc latency 27 31 21 24 19 22 wait states 00 00 00 t1 11 11 11 t2 23 23 23 t3 12 12 12 t4 11 11 11 t5 11 11 11 total latency 33 39 27 32 25 30 mbits/s 77 66 95 80 102 85
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1706 order number: 320066-003us
order number: 320066-003us test and debug, volume 5 of 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1708 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1709 intel ? ep80579 integrated processor 43.0 global design for test features 43.1 jtag 43.1.1 jtag functions overview the jtag functionality, has the following attributes. ? the jtag tap controller is compliant with the ieee 1149.1 specification . ? the jtag block supports the tap controllers in ia-32 core and imch. ? the jtag block supports the io boundary scan requirement implementing all the mandatory and some optional instructions from the ieee 1149.1 specification. 43.1.2 ep80579 tap controllers the jtag test access port (tap) controller requires 4 input pins: test reset ( trst# , active low), test clock ( tck ), test mode select ( tms ) and the serial test data in ( tdi ). tms controls tsoche tap state transitions. the tap has one output pin, the serial test data out ( tdo ). 43.1.2.1 ia-32 core there are two jtag test access port (tap) controllers: one in the ia-32 core, and one ?master? tap in the mch. the ia-32 core tap is present as a result of the soc integration and performs no jtag functions besides bypass and idcode. 43.1.2.2 mch tap extension the tap controller in the imch (in the cmi), is the master. it executes all of the ieee 1149/1 compliant jtag and boundary scan functions in the ep80579. serial taps have the issue that they have a bypass register length >1. this is not desirable from a ieee 1149.1 compliance standpoint. to get around this, two bsdls are published, one each for the imch and ia-32 core. the imch tap acts as the master tap, supporting the public instructions for customer usage. the ia-32 core tap?s public boundary scan instructions, while still supported and available, do not perform any meaningful function since the ia-32 core?s tap does not control any io pins directly. the appropriate boundary scan functionality is performed by the corresponding instructions in the imch tap controller. both taps support the bypass and idcode instructions. this is summarized in ta b l e 4 3 - 1 .
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1710 order number: 320066-003us 43.1.3 ep80579 jtag id codes on account of the multiple taps, the ep80579 supports and displays multiple idcodes. this is described below in ta bl e 4 3 - 2 . 43.1.4 special requirem ents and limitations the jtag implementation has the following requirements for proper jtag operation. ? for proper boundary scan operation, the following gbe reset pins need to be in the specified states: sys_pwr_ok = 1 and aux_pwr_good = 1 . this requirement is true even if the gbe units are disabled. these additional non-jtag pins must be automatically driven to the proper values by the platform's power-up devices when the ep80579 is powered up for boundary scan testing. ? several high-speed interfaces and critical system reset and power related pins have been removed from the boundary scan chain. these are documented in section 43.2.1, ?jtag boundary scan? . 43.1.5 jtag instructions summary: mch the table in this section summarizes the ep80579-specific jtag instructions implemented in the mch section of the chip. the jtag instructions are classified as follows: ? public : these instructions are available to anyone. table 43-1. ep80579 taps public instructions public instruction mch tap controller vmc tap controller bypass supported supported idcode ep80579 idcode; unique per ep80579 silicon stepping ia-32 core idcode; fixed for all products using the core extest boundary scan for ep80579 ios implemented, but not connected to any io pads table 43-2. ep80579 tap idcode values jtag tap controller idcode comments imch (ep80579) 32?h 0e66_0013 the 4 msbs are incremented for each ep80579 silicon stepping (major or minor) ia-32 core 32?h 0b36_0013 fixed for all products and steppings using this core
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1711 intel ? ep80579 integrated processor table 43-3. jtag instructions summary for mch opcode (8?hxx) instruction register size type special impltn. section description 00 extest 884 public - section 45.2.1.1.1 boundary scan -- extest 01 samppre 884 public - section 45.2.1.1.2 boundary scan -- sample preload 02 idcode 32 public - section 45.2.1.1.3 idcode 03 reserved not implemented 05-07 reserved not implemented 08 highz 0 public - section 45.2.1.1.4 boundary scan -- highz 09 reserved not implemented ff bypass 0 public - section 45.2.1.1.5 bypass 16-1b reserved not implemented 43-46 reserved not implemented 6c-6f reserved not implemented
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1712 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1713 intel ? ep80579 integrated processor 43.2 i/o testing the ep80579 implements jtag boundary scan to allow testing of the i/o pins. 43.2.1 jtag boundary scan the ep80579 implements ieee 1149.1 compliant jtag boundary scan (bscan) on all its interfaces withthe exception noted below. the three high-speed interfaces, pcie, sata and usb2 did not implement jtag bscan. these are tested with an xor chain that covers the afes of all 3 interfaces ( section 46.2.3, ?xor chains? ). in addition, several compliance pins were excluded from the bscan chain to ensure proper functionality. these are listed in table 43-4 . the boundary scan chain is defined in the ep80579 bsdl file. 43.2.1.1 pins excluded from boundary scan chain several critical compliance pins were excluded from the boundary scan chain. these are listed below in ta b l e 4 3 - 4 . table 43-4. compliance pins excluded from boundary scan chain interface excluded pin(s) rtc rtcx1, rtcx2, rtest_n ich misc intvrmen power mgmt pwrok, rsmrst_n smbus intruder_n cru clks100, clkp100, clkn100 leb exrcmp, exrcmn ddr d_rcompx, d_ddrcres[2:0], d_drvcres, d_slewcres vc signal xxthrmdc_out, xxthrmda_in, xxtpcd_out, xxtpcl_out, xxhfpll_out gbe gbe_rcompp, gbe_rcompn, sys_pwr_ok, gbe_aux_pwr_good
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1714 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1715 intel ? ep80579 integrated processor 44.0 ia-32 core the testability features supported by the ia-32 core integrated into intel ? ep80579 integrated processor are described in this section. 44.1 jtag the ia-32 core tap (test access port) complies with the ieee 1149.1 (?jtag?) test architecture standard. the tap implements an instruction set of 6 functions as follows: ? sample/preload ?extest ?clamp ?highz ?idcode ?bypass 44.1.1 usage there are seven 1149.1-defined public instructions implemented in the ia-32 core tap. these instructions are described in ta b l e 4 4 - 1 . these instructions select from among three different tap data registers ? the boundary scan, device id, and bypass registers. table 44-1. 1149.1 public instructions in the ia-32 core tap tap instruction (op-code) function during stopclk data register selected action during... rt/idle capture-dr shift-dr update-dr sample/ preload (0000001) yes boundary scan ? sample all ia- 32 core pins shift bscan reg update bscan reg. outputs extest (0000000) yes boundary scan ? sample all ia- 32 core pins shift bscan reg update ia-32 core outputs clamp (0000100) yes bypass ? reset bypass reg shift bypass reg ? highz (0001000) yes bypass ? reset bypass reg shift bypass reg ? idcode (0000010) yes device id ? load ia-32 core id code shift id reg ? bypass (1111111) yes bypass ? reset bypass reg shift bypass reg ?
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1716 order number: 320066-003us the operation of these instructions is summarized as follows: ? sample/preload : this is the boundary scan command. the ia-32 core operates normally. ia-32 core pins are sampled into the boundary scan register on capturedr, shifted out on shiftdr. ? extest : same as sample, except the ia-32 core outputs are driven directly from the boundary scan register (so that the external pins wiggle as you shift the results out). ? clamp : the ia-32 core outputs are driven directly from the previously-loaded value in the boundary scan register; the 1-bit tap bypass register is connected between tdi and tdo. ? highz : all outputs of the ia-32 core are driven to their high-impedance state. ? idcode : the ia-32 core operates normally; the device id register is read using this tap instruction. the idcode returned contains the fields described in ta b l e 4 4 - 2 . ? bypass : the ia-32 core operates normally; tap pins tdi and tdo access the 1- bit bypass register. 44.1.1.1 description full details of the operation of these public instructions can be found in the 1149.1 standard. please note that the op-codes for the public instructions are an intel standard and do not vary from processor to processor. the contents of the device id register are shown in ta b l e 4 4 - 2 . note that the version number changes for each stepping. the rest of the fields do not change during the life of the product. ia-32 core idcode value is xb360013h, where x represent the stepping number (x=0000 for a-0). table 44-2. device id register bit-fields field name bit position(s) value function version number 31-28 xxxx (0000 for a-0) what version of ia-32 core this unit is. should increment with each stepping part number 27-12 1011001101100000 (request number 101100) (product 11011) (end user/market 00000) number chosen by intel to describe what part this is. manufacturer identity 11-1 00000001001 identity code that uniquely identifies intel. device id register implemented 0 1 must always be a 1 if the device id register exists.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1717 intel ? ep80579 integrated processor 45.0 imch design for test 45.1 imch design for test features 45.1.1 features the imch includes a number of design for test features. these features are described this section. 45.2 jtag 45.2.1 imch jtag instructions ta bl e 4 5 - 1 below lists the jtag chains, their public or private designation, the chain length, and a short descriptive name. the chains are described in more detail in later sections. due to the nature of the jtag design in ep80579, there are two operating modes in which the instructions below are accessible. in the default serial mode (i.e. mch jtag + ia-32 core jtag), the tdi value represents the full input instruction required. 45.2.1.1 jtag chain details descriptions follow for the jtag chain. 45.2.1.1.1 extest the extest instruction allows circuitry or wiring external to the devices to be tested. output boundary scan register cells are used to apply stimulus, while boundary scan cells at the inputs pins are used to capture data. i/o cells can be used for either purpose, depending on the value set in the corresponding output enable cell. note that some signals are prevented from driving out during extest: xxpwrgd, xxrstinn, and xxextintrnn. table 45-1. imch jtag instructions mnemonic parallel mode ir hex serial mode ir hex public chain length description extest 00000000 00 000000001111111 007f public 884 extest samppre 00000001 01 000000011111111 00ff public 884 sample preload idcode 00000010 02 000000101111111 017f public 32 idcode highz 00001000 08 000010001111111 047f public 0 highz bypass 11111111 ff 111111111111111 7fff public 0 bypass
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1718 order number: 320066-003us 45.2.1.1.2 sample/preload the sample/preload instruction is used to allow scanning of the boundary scan register without causing interference to the normal operation of the device. two functions can be performed by use of the sample/preload instruction. sample - allows a snapshot of the data flowing into and out of the device to be taken without affecting the normal operation of the device. preload - allows an initial pattern to be placed into the boundary scan register cells. this allows initial known data to be present prior to the selection of another boundary scan test operation. 45.2.1.1.3 idcode this instruction is used to determine the manufacturer, part number, and revision level of the device being accessed. this instruction selects only the device identification register to be connected for serial access between tdi and tdo in the shift-dr controller state. when this instruction is selected, the operation of the test logic shall have no effect on the operation of the on-chip system logic. reading the idcode returns a single value. the id consists of 6 fields. the first field is for the version and stepping of the device. the part number field contains 3 fields. field #1 is the product category, and for a server, has a value of ?000 100? binary. field #2 is product type and is ?01 000? for the imch. field #3 is an assigned chronological value within a product type. the manufacturer id is ?000 0000 1001? for intel as assigned by ieee. the last field is filled by a binary ?1?. the jtag 32-bit id contains information in order to uniquely identify a component, and its manufacturer. note that this id does not uniquely distinguish between devices of a given component type. this id does not contain a device serial number. the fields as defined are shown in the table below. the revision codes must be changed to match chip specification. 45.2.1.1.4 highz the highz instruction is used to force all outputs of the device (except tdo) into a high impedance state. this instruction shall select the bypass register to be connected between tdi and tdo in the shift-dr controller state. 45.2.1.1.5 bypass the bypass command selects the bypass register to be connected for serial access between tdi and tdo pins of the device. the bypass register is a single bit register and is used to provide a minimum-length serial path through the device. this allows more rapid movement of test data to and from other components in the system. table 45-2. jtag device identification register field designations version/ stepping part number manufacturer id hardwired ?1? field #1 field #2 field #3 4 bits 6 bits 5 bits 5 bits 11 bits 1 bit
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1719 intel ? ep80579 integrated processor 45.3 high speed i/o testing there is a single xor chain which connects pcie pads, along with usb and sata pads. the definition for this is located in the ich xor chain section ( section 46.2.3, ?xor chains? ).
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1720 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1721 intel ? ep80579 integrated processor 46.0 ich design for test 46.1 jtag the iich in the ep80579 does not have a jtag interface. 46.2 i/o test mode 46.2.1 test mode entry methods non-functional test modes are dedicated test modes where the chip is not operating in its normal manner. this test mode includes boundary scan. functional test modes are features built into the existing functional modes that allow the iich to be optimally tested and/or margined in its normal operating mode. 46.2.1.1 non-functional test mode entry this section covers the non-functional test mode entry methods. 46.2.1.1.1 serial test mode (stm) entry the non-functional test mode is activated with the serial test mode entry. this method uses a single test pin (dfxtest#) to write to a test-mode command register or to read from a test-mode status register. dfxtest_n pin on ep80579 is shared between iich and imch. by default it works as dfxtest_n pin for iich and if jtag_instr_0x73 is set in the mch, then it acts as testnn pin for imch. the protocol for this serial test mode entry is based on pciclk and is depicted in ta bl e 4 6 - 1 . for either a read or a write, an 18-bit serial command field is fed into the test pin, prefaced with a ?0? as the start bit (the idle condition of the test pin must be a logic-high). for a write, the 18-bit command field is followed by 32 bits of write data, which is fed into the appropriate test-mode command register. for a read, the 18-bit command field is followed by one clock of turn-around, followed by the test-pin driving out 32 bits of read data. figure 46-1 and figure 46-2 demonstrate the timing of the serial test mode entry read and write cycles. it is important that test modes are not activated until after the entire data field has been written. it is also important that if a register is read, that its value is sampled at the end of the turn-around cycle. all serial values are put out msb-first.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1722 order number: 320066-003us all stm accessible registers are implemented as sticky registers. table 46-1. serial test mode entry command field bit field default and access description [17:13] 00000b ? write-only register index (31-0) [12:11] 00b ? write-only read/write enable (11 ? write 01 ? read, x0 ? reserved) [10:0] 000000000b ? write-only reserved figure 46-1. serial test mode entry for write figure 46-2. serial test mode entry for read
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1723 intel ? ep80579 integrated processor 46.2.2 test mode registers 46.2.2.1 test0 - test control register 0 table 46-2. test control register 0 description: view: stm base address: na offset start: offset end: na na size: 32 bit default: 000100001000000000000000 00000000 power well: core bit range bit acronym bit description sticky bit reset value bit access 31 reserved reserved 0b rw 30 reserved reserved 0b rw 29 reserved reserved rw 28 reserved reserved 0b rw 27 reserved reserved 1b rw 26 reserved reserved 0b rw 25 :24 reserved reserved 00b rw 23 reserved reserved. 0b rw 22 reserved reserved 1b rw 21 :19 reserved reserved 000b rw 18 reserved reserved 0b rw 17 reserved reserved 0b rw 16 reserved reserved 0b rw 15 reserved reserved 0b rw 14 :13 reserved reserved 00b rw 12 reserved reserved 0b rw 11 reserved reserved 0b rw 10 reserved reserved 0b rw 09 reserved reserved 0b rw 08 xor xor mode enable. refer to section 46.2.3 for more information. y0b rw 07 reserved reserved 0b rw 06 reserved reserved 0b rw 05 :04 reserved reserved 00b rw 03 :01 reserved reserved 000b wo 00 reserved reserved 0b rw
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1724 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1725 intel ? ep80579 integrated processor 46.2.3 xor chains xor chains are used to validate connectivity of high speed io pins when jtag control is unavailable. this technique chains together pins in a serial fashion, with an xor gate between each pin, effectively creating a single multi-input xor gate. by toggling the pins individually or in combination, the connectivity of the pins at the platform level, and the functionality of the i/o driver itself can be validated. there is only one xor chain in to cover the afes of pci express, sata and usb. this mode can be entered by setting bit 8 of test control register 0. table 46-3. xor chains xor chain order comments pea0_rn[6] first pin / input pin to xor chain pea0_rp[6] pea0_tp[6] pea0_tn[6] pea0_rn[7] pea0_rp[7] pea0_tp[7] pea0_tn[7] pea0_rn[4] pea0_rp[4] pea0_tp[4] pea0_tn[4] pea0_rn[5] pea0_rp[5] pea0_tp[5] pea0_tn[5] pea_rcompo pea_icompo pea0_rn[2] pea0_rp[2] pea0_tp[2] pea0_tn[2] pea0_rn[3] pea0_rp[3] pea0_tp[3] pea0_tn[3] pea0_rn[0] pea0_rp[0] pea0_tp[0] pea0_tn[0] pea0_rn[1] pea0_rp[1]
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1726 order number: 320066-003us these signals listed below enable the xor test mode for pci express afe and need to be connected to dt_xor signal: ? input_comp_oxoren ? input_iol0_oxoren0 ? input_iol0_oxoren1 ? input_iol1_oxoren0 ? input_iol1_oxoren ? input_iou0_oxoren0 ? input_iou0_oxoren1 ? input_iou1_oxoren0 ? input_iou1_oxoren1 pea0_tp[1] pea0_tn[1] sata_rbias sata_rbiassense sata_rxn0 sata_rxp0 sata_txn0 sata_txp0 sata_rxn1 sata_rxp1 sata_txn1 sata_txp1 usbn0 usbp0 usbn1 usbp1 ri_n xor chain output pin table 46-3. xor chains
order number: 320066-003us technical specifications, volume 6 of 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1728 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1729 intel ? ep80579 integrated processor 47.0 skus, power savings and pre-boot firmware 47.1 overview this section provides an overview of the various ep80579 skus. the skus are designed to optimize cost, performance, temperature environment (industial temperature support) and power consumption. several options allow designers to further reduce power consumption by disabling functional units that may not be utilized by the target application. 47.2 skus, strap options and pre-boot firmware programmable configuration modes 47.2.1 sku features ta bl e 4 7 - 1 outlines the various skus available.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1730 order number: 320066-003us table 47-1. base features of ep80579 skus sku overview application target intel ? ep80579 integrated processor intel ? ep80579 integrated processor with intel ? quickassist technology part number nu80579 ez600c nu80579 ez600ct nu80579 ez004c nu80579 ez009c nu80579 eb600c nu80579 ed004c nu80579 ed004ct nu80579 ed009c sku id 28461375 processor frequency (mhz) 600 600 1066 1200/1066 600 1066 1066 1200/1066 industrial temp no yes no no no no yes no asu ? no no no no yes yes yes yes ssu ? no no no no yes yes yes yes 3x tdm ? no no no no 12 t1/e1 12 t1/e1 12 t1/e1 12 t1/e1 1x ddr2 (mt/s) 400/533/ 667 400/533/ 667 400/533/ 667/800 400/533/ 667/800 400/533/ 667 400/533/ 667/800 400/533/ 667/800 400/533/ 667/800 2x sata gen1, gen2 pci-ex (root) 1x8, 2x4, or 2x1 3x ge (10/100/100) rgmii/rmii 2x usb 1.1 or 2.0 yes spi ? yes lpc yes 2x uart yes 2x smbus yes wdt yes rtc yes 36x gpio yes 2x can yes ieee 1588-2008 hardware assist yes local exp bus yes ssp yes ? intel recommends using the spi for pre-boot firmware due to the reduced availability of lpc fwh. ? feature must be enabled with the ep80579 software. refer to the ep80579 software documentation.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1731 intel ? ep80579 integrated processor 47.2.2 ddr2 frequencies supported by the ep80579 supported ddr2 frequencies are based on the sku and the tolapai operating frequency. table 47-2 lists the supported ddr2 frequencies. the supported frequencies are defined as frequency blocks. the ddr2 interface is defined as a function of the skus shown in table 47-1, ?base features of ep80579 skus? . 47.2.3 strap options (platform-based configuration) the tolapai provides an external pull-down strap pin (v_sel) that allows the platform to select ia-32 core frequency. the value of v_sel determines the operating point (frequency and voltage) of the ia-32 core in conjunction with the value of the tolapai output pin, bsel. bsel is derived from the ia-32 core bsel output and indicates the fixed fsb frequency. the v_sel pin is driven by the tolapai to a default value corresponding to the sku shown in table 47-1, ?base features of ep80579 skus? on page 1730 , but may be strapped low by the platform to override the sku value; this causes the ia-32 core to operate at the lowest gear ratio (multiplier applied to the fsb frequency to obtain the ia-32 core frequency) and voltage combination corresponding to the sku?s fsb frequency. ta bl e 4 7 - 3 shows the tolapai strap options: table 47-2. ia-32 core internal bus and ddr2 frequencies ia-32 core [mhz] internal quad pump fsb [mhz] ddr2 supported frequencies (mhz) 1,200 533 400, 533, 667, 800 1,066 533 400, 533, 667, 800 600 400 400, 533, 667 table 47-3. tolapai strap options sku id manufacturing frequency sku (fsb/intel architecture mhz) bsel value 1 v_sel value operating frequency (fsb/ia-32 core mhz) ia-32 core voltage 5/6 533/1200 1 1 533/1200 1.30v 533/1200 1 0 533/1066 1.30v 3/4/7 533/1066 1 0 533/1066 1.30v -- -- 0 1 reserved -- 1/2/8 400/600 0 0 400/600 1.0v notes: 1. the bsel output to the clock generator on the board assumes that ?0? indicates 400 mhz fsb and '1? indicates 533 mhz fsb.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1732 order number: 320066-003us 47.2.4 pre-boot firmware programmable sku options pre-boot firmware programmable sku options allow certain features to be disabled. this is helpful when downgrading a part for power savings. ? power savings: software (pre-boot firmware) can disable interface device to save power. ta b l e 4 7 - 4 lists the pre-boot firmware programmable features: table 47-4. ep80579 pre-boot firmware programmable options pre-boot firmware programmable features 1 accelerator services unit (asu) security services unit (ssu) gigabit ethernet (per port) can 0/1 ieee 1588-2008 hardware assist ssp usb pci express* (per controller) sata (per port) notes: 1. refer to the ep80579 software and the, intel ? ep80579 integrated processor product line firmware writer's guide.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1733 intel ? ep80579 integrated processor 48.0 package specifications this chapter provides ep80579 package specifications. 48.1 package introduction the ep80579 is offered in a 1,088 ball, flip-chip ball grid array (fcbga) package with lead-free only (rohs 5/6 compliant) for commercial and industrial applications. 48.2 functional signal definitions ta bl e 4 8 - 1 provides the legend for interpreting the type field that appears throughout the tables in this section. 48.3 jtag boundary scan chain (bsc) and xor chain the ep80579 implements a consistent, ieee 1149.1 compliant jtag boundary scan chain (bsc) for most interfaces (see section 48.4, ?signal pin descriptions? for the interfaces and signals) enabling a low-cost manufacturing test for boards. the interfaces include the iich interfaces. the bsc cell is defined in the boundary scan description language (bsdl) documentation and the boundary scan is initiated by the jtag entry in the imch side. three high-speed interfaces, pci express*, sata and usb, are not implemented in the jtag boundary scan. these interfaces are in an xor chain to validate connectivity of high speed io pins when jtag control is unavailable (see table 48-2, ?xor chain elements? and section 48.4, ?signal pin descriptions? for the interfaces and signals). xor chain mode is initiated by the serial test mode entry of the iich side. the xor chain provides the sequence of elements that include first element and xor output (last element) to allow the reader to know the chain starting and ending points. this table 48-1. signal type definitions symbol description # active low signal i input pin only o output pin only i/o pin can be either an input or output od open drain pin pwr power pin gnd ground pin reservedn pin must be connected as described, where n is the reserved pin number ncn no connection, where n is the nc pin number
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1734 order number: 320066-003us technique chains together pins in a serial fashion, with an xor gate between each pin, effectively creating a single multi-input xor gate. by toggling the pins individually or in combination, the connectivity of the pins are validated at the output pin. note: a test point must be placed on the board for each of these xor pins. 48.4 signal pin descriptions this section provides i/o signal definitions. the signals are categorized into one of several blocks: ? ia-32 core ?imch ? iich ?aioc ? miscellaneous ?power in each block, there are specific functional group interfaces. table 48-3 summarizes the signal pin tables that appear throughout this section. table 48-2. xor chain elements xor chain elements xor chain elements xor chain elements pea0_rn[6] -> first elements pea_rcompo pea0_tn[1] pea0_rp[6] pea_icompo sata_rbiasp pea0_tp[6] pea0_rn[2] sata_rbiasn pea0_tn[6] pea0_rp[2] sata_rxn0 pea0_rn[7] pea0_tp[2] sata_rxp0 pea0_rp[7] pea0_tn[2] sata_txn0 pea0_tp[7] pea0_rn[3] sata_txp0 pea0_tn[7] pea0_rp[3] sata_rxn1 pea0_rn[4] pea0_tp[3] sata_rxp1 pea0_rp[4] pea0_tn[3] sata_txn1 pea0_tp[4] pea0_rn[0] sata_txp1 pea0_tn[4] pea0_rp[0] usbn0 pea0_rn[5] pea0_tp[0] usbp0 pea0_rp[5] pea0_tn[0] usbn1 pea0_tp[5] pea0_rn[1] usbp1 pea0_tn[5] pea0_rp[1] ri# -> xor output pea_icompi pea0_tp[1]
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1735 intel ? ep80579 integrated processor the tables in this section list the signal pins associated with each interface and signal group on the ep80579. some of the pins provide either normal mode or alternate mode. the signal column provides the name of the signal that is associated with a pin in a particular mode. table 48-3. signal pin description references block interface table reference ia-32 core thermal diode table 48-4 global clock cru table 48-5 sideband miscellaneous signals table 48-6 imch imch clock/reset table 48-7 ddr2 interface table 48-8 pci express* interface table 48-9 iich real time clock interface table 48-10 general purpose i/o signals (gpio) and interrupts table 48-11 and table 48-12 serial peripheral interface (spi) table 48-13 low pin count (lpc) interface table 48-14 smbus interface table 48-15 uart interface table 48-16 serial ata (sata) interface table 48-17 universal serial bus (usb) interface table 48-18 power management interface table 48-19 iich miscellaneous signals table 48-20 aioc controller area network bus table 48-21 gigabit ethernet (gbe) interface table 48-22 time division multiplexing (tdm) interface table 48-23 local expansion bus (leb) interface table 48-24 synchronous serial port (ssp) interface table 48-25 ieee 1588-2008 hardware assist interface table 48-26 misc. jtag table 48-27 miscellaneous signals table 48-28 reserved table 48-29 no connect table 48-30 power power and ground table 48-31
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1736 order number: 320066-003us 48.4.1 ia-32 core 48.4.1.1 thermal diode 48.4.1.2 global clock cru table 48-4. ia-32 core thermal signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode thermdc analog o 1 ia-32 core thermal diode: thermal diode cathode (input). thermda analog i 1 ia-32 core thermal diode: thermal diode anode (output). total 2 table 48-5. global clock and reset (cru) signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode clkp100 lvds i 1 cru clock (differential) positive side of the 100mhz clock input. clkn100 lvds i 1 cru clock (differential): negative side of the 100mhz clock input. total 2
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1737 intel ? ep80579 integrated processor 48.4.1.3 sideband miscellaneous signals table 48-6. sideband miscellaneous signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode cpuslp_out# lvttl,3.3v o 1 bsc cpu sleep: this ep80579 output signal is made visible to the platform for debug purposes only. this internal ep80579 signal places the processor into a state that saves substantial power compared to the stop-grant state. when ep80579 is in this state, it will not recognize snoops or interrupts. the processor will recognize only assertion of the cpurst# signal, and deassertion of cpuslp_out# while in sleep state. if cpuslp_out# is deasserted, the processor exits sleep state and returns to stop- grant state, restarting its internal clock signals to the bus and processor core units. init33v_out# lvttl,3.3v o 1 bsc cpu initialization: this 3.3v ep80579 output signal is made visible to the platform to reset the firmware hub. internal ep80579 signal that when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init33v_out# assertion. init33v_out# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/ output write bus transaction. nmi lvttl,3.3v i/o 1 bsc non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor, if configured. the processor detects an nmi as a rising edge on nmi. nmi is reset by setting the corresponding nmi source enable/disable bit in the nmi status and control register (i/o register 61h), except when an external platform agent is driving the nmi pin. smi_out# lvttl,3.3v o 1 bsc system management interrupt: this ep80579 output signal is made visible to the platform for debug purposes only. this internal ep80579 signal is active low output synchronous to pciclk that is asserted in response to one of many enabled hardware or software events. on accepting a system management interrupt, the processor saves the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1738 order number: 320066-003us stpclk_out# lvttl,3.3v o 1 bsc stop clock request: this ep80579 output signal is made visible to the platform for debug purposes only. this internal ep80579 signal is an active-low output synchronous to pciclk that is asserted in response to one of many hardware or software events. when the processor samples stpclk_out# asserted, it causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the cpu fsb and cpu apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk_out# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk_out# has no effect on the bus clock; stpclk_out# is an asynchronous cpu input generated by the ep80579 iich. rcin# lvttl,3.3v i 1 bsc keyboard controller reset processor: the keyboard controller can generate init_n to the processor. this saves the external or gate of other sources of init_n. when the ep80579 detects the assertion of this signal, init_n is generated for 16 pciclk clocks. the ep80579 will ignore rcin# assertion during transitions to the s3, s4 and s5 states. a20gate lvttl,3.3v i 1 bsc a20 gate: a signal from the keyboard controller. acts as an alternative method to force the a20m_n signal active. saves the external or gate needed with various other chipsets. cpurst# lvttl,3.3v o 1 bsc processor bus reset: the imch asserts cpurst# while rstin# is asserted and for approximately 1 ms after rstin# is deasserted. the cpurst# allows the processors to begin execution in a known state. this ep80579 signal is for the use by the debug tool purpose. cpupwrgd_out lvttl,3.3v od o 1 10k up bsc cpupwrgd is an open drain signal, this signal requires an external pull-up resistor. this ep80579 output signal is made externally visible to the platform for debug purposes only. cpupwrgd monitors an internal ep80579 signal connected directly from the iich to the processor and represents a logical and of pwrok and vrmpwrgd signals. this signal also must be driven high throughout boundary scan operation. ierr# lvttl,3.3v o 1 bsc ierr (internal error) is asserted by a processor as the result of an internal error. assertion of ierr is usually accompanied by a shutdown transaction on the fsb. this transaction may optionally be converted to an external error signal (e.g., nmi) by the ep80579. the processor will keep ierr asserted until the assertion of init33v_out# or the ep80579 is reset using sys_reset#. for termination requirements please refer to the platform design guides. total 10 table 48-6. sideband miscellaneous signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1739 intel ? ep80579 integrated processor 48.4.2 integrated memory controller hub (imch) 48.4.2.1 imch reset 48.4.2.2 ddr2 sdram table 48-7. imch reset signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode rstin# lvttl,3.3v i 1 bsc imch reset input: this input must be connected to pltrst#. pwrgd lvttl,3.3v i 1 bsc imch power good: asynchronously resets the entire imch component, including ?sticky? bits. driven by platform logic to indicate all board power supplies are valid. total 2 table 48-8. ddr2 interface signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode ddr_ck[5:0] sstl_18 o 6 bsc ddr channel command clock (differential): the positive side of the command clocks used by the ddr drams to latch the ddr_a[14:0], ddr_ba[2:0], ddr_ras#, ddr_cas#, ddr_we#, ddr_cke[1:0], and ddr_cs[1:0]# signals. ddr_ck[5:0]# sstl_18 o 6 bsc ddr channel command clock (differential): the negative side of the differential command clock (see ddr_ck[5:0]). ddr_cs[1:0]# sstl_18 o 2 bsc ddr channel chip select: used to indicate to which dram device cycles are targeted. ddr_ras# sstl_18 o 1 bsc ddr channel row address strobe: used to indicate a valid row address and open a row ddr_cas# sstl_18 o 1 bsc ddr channel column address strobe: used to indicate a valid column address and initiate a transaction. ddr_we# sstl_18 o 1 bsc ddr channel write enable: used to indicate a write cycle. ddr_dm[8:0] sstl_18 o 9 bsc ddr channel data mask: data mask for write data. ddr_ba[2:0] sstl_18 o 3 bsc ddr channel bank address: the ddr bank address signals. these signals are outputs of the imch and select which bank within a row is selected. ddr_a[14:0] sstl_18 o 15 bsc ddr channel memory address: the ddr memory address signals. ddr_dq[63:0] sstl_18 i/o 64 bsc ddr channel data bus: the ddr data bus provides the data to/from the dram devices. ddr_ecc[7:0] sstl_18 i/o 8 bsc ddr channel ecc bits: ecc bits for the data on the interface.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1740 order number: 320066-003us ddr_dqs[8:0] sstl_18 i/o 9 bsc ddr channel data strobes (differential): the positive side of the data strobe. each data strobe is used to strobe a set of four or eight data signals (depending on whether x4 or x8 dram devices are used). ddr_dqs[8:0]# sstl_18 i/o 9 bsc ddr channel data strobes (differential): the negative side of the data strobe (see d_dqs[8:0]). ddr_cke[1:0] sstl_18 o 2 bsc ddr channel clock enable: independent per- dimm-slot clock enables used by the controller during the initialization sequence. ddr_odt0 sstl_18 i/o 1 bsc ddr compensation: on-die termination configuration. ddr_odt1 sstl_18 i/o 1 bsc ddr compensation: on-die termination configuration. ddr_rcompx analog i 1 ddr compensation: cmd/ck/add pin slewrate control. ddr_cres[2:0] analog i/o 3 ddr compensation: resistive compensation i/ o's ddr_drvcres analog i/o 1 ddr compensation ddr_slewcres analog i/o 1 ddr compensation: dq/dqs/dm pin slewrate control. total 144 table 48-8. ddr2 interface signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1741 intel ? ep80579 integrated processor 48.4.2.3 pci express* table 48-9. pci express interface signals (sheet 1 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode pea0_tp[0] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair. these signals are an output (tx) from the ep80579?s perspective, and must be connected to the input (receive or rx) signals of the other pci express device. the signals for this 1x8 interface can be trained to 2x4 or 2x1 ports. these port configurations map to signals as follows (y is either "n" or "p"): 1x8 interface configuration: - pea0_ty[7:0] = link 0 2x4 interface configuration: - pea1_ty[7:4] = link 1 - pea0_ty[3:0] = link 0 2x1 interface configuration: - pea1_ty[4] = link 1 - pea0_ty[0] = link 0 pea0_tn[0] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_rp[0] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair. these signals are an input (rx) from the ep80579?s perspective, and must be connected to the output (transmit or tx) signals of the other pci express device. the signals for this 1x8 interface can be trained to 2x4 or 2x1 ports. these port configurations map to signals as follows (y is either "n" or "p"): 1x8 interface configuration: - pea0_ry[7:0] = link 0 2x4 interface configuration: - pea1_ry[7:4] = link 1, - pea0_ry[3:0] = link 0 2x1 interface configuration: - pea1_ry[4] = link 1, - pea0_ry[0] = link 0 pea0_rn[0] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rp[0]). pea0_tp[1] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[1] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0])
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1742 order number: 320066-003us pea0_rp[1] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[1] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). pea0_tp[2] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[2] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0]) pea0_rp[2] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[2] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). pea0_tp[3] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[3] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0]) pea0_rp[3] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[3] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). pea0_tp[4] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[4] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0]) pea0_rp[4] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[4] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). table 48-9. pci express interface signals (sheet 2 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1743 intel ? ep80579 integrated processor pea0_tp[5] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[5] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0]) pea0_rp[5] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[5] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). pea0_tp[6] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[6] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0]) pea0_rp[6] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[6] lv diff i 1 xor (first eleme nt) pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). pea0_tp[7] lv diff o 1 xor pci express interface port a transmit data pair (differential): the positive side of the pci express port a transmit data pair (see pea0_tp[0]). pea0_tn[7] lv diff o 1 xor pci express interface port a transmit data pair (differential): the negative side of the pci express port a transmit data pair (see pea0_tn[0]) pea0_rp[7] lv diff i 1 xor pci express interface port a receive data pair (differential): the positive side of the pci express port a receive data pair (see pea0_rp[0]). pea0_rn[7] lv diff i 1 xor pci express interface port a receive data pair (differential): the negative side of the pci express port a receive data pair (see pea0_rn[0]). pea_clkn lv diff i 1 pci express port a clock (differential): the negative side of the reference clock input. pea_clkp lv diff i 1 pci express port a clock (differential): the positive side of the reference clock input, see pea_clkn. pea_rcompo analog i 1 xor pci express port a compensation: used to calibrate the pci express high speed serial input/output buffers. table 48-9. pci express interface signals (sheet 3 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1744 order number: 320066-003us 48.4.3 integrated i/o controller hub (iich) 48.4.3.1 real time clock 48.4.3.2 general purpose i/o (gpio) and interrupts pea_icompi analog i 1 xor pci express port a compensation: used to calibrate the pci express high speed serial input/output buffers pea_icompo analog i 1 xor pci express port a compensation: used to calibrate the pci express high speed serial input/output buffers. total 37 table 48-10. real time clock interface signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode rtcx1 analog i 1 rtc crystal input 1: connected to the 32.768 khz crystal. if no external crystal is used, then rtcx1 can be driven with the desired clock rate. rtcx2 analog o 1 rtc crystal input 2: connected to the 32.768 khz crystal. if no external crystal is used, then rtcx2 should be left floating. rtest# lvttl,3.3v i 1 rtc test enable: oscillator test enable input. an external rc circuit is required to drive this test input. total 3 table 48-11. general-purpose io signals (sheet 1 of 5) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode gpio[0] lvttl,3.3v i 1 bsc general purpose io 0: reside in the core power well. gpio[1] lvttl,3.3v i 1 bsc general purpose io 1: reside in the core power well. gpio[6] lvttl,3.3v i 1 bsc general purpose io 6: resides in the core power well. this pin is not available if smi mode is enabled. gpio[7] lvttl,3.3v i 1 bsc general purpose io 7: resides in the core power well. gpio[8] lvttl,3.3v i 1 bsc general purpose io 8: resides in the suspend power well. table 48-9. pci express interface signals (sheet 4 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1745 intel ? ep80579 integrated processor gpio[9] lvttl,3.3v i 1 bsc general purpose io 9: resides in the suspend power well. gpio[10] lvttl,3.3v i 1 bsc general purpose io 10: resides in the suspend power well. gpio[12] lvttl,3.3v i 1 bsc general purpose io 12: resides in the core power well. gpio[13] lvttl,3.3v i 1 bsc general purpose io 13: resides in the core power well. gpio[14] lvttl,3.3v i 1 bsc general purpose io 14: resides in the suspend power well. gpio[15] lvttl,3.3v i 1 bsc general purpose io 15: resides in the suspend power well. gp16_irq24 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 16: this signal can function as either gpio[16] or irq[24]. resides in the core power well. note: internal pullup is always enabled (50k nominal). a16 override strap: this strap selects the treatment of a16 for cycles going to bios space (but not feature space) in the fwh. the ep80579 interprets this strap as follows: 0 = iich does not invert a16. 1 = iich inverts a16 on some bios cycles (default) gp17_irq25 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 17: this signal can function as either gpio[17] or irq[25]. resides in the core power well. note: internal pullup is always enabled (50k nominal). boot bios selection strap: this strap selects the source of the bios during boot. the ep80579 interprets this strap as follows: gp17 gp33 boot option 0 0 boot bios from spi 0 1 reserved 1 0 reserved 1 1 (default) boot bios from lpc note: intel recommends using the spi for pre-boot firmware due to the reduced availability of lpc fwh. gp18_irq36 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 18: this signal can function as either gpio[18] or irq[36]. resides in the core power well. notes: ? internal pullup is always enabled (50k nominal). ? do not drive this signal low until the cpurst# signal is de-asserted. table 48-11. general-purpose io signals (sheet 2 of 5) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1746 order number: 320066-003us gp19_irq37 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 19: this signal can function as either gpio[19] or irq[37]. resides in the core power well. notes: ? internal pullup is always enabled (50k nominal). ? do not drive this signal low until the cpurst# signal is de-asserted. gp20_irq26 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 20: this signal can function as either gpio[20] or irq[26]. resides in the core power well. gp21_irq27 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 21: this signal can function as either gpio[21] or irq[27]. resides in the core power well. notes: ? internal pullup is always enabled (50k nominal). ? do not drive this signal low until the cpurst# signal is de-asserted. gp23_irq28 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 23: this signal can function as either gpio[23] or irq[28]. resides in the core power well. notes: ? internal pullup is always enabled (50k nominal). ? do not drive this signal low until the cpurst# signal is de-asserted. gp24_irq29 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 24: this signal can function as either gpio[24] or irq[29]. resides in the suspend power well. gp25_irq38 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 25: this signal can function as either gpio[25] or irq[38]. resides in the suspend power well. gp27_irq39 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 27: this signal can function as either gpio[27] or irq[39]. resides in the suspend power well. gp28_irq30 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 28: this signal can function as either gpio[28] or irq[30]. resides in the suspend power well. gp30_irq31 lvttl,3.3v i 1 no pullup required in irq mode bsc general purpose io 30: this signal can function as either gpio[30] or irq[31]. resides in the core power well. gp31_irq32 lvttl,3.3v i 1 no pullup required in irq mode bsc general purpose io 31: this signal can function as either gpio[31] or irq[32]. resides in the core power well. table 48-11. general-purpose io signals (sheet 3 of 5) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1747 intel ? ep80579 integrated processor gp33_irq33 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 33: this signal can function as either gpio[33] or irq[33]. resides in the core power well. note: internal pullup is always enabled (50k nominal). boot bios selection strap: this strap selects the source of the bios during boot. the ep80579 interprets this strap as follows: gp17 gp33 boot option 0 0 boot bios from spi 0 1 reserved 1 0 reserved 1 1 (default) boot bios from lpc note: intel recommends using the spi for pre-boot firmware due to the reduced availability of lpc fwh. gp34_irq34 lvttl,3.3v i/o 1 no pullup required in irq mode bsc general purpose io 34: this signal can function as either gpio[34] or irq[34]. resides in the core power well. gp40_irq35 lvttl,3.3v i 1 no pullup required in irq mode bsc general purpose io 40: this signal can function as either gpio[40] or irq[35]. resides in the core power well. gpio[48] lvttl,3.3v o 1 bsc general purpose io 48: resides in the core power well. note: internal pullup is always enabled (50k nominal). the ep80579 interprets this strap as follows: 0 = reserved 1 = uart/gpio mode (default). gp5_pirqh# lvttl,3.3v i 1 10k up (in pirq mode) bsc pci interrupt requests: general purpose or pci interrupt pin. in non-apic mode, the gp5_pirqh# signal is fixed routed to irq[23]. this signal is 5 v tolerant. gp4_pirqg# lvttl,3.3v i 1 10k up (in pirq mode) bsc pci interrupt requests: general purpose or pci interrupt pin. in non-apic mode, the gp4_pirqg# signal is fixed routed to irq[22]. this signal is 5 v tolerant. gp3_pirqf# lvttl,3.3v i 1 10k up (in pirq mode) bsc pci interrupt requests: general purpose or pci interrupt pin. in non-apic mode, the gp3_pirqf# signal is fixed routed to irq[21]. this signal is 5 v tolerant. gp2_pirqe# lvttl,3.3v i 1 10k up (in pirq mode) bsc pci interrupt requests: general purpose or pci interrupt pin. in non-apic mode, the gp2_pirqe# signal is fixed routed to irq[20]. this signal is 5 v tolerant. table 48-11. general-purpose io signals (sheet 4 of 5) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1748 order number: 320066-003us gp41_ldrq[1]# lvttl,3.3v i 1 bsc lpc serial dma/master request input bit 1: used by lpc devices, such as super i/o chips, to request dma or bus master access.this signal is typically connected to external super i/o device. note: internal pullup is always enabled (50k nominal). gp41_ldrq1# may optionally be used as gpi[41]. gp26_sata0gp lvttl,3.3v i 1 bsc serial ata port 0 general purpose: this input pin can be configured as an interlock switch for sata port 0 or as a general purpose input, depending on the platform needs. when used as an interlock switch status indication, this signal must be driven to '0' to indicate that the switch is closed, and to '1' to indicate that the switch is open. if interlock switches are not required, the platform can configure this signal as gpi[26]. note: gp26_sata0gp and gp29_sata1gp must be configured for the same purpose (i.e., either both sataxgp or both gpio functionality). gp29_sata1gp lvttl,3.3v i 1 bsc serial ata port 1 general purpose: same function as gp26_sata0gp, except for sata port 1. when used as an interlock switch status indication, this signal must be driven to '0' to indicate that the switch is closed, and to '1' to indicate that the switch is open. if interlock switches are not required, the platform can configure this signal as gpi[29]. note: gp26_sata0gp and gp29_sata1gp must be configured for the same purpose (i.e., either both sataxgp or both gpio functionality). gp11_smbalert # lvttl,3.3v i 1 10k up (in smbalert mode) bsc smbus alert: this signal is used to wake the system or generate an smi. note that the platform can also elect to use this signal as gpi[11] if smbalert functionality is not needed. when this signal is used as smbalert#, an external pull-up is required. total 36 table 48-11. general-purpose io signals (sheet 5 of 5) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode table 48-12. iich interrupt signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode gp5_pirqh# see gpio interface. gp4_pirqg# see gpio interface. gp3_pirqf# see gpio interface.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1749 intel ? ep80579 integrated processor 48.4.3.3 serial peripheral interface (spi) 1 48.4.3.4 low pin count (lpc) interface gp2_pirqe# see gpio interface. serirq lvttl,3.3v i 1 10k up (in pirq mode) bsc serial interrupt request: this pin implements the serial interrupt protocol. this signal is not 5v tolerant. it is 3.3 v tolerant. total 1 1. intel recommends using the spi for pre-boot firmware due to the reduced availability of lpc fwh. table 48-13. spi interface signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/ alternate mode spi_sclk lvttl,3.3v o 1 bsc serial bit-rate clock spi_cs# lvttl,3.3v o 1 bsc cs for slave spi_mosi lvttl,3.3v o 1 bsc master data out/slave in spi_miso lvttl,3.3v i 1 bsc master data in/slave out total 4 table 48-14. lpc and fwh interface signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode lad[3:0] lvttl,3.3v i/o 4 bsc lpc multiplexed command, address, data lad[3:0] may be used as firmware hub [3:0] signals. lframe# lvttl,3.3v o 1 bsc lpc frame: lframe# indicates the start of an lpc cycle, or an abort. lframe# may be used as firmware hub [4] signal. gp41_ldrq[1]# see gpio interface. table 48-12. iich interrupt signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1750 order number: 320066-003us 48.4.3.5 smbus ldrq[0]# lvttl,3.3v i 1 bsc lpc serial dma/master request input bit 0: used by lpc devices, such as super i/o chips, to request dma or bus master access.this signal is typically connected to external super i/o device. pciclk lvttl,3.3v i 1 bsc lpc clock. pci clock used for the lpc bus (up to 33mhz) total 7 table 48-15. smbus interface signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode smbdata lvttl,3.3v od i/o 1 8.2k up bsc smbus data: smbus data signal. an external pull-up is required. smbclk lvttl,3.3v od i/o 1 8.2k up bsc smbus clock: smbus clock signal. an external pull-up is required. gp11_smbalert# see gpio interface. intruder# lvttl,3.3v i 1 smbus intruder detect: detects if the system case has been opened. can be set to disables the system if the box is detected open. this input signal is in the rtc well. this pin's status is readable, so it can be used like a gpi if the intruder switch is not needed. smlink[1:0] lvttl,3.3v od i/o 2 8.2k up bsc smbus system management link: smbus link to optional external system management asic or lan controller. external pull-ups are required. note that smlink[0] corresponds to an smbus clock signal, and smlink[1] corresponds to an smbus data signal. smbsda lvttl,3.3v od i/o 1 8.2k up bsc smbus data: data signal for the imch smbus interface. an external pull-up is required. smbscl lvttl,3.3v od i/o 1 8.2k up bsc smbus clock: clock signal for the imch smbus interface. an external pull-up is required. total 7 table 48-14. lpc and fwh interface signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1751 intel ? ep80579 integrated processor 48.4.3.6 uart interface table 48-16. uart signals (sheet 1 of 3) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode siu_cts1# lvttl,3.3v i/o 1 bsc uart port 1 clear to send: active low, this pin indicates that data can be exchanged between uart port 1 and the external interface. this pin has no effect on the transmitter. note: this pin could be used as modem status input whose condition can be tested by the processor by reading bit 4 (cts) of the modem status register (msr). bit 4 is the compliment of the cts# signal. bit0 (dcts) of the msr indicates whether the cts# input has changed state since the previous reading of the msr. when the cts bit of the msr changes state an interrupt is generated if the modem status interrupt is enabled. siu_cts2# lvttl,3.3v i/o 1 bsc uart port 2 clear to send. refer to uart port 1 clear to send (siu_cts1#) for more information. siu_dcd1# lvttl,3.3v i/o 1 bsc uart port 1 data carrier detect: active low, this pin indicates that data carrier has been detected by the external agent for uart port 1. note: this pin is modem status input which condition can be tested by the processor by reading bit 7 (dcd) of the modem status register (msr). bit 7 is complement of the dcd# signal. bit 3 (ddcd) of the msr indicates whether the dcd# input has changed state since the previous reading of the msr. when the dcd bin of the msr changes state an interrupt is generated if the modem status interrupt is enabled. siu_dcd2# lvttl,3.3v i/o 1 bsc uart port 2 data carrier detect. refer to uart port 1 data carrier detect (siu_dcd1) for more information. siu_dsr1# lvttl,3.3v i/o 1 bsc uart port 1 data set ready: active low, this pin indicates that the external agent is ready to communicate with uart port 1. this pin has no effect on the transmitter. note: this pin could be used as modem status input whose condition can be tested by the processor by reading bit 5 (dsr) of the modem status register (msr). bit 5 is the complement of the dsr# signal. bit 1 (ddsr) of the modem status register (msr) indicates whether the dsr# input has changed state since the previous reading of the msr. when the dsr bin of the msr changes state an interrupt is generated if the modem status interrupt is enabled. siu_dsr2# lvttl,3.3v i/o 1 bsc uart port 2 data set ready. refer to uart port 1 data set ready for more information.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1752 order number: 320066-003us siu_dtr1# lvttl,3.3v i/o 1 bsc uart port 1 data terminal ready: when low, this pin informs the modem or data set that the uart port 1 is ready to establish a communication link. the dtr# output signal can be set to an active low by programming the dtr (bit 0) of the modem control register to a logic ?1?. a reset operation sets this signal to its inactive state (logic ?1?). loop mode operation holds this signal in its inactive state. siw configuration port address select strap: this strap selects the io address for the siw configuration port. the ep80579 interprets the strap as follows: 0 = io addresses 20eh and 20fh 1 = io addresses 04eh and 04fh (default) siu_dtr2# lvttl,3.3v i/o 1 bsc uart port 2 data terminal ready. refer to uart port 1 data terminal ready (siu_dtr1#) for more information. note: do not drive this signal low until the cpurst# signal is de-asserted. siu_ri1# lvttl,3.3v i/o 1 bsc uart port 1 ring indicator: active low, this pin indicates that a telephone ringing signal has been received by the external agent for uart port 1. note: this pin is modem status input whose condition can be tested by the processor by reading bit 6 (ri) of the msr. bit 6 is the complement of the ri# signal. bit 2 (teri) of the msr indicates whether the ri# input has transitioned back to an inactive state. when the ri bit of the msr changes from a 1 to 0 an interrupt is generated if the modem status interrupt is enabled. siu_ri2# lvttl,3.3v i/o 1 bsc uart port 2 ring indicator. refer to uart port 1 ring indicator (siu_ri1#) for more information. siu_rts1# lvttl,3.3v i/o 1 bsc uart port 1 request to send: when low this pin informs the modem or data set that uart port 1 is wants to send data on an established communication link. the rts# output signal can be set to an active low by programming the rts (bit 1) of the modem control register to a logic ?1?. a reset operation sets this signal to its inactive state (logic ?1?). loop mode operation holds this signal in its inactive state. note: do not drive this signal low until the cpurst# signal is de-asserted. siu_rts2# lvttl,3.3v i/o 1 bsc uart port 2 request to send. refer to uart port 1 request to send (siu_rts1#) for more information. note: do not drive this signal low until the cpurst# signal is de-asserted. siu_rxd1 lvttl,3.3v i/o 1 bsc uart port 1 serial data input: serial data input form device pin to the receive port for uart port 1. siu_rxd2 lvttl,3.3v i/o 1 bsc uart port 2 serial data input: serial data input form device pin to the receive port for uart port 2. table 48-16. uart signals (sheet 2 of 3) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1753 intel ? ep80579 integrated processor 48.4.3.7 serial ata (sata) interface siu_txd1 lvttl,3.3v i/o 1 bsc uart port 1 serial data output: serial data output to the communication peripheral/modem or data set for uart port 1. upon reset, the txd pins will be set to marking condition (logic ?1? state). siu_txd2 lvttl,3.3v i/o 1 bsc uart port 2 serial data output: serial data output to the communication peripheral/modem or data set for uart port 2. upon reset, the txd pins will be set to marking condition (logic ?1? state). gpio irq strap: this strap selects the interrupt capabilities of some gpio pins on the ep80579 . the ep80579 interprets this strap as follows: 0 = gpio irq capability enabled. 1 = gpio irq capability disabled (default) uart_clk lvttl,3.3v i 1 bsc uart clock: input clock to the siu. this clock is passed to the baud clock generation logic for the uart in the siu. the clock can run at either 14.7456, 33, or 48 mhz. total 17 table 48-17. serial ata interface signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode sata_txp0 lv diff o 1 xor serial ata interface port 0 transmit data pair (differential): the positive side of the port 0 transmit data pair. sata_txn0 lv diff o 1 xor serial ata interface port 0 transmit data pair (differential): the negative side of the port 0 transmit data pair. sata_rxp0 lv diff i 1 xor serial ata interface port 0 receive data pair (differential): the positive side of the port 0 receive data pair. sata_rxn0 lv diff i 1 xor serial ata interface port 0 receive data pair (differential): the negative side of the port 0 receive data pair. sata_clkrefn cmos i 1 serial ata reference clock (differential): the negative side of the 100mhz clock input from the clock generator for the sata pll. sata_clkrefp cmos i 1 serial ata reference clock (differential): the positive side of the 100mhz clock input from the clock generator for the sata pll. sata_txp1 lv diff o 1 xor serial ata interface port 1 transmit data pair (differential): the positive side of the port 1 transmit data pair. table 48-16. uart signals (sheet 3 of 3) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1754 order number: 320066-003us sata_txn1 lv diff o 1 xor serial ata interface port 1 transmit data pair (differential): the negative side of the port 1 transmit data pair. sata_rxp1 lv diff i 1 xor serial ata interface port 1 receive data pair (differential): the positive side of the port 1 receive data pair. sata_rxn1 lv diff i 1 xor serial ata interface port 1 receive data pair (differential): the negative side of the port 1 receive data pair. sata_rbias analog i 1 xor serial ata resistor bias (positive): analog connection point for an external bias resistor. sata_rbias# analog i 1 xor serial ata resistor bias (negative): analog connection point for an external bias resistor. gp26_sata0gp see gpio interface. gp29_sata1gp see gpio interface. sataled# lvttl,3.3v od o 1 220 to 10k ohms bsc serial ata led: this is an open-collector/open- drain output signal driven during sata command activity. it is to be connected to external circuitry that can provide the current to drive a platform led. when active, the led is on. when tristated, the led is off. an external pull-up resistor is required. total 13 table 48-17. serial ata interface signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1755 intel ? ep80579 integrated processor 48.4.3.8 universal serial bus (usb) interface table 48-18. usb interface signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode usbp0 lv diff i/o 1 xor usb port 0 signal (differential): the positive side of the differential pair that is used to transmit data/address/command signals for usb port 0. note: external resistors are not required on these signals. the chip integrates the 15 k-ohm pull-down and provides an output driver impedance of 45 ohm which requires no external series resistor. usbn0 lv diff i/o 1 xor usb port 0 signal (differential): the negative side of the differential pair that is used to transmit data/address/command signals for usb port 0 (see usbp0). usbp1 lv diff i/o 1 xor usb port 1 signal (differential): the positive side of the differential pairs that are used to transmit data/address/command signals for usb port 0. note: external resistors are not required on these signals. the chip integrates the 15 k-ohm pull-down and provides an output driver impedance of 45 ohm which requires no external series resistor. usbn1 lv diff i/o 1 xor usb port 1 signal (differential): the negative side of the differential pair that is used to transmit data/address/command signals for usb port 0 (see usbp1). oc[1]# lvttl,3.3v i 1 10k up bsc usb port 1 overcurrent indicator: this signal sets corresponding bits in the usb controller to indicate that an overcurrent condition has occurred on usb port 1. oc[0]# lvttl,3.3v i 1 10k up bsc usb port 0 overcurrent indicator: this signal sets corresponding bits in the usb controller to indicate that an overcurrent condition has occurred on usb port 0. usb_rbiasp analog o 1 usb controller resistor bias (positive): analog connection point for an external resistor. used to set transmit currents and internal load resistors. usb_rbiasn analog i 1 usb controller resistor bias (negative): analog connection point for an external resistor. used to set transmit currents and internal load resistors clk48 lvttl,3.3v i 1 usb controller reference clock: 48mhz reference clock for the usb controller. total 9
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1756 order number: 320066-003us 48.4.3.9 power management interface table 48-19. power management interface signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode pltrst# lvttl,3.3v o 1 bsc platform reset: the ep80579 asserts pltrst# to reset devices that reside on the pci bus. the iich asserts pltrst# during power-up and when a hard reset sequence is initiated through the 0cf9h register. pltrst# is driven inactive a minimum of 1 ms after both pwrok and vrmpwrgd are driven high. pltrst# is driven for a minimum of 1 ms when initiated through the 0cf9h register. note: pltrst# is in the 3.3v vccpsus well. prochot# lvttl,3.3v o 1 bsc processor hot thermal alarm: this signal will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit has been activated, if enabled. thrmtrip# lvttl,3.3v od i/o 1 10k (maximum) up bsc thermal trip: the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. when low, indicates that a thermal trip on behalf of the processor has occurred, and corrective action will be taken (immediately transitions the ep80579 to a s5 state). this is an open-drain signal which optionally allows the platform to force an s5 transition. slp_s3# lvttl,3.3v o 1 bsc s3 sleep control: slp_s3# is for power plane control. this signal shuts off power to all non- critical systems when in s3 (suspend to ram), s4 (suspend to disk), or s5 (soft off) states. slp_s4# lvttl,3.3v o 1 bsc s4 sleep control: slp_s4# is for power plane control. this signal shuts power to all non-critical systems when in the s4 (suspend to disk) or s5 (soft off) state. note: this pin must be used to control the dram power to use the ep80579 's dram power- cycling feature. slp_s5# lvttl,3.3v o 1 bsc s5 sleep control: slp_s5# is for power plane control. this signal is used to shut power off to all non-critical systems when in the s5 (soft off) states. pwrok lvttl,3.3v i 1 power ok: when asserted, pwrok is an indication that core power has been stable for at least 99ms and pciclk has been toggling cleanly for at least 1 ms. pwrok can be driven asynchronously. when pwrok is low, pltrst# is asserted. note that it is required that the core power has been valid for 99ms prior to pwrok assertion in order to comply with the 100ms pci 2.3 specification on pltrst# deassertion.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1757 intel ? ep80579 integrated processor pwrbtn# lvttl,3.3v i 1 bsc power button: causes smi or sci to indicate to system request to go to a sleep state. if already in sleep state, will cause a wake event. if pwrbtn# is pressed for four seconds, will cause unconditional transition (power button override) to the s5 state. override will occur even if the system is in the s3 or s4 state. this signal has an internal pullup resistor and has an internal 16 ms de-bounce on the input. ri# lvttl,3.3v i 1 bsc/ xor output ring indicate: from the modem interface. can be enabled as a wake event and is preserved during power failures. sys_reset# lvttl,3.3v i 1 bsc system reset: this pin forces an internal reset after being debounced. the ep80579 will reset immediately if the smbus is idle; otherwise, it will wait up to 25 ms 2 ms for the smbus to idle before forcing a reset on the system. rsmrst# lvttl,3.3v i 1 resume well reset: used for resetting the resume well. an external rc circuit is required to guarantee that the resume well power is valid prior to rsmrst# going high. sus_stat# lvttl,3.3v o 1 bsc suspend status: this signal is asserted to indicate that the system will be entering a low power state soon. this can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. it can also be used by other peripherals as an indication that they must isolate their outputs that may be going to powered-off planes. this signal is called lpcpd# on the lpc i/f. susclk lvttl,3.3v o 1 bsc suspend clock: output of the rtc clock generator circuit (32.768 khz). susclk will have a duty cycle that can be as low as 30% or as high as 70%. vrmpwrgd lvttl,3.3v i 1 bsc voltage regulator power good: this is the processor?s vrm power good, and will save an external and gate. this signal is internally anded with the atx power supply?s pwrok signal. traditionally, this and gate has been external to the chipset. total 14 table 48-19. power management interface signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1758 order number: 320066-003us 48.4.3.10 iich miscellaneous signals table 48-20. iich miscellaneous signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode clk14 lvttl,3.3v i 1 bsc timer oscillator clock: used for 8254 timers and hpet (high precision event timer). runs at 14.31818 mhz. this clock stops (and should be low) during s3 and s5 state. clk14 must be accurate to within 500ppm over 100usecs (and longer periods) in order to meet hpet accuracy requirements. pe_hpintr# lvttl,3.3v i 1 10k to 100k up bsc imch pci express hot-plug controller interrupt: input pin to hot-plug controller on pci express bus. not 5v tolerant. note: because pci express hot plug is not supported in the ep80579, this pin must be pulled up to 3.3v through a 10k to 100k pull-up resistor. bsel lvttl,3.3v o 1 bsc ia fsb frequency select: the cpu select (bsel) encodings are used at power-on to specify the frequency mode of the fsb pll circuitry. the ep80579 interprets bsel as follows: 0 = 400mhz fsb 1 = 533mhz fsb bsel is driven by the on-die cpu based on its configuration. v_sel lvttl,3.3v i/od 1 10k up bsc ia voltage select: the voltage select encodings are used in conjunction with bsel at power-on to specify the operating voltage of the ia cpu. this signal is a 3.3v od output with an external pullup. the ep80579 interprets v_sel as follows when bsel is 0 (400mhz fsb): 0 = 1.00v ia core voltage vccvc 1 = reserved and as follows when bsel is 1 (533mhz fsb): 0 = 1.30v ia core voltage vccvc 1 = 1.30v ia core voltage vccvc the voltage supply for these pins must be valid before the voltage regulator can supply vccvc to the processor. the v_sel pin is needed to support the processor voltage specification variations defined above. the vr must supply the voltage that is requested by the pins. wdt_tout# lvttl,3.3v o 1 bsc watchdog timer output signal: the signal is driven low when the main 35-bit down counter reaches zero during the second stage. the wdt_tout_cnf bit in the wdt lock register determines if the output is to change from the previous state if another time out occurs, or wdt_tout_n is driven low until the system is reset or power is cycled. total 5
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1759 intel ? ep80579 integrated processor 48.4.4 acceleration and i/o complex (aioc) 48.4.4.1 controller area network (can) bus table 48-21. controller area network bus signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode cn0rxd lvttl,3.3v i 1 bsc can bus channel 0: receive data signal. connect to the respective rxd of the external driver. cn0txd lvttl,3.3v o 1 bsc can bus channel 0: transmit data signal. connect to the respective txd of the external driver. cn0txen lvttl,3.3v o 1 bsc can bus channel 0: data enable signal. cn1rxd lvttl,3.3v i 1 bsc can bus channel 1: receive data signal. connect to the respective rxd of the external driver. cn1txd lvttl,3.3v o 1 bsc can bus channel 1: transmit data signal. connect to the respective txd of the external driver. cn1txen lvttl,3.3v o 1 bsc can bus channel 1: data enable signal. total 6
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1760 order number: 320066-003us 48.4.4.2 gigabit ethernet (gbe) interface table 48-22. gigabit ethernet interface signals (sheet 1 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode gbe0_txclk 2.5vcmos o 1 bsc gigabit ethernet controller port 0 transmit clock: transmit clock for gbe port 0. the interpretation of this signal depends on the interface mode that the controller is operating in. for rgmii this signal is the transmit clock, it is disabled for rmii. gbe0_txctl 2.5vcmos o 1 bsc gigabit ethernet controller port 0 transmit control: transmit control for gbe port 0. the interpretation of this signal depends on the interface mode that the controller is operating in. for rgmii and rmii, this signal is the transmit control and transmit enable, respectively. gbe0_txdata[3:0] 2.5vcmos o 4 bsc gigabit ethernet controller port 0 transmit control: transmit control for gbe port 0. the interpretation of these signals depends on the interface mode that the controller is operating in. for rgmii, gbe0_txdata[3:0] - transmit data and for rmii, gbe0_txdata[3:2] - disabled gbe0_txdata[1:0] - transmit data gbe0_rxclk 2.5vcmos i 1 bsc gigabit ethernet controller port 0 receive clock: receive clock for gbe port 0. the interpretation of this signal depends on the interface mode that the controller is operating in. for rgmii this signal is the receive clock, it is disabled for rmii. the gben_rxclk?s can be tied to gnd as they are not required in rmii mode ? only in rgmii. gbe0_rxctl 2.5vcmos i 1 bsc gigabit ethernet controller port 0 receive control: receive control for gbe port 0. the interpretation of this signal depends on the interface mode that the controller is operating in. for rgmii and rmii, this signal is the receive control and carrier sense/receive data valid, respectively. gbe0_rxdata[3:0] 2.5vcmos i 4 bsc gigabit ethernet controller port 0 receive data: receive data for gbe port 0. the interpretation of these signals depends on the interface mode that the controller is operating in. for rgmii, gbe0_rxdata[3:0] - receive data and for rmii, gbe0_rxdata[3] - receive error gbe0_rxdata[2] - disabled gbe0_rxdata[1:0] - receive data
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1761 intel ? ep80579 integrated processor gbe1_txclk 2.5vcmos o 1 bsc gigabit ethernet controller port 1 transmit clock: transmit clock for gbe port 1. see gbe0_txclk. gbe1_txctl 2.5vcmos o 1 bsc gigabit ethernet controller port 1 transmit control: transmit control for gbe port 1. see gbe0_txctl. gbe1_txdata[3:0] 2.5vcmos o 4 bsc gigabit ethernet controller port 1 transmit data: transmit data for gbe port 1. see gbe0_txdata[3:0]. gbe1_rxclk 2.5vcmos i 1 bsc gigabit ethernet controller port 1 receive clock: receive clock for gbe port 1. see gbe0_rxclk. gbe1_rxctl 2.5vcmos i 1 bsc gigabit ethernet controller port 1 receive control: receive control for gbe port 1. see gbe0_rxctl. gbe1_rxdata[3:0] 2.5vcmos i 4 bsc gigabit ethernet controller port 1 receive data: receive data for gbe port 1. see gbe0_rxdata[3:0]. gbe2_txclk 2.5vcmos o 1 bsc gigabit ethernet controller port 2 transmit clock: transmit clock for gbe port 2. see gbe0_txclk. gbe2_txctl 2.5vcmos o 1 bsc gigabit ethernet controller port 2 transmit control: transmit control for gbe port 2. see gbe0_txctl. gbe2_txdata[3:0] 2.5vcmos o 4 bsc gigabit ethernet controller port 2 transmit data: transmit data for gbe port 2. see gbe0_txdata[3:0]. gbe2_rxclk 2.5vcmos i 1 bsc gigabit ethernet controller port 2 receive clock: receive clock for gbe port 2. see gbe0_rxclk. gbe2_rxctl 2.5vcmos i 1 bsc gigabit ethernet controller port 2 receive control: receive control for gbe port 2. see gbe0_rxctl. gbe2_rxdata[3:0] 2.5vcmos i 4 bsc gigabit ethernet controller port 2 receive data: receive data for gbe port 2. see gbe0_rxdata[3:0]. mdc 2.5vcmos o 1 bsc gigabit ethernet controller management channel clock: serial clock for the management channel. mdio 2.5vcmos i/o 1 bsc gigabit ethernet controller management channel data: serial data for the management channel. table 48-22. gigabit ethernet interface signals (sheet 2 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1762 order number: 320066-003us gbe_refclk 2.5vcmos i 1 bsc gigabit ethernet controller reference clock: 50mhz or 125mhz (depend on mode) reference clock for the gbe controller. in rgmii mode or mixed mode (rgmii and rmii), the frequency of this clock must be 125mhz regardless of the individual port transmit and receive rates and this clock must always be present. in rmii mode (all ports only), there are two clocks required. the gbe_refclk_rmii is required as per the rmii spec. the gbe_refclk is also required for the rcomp controller and the retrieval of the port information from the eeprom. in rmii mode (all ports only), the gbe_refclk can be either 50mhz or 125mhz. if both clock are the same frequency, connecting gbe_refclk and gbe_refclk_rmii to the same source will work fine. gbe_refclk_rmii 2.5vcmos i 1 bsc gigabit ethernet controller rmii reference clock: 50mhz reference clock for the gbe controller in rmii mode. the frequency of this clock is 50mhz regardless of the individual port transmit / receive rates and must always be present. gbe_rcompp analog i/o 1 50 down (to vss) gigabit ethernet controller compensation: off- die reference resistor to which the output driver pull up output impedance is matched (nominally 50 ohms to ground). gbe_rcompn analog i/o 1 50 up (to vccsus25) gigabit ethernet controller compensation: off- die reference resistor to which the output driver pull down output impedance is matched (nominally 50 ohms to vccsus25). eedi 2.5vcmos o 1 10k up (if aux_pwr_ present), otherwise 4.7k down bsc gigabit ethernet controller eeprom input data: lvttl data output to serial eeprom. this pin is also sampled at an edge of gbe_aux_pwr_good to indicate the presence of the auxiliary power supply for gbe0. gigabit ethernet controller aux_pwr strap: this strap indicates if an auxiliary supply is being used for gbe0. the ep80579 interprets the strap as follows: 0 = no aux_pwr mode (i.e., auxiliary supply is not used). 1 = aux_pwr mode support (i.e., auxiliary supply is used) eedo 2.5vcmos i 1 bsc gigabit ethernet controller eeprom output data. eecs 2.5vcmos o 1 bsc gigabit ethernet controller eeprom chip select: chip select to enable the eeprom device. eesk 2.5vcmos o 1 bsc gigabit ethernet controller eeprom shift clock: clock for the eeprom interface, frequency is ~1mhz. table 48-22. gigabit ethernet interface signals (sheet 3 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1763 intel ? ep80579 integrated processor gbe_pme_wake 2.5vcmos od o 1 bsc gigabit ethernet controller wake: this active low signal is used by the gbe?s to signal that a pme event has occurred. it is the wired or of all three gigabit ethernet controllers on the ep80579 . sys_pwr_ok 2.5vcmos i 1 gigabit ethernet controller: this is the pwr_good signal used by gbes supplied by primary core power. this signal indicates that all chip power supplies are on and stable. this signal should be asserted once core power is stable. gbe_aux_pwr_go od 2.5vcmos i 1 gigabit ethernet controller power good: input signifying that the gbe port 0 and miscellaneous support io power supplies are on and stable (this is the pwr_good signal which is pinned out for gbe port 0 only). when an auxiliary power supply is used for gbe port 0, this signal should be asserted once that auxiliary power is stable. if core power is used for gbe port 0 then this pin should be tied to the core power ok signal sys_pwr_ok. total 49 table 48-22. gigabit ethernet interface signals (sheet 4 of 4) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1764 order number: 320066-003us 48.4.4.3 time division multiplexing (tdm) interface table 48-23. tdm interface signals a , b a. feature must be enabled with the ep80579 software. refer to the software for the intel ? ep80579 integrated processor product line. b. certain skus may not contain this feature. for complete information about product features, see section 47.2.1, ?sku features? . signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode rx_clk0 lvttl,3.3v i/o 1 bsc tdm interface port 0: receive clock. tx_clk0 lvttl,3.3v i/o 1 bsc tdm interface port 0: transmit clock. tx_frame0 lvttl,3.3v i/o 1 bsc tdm interface port 0: transmit frame. tx_data_out0 lvttl,3.3v o 1 bsc tdm interface port 0: transmit data output. rx_frame0 lvttl,3.3v i/o 1 bsc tdm interface port 0: receive frame. rx_data_in0 lvttl,3.3v i 1 bsc tdm interface port 0: receive data input. rx_clk1 lvttl,3.3v i/o 1 bsc tdm interface port 1: receive clock. tx_clk1 lvttl,3.3v i/o 1 bsc tdm interface port 1: transmit clock. tx_frame1 lvttl,3.3v i/o 1 bsc tdm interface port 1: transmit frame. tx_data_out1 lvttl,3.3v o 1 bsc tdm interface port 1: transmit data output. rx_frame1 lvttl,3.3v i/o 1 bsc tdm interface port 1: receive frame. rx_data_in1 lvttl,3.3v i 1 bsc tdm interface port 1: receive data input. rx_clk2 lvttl,3.3v i/o 1 bsc tdm interface port 2: receive clock. tx_clk2 lvttl,3.3v i/o 1 bsc tdm interface port 2: transmit clock. tx_frame2 lvttl,3.3v i/o 1 bsc tdm interface port 2: transmit frame. tx_data_out2 lvttl,3.3v o 1 bsc tdm interface port 2: transmit data output. rx_frame2 lvttl,3.3v i/o 1 bsc tdm interface port 2: receive frame. rx_data_in2 lvttl,3.3v i 1 bsc tdm interface port 2: receive data input. total 18
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1765 intel ? ep80579 integrated processor 48.4.4.4 local expansion bus (leb) interface table 48-24. expansion bus signals (sheet 1 of 3) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode ex_ale lvttl,3.3v o 1 bsc expansion bus address latch enable/advance/ ld#: address latch enable signal for the expansion bus. exale has pull-ups enabled when pll_lock is deasserted. these pull-ups are disabled when pll_lock is asserted and the ep80579 drives the signal based upon grant. exale is driven by the ep80579. ex_addr[24:0] lvttl,3.3v io 25 bsc expansion bus address: the 25-bit address bus for the expansion bus. exadx has pull-ups enabled when pll_lock is deasserted to allow sampling of configuration bits that select the address space size (see strapping discussion). these pull-ups are disabled when pll_lock is asserted and the ep80579 drives the signal based upon grant. exadx driven by the ep80579. expansion bus memory size strap: this strap selects the size of the memory space that the expansion bus claims for its mmio region. bits 23, 22, and 21 encode the size. the ep80579 interprets the value of the exad[23:21] pins as follows: 000b - 0mb (i.e., expansion bus disabled) 001b - 32mb 010b - 64mb 011b - 128mb 1xxb - 256mb note: expansion bus memory size should be configured by strapping or by pre-boot firmware to determine leb_size. ex_be[1:0]# lvttl,3.3v io 2 bsc expansion bus byte enable: byte enables for the 16-bit data bus in the expansion bus. exbex has pull-ups enabled when pll_lock is deasserted. these pull-ups are disabled when pll_lock is asserted and the ep80579 drives the signal based upon grant. exbex is driven by ep80579. these signals are active-low. ex_clk lvttl,3.3v i 1 bsc expansion bus clock: exclk is always an input. may be driven from a gpio clock or from an external clock source. maximum frequency: 80mhz minimum frequency: 33mhz
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1766 order number: 320066-003us ex_cs[7:0]# lvttl,3.3v io 8 bsc expansion bus target chip selects: chip selects to select expansion bus devices. excs has pull-ups enabled when pll_lock is deasserted. these pull-ups are disabled when pll_lock is asserted and the ep80579 drives the signal based upon grant. excs is driven by the ep80579. these signals are active-low. ex_data[15:0] lvttl,3.3v io 16 bsc expansion bus data: the 16-bit data bus for the expansion bus. exda has pull-ups enabled when pll_lock is deasserted. these pull-ups are disabled when pll_lock is asserted and the ep80579 drives the signal based upon grant. exda is driven by the ep80579 during outbound writes, and inbound reads, and when the bus is idle. ex_iowait# lvttl,3.3v i 1 bsc expansion bus target wait #. ex_iowait_n is always an input. reset value is driven from the board. this signal is active-low. ex_parity[1:0] lvttl,3.3v io 2 bsc expansion bus parity: parity bits for the two bytes on the data bus. expar0 = parity for exda[7:0] expar1 = parity for exda[15:8] exparx has pull-ups enabled when pll_lock is deasserted. these pull-ups are disabled when pll_lock is asserted. exparx is driven with the same timing as exdax. ex_rd# lvttl,3.3v io 1 bsc expansion bus read: read signal for the expansion bus. exrdn has pull-ups enabled when pll_lock is deasserted. these pull-ups are disabled when pll_lock is asserted and the ep80579 drives the signal based upon grant. exrdn is driven by the ep80579. this signal is active-low. ex_rdy[3:0]# lvttl,3.3v i 4 bsc expansion bus hpi ready: hpi ready signal for the expansion bus. exrdyx are always inputs. exrdy0 = ready signal for chip select #4 exrdy1 = ready signal for chip select #5 exrdy2 = ready signal for chip select #6 exrdy3 = ready signal for chip select #7 this signal is active-low. ex_burst lvttl,3.3v i 1 bsc expansion bus burst size: burst size signal. ex_burst is an input in normal operation. ex_wr# lvttl,3.3v io 1 bsc expansion bus write: write signal. this signal is active-low. table 48-24. expansion bus signals (sheet 2 of 3) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1767 intel ? ep80579 integrated processor ex_rcompp analog io 1 50 down expansion bus compensation: resistive compensation, controls the drive high strength of ex outputs. connect to a 50 pulldown resistor. ex_rcompn analog io 1 50 up (to vcc3p3) expansion bus compensation: resistive compensation, controls the drive low strength of the ex outputs. connect to a 50 pullup resistor, pulled up to vcc3p3. total 65 table 48-24. expansion bus signals (sheet 3 of 3) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1768 order number: 320066-003us 48.4.4.5 synchronous serial port (ssp) interface 48.4.4.6 ieee 1588-2008 hardware assist interface table 48-25. ssp interface signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode ssp_sclk lvttl,3.3v o 1 bsc ssp interface clock: serial bit-rate clock (1.84mhz maximum frequency). this is the bit- rate clock, driven from the ssp port to the peripheral. normally, it toggles only when data is actively being transmitted. ssp_sfrm lvttl,3.3v o 1 bsc ssp interface frame indicator: this is the framing signal and indicates the beginning and the end of a serialized data word. ssp_txd lvttl,3.3v o 1 bsc ssp interface transmit data: this is the transmit (i.e., outbound) serialized data lines. the word length and msb/lsb orientation are a function of the selected serial data format. ssp_rxd lvttl,3.3v i 1 bsc ssp interface receive data: this is the receive (i.e., inbound) serialized data lines. the word length and msb/lsb orientation are a function of the selected serial data format. ssp_extclk lvttl,3.3v i 1 bsc ssp interface external clock: this clock can be selected to replace the internally-generated clock that is used to generate the serial bit-rate clock (sspclk). total 5 table 48-26. ieee 1588-2008 hardware assist interface signals (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode 1588_testmode _data lvttl,3.3v o 1 bsc ieee 1588-2008 hardware assist test output: this signal will reflect bits of the internal system timer depending on the setting of internal control bits in the 1588_test register. 1588_pps lvttl,3.3v o 1 bsc ieee 1588-2008 hardware assist pulse per second output - this signal is asserted high when a match occurs between the compare register and lower 32 bits of system time. clearing of this signal is under firmware control. the register and pin can be used to create a pulse per second event. asmssig lvttl,3.3v i 1 bsc ieee 1588-2008 hardware assist auxiliary slave mode snapshot: an active high level on this input causes a snapshot of system time to be captured in the asms register. ammssig lvttl,3.3v i 1 bsc ieee 1588-2008 hardware assist auxiliary master mode snapshot: an active high level on this input causes a snapshot of system time to be captured in the amms register.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1769 intel ? ep80579 integrated processor 48.4.5 miscellaneous 48.4.5.1 jtag 1588_rx_snap lvttl,3.3v o 1 bsc ieee 1588-2008 hardware assist receive snapshot taken output: this signal will pulse high for eight pclks whenever a timestamp has been taken on the receive channel. the receive channel that is monitored is determined by the control bits in the ts_test register. 1588_tx_snap lvttl,3.3v o 1 bsc ieee 1588-2008 hardware assist transmit snapshot taken output: this signal will pulse high for eight pclks whenever a timestamp has been taken on the transmit channel. the transmit channel that is monitored is determined by the control bits in the ts_test register. total 6 table 48-27. jtag interface signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode tms lvcmos, 1.2v i1 test interface: test mode select. input in normal operation. tdi lvcmos, 1.2v i1 test interface: test data in. input in normal operation. tdo lvcmos, 1.2v od o 1 test interface: test data out tck lvcmos, 1.2v i1 test interface: test clock. input in normal operation. trst# lvcmos, 1.2v i1 test interface: test reset. input in normal operation. bpm0 sstl_18 od i/o 1 bsc itp debug interface bpm1 sstl_18 od i/o 1 bsc itp debug interface bpm2 sstl_18 od i/o 1 bsc itp debug interface bpm3 sstl_18 od i/o 1 bsc itp debug interface bpm3_in lvcmos, 1.2v i1 bsc itp debug interface: ia-32 core breakpoint monitor. should be a nc (no-connect, left floating) if not used. bpm4_prdy_out lvttl,3.3v od o 1 50 ohm pullup to 1.2v bsc itp debug interface: ia-32 core prdy. open drain output. bpm5_preq_in lvcmos, 1.2v i1 bsc itp debug interface: ia-32 core preq should be a nc (no-connect, left floating) if not used. total 12 table 48-26. ieee 1588-2008 hardware assist interface signals (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1770 order number: 320066-003us 48.4.5.2 miscellaneous signals 48.4.5.3 reserved table 48-28. miscellaneous signals signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode pme# lvttl,3.3v i/od 1 bsc pci power management event: driven by pci peripherals to wake the system from low-power states s3, s4 and s5. it can also cause an sci from the s0 state. note that in some cases the ep80579 may drive pme# active (low) due to an internal wake event. it will not drive pme# high (but it may be pulled up using the internal pull- up resistor). pme# is in the 3.3v vccpsus power plane and has an internal pull-up resistor. pcirst# lvttl,3.3v o 1 bsc pci reset: this is the secondary parallel pci bus reset signal. it is a logical or of the primary interface pltrst# signal and the state of the secondary bus reset bit. note: pcirst# is in the 3.3v vccpsus well. spkr lvttl,3.3v o 1 bsc speaker: the spkr signal is the output of counter 2 and is internally ?anded? with port 061h bit 1 to provide speaker data enable. this signal drives an external speaker driver device, which in turn drives the system speaker. upon pltrst#, its output state is 0. this signal has a weak internal pull-down resistor. spkr is sampled at platform reset as a functional strap. no reboot strap: this strap controls the re-boot behavior of timeouts in the tco timer. the ep80579 interprets the strap as follows: 0 = reboot on second timeout of tco timer (default). 1 = no re-boot on second timeout of tco timer. total 3 table 48-29. reserved pin list (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode reserved0 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved1 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved2 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1771 intel ? ep80579 integrated processor 48.4.5.4 no connect reserved3 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved4 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved5 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved6 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved7 1 bsc reserved: this signal must be connected to vss. reserved8 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved9 1 bsc reserved: this signal must be connected to vss. reserved10 1 10k up bsc reserved: must have external pull-up to vccpsus. reserved11 1 bsc reserved: this pin must be tied low (vss) externally on the platform. reserved12-14 3 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved15 1 bsc reserved: this signal must be connected to vss. reserved16 lvttl,3.3v i 1 10k up bsc reserved: this signal must be connected to a 10k-ohm pull-up to 3.3v. reserved17 lv i/o 1 bsc reserved: this signal must be connected to vss. reserved18 lvttl,3.3v i 1 10k down bsc reserved: this signal must be connected to vss via 10k-ohm pulldown. reserved19-20 lvttl,3.3v i 2 10k up bsc reserved: this signal must be connected to a 10k-ohm pull-up to 3.3v. total 21 table 48-30. no connect pin list (sheet 1 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode nc_sus_two 1 bsc no connect nc_two 1 bsc no connect nc7 1 bsc no connect nc9 1 bsc no connect nc10 1 bsc no connect nc11 1 bsc no connect table 48-29. reserved pin list (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1772 order number: 320066-003us 48.4.6 power nc12 1 no connect. nc13 1 no connect. nc14 1 no connect. nc15 1 no connect. nc16 1 no connect. nc17 1 no connect nc18 1 no connect nc19 1 no connect nc20 1 no connect nc21 1 no connect nc22 1 no connect nc34 1 bsc no connect nc35 1 bsc no connect nc36 1 bsc no connect nc37 1 bsc no connect nc38 1 bsc no connect nc40-nc47 8 bsc no connect nc48 1 bsc no connect nc50-nc53 4 bsc no connect nc54 1 bsc no connect nc55 1 bsc no connect nc56 1 10k down reserved: this signal must be connected to vss via 10k-ohm pulldown. nc57-nc59 3 bsc noconnect total 41 table 48-31. power and ground summary pin list (sheet 1 of 2) signal name signal description normal/alternate mode ball count vccausb12 1.2v power supply for usb interface. analog power. 3 vcc 1.2v power supply 85 vcc18 1.8v power supply for ddr circuitry. io power. 20 vcctmp18 1.8v power supply for the thermal sensor. this supply can be optionally shut off in s3 sustain mode. 1 vccusb12 1.2v power supply for usb interface. digital power. 7 vcc1p2_usbsus 1.2v sustain supply for core logic in usb interface. 1 vcc33 3.3v power supply 15 table 48-30. no connect pin list (sheet 2 of 2) signal name io type direction ball count external pull-up/ down [ohms] bsc/ xor signal description normal/alternate mode
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1773 intel ? ep80579 integrated processor 48.5 flip-chip ball grid array (fcbga) package dimensions the fcbga package is shown in the following illustrations: ? figure 48-1, ?fcbga package ? top and side views? on page 1775 vccgbe33 3.3v power supply for gigabit ethernet interfaces. 1 vccsata33 3.3v power supply for sata interface. 1 vcc50 5.0v power supply 7 vcc50_sus 5.0v power supply for 5.0v tolerance in sustain well 1 vcca[1] 1.20v power supply for ia-32 core. minimum voltage is 1.20v-5%, even in low- power applications. 1 vcca[2] 1.20v power supply for ia-32 core. minimum voltage is 1.20v-5%, even in low- power applications. 1 vccabg3p3_usb 3.3v power supply for usb interface. analog bandgap power. 1 vccabgp033 3.3v power supply for pci express circuitry. analog bandgap power. 1 vccahpll analog 1.2v supply for cru circuitry (cru pll and refclk inputs). 1 vccape 1.2v power supply for pci express circuitry. analog power. 12 vccape0pll12 1.2v power supply for pci express circuitry. pll digital power. 2 vccapll 1.2v power supply for sata interface. 1 vccarx 1.2v power supply for sata interface. analog receiver power. 3 vccasatabg3p3 3.3v power supply for sata interface. analog bandgap power. 1 vccatx 1.2v power supply for sata interface. analog transmitter power. 3 vccvc 1.30v or 1.00v cpu power supply for ia-32 core. this supply is 1.30v for 1200mhz, 1.30v for 1066mhz, and 1.00v for 600mhz (see v_sel signal description in the ich miscellaneous signals). 1 vcc25 2.5v power supply for gigabit ethernet interfaces. 4 vccsus25 2.5v sustain power supply for gigabit ethernet interfaces. 4 vccprtc 3.3v power supply for the rtc (this supply can drop to 2.0v if all other planes are shut off). this power is not expected to be shut off unless the rtc battery is removed or drained.mthellomthellonote: implementations must not attempt to clear cmos by using a jumper to pull vccprtc low. clearing cmos can be done by using a jumper on rtest_n or gpi. 1 vccpsus 3.3v sustain supply for io logic 3 vccgbepsus 3.3v sustain supply for io logic for gigabit ethernet interfaces. 1 vccrpe 1.2v power supply for pci express circuitry. digital receiver power. 8 vccsata 1.2v power supply for sata interface. 2 vccsus1 1.2v sustain supply for core logic 4 vccvc 1.30v or 1.00v cpu power supply for ia-32 core. this supply is 1.30v for 1200mhz, 1.30v for 1066mhz, and 1.00v for 600mhz (see v_sel signal description in the ich miscellaneous signals). 45 vss ground 292 vssa analog ground 1 vttddr 0.9v power supply for ddr circuitry. terminal voltage. 14 total 549 table 48-31. power and ground summary pin list (sheet 2 of 2) signal name signal description normal/alternate mode ball count
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1774 order number: 320066-003us ? figure 48-2, ?fcbga package ? front and detail views? on page 1776 ? figure 48-3, ?fcbga package ? bottom view? on page 1777
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1775 intel ? ep80579 integrated processor figure 48-1. fcbga package ? top and side views b6452-03 this drawing contains intel corporation confidential information . it is disclosed in confidence and its contents may not be disclosed, reproduced, displayed or modified, without the prior written consent of intel corporation. symbol millimeters [inches] min max e 37.45 [1.474] 37.55 [1.478] d 37.45 [1.474] 37.55 [1.478] c 1 33.5 [1.319] c 2 33.5 [1.319] a 3.386 [.133] 3.78 [.149] a 1 0.4 [.016] 0.6 [.024] a 2 e 1 34.944 basic [1.376] d 1 34.944 basic [1.376] h 1 17.472 basic [0.6879] h 2 17.472 basic [0.6879] e 1.092 basic [0.043] b 0.61 [.024] comments 1 [.039] c b 1 [.039] c a ?0.203 [.008] l c a ?0.04 [.002] l b c 1.085 [.043] 1.255 [.049] top view e c 1 b c 2 d a side view
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1776 order number: 320066-003us figure 48-2. fcbga package ? front and detail views b6453-02 this drawing contains intel corporation confidential information. it is disclosed in confidence and its contents may not be disclosed, reproduced, displayed or modified, without the prior written consent of intel corporation . symbol millimeters (inches) min max e 37.45 [1.474] 37.55 [1.478] d 37.45 [1.474] 37.55 [1.478] c 1 33.5 [1.319] c 2 33.5 [1.319] a 3.386 [.133] 3.78 [.149] a 1 0.4 [.016] 0.6 [.024] a 2 e 1 34.944 basic [1.376] d 1 34.944 basic [1.376] h 1 17.472 basic [0.6879] h 2 17.472 basic [0.6879] e 1.092 basic [0.043] b 0.61 [.024] comments 1 [.039] c b 1 [.039] c a ?0.203 [.008] l c a ?0.04 [.002] l b c 1.085 [.043] 1.255 [.049] front view a detail a scale 20:1 a c ?b ihs lid 0.125 [.005] 0.203 [.008] c ihs sealant a 1 package substrate a 2
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1777 intel ? ep80579 integrated processor figure 48-3. fcbga package ? bottom view b6454-03 this drawing contains intel corporation confidential information. it is disclosed in confidence and its contents may not be disclosed, reproduced, displayed or modified, without the prior written consent of intel corporation . symbol millimeters [inches] min max e 37.45 [1.474] 37.55 [1.478] d 37.45 [1.474] 37.55 [1.478] c 1 33.5 [1.319] c 2 33.5 [1.319] a 3.386 [.133] 3.78 [.149] a 1 0.4 [.016] 0.6 [.024] a 2 e 1 34.944 basic [1.376] d 1 34.944 basic [1.376] h 1 17.472 basic [0.6879] h 2 17.472 basic [0.6879] e 1.092 basic [0.043] comments 1 [.039] c b 1 [.039] c a ?0.203 [.008] l c a ?0.04 [.002] l b c 1.085 [.043] 1.255 [.049] bottom view h 1 e 1 h 2 d 1 e e an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 13 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24 27 26 29 28 31 30 33 32 detail f multiple places 0.015 min f f ?0.630.01 (metal diameter) ?0.560.02 (solder resist opening) solder resist opening ?0.560.02 [0.022] see detail f above b 0.61 [0.024]
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1778 order number: 320066-003us 48.6 ball map information this section contains the following ball map information: ? table 48-32, ?alphabetical ball listing? on page 1779 ? table 48-33, ?alphabetical signal listing? on page 1788 ? table 48-34, ?ep80579 ball map (bottom view, left side)? on page 1797 ? table 48-35, ?ep80579 ball map (bottom view, right side)? on page 1799 ? table 48-36, ?ep80579 ball map (top view, left side)? on page 1801 ? table 48-37, ?ep80579 ball map (top view, right side)? on page 1803 ? table 48-38, ?package trace length? on page 1805
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1779 48.0 package specifications table 48-32. alphabetical ball listing ball signal a2 vss a3 vss a4 gpio[15] a5 pltrst# a6 slp_s3# a7 vss a8 nc22 a9 usb_rbiasn a10 vss a11 usbn0 a12 usbn1 a13 vss a14 sata_rxp0 a15 sata_rxp1 a16 vss a17 pea0_rn[6] a18 pea0_rp[7] a19 pea0_rn[4] a20 pea0_rp[5] a21 vss a22 pea_icompo a23 vss a24 pea0_rn[3] a25 pea0_rp[2] a26 pea0_rn[1] a27 pea0_rp[0] a28 vccape a29 vccvc a30 vss a31 vss a32 vss a33 vss b1 vss b2 vss b3 pme# b4 gpio[10] b5 smlink[1] b6 sus_stat# b7 vccusb12 b8 nc21 b9 usb_rbiasp b10 vccusb12 b11 usbp0 b12 usbp1 b13 vccarx b14 sata_rxn0 b15 sata_rxn1 b16 vccatx b17 pea0_rp[6] b18 pea0_rn[7] b19 pea0_rp[4] b20 pea0_rn[5] b21 vccape b22 pea_icompi b23 vccrpe b24 pea0_rp[3] b25 pea0_rn[2] b26 pea0_rp[1] b27 pea0_rn[0] b28 vss b29 reserved17 b30 vccvc b31 clkn100 b32 vss b33 vss c1 vss c2 vss c3 vss c4 vss c5 smbclk c6 vss c7 slp_s4# c8 vccusb12 c9 vss c10 vss c11 vccusb12 c12 vss c13 vccsata33 c14 vccarx c15 vccapll c16 vccatx c17 vss ball signal c18 vccrpe c19 vccape c20 vss c21 vss c22 vccape c23 vss c24 vccape c25 vss c26 vccrpe c27 vss c28 vccape c29 vss c30 clkp100 c31 nc35 c32 bpm2 c33 vss d1 gp2_pirqe# d2 vss d3 vss d4 gpio[9] d5 gpio[8] d6 reserved10 d7 sys_reset# d8 ri# d9 vss d10 vss d11 clk48 d12 oc[1]# d13 vccausb12 d14 sata_txp0 d15 sata_txp1 d16 vss d17 pea0_tn[6] d18 pea0_tp[7] d19 pea0_tn[4] d20 pea0_tp[5] d21 vccrpe d22 pea_clkn d23 vccrpe d24 pea0_tn[3] d25 pea0_tp[2] ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1780 48.0 package specifications d26 pea0_tn[1] d27 pea0_tp[0] d28 nc19 d29 nc54 d30 nc38 d31 ddr_ck[4] d32 ddr_ck[4]# d33 vss e1 vss e2 vss e3 vss e4 gp11_smbalert# e5 vcc33 e6 vss e7 susclk e8 vss e9 vccusb12 e10 vss e11 vss e12 oc[0]# e13 vss e14 sata_txn0 e15 sata_txn1 e16 vccatx e17 pea0_tp[6] e18 pea0_tn[7] e19 pea0_tp[4] e20 pea0_tn[5] e21 pea_rcompo e22 pea_clkp e23 vccrpe e24 pea0_tp[3] e25 pea0_tn[2] e26 pea0_tp[1] e27 pea0_tn[0] e28 nc17 e29 nc34 e30 nc50 e31 ddr_dq[4] e32 ddr_dq[5] e33 bpm0 ball signal f1 rtcx1 f2 rtcx2 f3 reserved11 f4 wdt_tout# f5 vss f6 vss f7 vss f8 vss f9 vss f10 vccpsus f11 vccusb12 f12 nc20 f13 vccausb12 f14 vccarx f15 sata_rbias f16 sata_rbias# f17 vccrpe f18 vccape0pll12 f19 vccape f20 vccape0pll12 f21 vccape f22 vccrpe f23 vccape f24 vcca[2] f25 vccape f26 thermda f27 thermdc f28 nc18 f29 vttddr f30 vss f31 ddr_dm[0] f32 ddr_dq[0] f33 ddr_dq[1] g1 gp5_pirqh# g2 v_sel g3 rsmrst# g4 gp29_sata1gp g5 gpio[14] g6 smbdata g7 pcirst# g8 vss ball signal g9 vss g10 vccusb12 g11 vccpsus g12 vss g13 sata_clkrefp g14 sata_clkrefn g15 vccabgp033 g16 vccape g17 vss g18 nc15 g19 nc12 g20 vccape g21 reserved9 g22 vccvc g23 vss g24 vcca[1] g25 vss g26 ddr_ck[5] g27 ddr_ck[5]# g28 bpm3 g29 vss g30 vcc18 g31 nc40 g32 ddr_dqs[0] g33 ddr_dqs[0]# h1 gp3_pirqf# h2 gpio[12] h3 gp16_irq24 h4 vcc33 h5 vss h6 vcc33 h7 smlink[0] h8 pwrbtn# h9 slp_s5# h10 vccsus1 h11 vss h12 vccabg3p3_usb h13 vss h14 vccsata h15 vccasatabg3p3 h16 vss ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1781 48.0 package specifications h17 vss h18 nc13 h19 nc14 h20 nc16 h21 vccvc h22 vss h23 vccvc h24 vccvc h25 vss h26 vccvc h27 vccvc h28 ddr_cs[0]# h29 vss h30 ddr_dq[7] h31 ddr_dq[6] h32 vss h33 ddr_dq[12] j1 serirq j2 vss j3 sataled# j4 gpio[7] j5 gpio[1] j6 nc_sus_two j7 gp25_irq38 j8 gp28_irq30 j9 vss j10 vccsus1 j11 vccpsus j12 vcc1p2_usbsus j13 vccausb12 j14 vccsata j15 vss j16 vccvc j17 vss j18 vccvc j19 vss j20 vccvc j21 vss j22 vccvc j23 vss j24 vccvc ball signal j25 nc51 j26 vccvc j27 ddr_ck[3]# j28 ddr_ck[3] j29 vcc18 j30 vss j31 ddr_dq[3] j32 ddr_dq[2] j33 ddr_dq[13] k1 lframe# k2 gp18_irq36 k3 gp17_irq25 k4 vcc50_sus k5 vss k6 pwrok k7 gp24_irq29 k8 gp27_irq39 k9 vcc50 k10 vss k11 vcc k12 vss k13 vcc k14 vss k15 vccvc k16 vss k17 vccvc k18 vss k19 vccvc k20 vss k21 vccvc k22 vss k23 vccvc k24 vss k25 nc48 k26 nc36 k27 nc37 k28 ddr_cs[1]# k29 vss k30 vcc18 k31 ddr_dq[8] k32 ddr_dq[9] ball signal k33 ddr_dm[1] l1 gp23_irq28 l2 ldrq[0]# l3 lad[2] l4 lad[3] l5 lad[1] l6 gpio[0] l7 rtest# l8 intruder# l9 vss l10 vcc l11 vss l12 vcc l13 vss l14 vcc l15 vss l16 vccvc l17 vss l18 vccvc l19 vss l20 vccvc l21 vss l22 vccvc l23 vss l24 vccvc l25 vss l26 ddr_odt1 l27 nc52 l28 vss l29 vttddr l30 vss l31 ddr_dqs[1] l32 ddr_dqs[1]# l33 nc41 m1 rcin# m2 smi_out# m3 vss m4 vcc33 m5 vccprtc m6 vss m7 cpupwrgd_out ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1782 48.0 package specifications m8 bsel m9 vccsus1 m10 vccsus1 m11 vcc m12 vss m13 vcc m14 vss m15 vcc m16 vss m17 vccvc m18 vss m19 vccvc m20 vss m21 vccvc m22 vss m23 vccvc m24 vss m25 ddr_cke[1] m26 bpm1 m27 ddr_dq[21] m28 ddr_dq[20] m29 vss m30 vcc18 m31 ddr_dq[10] m32 ddr_dq[15] m33 ddr_dq[14] n1 clk14 n2 pciclk n3 stpclk_out# n4 gp21_irq27 n5 gp30_irq31 n6 lad[0] n7 gp4_pirqg# n8 gpio[13] n9 gpio[6] n10 vcc n11 vss n12 vcc n13 vss n14 vcc n15 vss ball signal n16 vcc n17 vss n18 vccvc n19 vss n20 vccvc n21 vss n22 vccvc n23 vss n24 vccvc n25 vcctmp18 n26 vss n27 ddr_dq[17] n28 ddr_dq[16] n29 vcc18 n30 vss n31 ddr_dq[29] n32 ddr_dq[28] n33 ddr_dq[11] p1 gp26_sata0gp p2 spkr p3 gp40_irq35 p4 gp33_irq33 p5 cpuslp_out# p6 gp41_ldrq[1]# p7 gp20_irq26 p8 gp19_irq37 p9 vcc50 p10 vss p11 vcc p12 vss p13 vcc p14 vss p15 vcc p16 vss p17 vcc p18 vss p19 vccvc p20 vss p21 vccvc p22 vss p23 vccvc ball signal p24 vss p25 vccvc p26 vss p27 nc42 p28 ddr_dm[2] p29 vss p30 vcc18 p31 vss p32 ddr_dq[25] p33 ddr_dq[24] r1 siu_cts1# r2 siu_txd1 r3 siu_rxd1 r4 vss r5 nmi r6 vcc33 r7 vss r8 vcc r9 vcc33 r10 vcc r11 vss r12 vcc r13 vss r14 vcc r15 vss r16 vcc r17 vss r18 vccvc r19 vss r20 vccvc r21 vss r22 vccvc r23 vss r24 vccvc r25 vss r26 vss r27 vcc18 r28 vss r29 ddr_dqs[2] r30 ddr_dqs[2]# r31 vss ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1783 48.0 package specifications r32 ddr_dm[3] r33 nc43 t1 siu_dcd2# t2 siu_cts2# t3 siu_txd2 t4 siu_rxd2 t5 siu_dcd1# t6 prochot# t7 gp34_irq34 t8 nc7 t9 vss t10 vss t11 vcc t12 vss t13 vcc t14 vss t15 vcc t16 vss t17 vcc t18 vss t19 vccahpll t20 vss t21 vccvc t22 vss t23 vccvc t24 vccvc t25 vcc18 t26 vss t27 ddr_dq[31] t28 ddr_dq[18] t29 ddr_dq[23] t30 ddr_dq[22] t31 ddr_dq[30] t32 ddr_dqs[3]# t33 ddr_dqs[3] u1 cpurst# u2 pe_hpintr# u3 nc_two u4 thrmtrip# u5 gpio[48] u6 siu_rts1# ball signal u7 siu_dtr1# u8 uart_clk u9 vcc50 u10 vcc u11 vss u12 vcc u13 vss u14 vcc u15 vss u16 vcc u17 vss u18 vcc u19 vssa u20 vcc u21 vss u22 vcc u23 vccvc u24 vcc u25 vccvc u26 vccvc u27 ddr_dq[27] u28 ddr_dq[19] u29 ddr_cres[2] u30 ddr_cres[1] u31 ddr_ck[2]# u32 ddr_ck[2] u33 ddr_dq[26] v1 init33v_out# v2 a20gate v3 vss v4 vcc33 v5 siu_dsr1# v6 vss v7 vrmpwrgd v8 vss v9 nc10 v10 vss v11 vcc v12 vss v13 vcc v14 vss ball signal v15 vcc v16 vss v17 vcc v18 vss v19 vcc v20 vss v21 vcc v22 vttddr v23 vcc v24 vttddr v25 vss v26 ddr_rcompx v27 ddr_cres[0] v28 ddr_slewcres v29 vttddr v30 ddr_ck[0] v31 ddr_ck[0]# v32 ddr_ecc[4] v33 ddr_drvcres w1 siu_ri2# w2 gp31_irq32 w3 siu_ri1# w4 siu_dsr2# w5 bpm5_preq_in w6 pwrgd w7 reserved15 w8 nc9 w9 nc11 w10 vcc w11 vss w12 vcc w13 vss w14 vcc w15 vss w16 vcc w17 vss w18 vcc w19 vss w20 vcc w21 vss w22 vcc ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1784 48.0 package specifications w23 vss w24 vcc w25 vss w26 ddr_dq[37] w27 ddr_dq[32] w28 ddr_dq[33] w29 vss w30 vcc18 w31 ddr_ecc[5] w32 ddr_ck[1] w33 ddr_ck[1]# y1 smbsda y2 bpm3_in y3 tck y4 siu_rts2# y5 smbscl y6 reserved16 y7 trst# y8 reserved6 y9 vcc50 y10 vss y11 vcc y12 vss y13 vcc y14 vss y15 vcc y16 vss y17 vcc y18 vss y19 vcc y20 vss y21 vcc y22 vss y23 vcc y24 vss y25 ddr_dq[36] y26 ddr_dm[4] y27 ddr_dqs[4] y28 ddr_dqs[4]# y29 vcc18 y30 vss ball signal y31 ddr_dm[8] y32 ddr_ecc[0] y33 ddr_ecc[1] aa1 tdi aa2 siu_dtr2# aa3 bpm4_prdy_out aa4 vss aa5 reserved8 aa6 vcc33 aa7 reserved7 aa8 vss aa9 tx_data_out1 aa10 vcc aa11 vss aa12 vcc aa13 vss aa14 vcc aa15 vss aa16 vcc aa17 vss aa18 vcc aa19 vss aa20 vcc aa21 vss aa22 vcc aa23 vss aa24 vcc aa25 vttddr aa26 nc44 aa27 ddr_dq[38] aa28 ddr_dq[39] aa29 vss aa30 vcc18 aa31 nc53 aa32 ddr_dqs[8] aa33 ddr_dqs[8]# ab1 reserved5 ab2 reserved3 ab3 reserved0 ab4 tx_clk0 ab5 tms ball signal ab6 reserved4 ab7 tx_frame0 ab8 rx_frame1 ab9 reserved18 ab10 vss ab11 vcc ab12 vss ab13 vcc ab14 vss ab15 vcc ab16 vss ab17 vcc ab18 vss ab19 vcc ab20 vss ab21 vcc ab22 vss ab23 vcc ab24 vss ab25 vss ab26 ddr_dq[34] ab27 ddr_dq[52] ab28 ddr_dq[35] ab29 vttddr ab30 vss ab31 ddr_ecc[2] ab32 ddr_ecc[6] ab33 ddr_ecc[7] ac1 tx_data_out0 ac2 rx_frame0 ac3 rstin# ac4 ierr# ac5 reserved1 ac6 rx_clk0 ac7 vss ac8 spi_mosi ac9 vcc50 ac10 vcc ac11 vss ac12 vcc ac13 vss ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1785 48.0 package specifications ac14 vcc ac15 vss ac16 vcc ac17 vss ac18 vcc ac19 vss ac20 vcc ac21 vss ac22 vcc ac23 vss ac24 vcc ac25 vttddr ac26 ddr_dq[49] ac27 ddr_dq[48] ac28 ddr_dq[53] ac29 vss ac30 vcc18 ac31 ddr_dq[45] ac32 ddr_ecc[3] ac33 ddr_dq[44] ad1 tx_frame1 ad2 rx_clk1 ad3 vss ad4 vcc33 ad5 tx_clk2 ad6 tx_frame2 ad7 rx_data_in2 ad8 cn0txd ad9 nc59 ad10 vss ad11 vcc ad12 vss ad13 vcc ad14 vss ad15 vcc ad16 vss ad17 vcc ad18 vss ad19 vcc ad20 vss ad21 vcc ball signal ad22 vss ad23 vcc ad24 vss ad25 vss ad26 ddr_dq[55] ad27 ddr_dm[6] ad28 nc46 ad29 vcc18 ad30 vss ad31 ddr_dm[5] ad32 ddr_dq[40] ad33 ddr_dq[41] ae1 rx_data_in1 ae2 tx_data_out2 ae3 rx_frame2 ae4 rx_data_in0 ae5 rx_clk2 ae6 nc56 ae7 cn0txen ae8 vss ae9 vcc33 ae10 vss ae11 vcc50 ae12 vss ae13 vss ae14 vcc50 ae15 reserved19 ae16 gbe_pme_wake ae17 gbe_rcompn ae18 vccsus25 ae19 vccgbe33 ae20 vcc25 ae21 vss ae22 vss ae23 vss ae24 vttddr ae25 vss ae26 ddr_dq[50] ae27 ddr_dqs[6] ae28 ddr_dqs[6]# ae29 vss ball signal ae30 vcc18 ae31 nc45 ae32 ddr_dqs[5] ae33 ddr_dqs[5]# af1 spi_miso af2 spi_cs# af3 spi_sclk af4 tx_clk1 af5 cn0rxd af6 vcc33 af7 ssp_rxd af8 ex_addr[19] af9 ex_addr[11] af10 ex_addr[5] af11 ex_cs[5]# af12 vss af13 vss af14 ex_data[1] af15 ex_rdy[1]# af16 eesk af17 gbe_rcompp af18 vss af19 gbe1_txctl af20 gbe1_txdata[1] af21 gbe2_txdata[3] af22 gbe2_txdata[0] af23 vttddr af24 vss af25 vss af26 ddr_dq[51] af27 ddr_ras# af28 ddr_dq[54] af29 vttddr af30 vss af31 ddr_dq[46] af32 ddr_dq[42] af33 ddr_dq[47] ag1 1588_rx_snap ag2 tdo ag3 1588_tx_snap ag4 vss ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1786 48.0 package specifications ag5 cn1txen ag6 vss ag7 ex_addr[17] ag8 ex_addr[13] ag9 ex_addr[7] ag10 ex_cs[3]# ag11 ex_rcompn ag12 ex_data[13] ag13 ex_data[5] ag14 nc57 ag15 ex_rdy[3]# ag16 eedi ag17 mdc ag18 vccsus25 ag19 vss ag20 vccgbepsus ag21 gbe2_txctl ag22 gbe2_txdata[1] ag23 vss ag24 vss ag25 vttddr ag26 ddr_ba[2] ag27 ddr_a[14] ag28 vss ag29 vss ag30 vcc18 ag31 ddr_dq[61] ag32 ddr_dq[43] ag33 ddr_dq[60] ah1 reserved2 ah2 asmssig ah3 ssp_extclk ah4 ssp_sfrm ah5 vss ah6 ex_addr[21] ah7 ex_addr[20] ah8 vss ah9 ex_addr[1] ah10 ex_clk ah11 vcc33 ah12 ex_data[11] ball signal ah13 ex_data[3] ah14 vss ah15 nc58 ah16 eecs ah17 mdio ah18 gbe0_txdata[0] ah19 gbe1_txclk ah20 gbe1_txdata[3] ah21 gbe2_rxdata[1] ah22 gbe2_txdata[2] ah23 vss ah24 vss ah25 vss ah26 ddr_a[12] ah27 ddr_a[9] ah28 ddr_a[11] ah29 vcc18 ah30 vss ah31 ddr_dqs[7]# ah32 ddr_dq[56] ah33 ddr_dq[57] aj1 ammssig aj2 vss aj3 cn1txd aj4 ssp_sclk aj5 ex_addr[23] aj6 ex_addr[15] aj7 vss aj8 vss aj9 ex_addr[3] aj10 ex_cs[7]# aj11 ex_rcompp aj12 vss aj13 ex_data[7] aj14 reserved20 aj15 ex_rdy[2]# aj16 reserved12 aj17 sys_pwr_ok aj18 gbe0_txdata[3] aj19 vcc25 aj20 vss ball signal aj21 vcc25 aj22 gbe2_txclk aj23 vss aj24 vss aj25 vttddr aj26 ddr_a[7] aj27 ddr_a[8] aj28 ddr_a[6] aj29 vss aj30 vcc18 aj31 ddr_dqs[7] aj32 ddr_dm[7] aj33 nc47 ak1 1588_pps ak2 cn1rxd ak3 ssp_txd ak4 ex_ale ak5 ex_addr[9] ak6 vss ak7 ex_addr[12] ak8 ex_addr[2] ak9 ex_addr[0] ak10 vss ak11 ex_data[14] ak12 vss ak13 ex_data[4] ak14 ex_rd# ak15 vss ak16 eedo ak17 vss ak18 vccsus25 ak19 gbe0_txdata[2] ak20 gbe0_txdata[1] ak21 gbe1_txdata[2] ak22 gbe1_rxdata[0] ak23 gbe1_txdata[0] ak24 vss ak25 vcc18 ak26 ddr_a[5] ak27 ddr_a[4] ak28 ddr_a[3] ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1787 48.0 package specifications ak29 vttddr ak30 vss ak31 vss ak32 vss ak33 vss al1 vss al2 1588_testmode_data al3 ex_addr[24] al4 vss al5 vcc33 al6 ex_addr[14] al7 ex_be[1]# al8 vss al9 vcc33 al10 ex_cs[0]# al11 ex_data[12] al12 ex_data[9] al13 ex_data[2] al14 ex_parity[1] al15 vcc33 al16 reserved13 al17 gbe_refclk_rmii al18 gbe0_rxclk al19 gbe0_txclk al20 gbe0_txctl al21 gbe1_rxdata[3] al22 gbe2_rxclk al23 gbe2_rxdata[2] al24 gbe2_rxdata[0] al25 vss al26 nc55 al27 ddr_a[1] al28 ddr_a[2] al29 ddr_odt0 al30 ddr_dq[58] al31 ddr_dq[62] al32 ddr_dq[63] al33 vss am1 vss am2 vss am3 ex_addr[22] ball signal am4 ex_addr[18] am5 ex_addr[10] am6 vss am7 ex_addr[4] am8 ex_cs[6]# am9 ex_cs[2]# am10 vss am11 ex_data[10] am12 ex_data[6] am13 vss am14 ex_parity[0] am15 ex_rdy[0]# am16 reserved14 am17 vccsus25 am18 gbe0_rxctl am19 vss am20 gbe0_rxdata[0] am21 gbe1_rxctl am22 vcc25 am23 vss am24 gbe2_rxdata[3] am25 vcc18 am26 ddr_a[0] am27 ddr_a[10] am28 ddr_ba[0] am29 ddr_ba[1] am30 ddr_dq[59] am31 vcc18 am32 vss am33 vss an1 vss an2 vss an3 vss an4 ex_addr[16] an5 ex_addr[8] an6 ex_addr[6] an7 ex_be[0]# an8 ex_cs[4]# an9 ex_cs[1]# an10 ex_data[15] an11 ex_data[8] ball signal an12 ex_data[0] an13 ex_iowait# an14 ex_burst an15 ex_wr# an16 gbe_aux_pwr_good an17 gbe_refclk an18 gbe0_rxdata[3] an19 gbe0_rxdata[2] an20 gbe0_rxdata[1] an21 gbe1_rxclk an22 gbe1_rxdata[2] an23 gbe1_rxdata[1] an24 gbe2_rxctl an25 vss an26 ddr_cas# an27 ddr_a[13] an28 ddr_we# an29 ddr_cke[0] an30 vss an31 vss an32 vss an33 vss ball signal
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1788 48.0 package specifications table 48-33. alphabetical signal listing signal ball 1588_pps ak1 1588_rx_snap ag1 1588_testmode_data al2 1588_tx_snap ag3 a20gate v2 ammssig aj1 asmssig ah2 bpm0 e33 bpm1 m26 bpm2 c32 bpm3 g28 bpm3_in y2 bpm4_prdy_out aa3 bpm5_preq_in w5 bsel m8 clk14 n1 clk48 d11 clkn100 b31 clkp100 c30 cn0rxd af5 cn0txd ad8 cn0txen ae7 cn1rxd ak2 cn1txd aj3 cn1txen ag5 cpupwrgd_out m7 cpurst# u1 cpuslp_out# p5 ddr_a[0] am26 ddr_a[1] al27 ddr_a[2] al28 ddr_a[3] ak28 ddr_a[4] ak27 ddr_a[5] ak26 ddr_a[6] aj28 ddr_a[7] aj26 ddr_a[8] aj27 ddr_a[9] ah27 ddr_a[10] am27 ddr_a[11] ah28 ddr_a[12] ah26 ddr_a[13] an27 ddr_a[14] ag27 ddr_ba[0] am28 ddr_ba[1] am29 ddr_ba[2] ag26 ddr_cas# an26 ddr_ck[0] v30 ddr_ck[0]# v31 ddr_ck[1] w32 ddr_ck[1]# w33 ddr_ck[2] u32 ddr_ck[2]# u31 ddr_ck[3] j28 ddr_ck[3]# j27 ddr_ck[4] d31 ddr_ck[4]# d32 ddr_ck[5] g26 ddr_ck[5]# g27 ddr_cke[0] an29 ddr_cke[1] m25 ddr_cres[0] v27 ddr_cres[1] u30 ddr_cres[2] u29 ddr_cs[0]# h28 ddr_cs[1]# k28 ddr_dm[0] f31 ddr_dm[1] k33 ddr_dm[2] p28 ddr_dm[3] r32 ddr_dm[4] y26 ddr_dm[5] ad31 ddr_dm[6] ad27 ddr_dm[7] aj32 ddr_dm[8] y31 ddr_dq[0] f32 ddr_dq[1] f33 ddr_dq[2] j32 ddr_dq[3] j31 ddr_dq[4] e31 ddr_dq[5] e32 ddr_dq[6] h31 signal ball ddr_dq[7] h30 ddr_dq[8] k31 ddr_dq[9] k32 ddr_dq[10] m31 ddr_dq[11] n33 ddr_dq[12] h33 ddr_dq[13] j33 ddr_dq[14] m33 ddr_dq[15] m32 ddr_dq[16] n28 ddr_dq[17] n27 ddr_dq[18] t28 ddr_dq[19] u28 ddr_dq[20] m28 ddr_dq[21] m27 ddr_dq[22] t30 ddr_dq[23] t29 ddr_dq[24] p33 ddr_dq[25] p32 ddr_dq[26] u33 ddr_dq[27] u27 ddr_dq[28] n32 ddr_dq[29] n31 ddr_dq[30] t31 ddr_dq[31] t27 ddr_dq[32] w27 ddr_dq[33] w28 ddr_dq[34] ab26 ddr_dq[35] ab28 ddr_dq[36] y25 ddr_dq[37] w26 ddr_dq[38] aa27 ddr_dq[39] aa28 ddr_dq[40] ad32 ddr_dq[41] ad33 ddr_dq[42] af32 ddr_dq[43] ag32 ddr_dq[44] ac33 ddr_dq[45] ac31 ddr_dq[46] af31 ddr_dq[47] af33 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1789 48.0 package specifications ddr_dq[48] ac27 ddr_dq[49] ac26 ddr_dq[50] ae26 ddr_dq[51] af26 ddr_dq[52] ab27 ddr_dq[53] ac28 ddr_dq[54] af28 ddr_dq[55] ad26 ddr_dq[56] ah32 ddr_dq[57] ah33 ddr_dq[58] al30 ddr_dq[59] am30 ddr_dq[60] ag33 ddr_dq[61] ag31 ddr_dq[62] al31 ddr_dq[63] al32 ddr_dqs[0] g32 ddr_dqs[0]# g33 ddr_dqs[1] l31 ddr_dqs[1]# l32 ddr_dqs[2] r29 ddr_dqs[2]# r30 ddr_dqs[3] t33 ddr_dqs[3]# t32 ddr_dqs[4] y27 ddr_dqs[4]# y28 ddr_dqs[5] ae32 ddr_dqs[5]# ae33 ddr_dqs[6] ae27 ddr_dqs[6]# ae28 ddr_dqs[7] aj31 ddr_dqs[7]# ah31 ddr_dqs[8] aa32 ddr_dqs[8]# aa33 ddr_drvcres v33 ddr_ecc[0] y32 ddr_ecc[1] y33 ddr_ecc[2] ab31 ddr_ecc[3] ac32 ddr_ecc[4] v32 ddr_ecc[5] w31 signal ball ddr_ecc[6] ab32 ddr_ecc[7] ab33 ddr_odt0 al29 ddr_odt1 l26 ddr_ras# af27 ddr_rcompx v26 ddr_slewcres v28 ddr_we# an28 eecs ah16 eedi ag16 eedo ak16 eesk af16 ex_addr[0] ak9 ex_addr[1] ah9 ex_addr[2] ak8 ex_addr[3] aj9 ex_addr[4] am7 ex_addr[5] af10 ex_addr[6] an6 ex_addr[7] ag9 ex_addr[8] an5 ex_addr[9] ak5 ex_addr[10] am5 ex_addr[11] af9 ex_addr[12] ak7 ex_addr[13] ag8 ex_addr[14] al6 ex_addr[15] aj6 ex_addr[16] an4 ex_addr[17] ag7 ex_addr[18] am4 ex_addr[19] af8 ex_addr[20] ah7 ex_addr[21] ah6 ex_addr[22] am3 ex_addr[23] aj5 ex_addr[24] al3 ex_ale ak4 ex_be[0]# an7 ex_be[1]# al7 ex_burst an14 signal ball ex_clk ah10 ex_cs[0]# al10 ex_cs[1]# an9 ex_cs[2]# am9 ex_cs[3]# ag10 ex_cs[4]# an8 ex_cs[5]# af11 ex_cs[6]# am8 ex_cs[7]# aj10 ex_data[0] an12 ex_data[1] af14 ex_data[2] al13 ex_data[3] ah13 ex_data[4] ak13 ex_data[5] ag13 ex_data[6] am12 ex_data[7] aj13 ex_data[8] an11 ex_data[9] al12 ex_data[10] am11 ex_data[11] ah12 ex_data[12] al11 ex_data[13] ag12 ex_data[14] ak11 ex_data[15] an10 nc57 ag14 ex_iowait# an13 ex_parity[0] am14 ex_parity[1] al14 ex_rcompn ag11 ex_rcompp aj11 ex_rd# ak14 ex_rdy[0]# am15 ex_rdy[1]# af15 ex_rdy[2]# aj15 ex_rdy[3]# ag15 reserved19 ae15 reserved20 aj14 nc58 ah15 nc59 ad9 ex_wr# an15 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1790 48.0 package specifications gbe0_rxclk al18 gbe0_rxctl am18 gbe0_rxdata[0] am20 gbe0_rxdata[1] an20 gbe0_rxdata[2] an19 gbe0_rxdata[3] an18 gbe0_txclk al19 gbe0_txctl al20 gbe0_txdata[0] ah18 gbe0_txdata[1] ak20 gbe0_txdata[2] ak19 gbe0_txdata[3] aj18 gbe1_rxclk an21 gbe1_rxctl am21 gbe1_rxdata[0] ak22 gbe1_rxdata[1] an23 gbe1_rxdata[2] an22 gbe1_rxdata[3] al21 gbe1_txclk ah19 gbe1_txctl af19 gbe1_txdata[0] ak23 gbe1_txdata[1] af20 gbe1_txdata[2] ak21 gbe1_txdata[3] ah20 gbe2_rxclk al22 gbe2_rxctl an24 gbe2_rxdata[0] al24 gbe2_rxdata[1] ah21 gbe2_rxdata[2] al23 gbe2_rxdata[3] am24 gbe2_txclk aj22 gbe2_txctl ag21 gbe2_txdata[0] af22 gbe2_txdata[1] ag22 gbe2_txdata[2] ah22 gbe2_txdata[3] af21 gbe_aux_pwr_good an16 gbe_pme_wake ae16 gbe_rcompn ae17 gbe_rcompp af17 gbe_refclk an17 signal ball gbe_refclk_rmii al17 gp2_pirqe# d1 gp3_pirqf# h1 gp4_pirqg# n7 gp5_pirqh# g1 gp11_smbalert# e4 gp16_irq24 h3 gp17_irq25 k3 gp18_irq36 k2 gp19_irq37 p8 gp20_irq26 p7 gp21_irq27 n4 gp23_irq28 l1 gp24_irq29 k7 gp25_irq38 j7 gp26_sata0gp p1 gp27_irq39 k8 gp28_irq30 j8 gp29_sata1gp g4 gp30_irq31 n5 gp31_irq32 w2 gp33_irq33 p4 gp34_irq34 t7 gp40_irq35 p3 gp41_ldrq[1]# p6 gpio[0] l6 gpio[1] j5 gpio[6] n9 gpio[7] j4 gpio[8] d5 gpio[9] d4 gpio[10] b4 gpio[12] h2 gpio[13] n8 gpio[14] g5 gpio[15] a4 gpio[48] u5 ierr# ac4 init33v_out# v1 intruder# l8 lad[0] n6 signal ball lad[1] l5 lad[2] l3 lad[3] l4 ldrq[0]# l2 lframe# k1 mdc ag17 mdio ah17 nc7 t8 nc9 w8 nc_sus_two j6 nc_two u3 nc10 v9 nc11 w9 nc12 g19 nc13 h18 nc14 h19 nc15 g18 nc16 h20 nc17 e28 nc18 f28 nc19 d28 nc20 f12 nc21 b8 nc22 a8 nc34 e29 nc35 c31 nc36 k26 nc37 k27 nc38 d30 nc40 g31 nc41 l33 nc42 p27 nc43 r33 nc44 aa26 nc45 ae31 nc46 ad28 nc47 aj33 nc48 k25 nc50 e30 nc51 j25 nc52 l27 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1791 48.0 package specifications nc53 aa31 nc54 d29 nc55 al26 nc56 ae6 nmi r5 oc[0]# e12 oc[1]# d12 pciclk n2 pcirst# g7 pe_hpintr# u2 pea0_rn[0] b27 pea0_rn[1] a26 pea0_rn[2] b25 pea0_rn[3] a24 pea0_rn[4] a19 pea0_rn[5] b20 pea0_rn[6] a17 pea0_rn[7] b18 pea0_rp[0] a27 pea0_rp[1] b26 pea0_rp[2] a25 pea0_rp[3] b24 pea0_rp[4] b19 pea0_rp[5] a20 pea0_rp[6] b17 pea0_rp[7] a18 pea0_tn[0] e27 pea0_tn[1] d26 pea0_tn[2] e25 pea0_tn[3] d24 pea0_tn[4] d19 pea0_tn[5] e20 pea0_tn[6] d17 pea0_tn[7] e18 pea0_tp[0] d27 pea0_tp[1] e26 pea0_tp[2] d25 pea0_tp[3] e24 pea0_tp[4] e19 pea0_tp[5] d20 pea0_tp[6] e17 signal ball pea0_tp[7] d18 pea_clkn d22 pea_clkp e22 pea_icompi b22 pea_icompo a22 pea_rcompo e21 pltrst# a5 pme# b3 prochot# t6 pwrbtn# h8 pwrgd w6 pwrok k6 rcin# m1 reserved0 ab3 reserved1 ac5 reserved2 ah1 reserved3 ab2 reserved4 ab6 reserved5 ab1 reserved6 y8 reserved7 aa7 reserved8 aa5 reserved9 g21 reserved10 d6 reserved11 f3 reserved12 aj16 reserved13 al16 reserved14 am16 reserved15 w7 reserved16 y6 reserved17 b29 reserved18 ab9 ri# d8 rsmrst# g3 rstin# ac3 rtcx1 f1 rtcx2 f2 rtest# l7 rx_clk0 ac6 rx_clk1 ad2 rx_clk2 ae5 signal ball rx_data_in0 ae4 rx_data_in1 ae1 rx_data_in2 ad7 rx_frame0 ac2 rx_frame1 ab8 rx_frame2 ae3 sata_clkrefn g14 sata_clkrefp g13 sata_rbias f15 sata_rbias# f16 sata_rxn0 b14 sata_rxn1 b15 sata_rxp0 a14 sata_rxp1 a15 sata_txn0 e14 sata_txn1 e15 sata_txp0 d14 sata_txp1 d15 sataled# j3 serirq j1 siu_cts1# r1 siu_cts2# t2 siu_dcd1# t5 siu_dcd2# t1 siu_dsr1# v5 siu_dsr2# w4 siu_dtr1# u7 siu_dtr2# aa2 siu_ri1# w3 siu_ri2# w1 siu_rts1# u6 siu_rts2# y4 siu_rxd1 r3 siu_rxd2 t4 siu_txd1 r2 siu_txd2 t3 slp_s3# a6 slp_s4# c7 slp_s5# h9 smbclk c5 smbdata g6 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1792 48.0 package specifications smbscl y5 smbsda y1 smi_out# m2 smlink[0] h7 smlink[1] b5 spi_cs# af2 spi_miso af1 spi_mosi ac8 spi_sclk af3 spkr p2 ssp_extclk ah3 ssp_rxd af7 ssp_sclk aj4 ssp_sfrm ah4 ssp_txd ak3 stpclk_out# n3 sus_stat# b6 susclk e7 sys_pwr_ok aj17 sys_reset# d7 tck y3 tdi aa1 tdo ag2 thermda f26 thermdc f27 thrmtrip# u4 tms ab5 trst# y7 tx_clk0 ab4 tx_clk1 af4 tx_clk2 ad5 tx_data_out0 ac1 tx_data_out1 aa9 tx_data_out2 ae2 tx_frame0 ab7 tx_frame1 ad1 tx_frame2 ad6 uart_clk u8 usb_rbiasn a9 usb_rbiasp b9 usbn0 a11 signal ball usbn1 a12 usbp0 b11 usbp1 b12 v_sel g2 vcc k11 vcc k13 vcc l10 vcc l12 vcc l14 vcc m11 vcc m13 vcc m15 vcc n10 vcc n12 vcc n14 vcc n16 vcc p11 vcc p13 vcc p15 vcc p17 vcc r8 vcc r10 vcc r12 vcc r14 vcc r16 vcc t11 vcc t13 vcc t15 vcc t17 vcc u10 vcc u12 vcc u14 vcc u16 vcc u18 vcc u20 vcc u22 vcc u24 vcc v11 vcc v13 vcc v15 vcc v17 signal ball vcc v19 vcc v21 vcc v23 vcc w10 vcc w12 vcc w14 vcc w16 vcc w18 vcc w20 vcc w22 vcc w24 vcc y11 vcc y13 vcc y15 vcc y17 vcc y19 vcc y21 vcc y23 vcc aa10 vcc aa12 vcc aa14 vcc aa16 vcc aa18 vcc aa20 vcc aa22 vcc aa24 vcc ab11 vcc ab13 vcc ab15 vcc ab17 vcc ab19 vcc ab21 vcc ab23 vcc ac10 vcc ac12 vcc ac14 vcc ac16 vcc ac18 vcc ac20 vcc ac22 vcc ac24 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1793 48.0 package specifications vcc ad11 vcc ad13 vcc ad15 vcc ad17 vcc ad19 vcc ad21 vcc ad23 vcc18 g30 vcc18 j29 vcc18 k30 vcc18 m30 vcc18 n29 vcc18 p30 vcc18 r27 vcc18 t25 vcc18 w30 vcc18 y29 vcc18 aa30 vcc18 ac30 vcc18 ad29 vcc18 ae30 vcc18 ag30 vcc18 ah29 vcc18 aj30 vcc18 ak25 vcc18 am25 vcc18 am31 vcc1p2_usbsus j12 vcc25 ae20 vcc25 aj19 vcc25 aj21 vcc25 am22 vcc33 e5 vcc33 h4 vcc33 h6 vcc33 m4 vcc33 r6 vcc33 r9 vcc33 v4 vcc33 aa6 vcc33 ad4 signal ball vcc33 ae9 vcc33 af6 vcc33 ah11 vcc33 al5 vcc33 al9 vcc33 al15 vcc50 k9 vcc50 p9 vcc50 u9 vcc50 y9 vcc50 ac9 vcc50 ae11 vcc50 ae14 vcc50_sus k4 vcca[1] g24 vcca[2] f24 vccabg3p3_usb h12 vccabgp033 g15 vccahpll t19 vccape a28 vccape b21 vccape c19 vccape c22 vccape c24 vccape c28 vccape f19 vccape f21 vccape f23 vccape f25 vccape g16 vccape g20 vccape0pll12 f18 vccape0pll12 f20 vccapll c15 vccarx b13 vccarx c14 vccarx f14 vccasatabg3p3 h15 vccatx b16 vccatx c16 vccatx e16 signal ball vccausb12 d13 vccausb12 f13 vccausb12 j13 vccgbe33 ae19 vccgbepsus ag20 vccprtc m5 vccpsus f10 vccpsus g11 vccpsus j11 vccrpe b23 vccrpe c18 vccrpe c26 vccrpe d21 vccrpe d23 vccrpe e23 vccrpe f17 vccrpe f22 vccsata h14 vccsata j14 vccsata33 c13 vccsus1 h10 vccsus1 j10 vccsus1 m9 vccsus1 m10 vccsus25 ae18 vccsus25 ag18 vccsus25 ak18 vccsus25 am17 vcctmp18 n25 vccusb12 b7 vccusb12 b10 vccusb12 c8 vccusb12 c11 vccusb12 e9 vccusb12 f11 vccusb12 g10 vccvc a29 vccvc b30 vccvc g22 vccvc h21 vccvc h23 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1794 48.0 package specifications vccvc h24 vccvc h26 vccvc h27 vccvc j16 vccvc j18 vccvc j20 vccvc j22 vccvc j24 vccvc j26 vccvc k15 vccvc k17 vccvc k19 vccvc k21 vccvc k23 vccvc l16 vccvc l18 vccvc l20 vccvc l22 vccvc l24 vccvc m17 vccvc m19 vccvc m21 vccvc m23 vccvc n18 vccvc n20 vccvc n22 vccvc n24 vccvc p19 vccvc p21 vccvc p23 vccvc p25 vccvc r18 vccvc r20 vccvc r22 vccvc r24 vccvc t21 vccvc t23 vccvc t24 vccvc u23 vccvc u25 vccvc u26 signal ball vrmpwrgd v7 vss a2 vss a3 vss a7 vss a10 vss a13 vss a16 vss a21 vss a23 vss a30 vss a31 vss a32 vss a33 vss b1 vss b2 vss b28 vss b32 vss b33 vss c1 vss c2 vss c3 vss c4 vss c6 vss c9 vss c10 vss c12 vss c17 vss c20 vss c21 vss c23 vss c25 vss c27 vss c29 vss c33 vss d2 vss d3 vss d9 vss d10 vss d16 vss d33 vss e1 signal ball vss e2 vss e3 vss e6 vss e8 vss e10 vss e11 vss e13 vss f5 vss f6 vss f7 vss f8 vss f9 vss f30 vss g8 vss g9 vss g12 vss g17 vss g23 vss g25 vss g29 vss h5 vss h11 vss h13 vss h16 vss h17 vss h22 vss h25 vss h29 vss h32 vss j2 vss j9 vss j15 vss j17 vss j19 vss j21 vss j23 vss j30 vss k5 vss k10 vss k12 vss k14 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1795 48.0 package specifications vss k16 vss k18 vss k20 vss k22 vss k24 vss k29 vss l9 vss l11 vss l13 vss l15 vss l17 vss l19 vss l21 vss l23 vss l25 vss l28 vss l30 vss m3 vss m6 vss m12 vss m14 vss m16 vss m18 vss m20 vss m22 vss m24 vss m29 vss n11 vss n13 vss n15 vss n17 vss n19 vss n21 vss n23 vss n26 vss n30 vss p10 vss p12 vss p14 vss p16 vss p18 signal ball vss p20 vss p22 vss p24 vss p26 vss p29 vss p31 vss r4 vss r7 vss r11 vss r13 vss r15 vss r17 vss r19 vss r21 vss r23 vss r25 vss r26 vss r28 vss r31 vss t9 vss t10 vss t12 vss t14 vss t16 vss t18 vss t20 vss t22 vss t26 vss u11 vss u13 vss u15 vss u17 vss u21 vss v3 vss v6 vss v8 vss v10 vss v12 vss v14 vss v16 vss v18 signal ball vss v20 vss v25 vss w11 vss w13 vss w15 vss w17 vss w19 vss w21 vss w23 vss w25 vss w29 vss y10 vss y12 vss y14 vss y16 vss y18 vss y20 vss y22 vss y24 vss y30 vss aa4 vss aa8 vss aa11 vss aa13 vss aa15 vss aa17 vss aa19 vss aa21 vss aa23 vss aa29 vss ab10 vss ab12 vss ab14 vss ab16 vss ab18 vss ab20 vss ab22 vss ab24 vss ab25 vss ab30 vss ac7 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1796 48.0 package specifications vss ac11 vss ac13 vss ac15 vss ac17 vss ac19 vss ac21 vss ac23 vss ac29 vss ad3 vss ad10 vss ad12 vss ad14 vss ad16 vss ad18 vss ad20 vss ad22 vss ad24 vss ad25 vss ad30 vss ae8 vss ae10 vss ae12 vss ae13 vss ae21 vss ae22 vss ae23 vss ae25 vss ae29 vss af12 vss af13 vss af18 vss af24 vss af25 vss af30 vss ag4 vss ag6 vss ag19 vss ag23 vss ag24 vss ag28 vss ag29 signal ball vss ah5 vss ah8 vss ah14 vss ah23 vss ah24 vss ah25 vss ah30 vss aj2 vss aj7 vss aj8 vss aj12 vss aj20 vss aj23 vss aj24 vss aj29 vss ak6 vss ak10 vss ak12 vss ak15 vss ak17 vss ak24 vss ak30 vss ak31 vss ak32 vss ak33 vss al1 vss al4 vss al8 vss al25 vss al33 vss am1 vss am2 vss am6 vss am10 vss am13 vss am19 vss am23 vss am32 vss am33 vss an1 vss an2 signal ball vss an3 vss an25 vss an30 vss an31 vss an32 vss an33 vssa u19 vttddr f29 vttddr l29 vttddr v22 vttddr v24 vttddr v29 vttddr aa25 vttddr ab29 vttddr ac25 vttddr ae24 vttddr af23 vttddr af29 vttddr ag25 vttddr aj25 vttddr ak29 wdt_tout# f4 signal ball
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1797 48.0 package specifications table 48-34. ep80579 ball map (bottom view, left side) (sheet 1 of 2) a b c d e f g h j k l m n p r t 1 vss vss gp2_p irqe# vss rtcx1 gp5_p irqh # gp3_p irqf# serir q lfram e# gp23_ irq28 rcin# clk14 gp26_ sata0 gp siu_c ts1# siu_d cd2# 2 vss vss vss vss vss rtcx2 v_sel gpio[ 12] vss gp18_ irq36 ldrq[ 0]# smi_o ut# pcicl k spkr siu_t xd1 siu_c ts2# 3 vss pme# vss vss vss reserv ed11 rsmr st# gp16_ irq24 satal ed# gp17_ irq25 lad[2 ] vss stpcl k_ou t# gp40_ irq35 siu_r xd1 siu_t xd2 4 gpio[ 15] gpio[ 10] vss gpio[ 9] gp11_ smba lert# wdt_ tout # gp29_ sata1 gp vcc33 gpio[ 7] vcc50 _sus lad[3 ] vcc33 gp21_ irq27 gp33_ irq33 vss siu_r xd2 5 pltrs t# smlin k[1] smbc lk gpio[ 8] vcc33 vss gpio[ 14] vss gpio[ 1] vss lad[1 ] vccpr tc gp30_ irq31 cpusl p_out # nmi siu_d cd1# 6 slp_s 3# sus_s tat# vss reserv ed10 vss vss smbd ata vcc33 nc_s us_t wo pwro k gpio[ 0] vss lad[0 ] gp41_ ldrq[ 1]# vcc33 proc hot# 7 vss vccu sb12 slp_s 4# sys_r eset# suscl k vss pcirs t# smlin k[0] gp25_ irq38 gp24_ irq29 rtest # cpup wrgd _out gp4_p irqg # gp20_ irq26 vss gp34_ irq34 8 nc22 nc21 vccu sb12 ri# vss vss vss pwrb tn# gp28_ irq30 gp27_ irq39 intru der# bsel gpio[ 13] gp19_ irq37 vcc nc7 9 usb_r biasn usb_r biasp vss vss vccu sb12 vss vss slp_s 5# vss vcc50 vss vccs us1 gpio[ 6] vcc50 vcc33 vss 10 vss vccu sb12 vss vss vss vccps us vccu sb12 vccs us1 vccs us1 vss vcc vccs us1 vcc vss vcc vss 11 usbn0 usbp0 vccu sb12 clk48 vss vccu sb12 vccps us vss vccps us vcc vss vcc vss vcc vss vcc 12 usbn1 usbp1 vss oc[1] # oc[0] # nc20 vss vcca bg3p3 _usb vcc1p 2_usb sus vss vcc vss vcc vss vcc vss 13 vss vcca rx vccs ata33 vcca usb12 vss vcca usb12 sata_ clkre fp vss vcca usb12 vcc vss vcc vss vcc vss vcc 14 sata_ rxp0 sata_ rxn0 vcca rx sata_ txp0 sata_ txn0 vcca rx sata_ clkre fn vccs ata vccs ata vss vcc vss vcc vss vcc vss 15 sata_ rxp1 sata_ rxn1 vccap ll sata_ txp1 sata_ txn1 sata_ rbias vcca bgp03 3 vcca satab g3p3 vss vccv c vss vcc vss vcc vss vcc 16 vss vccat x vccat x vss vccat x sata_ rbias # vccap e vss vccv c vss vccv c vss vcc vss vcc vss 17 pea0_ rn[6] pea0_ rp[6] vss pea0_ tn[6] pea0_ tp[6] vccrp e vss vss vss vccv c vss vccv c vss vcc vss vcc 18 pea0_ rp[7] pea0_ rn[7] vccrp e pea0_ tp[7] pea0_ tn[7] vccap e0pll 12 nc15 nc13 vccv c vss vccv c vss vccv c vss vccv c vss 19 pea0_ rn[4] pea0_ rp[4] vccap e pea0_ tn[4] pea0_ tp[4] vccap e nc12 nc14 vss vccv c vss vccv c vss vccv c vss vcca hpll 20 pea0_ rp[5] pea0_ rn[5] vss pea0_ tp[5] pea0_ tn[5] vccap e0pll 12 vccap e nc16 vccv c vss vccv c vss vccv c vss vccv c vss
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1798 48.0 package specifications 21 vss vccap e vss vccrp e pea_r comp o vccap e reserv ed9 vccv c vss vccv c vss vccv c vss vccv c vss vccv c 22 pea_i comp o pea_i compi vccap e pea_c lkn pea_c lkp vccrp e vccv c vss vccv c vss vccv c vss vccv c vss vccv c vss 23 vss vccrp e vss vccrp e vccrp e vccap e vss vccv c vss vccv c vss vccv c vss vccv c vss vccv c 24 pea0_ rn[3] pea0_ rp[3] vccap e pea0_ tn[3] pea0_ tp[3] vcca[ 2] vcca[ 1] vccv c vccv c vss vccv c vss vccv c vss vccv c vccv c 25 pea0_ rp[2] pea0_ rn[2] vss pea0_ tp[2] pea0_ tn[2] vccap e vss vss nc51 nc48 vss ddr_ cke[1 ] vcct mp18 vccv c vss vcc18 26 pea0_ rn[1] pea0_ rp[1] vccrp e pea0_ tn[1] pea0_ tp[1] ther mda ddr_ ck[5] vccv c vccv c nc36 ddr_ odt1 bpm1 vss vss vss vss 27 pea0_ rp[0] pea0_ rn[0] vss pea0_ tp[0] pea0_ tn[0] ther mdc ddr_ ck[5] # vccv c ddr_ ck[3] # nc37 nc52 ddr_ dq[21 ] ddr_ dq[17 ] nc42 vcc18 ddr_ dq[31 ] 28 vccap e vss vccap e nc19 nc17 nc18 bpm3 ddr_ cs[0] # ddr_ ck[3] ddr_ cs[1] # vss ddr_ dq[20 ] ddr_ dq[16 ] ddr_ dm[2] vss ddr_ dq[18 ] 29 vccv c reserv ed17 vss nc54 nc34 vttdd r vss vss vcc18 vss vttdd r vss vcc18 vss ddr_ dqs[2 ] ddr_ dq[23 ] 30 vss vccv c clkp1 00 nc38 nc50 vss vcc18 ddr_ dq[7] vss vcc18 vss vcc18 vss vcc18 ddr_ dqs[2 ]# ddr_ dq[22 ] 31 vss clkn1 00 nc35 ddr_ ck[4] ddr_ dq[4] ddr_ dm[0] nc40 ddr_ dq[6] ddr_ dq[3] ddr_ dq[8] ddr_ dqs[1 ] ddr_ dq[10 ] ddr_ dq[29 ] vss vss ddr_ dq[30 ] 32 vss vss bpm2 ddr_ ck[4] # ddr_ dq[5] ddr_ dq[0] ddr_ dqs[0 ] vss ddr_ dq[2] ddr_ dq[9] ddr_ dqs[1 ]# ddr_ dq[15 ] ddr_ dq[28 ] ddr_ dq[25 ] ddr_ dm[3] ddr_ dqs[3 ]# 33 vss vss vss vss bpm0 ddr_ dq[1] ddr_ dqs[0 ]# ddr_ dq[12 ] ddr_ dq[13 ] ddr_ dm[1] nc41 ddr_ dq[14 ] ddr_ dq[11 ] ddr_ dq[24 ] nc43 ddr_ dqs[3 ] table 48-34. ep80579 ball map (bottom view, left side) (sheet 2 of 2) a b c d e f g h j k l m n p r t
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1799 48.0 package specifications table 48-35. ep80579 ball map (bottom view, right side) (sheet 1 of 2) u v w y aa ab ac ad ae af ag ah aj ak al am an cpur st# init3 3v_o ut# siu_r i2# smbs da tdi reser ved5 tx_d ata_o ut0 tx_fr ame1 rx_d ata_i n1 spi_m iso 1588_ rx_s nap reser ved2 amms sig 1588_ pps vss vss vss 1 pe_hp intr # a20g ate gp31_ irq32 bpm3 _in siu_d tr2# reser ved3 rx_fr ame0 rx_cl k1 tx_d ata_o ut2 spi_c s# tdo asms sig vss cn1r xd 1588_ test mode _data vss vss 2 nc_t wo vss siu_r i1# tck bpm4 _prd y_ou t reser ved0 rstin # vss rx_fr ame2 spi_s clk 1588_ tx_s nap ssp_e xtclk cn1t xd ssp_t xd ex_a ddr[ 24] ex_a ddr[ 22] vss 3 thrm trip# vcc3 3 siu_d sr2# siu_r ts2# vss tx_cl k0 ierr# vcc3 3 rx_d ata_i n0 tx_cl k1 vss ssp_s frm ssp_s clk ex_al e vss ex_a ddr[ 18] ex_a ddr[ 16] 4 gpio[ 48] siu_d sr1# bpm5 _pre q_in smbs cl reser ved8 tms reser ved1 tx_cl k2 rx_cl k2 cn0r xd cn1t xen vss ex_a ddr[ 23] ex_a ddr[ 9] vcc3 3 ex_a ddr[ 10] ex_a ddr[ 8] 5 siu_r ts1# vss pwrg d reser ved16 vcc3 3 reser ved4 rx_cl k0 tx_fr ame2 nc56 vcc3 3 vss ex_a ddr[ 21] ex_a ddr[ 15] vss ex_a ddr[ 14] vss ex_a ddr[ 6] 6 siu_d tr1# vrmp wrgd reser ved15 trst # reser ved7 tx_fr ame0 vss rx_d ata_i n2 cn0t xen ssp_r xd ex_a ddr[ 17] ex_a ddr[ 20] vss ex_a ddr[ 12] ex_be [1]# ex_a ddr[ 4] ex_be [0]# 7 uart _clk vss nc9 reser ved6 vss rx_fr ame1 spi_m osi cn0t xd vss ex_a ddr[ 19] ex_a ddr[ 13] vss vss ex_a ddr[ 2] vss ex_c s[6]# ex_c s[4]# 8 vcc5 0 nc10 nc11 vcc5 0 tx_d ata_o ut1 reser ved18 vcc5 0 nc59 vcc3 3 ex_a ddr[ 11] ex_a ddr[ 7] ex_a ddr[ 1] ex_a ddr[ 3] ex_a ddr[ 0] vcc3 3 ex_c s[2]# ex_c s[1]# 9 vcc vss vcc vss vcc vss vcc vss vss ex_a ddr[ 5] ex_c s[3]# ex_cl k ex_c s[7]# vss ex_c s[0]# vss ex_d ata[1 5] 10 vss vcc vss vcc vss vcc vss vcc vcc5 0 ex_c s[5]# ex_r comp n vcc3 3 ex_r comp p ex_d ata[1 4] ex_d ata[1 2] ex_d ata[1 0] ex_d ata[8 ] 11 vcc vss vcc vss vcc vss vcc vss vss vss ex_d ata[1 3] ex_d ata[1 1] vss vss ex_d ata[9 ] ex_d ata[6 ] ex_d ata[0 ] 12 vss vcc vss vcc vss vcc vss vcc vss vss ex_d ata[5 ] ex_d ata[3 ] ex_d ata[7 ] ex_d ata[4 ] ex_d ata[2 ] vss ex_io wait # 13 vcc vss vcc vss vcc vss vcc vss vcc5 0 ex_d ata[1 ] nc57 vss reser ved20 ex_r d# ex_pa rity[ 1] ex_pa rity[ 0] ex_b urst 14 vss vcc vss vcc vss vcc vss vcc reser ved19 ex_r dy[1] # ex_r dy[3] # nc58 ex_r dy[2] # vss vcc3 3 ex_r dy[0] # ex_w r# 15 vcc vss vcc vss vcc vss vcc vss gbe_ pme_ wake eesk eedi eecs reser ved12 eedo reser ved13 reser ved14 gbe_ aux_ pwr_ good 16 vss vcc vss vcc vss vcc vss vcc gbe_ rcom pn gbe_ rcom pp mdc mdio sys_p wr_o k vss gbe_ refcl k_rmi i vccs us25 gbe_ refcl k 17
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1800 48.0 package specifications vcc vss vcc vss vcc vss vcc vss vccs us25 vss vccs us25 gbe0 _txd ata[0 ] gbe0 _txd ata[3 ] vccs us25 gbe0 _rxcl k gbe0 _rxct l gbe0 _rxd ata[3 ] 18 vssa vcc vss vcc vss vcc vss vcc vccg be33 gbe1 _txct l vss gbe1 _txcl k vcc2 5 gbe0 _txd ata[2 ] gbe0 _txcl k vss gbe0 _rxd ata[2 ] 19 vcc vss vcc vss vcc vss vcc vss vcc2 5 gbe1 _txd ata[1 ] vccg beps us gbe1 _txd ata[3 ] vss gbe0 _txd ata[1 ] gbe0 _txct l gbe0 _rxd ata[0 ] gbe0 _rxd ata[1 ] 20 vss vcc vss vcc vss vcc vss vcc vss gbe2 _txd ata[3 ] gbe2 _txct l gbe2 _rxd ata[1 ] vcc2 5 gbe1 _txd ata[2 ] gbe1 _rxd ata[3 ] gbe1 _rxct l gbe1 _rxcl k 21 vcc vttd dr vcc vss vcc vss vcc vss vss gbe2 _txd ata[0 ] gbe2 _txd ata[1 ] gbe2 _txd ata[2 ] gbe2 _txcl k gbe1 _rxd ata[0 ] gbe2 _rxcl k vcc2 5 gbe1 _rxd ata[2 ] 22 vccv c vcc vss vcc vss vcc vss vcc vss vttd dr vss vss vss gbe1 _txd ata[0 ] gbe2 _rxd ata[2 ] vss gbe1 _rxd ata[1 ] 23 vcc vttd dr vcc vss vcc vss vcc vss vttd dr vss vss vss vss vss gbe2 _rxd ata[0 ] gbe2 _rxd ata[3 ] gbe2 _rxct l 24 vccv c vss vss ddr_ dq[36 ] vttd dr vss vttd dr vss vss vss vttd dr vss vttd dr vcc1 8 vss vcc1 8 vss 25 vccv c ddr_ rcom px ddr_ dq[37 ] ddr_ dm[4] nc44 ddr_ dq[34 ] ddr_ dq[49 ] ddr_ dq[55 ] ddr_ dq[50 ] ddr_ dq[51 ] ddr_ ba[2] ddr_ a[12] ddr_ a[7] ddr_ a[5] nc55 ddr_ a[0] ddr_ cas# 26 ddr_ dq[27 ] ddr_ cres[ 0] ddr_ dq[32 ] ddr_ dqs[ 4] ddr_ dq[38 ] ddr_ dq[52 ] ddr_ dq[48 ] ddr_ dm[6] ddr_ dqs[ 6] ddr_ ras# ddr_ a[14] ddr_ a[9] ddr_ a[8] ddr_ a[4] ddr_ a[1] ddr_ a[10] ddr_ a[13] 27 ddr_ dq[19 ] ddr_ slew cres ddr_ dq[33 ] ddr_ dqs[ 4]# ddr_ dq[39 ] ddr_ dq[35 ] ddr_ dq[53 ] nc46 ddr_ dqs[ 6]# ddr_ dq[54 ] vss ddr_ a[11] ddr_ a[6] ddr_ a[3] ddr_ a[2] ddr_ ba[0] ddr_ we# 28 ddr_ cres[ 2] vttd dr vss vcc1 8 vss vttd dr vss vcc1 8 vss vttd dr vss vcc1 8 vss vttd dr ddr_ odt0 ddr_ ba[1] ddr_ cke[0 ] 29 ddr_ cres[ 1] ddr_ ck[0] vcc1 8 vss vcc1 8 vss vcc1 8 vss vcc1 8 vss vcc1 8 vss vcc1 8 vss ddr_ dq[58 ] ddr_ dq[59 ] vss 30 ddr_ ck[2] # ddr_ ck[0] # ddr_ ecc[5 ] ddr_ dm[8] nc53 ddr_ ecc[2 ] ddr_ dq[45 ] ddr_ dm[5] nc45 ddr_ dq[46 ] ddr_ dq[61 ] ddr_ dqs[ 7]# ddr_ dqs[ 7] vss ddr_ dq[62 ] vcc1 8 vss 31 ddr_ ck[2] ddr_ ecc[4 ] ddr_ ck[1] ddr_ ecc[0 ] ddr_ dqs[ 8] ddr_ ecc[6 ] ddr_ ecc[3 ] ddr_ dq[40 ] ddr_ dqs[ 5] ddr_ dq[42 ] ddr_ dq[43 ] ddr_ dq[56 ] ddr_ dm[7] vss ddr_ dq[63 ] vss vss 32 ddr_ dq[26 ] ddr_ drvc res ddr_ ck[1] # ddr_ ecc[1 ] ddr_ dqs[ 8]# ddr_ ecc[7 ] ddr_ dq[44 ] ddr_ dq[41 ] ddr_ dqs[ 5]# ddr_ dq[47 ] ddr_ dq[60 ] ddr_ dq[57 ] nc47 vss vss vss vss 33 table 48-35. ep80579 ball map (bottom view, right side) (sheet 2 of 2) u v w y aa ab ac ad ae af ag ah aj ak al am an
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1801 48.0 package specifications table 48-36. ep80579 ball map (top view, left side) (sheet 1 of 2) an am al ak aj ah ag af ae ad ac ab aa y w v u 1 vss vss vss 1588_ pps amms sig reser ved2 1588_ rx_s nap spi_m iso rx_d ata_i n1 tx_fr ame1 tx_d ata_o ut0 reser ved5 tdi smbs da siu_r i2# init3 3v_o ut# cpur st# 2 vss vss 1588_ test mode _data cn1r xd vss asms sig tdo spi_c s# tx_d ata_o ut2 rx_cl k1 rx_fr ame0 reser ved3 siu_d tr2# bpm3 _in gp31_ irq32 a20g ate pe_h pintr # 3 vss ex_a ddr[ 22] ex_a ddr[ 24] ssp_t xd cn1t xd ssp_e xtclk 1588_ tx_s nap spi_s clk rx_fr ame2 vss rstin # reser ved0 bpm4 _prd y_ou t tck siu_r i1# vss nc_t wo 4 ex_a ddr[ 16] ex_a ddr[ 18] vss ex_al e ssp_s clk ssp_s frm vss tx_cl k1 rx_d ata_i n0 vcc3 3 ierr# tx_cl k0 vss siu_r ts2# siu_d sr2# vcc3 3 thrm trip # 5 ex_a ddr[ 8] ex_a ddr[ 10] vcc3 3 ex_a ddr[ 9] ex_a ddr[ 23] vss cn1t xen cn0r xd rx_cl k2 tx_cl k2 reser ved1 tms reser ved8 smbs cl bpm5 _pre q_in siu_d sr1# gpio[ 48] 6 ex_a ddr[ 6] vss ex_a ddr[ 14] vss ex_a ddr[ 15] ex_a ddr[ 21] vss vcc3 3 nc56 tx_fr ame2 rx_cl k0 reser ved4 vcc3 3 reser ved16 pwrg d vss siu_ rts1 # 7 ex_be [0]# ex_a ddr[ 4] ex_be [1]# ex_a ddr[ 12] vss ex_a ddr[ 20] ex_a ddr[ 17] ssp_r xd cn0t xen rx_d ata_i n2 vss tx_fr ame0 reser ved7 trst # reser ved15 vrmp wrgd siu_ dtr1 # 8 ex_c s[4]# ex_c s[6]# vss ex_a ddr[ 2] vss vss ex_a ddr[ 13] ex_a ddr[ 19] vss cn0t xd spi_m osi rx_fr ame1 vss reser ved6 nc9 vss uart _clk 9 ex_c s[1]# ex_c s[2]# vcc3 3 ex_a ddr[ 0] ex_a ddr[ 3] ex_a ddr[ 1] ex_a ddr[ 7] ex_a ddr[ 11] vcc3 3 nc59 vcc5 0 reser ved18 tx_d ata_o ut1 vcc5 0 nc11 nc10 vcc5 0 10 ex_d ata[1 5] vss ex_c s[0]# vss ex_c s[7]# ex_cl k ex_c s[3]# ex_a ddr[ 5] vss vss vcc vss vcc vss vcc vss vcc 11 ex_d ata[8 ] ex_d ata[1 0] ex_d ata[1 2] ex_d ata[1 4] ex_r comp p vcc3 3 ex_r comp n ex_c s[5]# vcc5 0 vcc vss vcc vss vcc vss vcc vss 12 ex_d ata[0 ] ex_d ata[6 ] ex_d ata[9 ] vss vss ex_d ata[1 1] ex_d ata[1 3] vss vss vss vcc vss vcc vss vcc vss vcc 13 ex_io wait # vss ex_d ata[2 ] ex_d ata[4 ] ex_d ata[7 ] ex_d ata[3 ] ex_d ata[5 ] vss vss vcc vss vcc vss vcc vss vcc vss 14 ex_b urst ex_pa rity[ 0] ex_pa rity[ 1] ex_r d# reser ved20 vss nc57 ex_d ata[1 ] vcc5 0 vss vcc vss vcc vss vcc vss vcc 15 ex_w r# ex_r dy[0] # vcc3 3 vss ex_r dy[2] # nc58 ex_r dy[3] # ex_r dy[1] # reser ved19 vcc vss vcc vss vcc vss vcc vss 16 gbe_ aux_ pwr_ good reser ved14 reser ved13 eedo reser ved12 eecs eedi eesk gbe_ pme_ wake vss vcc vss vcc vss vcc vss vcc 17 gbe_ refcl k vccs us25 gbe_ refcl k_rmi i vss sys_p wr_o k mdio mdc gbe_ rcom pp gbe_ rcom pn vcc vss vcc vss vcc vss vcc vss
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1802 48.0 package specifications 18 gbe0 _rxd ata[3 ] gbe0 _rxct l gbe0 _rxcl k vccs us25 gbe0 _txd ata[3 ] gbe0 _txd ata[0 ] vccs us25 vss vccs us25 vss vcc vss vcc vss vcc vss vcc 19 gbe0 _rxd ata[2 ] vss gbe0 _txcl k gbe0 _txd ata[2 ] vcc2 5 gbe1 _txcl k vss gbe1 _txct l vccg be33 vcc vss vcc vss vcc vss vcc vssa 20 gbe0 _rxd ata[1 ] gbe0 _rxd ata[0 ] gbe0 _txct l gbe0 _txd ata[1 ] vss gbe1 _txd ata[3 ] vccg beps us gbe1 _txd ata[1 ] vcc2 5 vss vcc vss vcc vss vcc vss vcc 21 gbe1 _rxcl k gbe1 _rxct l gbe1 _rxd ata[3 ] gbe1 _txd ata[2 ] vcc2 5 gbe2 _rxd ata[1 ] gbe2 _txct l gbe2 _txd ata[3 ] vss vcc vss vcc vss vcc vss vcc vss 22 gbe1 _rxd ata[2 ] vcc2 5 gbe2 _rxcl k gbe1 _rxd ata[0 ] gbe2 _txcl k gbe2 _txd ata[2 ] gbe2 _txd ata[1 ] gbe2 _txd ata[0 ] vss vss vcc vss vcc vss vcc vttd dr vcc 23 gbe1 _rxd ata[1 ] vss gbe2 _rxd ata[2 ] gbe1 _txd ata[0 ] vss vss vss vttd dr vss vcc vss vcc vss vcc vss vcc vccv c 24 gbe2 _rxct l gbe2 _rxd ata[3 ] gbe2 _rxd ata[0 ] vss vss vss vss vss vttd dr vss vcc vss vcc vss vcc vttd dr vcc 25 vss vcc1 8 vss vcc1 8 vttd dr vss vttd dr vss vss vss vttd dr vss vttd dr ddr_ dq[36 ] vss vss vccv c 26 ddr_ cas# ddr_ a[0] nc55 ddr_ a[5] ddr_ a[7] ddr_ a[12] ddr_ ba[2] ddr_ dq[51 ] ddr_ dq[50 ] ddr_ dq[55 ] ddr_ dq[49 ] ddr_ dq[34 ] nc44 ddr_ dm[4] ddr_ dq[37 ] ddr_ rcom px vccv c 27 ddr_ a[13] ddr_ a[10] ddr_ a[1] ddr_ a[4] ddr_ a[8] ddr_ a[9] ddr_ a[14] ddr_ ras# ddr_ dqs[ 6] ddr_ dm[6] ddr_ dq[48 ] ddr_ dq[52 ] ddr_ dq[38 ] ddr_ dqs[ 4] ddr_ dq[32 ] ddr_ cres[ 0] ddr_ dq[2 7] 28 ddr_ we# ddr_ ba[0] ddr_ a[2] ddr_ a[3] ddr_ a[6] ddr_ a[11] vss ddr_ dq[54 ] ddr_ dqs[ 6]# nc46 ddr_ dq[53 ] ddr_ dq[35 ] ddr_ dq[39 ] ddr_ dqs[ 4]# ddr_ dq[33 ] ddr_ slew cres ddr_ dq[1 9] 29 ddr_ cke[0 ] ddr_ ba[1] ddr_ odt0 vttd dr vss vcc1 8 vss vttd dr vss vcc1 8 vss vttd dr vss vcc1 8 vss vttd dr ddr_ cres [2] 30 vss ddr_ dq[59 ] ddr_ dq[58 ] vss vcc1 8 vss vcc1 8 vss vcc1 8 vss vcc1 8 vss vcc1 8 vss vcc1 8 ddr_ ck[0] ddr_ cres [1] 31 vss vcc1 8 ddr_ dq[62 ] vss ddr_ dqs[ 7] ddr_ dqs[ 7]# ddr_ dq[61 ] ddr_ dq[46 ] nc45 ddr_ dm[5] ddr_ dq[45 ] ddr_ ecc[2 ] nc53 ddr_ dm[8] ddr_ ecc[5 ] ddr_ ck[0] # ddr_ ck[2] # 32 vss vss ddr_ dq[63 ] vss ddr_ dm[7] ddr_ dq[56 ] ddr_ dq[43 ] ddr_ dq[42 ] ddr_ dqs[ 5] ddr_ dq[40 ] ddr_ ecc[3 ] ddr_ ecc[6 ] ddr_ dqs[ 8] ddr_ ecc[0 ] ddr_ ck[1] ddr_ ecc[4 ] ddr_ ck[2] 33 vss vss vss vss nc47 ddr_ dq[57 ] ddr_ dq[60 ] ddr_ dq[47 ] ddr_ dqs[ 5]# ddr_ dq[41 ] ddr_ dq[44 ] ddr_ ecc[7 ] ddr_ dqs[ 8]# ddr_ ecc[1 ] ddr_ ck[1] # ddr_ drvc res ddr_ dq[2 6] table 48-36. ep80579 ball map (top view, left side) (sheet 2 of 2) an am al ak aj ah ag af ae ad ac ab aa y w v u
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1803 intel ? ep80579 integrated processor table 48-37. ep80579 ball map (top view, right side) (sheet 1 of 2) t r p n m l k j h g f e d c b a siu_d cd2# siu_c ts1# gp26_ sata0 gp clk14 rcin # gp23_ irq28 lfra me# serir q gp3_p irqf # gp5_p irqh # rtcx1 vss gp2_p irqe # vss vss 1 siu_c ts2# siu_t xd1 spkr pcicl k smi_ out# ldrq[ 0]# gp18_ irq36 vss gpio[ 12] v_sel rtcx2 vss vss vss vss vss 2 siu_t xd2 siu_r xd1 gp40_ irq35 stpcl k_ou t# vss lad[2 ] gp17_ irq25 satal ed# gp16_ irq24 rsmr st# reser ved11 vss vss vss pme# vss 3 siu_r xd2 vss gp33_ irq33 gp21_ irq27 vcc3 3 lad[3 ] vcc5 0_su s gpio[ 7] vcc3 3 gp29_ sata1 gp wdt_ tout # gp11_ smba lert# gpio[ 9] vss gpio[ 10] gpio[ 15] 4 siu_d cd1# nmi cpusl p_ou t# gp30_ irq31 vccp rtc lad[1 ] vss gpio[ 1] vss gpio[ 14] vss vcc3 3 gpio[ 8] smbc lk smlin k[1] pltrs t# 5 proc hot# vcc3 3 gp41_ ldrq[ 1]# lad[0 ] vss gpio[ 0] pwro k nc_s us_t wo vcc3 3 smbd ata vss vss reser ved10 vss sus_ stat # slp_s 3# 6 gp34_ irq34 vss gp20_ irq26 gp4_p irqg # cpup wrgd _out rtest # gp24_ irq29 gp25_ irq38 smlin k[0] pcirs t# vss susc lk sys_ reset # slp_s 4# vccu sb12 vss 7 nc7 vcc gp19_ irq37 gpio[ 13] bsel intru der# gp27_ irq39 gp28_ irq30 pwrb tn# vss vss vss ri# vccu sb12 nc21 nc22 8 vss vcc3 3 vcc5 0 gpio[ 6] vccs us1 vss vcc5 0 vss slp_s 5# vss vss vccu sb12 vss vss usb_ rbias p usb_ rbias n 9 vss vcc vss vcc vccs us1 vcc vss vccs us1 vccs us1 vccu sb12 vccp sus vss vss vss vccu sb12 vss 10 vcc vss vcc vss vcc vss vcc vccp sus vss vccp sus vccu sb12 vss clk48 vccu sb12 usbp 0 usbn 0 11 vss vcc vss vcc vss vcc vss vcc1 p2_us bsus vcca bg3p 3_us b vss nc20 oc[0] # oc[1] # vss usbp 1 usbn 1 12 vcc vss vcc vss vcc vss vcc vcca usb1 2 vss sata_ clkre fp vcca usb1 2 vss vcca usb1 2 vccs ata33 vcca rx vss 13 vss vcc vss vcc vss vcc vss vccs ata vccs ata sata_ clkre fn vcca rx sata_ txn0 sata_ txp0 vcca rx sata_ rxn0 sata_ rxp0 14 vcc vss vcc vss vcc vss vccv c vss vcca satab g3p3 vcca bgp0 33 sata_ rbias sata_ txn1 sata_ txp1 vcca pll sata_ rxn1 sata_ rxp1 15 vss vcc vss vcc vss vccv c vss vccv c vss vcca pe sata_ rbias # vcca tx vss vcca tx vcca tx vss 16 vcc vss vcc vss vccv c vss vccv c vss vss vss vccr pe pea0_ tp[6] pea0_ tn[6] vss pea0_ rp[6] pea0_ rn[6] 17 vss vccv c vss vccv c vss vccv c vss vccv c nc13 nc15 vcca pe0pl l12 pea0_ tn[7] pea0_ tp[7] vccr pe pea0_ rn[7] pea0_ rp[7] 18 vcca hpll vss vccv c vss vccv c vss vccv c vss nc14 nc12 vcca pe pea0_ tp[4] pea0_ tn[4] vcca pe pea0_ rp[4] pea0_ rn[4] 19 vss vccv c vss vccv c vss vccv c vss vccv c nc16 vcca pe vcca pe0pl l12 pea0_ tn[5] pea0_ tp[5] vss pea0_ rn[5] pea0_ rp[5] 20
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1804 48.0 package specifications vccv c vss vccv c vss vccv c vss vccv c vss vccv c reser ved9 vcca pe pea_r comp o vccr pe vss vcca pe vss 21 vss vccv c vss vccv c vss vccv c vss vccv c vss vccv c vccr pe pea_c lkp pea_c lkn vcca pe pea_i comp i pea_i comp o 22 vccv c vss vccv c vss vccv c vss vccv c vss vccv c vss vcca pe vccr pe vccr pe vss vccr pe vss 23 vccv c vccv c vss vccv c vss vccv c vss vccv c vccv c vcca[ 1] vcca[ 2] pea0_ tp[3] pea0_ tn[3] vcca pe pea0_ rp[3] pea0_ rn[3] 24 vcc1 8 vss vccv c vcct mp18 ddr_ cke[1 ] vss nc48 nc51 vss vss vcca pe pea0_ tn[2] pea0_ tp[2] vss pea0_ rn[2] pea0_ rp[2] 25 vss vss vss vss bpm1 ddr_ odt1 nc36 vccv c vccv c ddr_ ck[5] ther mda pea0_ tp[1] pea0_ tn[1] vccr pe pea0_ rp[1] pea0_ rn[1] 26 ddr_ dq[31 ] vcc1 8 nc42 ddr_ dq[17 ] ddr_ dq[21 ] nc52 nc37 ddr_ ck[3] # vccv c ddr_ ck[5] # ther mdc pea0_ tn[0] pea0_ tp[0] vss pea0_ rn[0] pea0_ rp[0] 27 ddr_ dq[18 ] vss ddr_ dm[2] ddr_ dq[16 ] ddr_ dq[20 ] vss ddr_ cs[1] # ddr_ ck[3] ddr_ cs[0] # bpm3 nc18 nc17 nc19 vcca pe vss vcca pe 28 ddr_ dq[23 ] ddr_ dqs[ 2] vss vcc1 8 vss vttd dr vss vcc1 8 vss vss vttd dr nc34 nc54 vss reser ved17 vccv c 29 ddr_ dq[22 ] ddr_ dqs[ 2]# vcc1 8 vss vcc1 8 vss vcc1 8 vss ddr_ dq[7] vcc1 8 vss nc50 nc38 clkp1 00 vccv c vss 30 ddr_ dq[30 ] vss vss ddr_ dq[29 ] ddr_ dq[10 ] ddr_ dqs[ 1] ddr_ dq[8] ddr_ dq[3] ddr_ dq[6] nc40 ddr_ dm[0] ddr_ dq[4] ddr_ ck[4] nc35 clkn 100 vss 31 ddr_ dqs[ 3]# ddr_ dm[3] ddr_ dq[25 ] ddr_ dq[28 ] ddr_ dq[15 ] ddr_ dqs[ 1]# ddr_ dq[9] ddr_ dq[2] vss ddr_ dqs[ 0] ddr_ dq[0] ddr_ dq[5] ddr_ ck[4] # bpm2 vss vss 32 ddr_ dqs[ 3] nc43 ddr_ dq[24 ] ddr_ dq[11 ] ddr_ dq[14 ] nc41 ddr_ dm[1] ddr_ dq[13 ] ddr_ dq[12 ] ddr_ dqs[ 0]# ddr_ dq[1] bpm0 vss vss vss vss 33 table 48-37. ep80579 ball map (top view, right side) (sheet 2 of 2) t r p n m l k j h g f e d c b a
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1805 intel ? ep80579 integrated processor table 48-38 provides package trace length information. table 48-38. package trace length (sheet 1 of 13) customer signal total length (mm) total length (mils) 1588_pps 15.960 628.330 1588_rx_snap 13.581 534.677 1588_testmode_data 16.580 652.746 1588_tx_snap 13.032 513.059 a20gate 12.984 511.170 ammssig 16.360 644.111 asmssig 14.539 572.386 bpm0 19.790 779.153 bpm1 7.665 301.752 bpm2 23.372 920.163 bpm3 15.018 591.244 bpm3_in 10.640 418.891 bpm4_prdy_out 9.977 392.789 bpm5_preq_in 7.131 280.761 bsel 4.774 187.963 clk14 13.402 527.633 clk48 10.313 406.043 clkn100 28.039 1103.907 clkp100 28.040 1103.919 cn0rxd 9.886 389.208 cn0txd 5.437 214.060 cn0txen 6.089 239.722 cn1rxd 15.780 621.272 cn1txd 13.976 550.234 cn1txen 9.552 376.073 cpupwrgd_out 6.051 238.228 cpuslp_out# 8.152 320.942 ddr_a[0] 11.991 472.082 ddr_a[1] 12.520 492.928 ddr_a[10] 12.664 498.573 ddr_a[11] 10.166 400.237 ddr_a[12] 8.497 334.547 ddr_a[13] 13.348 525.503 ddr_a[14] 7.905 311.224 ddr_a[2] 12.209 480.670 ddr_a[3] 12.519 492.866 ddr_a[4] 10.987 432.547 ddr_a[5] 11.173 439.863 ddr_a[6] 11.900 468.487
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1806 48.0 package specifications ddr_a[7] 10.914 429.703 ddr_a[8] 10.953 431.225 ddr_a[9] 8.565 337.189 ddr_ba[0] 13.353 525.719 ddr_ba[1] 14.483 570.216 ddr_ba[2] 7.122 280.410 ddr_cas# 12.640 497.644 ddr_ck[0] 21.164 833.246 ddr_ck[0]# 21.164 833.220 ddr_ck[1] 21.166 833.317 ddr_ck[1]# 21.165 833.283 ddr_ck[2] 21.160 833.058 ddr_ck[2]# 21.164 833.237 ddr_ck[3] 21.163 833.191 ddr_ck[3]# 21.163 833.205 ddr_ck[4] 21.164 833.220 ddr_ck[4]# 21.162 833.159 ddr_ck[5] 21.162 833.165 ddr_ck[5]# 21.163 833.189 ddr_cke[0] 14.509 571.209 ddr_cke[1] 6.765 266.353 ddr_cres[0] 6.325 249.020 ddr_cres[1] 9.819 386.589 ddr_cres[2] 9.819 386.594 ddr_cs[0]# 17.620 693.688 ddr_cs[1]# 11.412 449.308 ddr_dm[0] 21.573 849.348 ddr_dm[1] 18.891 743.742 ddr_dm[2] 15.674 617.103 ddr_dm[3] 16.218 638.499 ddr_dm[4] 9.844 387.567 ddr_dm[5] 16.331 642.951 ddr_dm[6] 9.274 365.120 ddr_dm[7] 17.633 694.213 ddr_dm[8] 16.625 654.511 ddr_dq[0] 21.574 849.363 ddr_dq[1] 21.578 849.520 ddr_dq[10] 18.891 743.726 ddr_dq[11] 18.882 743.372 ddr_dq[12] 18.891 743.744 ddr_dq[13] 18.896 743.920 ddr_dq[14] 18.896 743.955 table 48-38. package trace length (sheet 2 of 13)
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1807 48.0 package specifications ddr_dq[15] 18.869 742.854 ddr_dq[16] 15.762 620.541 ddr_dq[17] 15.764 620.616 ddr_dq[18] 15.763 620.590 ddr_dq[19] 15.766 620.689 ddr_dq[2] 21.573 849.315 ddr_dq[20] 15.759 620.444 ddr_dq[21] 15.762 620.563 ddr_dq[22] 15.763 620.577 ddr_dq[23] 15.760 620.462 ddr_dq[24] 16.207 638.063 ddr_dq[25] 16.220 638.574 ddr_dq[26] 16.207 638.061 ddr_dq[27] 16.208 638.123 ddr_dq[28] 16.219 638.530 ddr_dq[29] 16.216 638.409 ddr_dq[3] 21.576 849.445 ddr_dq[30] 16.208 638.102 ddr_dq[31] 16.214 638.328 ddr_dq[32] 9.830 387.025 ddr_dq[33] 9.846 387.648 ddr_dq[34] 9.849 387.771 ddr_dq[35] 9.844 387.570 ddr_dq[36] 9.844 387.567 ddr_dq[37] 9.841 387.439 ddr_dq[38] 9.797 385.700 ddr_dq[39] 9.844 387.577 ddr_dq[4] 21.705 854.517 ddr_dq[40] 16.363 644.215 ddr_dq[41] 16.328 642.825 ddr_dq[42] 16.329 642.874 ddr_dq[43] 16.347 643.580 ddr_dq[44] 16.332 642.987 ddr_dq[45] 16.332 642.996 ddr_dq[46] 16.314 642.268 ddr_dq[47] 16.296 641.593 ddr_dq[48] 9.275 365.140 ddr_dq[49] 9.278 365.279 ddr_dq[5] 21.641 852.025 ddr_dq[50] 9.263 364.685 ddr_dq[51] 9.263 364.683 ddr_dq[52] 9.281 365.387 table 48-38. package trace length (sheet 3 of 13)
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1808 48.0 package specifications ddr_dq[53] 9.279 365.315 ddr_dq[54] 9.286 365.578 ddr_dq[55] 9.323 367.049 ddr_dq[56] 17.637 694.380 ddr_dq[57] 17.613 693.420 ddr_dq[58] 17.621 693.739 ddr_dq[59] 17.653 694.993 ddr_dq[6] 21.578 849.508 ddr_dq[60] 17.632 694.158 ddr_dq[61] 17.634 694.259 ddr_dq[62] 17.636 694.313 ddr_dq[63] 17.630 694.105 ddr_dq[7] 21.577 849.491 ddr_dq[8] 18.878 743.244 ddr_dq[9] 18.887 743.585 ddr_dqs[0] 21.573 849.330 ddr_dqs[0]# 21.579 849.555 ddr_dqs[1] 18.895 743.887 ddr_dqs[1]# 18.896 743.928 ddr_dqs[2] 15.763 620.607 ddr_dqs[2]# 15.762 620.552 ddr_dqs[3] 16.215 638.376 ddr_dqs[3]# 16.210 638.183 ddr_dqs[4] 9.851 387.826 ddr_dqs[4]# 9.852 387.865 ddr_dqs[5] 16.326 642.759 ddr_dqs[5]# 16.327 642.790 ddr_dqs[6] 9.282 365.449 ddr_dqs[6]# 9.282 365.450 ddr_dqs[7] 17.635 694.288 ddr_dqs[7]# 17.636 694.332 ddr_dqs[8] 16.623 654.465 ddr_dqs[8]# 16.622 654.409 ddr_drvcres 17.435 686.408 ddr_ecc[0] 16.624 654.476 ddr_ecc[1] 16.639 655.072 ddr_ecc[2] 16.632 654.806 ddr_ecc[3] 16.625 654.526 ddr_ecc[4] 16.623 654.455 ddr_ecc[5] 16.624 654.483 ddr_ecc[6] 16.618 654.260 ddr_ecc[7] 16.631 654.761 table 48-38. package trace length (sheet 4 of 13)
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1809 48.0 package specifications ddr_odt0 13.422 528.444 ddr_odt1 9.022 355.190 ddr_ras# 7.307 287.675 ddr_rcompx 5.341 210.280 ddr_slewcres 7.752 305.192 ddr_we# 13.589 535.005 eecs 6.423 252.856 eedi 5.028 197.952 eedo 7.934 312.350 eesk 3.712 146.150 ex_addr[0] 9.577 377.058 ex_addr[1] 8.329 327.909 ex_addr[10] 14.301 563.029 ex_addr[11] 5.763 226.882 ex_addr[12] 11.074 435.991 ex_addr[13] 7.193 283.205 ex_addr[14] 12.202 480.380 ex_addr[15] 11.131 438.227 ex_addr[16] 15.750 620.088 ex_addr[17] 7.988 314.474 ex_addr[18] 14.348 564.887 ex_addr[19] 6.211 244.535 ex_addr[2] 11.191 440.593 ex_addr[20] 8.508 334.979 ex_addr[21] 10.344 407.225 ex_addr[22] 15.206 598.648 ex_addr[23] 12.119 477.116 ex_addr[24] 14.198 558.982 ex_addr[3] 9.758 384.181 ex_addr[4] 13.241 521.283 ex_addr[5] 5.231 205.950 ex_addr[6] 14.716 579.354 ex_addr[7] 6.677 262.866 ex_addr[8] 15.010 590.942 ex_addr[9] 13.169 518.482 ex_ale 13.633 536.744 ex_be[0]# 13.966 549.828 ex_be[1]# 13.394 527.324 ex_burst 11.580 455.896 ex_clk 7.766 305.734 ex_cs[0]# 10.246 403.396 ex_cs[1]# 12.869 506.664 table 48-38. package trace length (sheet 5 of 13)
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1810 48.0 package specifications ex_cs[2]# 11.633 457.976 ex_cs[3]# 6.433 253.281 ex_cs[4]# 13.385 526.957 ex_cs[5]# 5.122 201.662 ex_cs[6]# 12.570 494.893 ex_cs[7]# 9.169 361.002 ex_data[0] 12.549 494.074 ex_data[1] 4.370 172.049 ex_data[10] 11.464 451.329 ex_data[11] 6.517 256.557 ex_data[12] 10.127 398.700 ex_data[13] 5.880 231.493 ex_data[14] 9.244 363.939 ex_data[15] 12.536 493.546 ex_data[2] 9.659 380.268 ex_data[3] 6.423 252.858 ex_data[4] 8.525 335.641 ex_data[5] 5.612 220.957 ex_data[6] 11.127 438.090 ex_data[7] 8.135 320.272 ex_data[8] 12.701 500.035 ex_data[9] 10.201 401.600 ex_iowait# 11.779 463.724 ex_parity[0] 10.170 400.413 ex_parity[1] 9.016 354.978 ex_rcompn 6.527 256.976 ex_rcompp 8.848 348.345 ex_rd# 8.364 329.302 ex_rdy[0]# 10.024 394.657 ex_rdy[1]# 4.821 189.808 ex_rdy[2]# 7.015 276.185 ex_rdy[3]# 5.475 215.564 reserved20 7.684 302.530 nc58 5.872 231.173 nc59 2.846 112.054 ex_wr# 10.965 431.704 gbe_aux_pwr_good 12.179 479.487 gbe_pme_wake 2.435 95.851 gbe_rcompn 3.108 122.376 gbe_rcompp 4.314 169.835 gbe_refclk 12.170 479.131 gbe_refclk_rmii 9.952 391.815 table 48-38. package trace length (sheet 6 of 13)
intel ? ep80579 integrated processor product line datasheet , volume 6 of 6 august 2009 datasheet order number: 320066--003us 1811 48.0 package specifications gbe0_rxclk 12.511 492.561 gbe0_rxctl 12.513 492.630 gbe0_rxdata[0] 12.512 492.611 gbe0_rxdata[1] 12.515 492.720 gbe0_rxdata[2] 12.507 492.398 gbe0_rxdata[3] 12.550 494.094 gbe0_txclk 11.522 453.608 gbe0_txctl 11.550 454.706 gbe0_txdata[0] 11.537 454.199 gbe0_txdata[1] 11.546 454.566 gbe0_txdata[2] 11.543 454.441 gbe0_txdata[3] 11.550 454.718 gbe1_rxclk 13.836 544.735 gbe1_rxctl 13.706 539.617 gbe1_rxdata[0] 13.774 542.284 gbe1_rxdata[1] 13.807 543.568 gbe1_rxdata[2] 13.830 544.505 gbe1_rxdata[3] 12.812 504.417 gbe1_txclk 11.354 447.015 gbe1_txctl 11.318 445.590 gbe1_txdata[0] 11.575 455.719 gbe1_txdata[1] 11.321 445.714 gbe1_txdata[2] 11.317 445.570 gbe1_txdata[3] 11.385 448.228 gbe2_rxclk 14.349 564.924 gbe2_rxctl 14.448 568.828 gbe2_rxdata[0] 14.454 569.038 gbe2_rxdata[1] 14.397 566.791 gbe2_rxdata[2] 14.364 565.506 gbe2_rxdata[3] 14.427 568.002 gbe2_txclk 9.814 386.392 gbe2_txctl 9.829 386.978 gbe2_txdata[0] 9.860 388.186 gbe2_txdata[1] 9.844 387.569 gbe2_txdata[2] 9.821 386.652 gbe2_txdata[3] 9.816 386.449 gp11_smbalert# 13.735 540.749 gp16_irq24 12.667 498.714 gp17_irq25 11.633 458.005 gp18_irq36 12.895 507.672 gp19_irq37 4.294 169.053 gp2_pirqe# 21.089 830.274 table 48-38. package trace length (sheet 7 of 13)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1812 order number: 320066-003us gp20_irq26 5.504 216.709 gp21_irq27 9.363 368.634 gp23_irq28 13.423 528.461 gp24_irq29 6.180 243.295 gp25_irq38 7.118 280.246 gp26_sata0gp 13.028 512.932 gp27_irq39 5.441 214.229 gp28_irq30 6.145 241.948 gp29_sata1gp 13.651 537.454 gp3_pirqf# 15.305 602.548 gp30_irq31 8.623 339.477 gp31_irq32 12.325 485.234 gp33_irq33 9.933 391.067 gp34_irq34 5.340 210.233 gp4_pirqg# 5.858 230.617 gp40_irq35 10.978 432.192 gp41_ldrq[1]# 6.898 271.569 gp5_pirqh# 15.920 626.760 gpio[0] 9.010 354.741 gpio[1] 10.515 413.962 gpio[10] 16.548 651.515 gpio[12] 13.810 543.711 gpio[13] 4.829 190.126 gpio[14] 9.831 387.039 gpio[15] 16.505 649.793 gpio[48] 7.488 294.791 gpio[6] 3.529 138.922 gpio[7] 11.371 447.666 gpio[8] 13.764 541.881 gpio[9] 14.464 569.455 ierr# 12.024 473.375 init33v_out# 14.076 554.186 intruder# 4.825 189.978 lad[0] 7.962 313.446 lad[1] 10.784 424.578 lad[2] 10.981 432.324 lad[3] 10.887 428.623 ldrq[0]# 12.223 481.210 lframe# 13.960 549.624 mdc 4.939 194.456 mdio 6.926 272.661 nc56 8.969 353.099 table 48-38. package trace length (sheet 8 of 13)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1813 intel ? ep80579 integrated processor nc57 5.263 207.203 nmi 7.702 303.246 oc[0]# 9.444 371.817 oc[1]# 9.652 379.993 pciclk 12.045 474.210 pcirst# 8.107 319.175 pe_hpintr# 11.288 444.427 pea_clkn 12.821 504.759 pea_clkp 12.820 504.708 pea_icompi 14.484 570.217 pea_icompo 17.850 702.754 pea_rcompo 10.914 429.683 pea0_rn[0] 17.987 708.157 pea0_rn[1] 19.005 748.238 pea0_rn[2] 17.869 703.509 pea0_rn[3] 16.952 667.417 pea0_rn[4] 13.150 517.714 pea0_rn[5] 14.652 576.834 pea0_rn[6] 12.543 493.836 pea0_rn[7] 12.432 489.463 pea0_rp[0] 17.986 708.127 pea0_rp[1] 19.006 748.251 pea0_rp[2] 17.871 703.580 pea0_rp[3] 16.953 667.460 pea0_rp[4] 13.150 517.721 pea0_rp[5] 14.652 576.843 pea0_rp[6] 12.545 493.878 pea0_rp[7] 12.433 489.489 pea0_tn[0] 15.850 624.018 pea0_tn[1] 15.885 625.394 pea0_tn[2] 15.158 596.780 pea0_tn[3] 14.917 587.283 pea0_tn[4] 11.376 447.854 pea0_tn[5] 12.011 472.889 pea0_tn[6] 10.478 412.523 pea0_tn[7] 10.320 406.280 pea0_tp[0] 15.852 624.096 pea0_tp[1] 15.886 625.441 pea0_tp[2] 15.155 596.668 pea0_tp[3] 14.920 587.387 pea0_tp[4] 11.374 447.781 pea0_tp[5] 12.015 473.021 table 48-38. package trace length (sheet 9 of 13)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1814 order number: 320066-003us pea0_tp[6] 10.473 412.327 pea0_tp[7] 10.320 406.299 pltrst# 14.629 575.934 pme# 17.160 675.587 prochot# 6.607 260.129 pwrbtn# 5.979 235.412 pwrgd 6.614 260.394 pwrok 8.173 321.784 rcin# 13.116 516.392 reserved18 3.466 136.458 reserved19 2.693 106.039 ri# 9.836 387.243 rsmrst# 13.264 522.220 rstin# 13.004 511.971 rtcx1 15.716 618.739 rtcx2 14.528 571.956 rtest# 6.026 237.230 rx_clk0 7.781 306.336 rx_clk1 12.076 475.418 rx_clk2 10.037 395.165 rx_data_in0 11.532 454.030 rx_data_in1 13.708 539.697 rx_data_in2 6.966 274.245 rx_frame0 11.473 451.709 rx_frame1 5.124 201.729 rx_frame2 11.077 436.117 sata_clkrefn 6.887 271.137 sata_clkrefp 6.887 271.122 sata_rbias 7.244 285.180 sata_rbias# 7.240 285.043 sata_rxn0 11.368 447.551 sata_rxn1 11.879 467.668 sata_rxp0 11.367 447.539 sata_rxp1 11.878 467.618 sata_txn0 8.527 335.728 sata_txn1 8.737 343.980 sata_txp0 8.528 335.767 sata_txp1 8.737 343.988 sataled# 12.290 483.847 serirq 14.808 582.997 siu_cts1# 12.658 498.346 siu_cts2# 11.522 453.641 table 48-38. package trace length (sheet 10 of 13)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1815 intel ? ep80579 integrated processor siu_dcd1# 8.662 341.015 siu_dcd2# 12.771 502.813 siu_dsr1# 8.047 316.821 siu_dsr2# 9.299 366.085 siu_dtr1# 5.291 208.319 siu_dtr2# 13.306 523.852 siu_ri1# 10.683 420.571 siu_ri2# 13.780 542.504 siu_rts1# 6.519 256.663 siu_rts2# 10.021 394.544 siu_rxd1 10.428 410.555 siu_rxd2 9.166 360.885 siu_txd1 11.680 459.861 siu_txd2 10.817 425.862 slp_s3# 13.629 536.592 slp_s4# 12.191 479.976 slp_s5# 5.919 233.020 smbclk 14.262 561.513 smbdata 8.956 352.596 smbscl 8.225 323.817 smbsda 12.143 478.077 smi_out# 12.124 477.316 smlink[0] 7.203 283.596 smlink[1] 15.500 610.226 spi_cs# 12.377 487.297 spi_miso 13.590 535.039 spi_mosi 4.715 185.648 spi_sclk 11.543 454.435 spkr 11.897 468.375 ssp_extclk 11.658 458.963 ssp_rxd 6.956 273.865 ssp_sclk 13.584 534.803 ssp_sfrm 11.775 463.580 ssp_txd 14.865 585.241 stpclk_out# 11.067 435.700 sus_stat# 12.854 506.066 susclk 10.910 429.537 sys_pwr_ok 8.287 326.244 sys_reset# 10.851 427.198 tck 9.399 370.022 tdi 12.463 490.658 tdo 16.247 639.650 table 48-38. package trace length (sheet 11 of 13)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1816 order number: 320066-003us thermda 15.663 616.660 thermdc 21.693 854.044 thrmtrip# 10.177 400.682 tms 9.491 373.675 trst# 5.699 224.384 tx_clk0 9.120 359.056 tx_clk1 12.360 486.597 tx_clk2 8.721 343.346 tx_data_out0 12.435 489.561 tx_data_out1 3.229 127.113 tx_data_out2 12.124 477.319 tx_frame0 6.446 253.781 tx_frame1 13.373 526.502 tx_frame2 7.880 310.248 uart_clk 4.251 167.356 usb_rbiasn 12.848 505.813 usb_rbiasp 11.917 469.164 usbn0 12.052 474.470 usbn1 12.031 473.662 usbp0 12.054 474.563 usbp1 12.034 473.779 v_sel 14.260 561.437 vcc 717.956 28266.002 vcc 10.440 411.038 vcc18 38.611 1520.102 vcc1p2_usbsus 4.633 182.385 vcc25 4.056 159.675 vcc33 23.406 921.500 vcc50 33.496 1318.736 vcc50_sus 11.967 471.138 vcca[1] 13.919 547.982 vcca[2] 13.440 529.123 vccabg3p3_usb 4.121 162.225 vccabgp033 6.969 274.374 vccahpll 2.351 92.569 vccape 10.158 399.930 vccape0pll12 7.954 313.154 vccape0pll12 9.638 379.466 vccapll 11.901 468.528 vccarx 0.784 30.856 vccasatabg3p3 3.618 142.431 vccatx 0.784 30.856 table 48-38. package trace length (sheet 12 of 13)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1817 intel ? ep80579 integrated processor vccausb12 1.045 41.142 vccgbe33 4.637 182.555 vccgbepsus 8.735 343.885 vccprtc 7.487 294.763 vccpsus 4.773 187.903 vccrpe 7.535 296.639 vccsata 2.491 98.056 vccsata33 11.246 442.738 vccsus1 15.545 612.007 vccsus25 4.409 173.599 vcctmp18 8.621 339.413 vccusb12 4.232 166.620 vccvc 10.622 418.189 vccvc 204.574 8054.101 vrmpwrgd 5.588 219.986 vss 266.015 10473.015 vssa 0.784 30.857 vttddr 7.470 294.093 wdt_tout# 14.519 571.632 table 48-38. package trace length (sheet 13 of 13)
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1818 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1819 intel ? ep80579 integrated processor 49.0 electrical specifications this chapter provides electrical specifications for the ep80579 interfaces. the information contained in this chapter is divided into the following sections: section title section link absolute maximum ratings section 49.1 input and i/o pin undershoot and overshoot section 49.1.1 power characteristics section 49.2 power supply requirements section 49.2.1 clocks section 49.3 power and reset sequencing section 49.4 ac/dc characteristics section 49.5 power management section 49.5.1 ddr2 section 49.5.2 pci express* section 49.5.3 serial ata (sata) section 49.5.4 universal serial bus (usb) section 49.5.5 system management bus (smbus) section 49.5.6 universal asynchronous receiver/transmitter (uart) section 49.5.7 serial peripheral interface (spi) section 49.5.8 low pin count (lpc) section 49.5.9 general purpose i/o (gpio) section 49.5.10 iich interrupt signal section 49.5.11 real time clock section 49.5.12 gigabit ethernet (gbe: rmii, rgmii, mdio, eeprom) section 49.5.13 time division multiplex (tdm) section 49.5.14 local expansion bus (leb) section 49.5.15 controller access network (can) section 49.5.16 sync serial port (ssp) section 49.5.17 ieee 1588-2008 hardware assist interface section 49.5.18 iich miscellaneous signals (misc. iich signals) section 49.5.19 clock resource unit (cru) section 49.5.20 sideband miscellaneous signals section 49.5.21 imch reset section 49.5.22 jtag section 49.5.23
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1820 order number: 320066-003us 49.1 absolute maximum ratings absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operate all supplies within the stated nominal operating voltage described in table 49-6, ?operating conditions power supply rails? on page 1823 . absolute maximum ratings are not the normal operating conditions of the device. all voltages are specified with respect to gnd unless otherwise specified. 49.1.1 input and i/o pin undershoot and overshoot specifications the following tables provide input and i/o pin undershoot and overshoot specifications: ? ta b l e 4 9 - 2 : applies to pci, jtag, sata, cru (15 pins) input and i/o pin groups ? ta b l e 4 9 - 3 : applies to ddr2 input and i/o pin group ? ta b l e 4 9 - 4 : applies to gbe input and i/o pin group ? ta b l e 4 9 - 5 : applies to input and i/o pin groups rtc, spi, usb, tdm, leb, can, ssp, ieee 1588-2008, ich miscellaneous, iich, smbus, uart, lpc, gpio, sideband miscellaneous, imch, pmi, and miscellaneous table 49-1. absolute maximum ratings parameter maximum rating notes operating temperature 0o c to 70o c operating temperature (industrial) -40o c to 85o c storage temperature -10o c to 45o c 1 supply voltage ia-32 core 600 mhz sku (1.0v nominal) 1.03v supply voltage ia-32 core 1066/1200 mhz sku (1.3v nominal) 1.326v supply voltage ddr2 (1.8v nominal) 1.89v supply voltage i/o (1.2v nominal) 1.26v supply voltage i/o (2.5v nominal) 2.62v supply voltage i/o (3.3v nominal) 3.46v supply voltage i/o (5.0v nominal) 5.25v note: 1. the component storage temperature range (pre-board assembly) is -45c to 75c for short-term exposure and -10c to 45c for sustained exposure. consistent with industry practice, intel does not specify storage conditions beyond component level (e.g. board or system level). in addition to this storage temperature specification, compliance to the latest ipc/jedec j-std-033b.1 joint industry standard is required for all surface mount devices (smds). this document governs handling, packing, shipping and use of moisture/reflow sensitive smds.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1821 intel ? ep80579 integrated processor table 49-2. undershoot and overshoot for pci, jtag, sata and cru signal groups vus a vos b pw c signal group d -0.35 1.35 2.00e-08 ? table 48-9, ?pci express interface signals? on page 1741 ; ? table 48-27, ?jtag interface signals? on page 1769 , ? table 48-17, ?serial ata interface signals? on page 1753 , ? table 48-5, ?global clock and reset (cru) signals? on page 1736 -0.4 1.4 2.00e-08 -0.45 1.45 2.00e-08 -0.5 1.5 8.88e-09 -0.55 1.55 3.66e-09 -0.6 1.6 1.66e-09 -0.65 1.65 6.64e-10 -0.7 1.7 2.46e-10 -0.75 1.75 1.28e-10 -0.8 1.8 8.47e-11 a. vus (voltage undershoot) - values of vpeak (peak undershoot voltage) for the maximum pulse width specified. b. vos (voltage overshoot) - values of vpeak (peak overshoot voltage) for the maximum pulse width specified. c. pw (pulse width) - maximum pulse width allowed for a given vpeak value (undershoot or overshoot), such that the reliability specifications of the device are not exceeded. d. values provided in this table apply to input and i/o pins in signal groups: pci, jtag, sata, and cru (15 pins). for more details, follow the table links provided. table 49-3. undershoot and overshoot for ddr2 signal group vus a vos b pw c signal group d -0.2 2 1.25e-10 table 48-8, ?ddr2 interface signals? on page 1739 -0.3 2.1 1.25e-10 -0.4 2.2 1.92e-09 -0.5 2.3 6.22e-10 -0.6 2.4 1.80e-11 -0.7 2.5 3.67e-12 -0.8 2.6 2.98e-12 -0.9 2.7 2.73e-12 -1 2.8 2.58e-12 -1.1 2.9 2.08e-12 a. vus (voltage undershoot) - values of vpeak (pea k undershoot voltage) for the maximum pulse width specified. b. vos (voltage overshoot) - values of vpeak (peak overshoot voltage) for the maximum pulse width specified. c. pw (pulse width) - maximum pulse width allowed for a given vpeak value (undershoot or overshoot), such that the reliability specifications of the device are not exceeded. d. values provided in this table apply to input and i/o pins in the ddr2 signal group. for more details, follow the table link provided.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1822 order number: 320066-003us table 49-4. undershoot and overshoot for gbe signal group vus a vos b pw c signal group d -0.1 3.4 1.25e-09 table 48-22, ?gigabit ethernet interface signals? on page 1760 -0.2 3.5 1.25e-09 -0.3 3.6 1.25e-09 -0.4 3.7 6.04e-10 -0.5 3.8 1.44e-10 -0.6 3.9 3.41e-11 -0.7 4 9.55e-12 -0.8 4.1 4.97e-12 -0.9 4.2 3.28e-12 -1 4.3 2.97e-12 a. vus (voltage undershoot) - values of vpeak (peak undershoot voltage) for the maximum pulse width specified. b. vos (voltage overshoot) - values of vpeak (peak overshoot voltage) for the maximum pulse width specified. c. pw (pulse width) - maximum pulse width allowed for a given vpeak value (undershoot or overshoot), such that the reliability specifications of the device are not exceeded. d. values provided in this table apply to input and i/o pins in the gbe signal group. for more details, follow the table link provided. table 49-5. undershoot and overshoot for rtc, spi, usb, tdm, lebus, can, ssp, ieee 1588-2008, ich miscellaneous, iich, smbus, uart, lpc, gpio, sideband miscellaneous, imch, pmi, and miscellaneous signal groups vus a vos b pw c signal group d -0.1 3.4 1.00e-08 refer to table 48-3, ?signal pin description references? on page 1735 for links to input and i/o pin signal descriptions -0.2 3.5 1.00e-08 -0.3 3.6 1.00e-08 -0.4 3.7 1.00e-08 -0.5 3.8 2.92e-09 -0.6 3.9 7.17e-10 -0.7 4 1.77e-10 -0.8 4.1 5.96e-11 -0.9 4.2 3.31e-11 -1 4.3 2.58e-11 a. vus (voltage undershoot) - values of vpeak (peak undershoot voltage) for the maximum pulse width specified. b. vos (voltage overshoot) - values of vpeak (peak overshoot voltage) for the maximum pulse width specified. c. pw (pulse width) - maximum pulse width allowed for a given vpeak value (undershoot or overshoot), such that the reliability specifications of the device are not exceeded. d. values provided in this table apply to input and i/o pins in signal groups: rtc, spi, usb, tdm, lebus, can, ssp, ieee 1588-2008, ich miscellaneous, iich, smbus, uart, lpc, gpio, sideband miscellaneous, imch, pmi, and miscellaneous. for more details, follow the table links provided.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1823 intel ? ep80579 integrated processor 49.2 power characteristics 49.2.1 power supply requirements this section describes areas related to the ep80579?s power, including: ? description of power supply requirements ? power wells and platform expectations for connecting the power wells ?power planes ta bl e 4 9 - 6 and ta bl e 4 9 - 7 defines the power supply requirements for each power rail. note: further details for the ep80579 power supply rails are provided in section 6-3, ?ep80579 power supply pins? table 49-6. operating conditions power supply rails (sheet 1 of 2) well/voltage rail symbol supply types tolerance +/- min nominal max unit notes core 1.0 v (ia-32 core) vccvc core power, freq @ 600 mhz 2% 0.98 1.00 1.02 v 1.3 v (ia-32 core) vccvc core power, freq @ 1066 mhz 2% 1.274 1.30 1.326 v 1.3 v (ia-32 core) vccvc core power, freq @ 1200 mhz 2% 1.274 1.30 1.326 v 1.2 v vcca[2:1] core pll analog power 5% 1.14 1.20 1.26 v i/o 1.2 v (soc logic, i/o) vcc cru, cru_pad, ddr2, expansion bus, gbe, imch_pad, misc i/o, pci, express*, sata core power 5% 1.14 1.2 1.26 v vccahpll cru analog pll power 5% 1.14 1.2 1.26 v vccape0pll12 pci express* pll digital power 5% 1.14 1.2 1.26 v vccape pci express* transmitter/receiver analog power 5% 1.14 1.2 1.26 v vccrpe pci express* receiver digital power 5% 1.14 1.2 1.26 v vccapll sata analog pll power 5% 1.14 1.2 1.26 v vccarx sata analog receiver power 5% 1.14 1.2 1.26 v vccatx sata analog transmitter power 5% 1.14 1.2 1.26 v vccsata sata power 5% 1.14 1.2 1.26 v vccausb12 usb analog power 5% 1.14 1.2 1.26 v vccusb12 usb digital power 5% 1.14 1.2 1.26 v 0.9 v (ddr2) vttddr ddr2 reference vttddr derived from vcc18, refer to section 49.5.2.2, ?ddr2 dc characteristics? 1.8 v vcc18 ddr2 i/o power/ random number generator power 5% 1.71 1.8 1.89 v
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1824 order number: 320066-003us i/o continued vcctmp18 thermal sensor power 5% 1.71 1.8 1.89 v 2.5 v vcc25 gbe 2.5v power 5% 2.375 2.5 2.625 v 3.3 v vcc33 cru_pad, expansion bus, imch_pad, misc i/o power 5% 3.135 3.3 3.465 v vccabgp033 pci express* bandgap analog power 5% 3.135 3.3 3.465 v vccgbe33 gbe 3.3 v power 5% 3.135 3.3 3.465 v vccsata33 sata power 5% 3.135 3.3 3.465 v vccabg3p3_usb usb2 analog bandgap power 5% 3.135 3.3 3.465 v vccasatabg3p3 sata analog bandgap power 5% 3.135 3.3 3.465 v 5 v vcc50 5v power supply 5% 4.75 5.0 5.25 v suspend 1.2 v sustain supply vcc1p2_usbsus usb, 1.2 v sustain power 5% 1.14 1.2 1.26 v vccsus1 gbe and iich sustain power 5% 1.14 1.2 1.26 2.5 v sustain supply vccsus25 2.5 v sustain power 5% 2.375 2.5 2.625 v 3.3 v sustain supply vccpsus iich, usb sustain power, i/o logic 5% 3.135 3.3 3.465 v vccgbepsus gbe 3.3 v sustain power, i/o logic 5% 3.135 3.3 3.465 v 5v sustain supply vcc50_sus 5v sustain well 5% 4.75 5.0 5.25 v rtc 3.3 vrtc vccprtc real time clock power 2.0 3.3 3.465 v 1 note: 1. 3.3 v power supply for the rtc (this supply can drop to 2.0 v if all other planes are shut off). this power is not expected to be shut off unless the rtc battery is removed or drained. table 49-6. operating conditions power supply rails (sheet 2 of 2) well/voltage rail symbol supply types tolerance +/- min nominal max unit notes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1825 intel ? ep80579 integrated processor table 49-7. maximum supply current embedded sku (sheet 1 of 2) well/ voltage rail symbol supply types sku id unit 2, 8 4 6 ia-32 core 1.0 v (ia-32 core) iccvc max supply current on vccvc 3.4 - - a 1.3 v (ia-32 core) iccvc max supply current on vccvc - 8.4 11.4 a i/o 1.2 v (soc logic, i/o) icc1_2 max supply current on vcc - soc/sata/ usb 9a icc_ape max supply current, pci express* tx/rx analog power 1.2 v on vccape 1a icc_sata max supply current, sata 1.2 v on vccarx 0.20 a max supply current, sata 1.2 v on vccatx 0.20 a icc_apll max supply current, sata pll 1.2 v on vccapll 0.08 a icc_pe0pll12 max supply current, pci express* pll digital power 1.2 v on vccape0pll12 0.08 a icc_cru_pll max supply current, cru pll 1.2 v on vccahpll 0.06 a icc_usb_pll max supply current, usb pll 1.2 v on vccausb12 0.02 a 0.9 v (ddr2) itt_ddr2 max supply current, ddr2 termination on vttddr 0.95 a 1.8 v icc18_ddr2 max supply current, ddr2 on vcc18 2.5 a 1.8 v icc18 max supply current for misc 1.8v on vcc18 0.3 a 2.5 v icc_gbe max supply current, gbe 2.5 v on vcc25 0.20 a 3.3 v icc_3_3 max supply current, 3.3 v i/o on vcc33 1.0 a icc_abgp033 max supply current, pci express* bandgap power 3.3 v on vccabgp033 0.04 a
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1826 order number: 320066-003us icc_abg3p3usb max supply current, usb bandgap power 3.3 v on vccabg3p3_usb 0.02 a icc_asatabg3p3 max supply current, sata afe bandgap power 3.3 v on vccasatabg3p3 0.04 a 5 v icc_5 max supply current, 5 v on vcc50 0.10 a suspend 1.2 v sustain supply icc_1sus max supply current, 1.2 v suspend well on vccsus1 0.70 a 2.5 v sustain supply icc_25sus 2.5 v suspend well max supply current on vccsus25 0.10 a 3.3 v sustain supply icc_33sus max supply current, 3.3 v suspend well on vccpsus 0.10 a 5v sustain supply icc_5sus max supply current, 5v suspend well on vcc50_sus 0.01 a rtc 3.3 vrtc iccrtc 1 rtc current, on vccprtc 6a notes: 1. iccrtc nominal data is taken with vccprtc at 3.0v while the system is under battery power and at room temperature. this is shown to provide an estimated battery life. maximum value of iccrtc is 2ma while operating under full power. table 49-7. maximum supply current embedded sku (sheet 2 of 2) well/ voltage rail symbol supply types sku id unit 2, 8 4 6
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1827 intel ? ep80579 integrated processor table 49-8. maximum supply current accelerated sku (sheet 1 of 2) well/ voltage rail symbol supply types sku id unit 13,75 ia-32 core 1.0 v (ia-32 core) iccvc max supply current on vccvc 3.4 - - a 1.3 v (ia-32 core) iccvc max supply current on vccvc - 8.4 11.4 a i/o 1.2 v (soc logic, i/o) icc1_2 max supply current on vcc - soc/sata/ usb 11 12 12 a icc_ape max supply current, pci express* tx/rx analog power 1.2v on vccape 1a icc_sata max supply current, sata 1.2v on vccarx 0.20 a max supply current, sata 1.2v on vccatx 0.20 a icc_apll max supply current, sata pll 1.2v on vccapll 0.08 a icc_pe0pll12 max supply current, pci express* pll digital power 1.2v on vccape0pll12 0.08 a icc_cru_pll max supply current, cru pll 1.2v on vccahpll 0.06 a icc_usb_pll max supply current, usb pll 1.2v on vccausb12 0.02 a 0.9 v (ddr2) itt_ddr2 max supply current, ddr2 termination on vttddr 0.95 a 1.8 v icc18_ddr2 max supply current, ddr2 on vcc18 2.5 a 1.8 v icc18 max supply current for misc 1.8v on vcc18 0.3 a 2.5 v icc_gbe max supply current, gbe 2.5v on vcc25 0.20 a 3.3 v icc_3_3 max supply current, 3.3v i/o on vcc33 1.0 a icc_abgp033 max supply current, pci express* bandgap power 3.3v on vccabgp033 0.04 a
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1828 order number: 320066-003us icc_abg3p3usb max supply current, usb bandgap power 3.3v on vccabg3p3_usb 0.02 a icc_asatabg3p3 max supply current, sata afe bandgap power 3.3v on vccasatabg3p3 0.04 a 5 v icc_5 max supply current, 5v on vcc50 0.10 a suspend 1.2 v sustain supply icc_1sus max supply current, 1.2v suspend well on vccsus1 0.70 a 2.5 v sustain supply icc_25sus 2.5v suspend well max supply current on vccsus25 0.10 a 3.3 v sustain supply icc_33sus max supply current, 3.3v suspend well on vccpsus 0.10 a 5 v sustain supply icc_5sus max supply current, 5v suspend well on vcc50_sus 0.01 a rtc 3.3 vrtc iccrtc 1 rtc current, on vccprtc 6a notes: 1. iccrtc nominal data is taken with vccprtc at 3.0v while the system is under battery power and at room temperature. this is shown to provide an estimated battery life. maximum value of iccrtc is 2ma while operating under full power. table 49-8. maximum supply current accelerated sku (sheet 2 of 2) well/ voltage rail symbol supply types sku id unit 13,75
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1829 intel ? ep80579 integrated processor 49.3 clocks 49.3.1 external clock requirements external clocks are supplied to the internal plls as the reference clock and to the other i/o devices. the ep80579 has internal plls that use the reference clock to generate the internal clocks. ta bl e 4 9 - 9 shows the external clocks that must be supplied for the ep80579 and its external interfaces. table 49-9. platform external /internal clock interface clock domain frequency source ddr2 200/266/320/400 mhz internal gbe 2.5, 25, 125 mhz external cru clock 100/133 mhz external pci express* 100 mhz external serial ata 100 mhz external usb2 48 mhz external uart 48/14.7456 mhz external lpc 33 mhz external expansion bus 33/80 mhz external clk14 14.31818 mhz external tdm 512 khz to 8.192 mhz external ssp 3.864 mhz external rtc 32.768 khz external susclk 32.768 khz internal smbus 10-100 khz external spi 17.86 mhz internal
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1830 order number: 320066-003us 49.4 power and reset sequencing the details for power and reset sequencing are described in chapter 6.0, ?ep80579 power sequencing and reset sequence?
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1831 intel ? ep80579 integrated processor 49.5 ac/dc characteristics 49.5.1 power management this section describes the electrical characteristics of the power management interface. 49.5.1.1 power management signal list refer to table 48-19, ?power management interface signals? on page 1756 for the power management signal description. 49.5.1.1.1 power management dc characteristics table 49-10. power management dc input characteristics table 49-11. power management dc output characteristics symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v 2 v il input voltage low - - - 0.8 v 2 leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1832 order number: 320066-003us 49.5.1.2 power management ac characteristics the following table and diagrams illustrate the sequencing that occurs for supported power state transitions. for more detail, see section 27.6, ?sleep states? . table 49-12. power sequencing signal timings (sheet 1 of 2) sym parameter min max units notes fig # t204 vccsus supplies active to rsmrst# inactive 10 ? ms 7 49-1 t214 vcc supplies active to pwrok, vrmpwrgd active 99 ? ms 11 49-1 , 49-3 t215 vcc active to stpclk# and cpuslp# inactive ? 50 ns - 49-1 , 49-3 t217 pwrok and vrmpwrgd / cpu_vrd_pwr_gd active and sys_reset# inactive to sus_stat# inactive and processor i/f signals latched to strap value. 32 38 rtcclk 1 49-1 , 49-3 t218 sus_stat# inactive to pltrst# and pcirst# inactive 2 3 rtcclk 49-1 , 49-3 t230 vccsus active to slp_s5#, slp_s4#, slp_s3#, sus_stat#, pltrst# and pcirst#active ?50 ns - 49-1 t231 t232 rsmrst# inactive to susclk running, slp_s5# inactive ? 110 ms 2 49-1 t233 slp_s5# inactive to slp_s4# inactive see note 10 10 49-1 t234 slp_s4# inactive to slp_s3# inactive 1 2 rtcclk 1 49-1 t271 s1 wake event to cpuslp# inactive 1 25 pciclk 8 49-2 susclk duty cycle 30 70 % 9 t280 stpclk# active to nsi message 0 pciclk 3 49-2 , 49-3 t281 nsi message to cpuslp# active 60 63 pciclk 8 49-2 t283 nsi message to sus_stat# active 2 rtcclk 1 49-3 t284 sus_stat# active to pltrst#, pcirst# active 7 17 rtcclk 1 49-3 t287 pltrst#, pcirst# active to slp_s3# active 1 2 rtcclk 1 49-3 t289 slp_s3# active to pwrok, vrmpwrgd / cpu_vrd_pwr_gd inactive 0 ms 4 49-3 t291 slp_s3# active to slp_s4# active 1 2 rtcclk 1 49-3 t294 pwrok, vrmpwrgd / cpu_vrd_pwr_gd inactive to vcc supplies inactive 20 ns 6 49-3 t295 slp_s4# active to slp_s5# active 1 2 rtcclk 1, 5 49-3 t296 wake event to slp_s5# inactive 1 10 rtcclk 1 49-3 notes: 1. these transitions are clocked off the internal rtc. 1 rtc clock is approximately 32 s. 2. if there is no rtc battery in the system, so vccprtc and the vccpsus supplies come up together, the delay from rtcrst# and an inactive rsmrst# prior to susclk toggling may be as much as 2.5 s. 3. stpclk# assertion triggers the processor to send a stop grant acknowledge cycle. 4. the ep80579 has no maximum timing requirement for this transition. it is up to the system designer to determine if the slp_s3#, slp_s4# and slp_s5# signals are used to control the power planes. 5. if the transition to s5 is due to power button override , slp_s3#, slp_s4# and slp_s5# are asserted together similar to timing t287 (pcirst# active to slp_s3# active). 6. vcc in diagram represents all core well supplies that are powered off in s3 state. 7. vccsus in diagram represents all sustainable supplies as identified in the suspend power well. 8. these transitions are clocked off the 33mhz pciclk. 1 pciclk is approximately 30ns. 9. susclk is an output of the rtc generator (32.768 khz), has a duty cycle that can be as low as 30% or as high as 70%. 10. the min/max times depend on the programming of the ?slp_s4# minimum assertion width? and the ?slp_s4# assertion stretch enable bits. note that this does not apply for synchronous smi?s. 11. the relationship that the active edge of sys_pwr_ok (platform signal connected to pwrok, pwrgd, and sys_pwr_ok pins) has to the active edge of vrmpwrgd/ cpu_vrd_pwr_gd in figure 6-1 must be observed.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1833 intel ? ep80579 integrated processor t297 slp_s5# inactive to slp_s4# inactive see note 10 10 49-3 t298 slp_s4# inactive to slp_s3# inactive 1 2 rtcclk 1 49-3 t299 s4 to slp_s4# inactive see note 10 10 49-3 t300 s3 wake event to slp_s3# inactive (s3 wake) 0 small as possible ms 1 49-3 t301 cpuslp# inactive to stpclk# inactive 8 pciclk - 49-2 table 49-12. power sequencing signal timings (sheet 2 of 2) sym parameter min max units notes fig # notes: 1. these transitions are clocked off the internal rtc. 1 rtc clock is approximately 32 s. 2. if there is no rtc battery in the system, so vccprtc and the vccpsus supplies come up together, the delay from rtcrst# and an inactive rsmrst# prior to susclk toggling may be as much as 2.5 s. 3. stpclk# assertion triggers the processor to send a stop grant acknowledge cycle. 4. the ep80579 has no maximum timing requirement for this transition. it is up to the system designer to determine if the slp_s3#, slp_s4# and slp_s5# signals are used to control the power planes. 5. if the transition to s5 is due to power button override, slp_s3#, slp_s4# and slp_s5# are asserted together similar to timing t287 (pcirst# active to slp_s3# active). 6. vcc in diagram represents all core well supplies that are powered off in s3 state. 7. vccsus in diagram represents all sustainable supplies as identified in the suspend power well. 8. these transitions are clocked off the 33mhz pciclk. 1 pciclk is approximately 30ns. 9. susclk is an output of the rtc generator (32.768 khz), has a duty cycle that can be as low as 30% or as high as 70%. 10. the min/max times depend on the programming of the ?slp_s4# minimum assertion width? and the ?slp_s4# assertion stretch enable bits. note that this does not apply for synchronous smi?s. 11. the relationship that the active edge of sys_pwr_ok (platform signal connected to pwrok, pwrgd, and sys_pwr_ok pins) has to the active edge of vrmpwrgd/ cpu_vrd_pwr_gd in figure 6-1 must be observed.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1834 order number: 320066-003us 49.5.1.2.1 power management timing diagrams figure 49-1. g3 (mechanical off) to s0 timings figure 49-2. s0 to s1 to s0 timing b6550-01 vccsus running susclk slp_s3# vcc supplies pwrok, vrmpwrgd sus_stat# pltrst#, pcirst# processor i/f signals stpclk#, cpuslp# rsmrst# t204 t214 t217 t218 t230 t231 t215 g3 s3 s0 s0 state g3 s5 system state s4 slp_s4# slp_s5# t232 t233 t234 strap values b6552-01 t280 t281 t271 t301 s0 s0 s1 s1 s1 s0 s0 state stpclk# nsi message cpuslp# wake event
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1835 intel ? ep80579 integrated processor 49.5.1.2.2 power management miscellaneous timing diagrams refer to section 6.1.3, ?ep80579 power sequencing and reset sequence? for additional timing requirements related to power management signals. figure 49-3. s0 to s5 to s0 timings, s3 cold b 6553-01 stpclk # nsi message sus_ stat# pltrst#, pcirst # slp_s3# (s3 cold config ) slp_s5# wake event , vcc supplies s0 s 0 s3 s3 s5 s0 t 283 t284 t287 t289 t294 t214 t217 t218 t215 t280 slp_s4# t291 t295 t297 t298 s4 s4 s3 s3/s4/s 5 s0 t296 t300 t299 t302 pwrok vrmpwrgd pwrgd sys_pwr_ok
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1836 order number: 320066-003us 49.5.2 ddr2 the ep80579 provides an integrated memory controller for direct-connection to a single channel of ddr2 with 400, 533, 640 and 800 mt/s unbuffered or registered memory devices, with a maximum support of up to two ranks. the electrical specifications of the ep80579?s ddr2 interface is compatible to the jedec* standard ddr2 sdram specification, jesd79-2b, january 2005 . the ac & dc operating conditions are included in chapter 5 of the jedec specification. refer to the subsections that follow for the electrical characteristics of the ep80579 ddr2 interface. 49.5.2.1 ddr2 signal list for ddr2 pin descriptions, refer to table 48-8, ?ddr2 interface signals? on page 1739 . 49.5.2.2 ddr2 dc characteristics table 49-13. ddr2 dc input characteristics signal group symbol parameter min nom max unit notes ddr2 sstl i/o v il (dc) input low voltage (dc) - - ddr_vref - 150 mv 1, 2 v ih (dc) input high voltage (dc) ddr_vref + 150 --mv 1, 2 i leak input leakage current (0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1837 intel ? ep80579 integrated processor r out output impedance 20.0 - 40.0 ohms 1 ddr_vref ddr2 reference voltage 0.49 x vcc18 0.50 x vcc18 0.51 x vcc18 v 1 vttddr ddr_vtt ddr2 termination voltage ddr_vref - 40 ddr_vref ddr_vref + 40 mv 1 vcc18 ddr_vdd ddr2 supply voltage 1.71 1.80 1.89 v 1 table 49-14. ddr2 dc output characteristics (sheet 2 of 2) signal group symbol parameter min nom max unit notes notes: 1. refer to the jesd-79-2 and sstl-18 specification for further details. 2. ddr2 dc parameters are specified with a 43 ohm test load to vdd/2 and with up to 22 ohm resistive compensation (rcomp). guaranteed by design. these values are typical values seen for this process, but not measured during production testing 3. i oh =0ma at v oh of 0.99*v cc ; i ol =0ma at v ol of 0.01*v cc 4. for open drain outputs, i ol , min=3ma 5. guaranteed by design. 6. slew rate measured from vil(ac) to vih(ac) 7. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. guaranteed by design. these values are typical values seen for this process, but not measured during production testing
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1838 order number: 320066-003us 49.5.2.3 ddr2 ac characteristics table 49-15. ddr2 differential input/output ac levels signal group symbol parameter min max unit notes ddr2 sstl i/o v il (ac) input low voltage (ac) - ddr_vref ? 200 mv 1, 2 v ih (ac) input high voltage (ac) ddr_vref + 200 -mv 1, 2 v id ac differential input voltage 400 - mv v ix differential cross point input voltage ddr_vref - 100 ddr_vref + 100 mv 1, 3 notes: 1. refer to the jesd-79-2 and sstl-18 specification for further details. 2. these input voltages apply only when the signals are inputs to the ep80579. when the signals are inputs to the sdram, the sdram input voltage specifications apply. 3. guaranteed by design. these values are typical values seen for this process, but not measured during production testing
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1839 intel ? ep80579 integrated processor table 49-16. ddr2-400 interface ac characteristics symbol parameter min max unit figures notes system memory clock timings t ck ddr_ck[5:0] period 5 - ns 49-9 t ch ddr_ck[5:0] high time 2.25 - ns 49-11 t cl ddr_ck[5:0] low time 2.25 ns 49-12 tjit ddr_ck[5:0] cycle to cycle jitter - 225 ps 6 tskew_ck-ck skew between any two system memory differential clock pairs (ddr_ck[5:0]/ddr_ck[5:0]#) - 0.06t ck ps 49-10 6 ddr_ck[x] to ddr_ck[y]# (where x does not equal y) 0.25t ck ps 49-10 6 tskew_ck- dqs skew between any system memory clock pair and any system memory strobe ?0.25t ck +0.25t ck ps 49-13 6 system memory command and control signal timings tcvb ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid before ddr_ck rising edge 1.94 - ns 49-8 tcva ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid after ddr_ck rising edge 1.94 - ns 49-8 system memory data and strobe signal timings tdvb ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 0.828 - ns 49-5 6 tdva ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 0.828 - ns 49-5 6 tdopw ddr_dq[63:0], ddr_ecc[7:0] output valid pulse width 2.25 - ns - 3 , 6 tsu_dqs ddr_dq and ddr_ecc input setup time to dqs crossing ?0.897 - ns 49-4 1 , 2, 6 thd_dqs ddr_dq and ddr_ecc input hold time after dqs crossing +1.60 - ns 49-4 1 , 6 twpre ddr_dqs write preamble duration 1.75 (nom) -ns 49-6 twpst ddr_dqs write postamble duration 2.00 (nom) -ns 49-7 notes: 1. data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the dqs delay programmed for a 90 degree phase shift. 2. refer to figure 49-4 . negative minimum setup time at the ep80579 pins is correct ? the dqs crossing at the ep80579 pins is expected to arrive before data becomes valid. data is latched by a delayed copy of dqs (see note 1 ), which nominally centers the strobe within the data valid window. refer to the ddr2 specification for further details. 3. tdopw defines the minimum time a given data bit is guaranteed valid at the pin. note that this is greater than the sum of minimum tdva and tdvb, since strobe-to-data alignment uncertainty subtracts from those times. 4. ac timings are specified into a 25 ohm test load (for dq and dqs) or 50 ohm test load (for other signals) terminated to vdd/2 5. this specification applies for writes only; that is, when the imch is driving the strobes as well as the clocks. refer to the jedec specification for an explanation of strobe to clock timing for ddr2 reads. 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1840 order number: 320066-003us table 49-17. ddr2-533 interface ac characteristics symbol parameter min max unit figures notes system memory clock timings t ck ddr_ck[5:0] period 3.75 - ns 49-9 t ch ddr_ck[5:0] high time 1.70 - ns 49-11 t cl ddr_ck[5:0] low time 1.70 ns 49-12 tjit ddr_ck[5:0] cycle to cycle jitter - 175 ps 6 tskew_ck-ck skew between any two system memory differential clock pairs (ddr_ck[5:0]/ddr_ck[5:0]#) - 0.06t ck ps 49-10 6 ddr_ck[x] to ddr_ck[y]# (where x does not equal y) 0.25t ck ps 49-10 6 tskew_ck- dqs skew between any system memory clock pair and any system memory strobe ?0.25t ck +0.25t ck ps 49-13 6 system memory command and control signal timings tcvb ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid before ddr_ck rising edge 1.379 - ns 49-8 tcva ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid after ddr_ck rising edge 1.379 - ns 49-8 system memory data and strobe signal timings tdvb ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 540.6 - ps 49-5 6 tdva ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 540.6 - ps 49-5 6 tdopw ddr_dq[63:0], ddr_ecc[7:0] output valid pulse width 1.70 - ns - 3 , 6 tsu_dqs ddr_dq and ddr_ecc input setup time to dqs crossing ?0.594 - ns 49-4 1 , 2, 6 thd_dqs ddr_dq and ddr_ecc input hold time after dqs crossing +1.281 - ns 49-4 1 , 6 twpre ddr_dqs write preamble duration 1.31 (nom) -ns 49-6 twpst ddr_dqs write postamble duration 1.50 (nom) -ns 49-7 notes: 1. data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the dqs delay programmed for a 90 degree phase shift. 2. refer to figure 49-5 . negative minimum setup time at the ep80579 pins is correct ? the dqs crossing at the ep80579 pins is expected to arrive before data becomes valid. data is latched by a delayed copy of dqs (see note 1 ), which nominally centers the strobe within the data valid window. refer to the ddr2 specification for further details. 3. tdopw defines the minimum time a given data bit is guaranteed valid at the pin. note that this is greater than the sum of minimum tdva and tdvb, since strobe-to-data alignment uncertainty subtracts from those times. 4. ac timings are specified into a 25 ohm test load (for dq and dqs) or 50 ohm test load (for other signals) terminated to vdd/2 5. this specification applies for writes only; that is, when the imch is driving the strobes as well as the clocks. refer to the jedec specification for an explanation of strobe to clock timing for ddr2 reads. 6. guaranteed by design.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1841 intel ? ep80579 integrated processor table 49-18. ddr2-667 interface ac characteristics symbol parameter min max unit figures notes system memory clock timings t ck ddr_ck[5:0] period 3.125 ns 49-9 t ch ddr_ck[5:0] high time 1.562 ns 49-11 t cl ddr_ck[5:0] low time 1.562 ns 49-12 tjit ddr_ck[5:0] cycle to cycle jitter 150 ps 6 tskew_ck-ck skew between any two system memory differential clock pairs (ddr_ck[5:0]/ddr_ck[5:0]#) - 0.06t ck ps 49-10 6 ddr_ck[x] to ddr_ck[y]# (where x does not equal y) 0.25t ck ps 49-10 6 tskew_ck- dqs skew between any system memory clock pair and any system memory strobe ?0.25t ck +0.25t ck ps 49-13 6 system memory command and control signal timings tcvb ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid before ddr_ck rising edge 1.04 ns 49-8 6 tcva ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid after ddr_ck rising edge 1.04 ns 49-8 6 system memory data and strobe signal timings tdvb ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 0.368 ns 49-5 6 tdva ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 0.368 ns 49-5 6 tdopw ddr_dq[63:0], ddr_ecc[7:0] output valid pulse width 1.35 ns - 3 , 6 tsu_dqs ddr_dq and ddr_ecc input setup time to dqs crossing ?0.413 ns 49-4 1 , 2, 6 thd_dqs ddr_dq and ddr_ecc input hold time after dqs crossing +1.087 ns 49-4 1 , 6 twpre ddr_dqs write preamble duration 1.05 (nom) ns 49-6 6 twpst ddr_dqs write postamble duration 1.20 (nom) ns 49-7 6 notes: 1. data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the dqs delay programmed for a 90 degree phase shift. 2. refer to figure 49-5 . negative minimum setup time at the ep80579 pins is correct ? the dqs crossing at the ep80579 pins is expected to arrive before data becomes valid. data is latched by a delayed copy of dqs (see note 1 ), which nominally centers the strobe within the data valid window. refer to the ddr2 specification for further details. 3. tdopw defines the minimum time a given data bit is guaranteed valid at the pin. note that this is greater than the sum of minimum tdva and tdvb, since strobe-to-data alignment uncertainty subtracts from those times. 4. ac timings are specified into a 25 ohm test load (for dq and dqs) or 50 ohm test load (for other signals) terminated to vdd/2 5. this specification applies for writes only; that is, when the imch is driving the strobes as well as the clocks. refer to the jedec specification for an explanation of strobe to clock timing for ddr2 reads. 6. guaranteed by design.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1842 order number: 320066-003us table 49-19. ddr2-800 interface ac characteristics symbol parameter min max unit figures notes system memory clock timings t ck ddr_ck[5:0] period 2.5 ns 49-9 t ch ddr_ck[5:0] high time 1.120 ns 49-11 t cl ddr_ck[5:0] low time 1.120 ns 49-12 tjit ddr_ck[5:0] cycle to cycle jitter 130 ps 6 tskew_ck-ck skew between any two system memory differential clock pairs (ddr_ck[5:0]/ddr_ck[5:0]#) - 0.06t ck ps 49-10 6 ddr_ck[x] to ddr_ck[y]# (where x does not equal y) 0.25t ck ps 49-10 6 tskew_ck- dqs skew between any system memory clock pair and any system memory strobe ?0.25t ck +0.25t ck ps 49-13 6 system memory command and control signal timings tcvb ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid before ddr_ck rising edge 0.819 ns 49-8 tcva ddr_ras#, ddr_cas#, ddr_we#, ddr_a[14:0], ddr_ba[2:0], ddr_cs[1:0]# valid after ddr_ck rising edge 0.819 ns 49-8 system memory data and strobe signal timings tdvb ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 0.372 ns 49-5 6 tdva ddr_dq[63:0], ddr_ecc[7:0], ddr_dm[8:0] valid before the corresponding ddr_dqs and ddr_dqs_l crossing 0.372 ns 49-5 6 tdopw ddr_dq[63:0], ddr_ecc[7:0] output valid pulse width 1.120 ns - 3 , 6 tsu_dqs ddr_dq and ddr_ecc input setup time to dqs crossing ?0.292 ns 49-4 1 , 2, 6 thd_dqs ddr_dq and ddr_ecc input hold time after dqs crossing +0.956 ns 49-4 1 , 6 twpre ddr_dqs write preamble duration 0.875 (nom) ns 49-6 6 twpst ddr_dqs write postamble duration 1.00 (nom) ns 49-7 6 notes: 1. data to strobe read setup and data from strobe read hold minimum requirements specified are determined with the dqs delay programmed for a 90 degree phase shift. 2. refer to figure 49-5 . negative minimum setup time at the ep80579 pins is correct ? the dqs crossing at the ep80579 pins is expected to arrive before data becomes valid. data is latched by a delayed copy of dqs (see note 1 ), which nominally centers the strobe within the data valid window. refer to the ddr2 specification for further details. 3. tdopw defines the minimum time a given data bit is guaranteed valid at the pin. note that this is greater than the sum of minimum tdva and tdvb, since strobe-to-data alignment uncertainty subtracts from those times. 4. ac timings are specified into a 25 ohm test load (for dq and dqs) or 50 ohm test load (for other signals) terminated to vdd/2 5. this specification applies for writes only; that is, when the imch is driving the strobes as well as the clocks. refer to the jedec specification for an explanation of strobe to clock timing for ddr2 reads. 6. guaranteed by design.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1843 intel ? ep80579 integrated processor 49.5.2.3.1 ddr2 ac timing diagrams figure 49-4. dq and cb (ecc) setup/hold relationship to/from dqs (read operation) figure 49-5. dq and cb (ecc) valid before and after dqs (write operation) dqsn observed at pins tsu_dqs thd_dqs dqs delay (90 deg. nom.) tsu_dqs thd_dqs dqsp observed at pins dq, cb observed at pins dqsn delayed internally dqsp delayed internally b6554-01 dqsn tdvb dqsp dq, cb b6555-01 0.5xvcc valid data valid data valid data valid data tdva tdvb tdva
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1844 order number: 320066-003us figure 49-6. write preamble duration figure 49-7. write postamble duration figure 49-8. control signals valid before and after ddr_ck rising edge figure 49-9. clock cycle time b6556-01 dqs twpre 0.5xvcc b6557-01 dqs twpst 0.5xvcc ddr_ck# tcvb ddr_ck ma, ba, ras#, cas#, we#, cs[1:0]# b6558-01 valid data tcva ddr_ck# tck ddr_ck b6560-01
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1845 intel ? ep80579 integrated processor figure 49-10.skew between any system memory differential clock pair (ddr_ck/ ddr_ck#) note: x represents one differential clock pair, and y represents another differential clock pair. ddr_ck# x ddr_ck x b6561-01 ddr_ck# y tskew ddr_ck y figure 49-11.ddr2 command clock high time figure 49-12.ddr2 command clock low time ddr_ck# tch ddr_ck b6562-01 ddr_ck tcl ddr_ck# b6563-01
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1846 order number: 320066-003us 49.5.3 pci express* this section describes the electrical characteristics of the pci express* interface. the pci express* interface signals are driven by transceivers designed specifically for high-speed serial communication. all pci express* signals are fully differential and operate in a current mode, rather than a voltage mode. these interfaces support a/c coupling to facilitate communication across independent power supply domains and signal at a rate well above the flight time of the interface. the nominal supply voltage for the pci express* interfaces is 1.2v, although receivers must tolerate up to 1.6v peak-to-peak across differentia l pairs as required by the pci express* interface specification . this section describes the electrical characteristics of the pci express* interface. 49.5.3.1 pci express* signal list for pci express* pin description refer to table 48-9, ?pci express interface signals? on page 1741 . 49.5.3.2 pci express* differential transmitter and receiver specifications this electrical specifications of the pci express* differential transmitter and receiver in the ep80579 are compliant with the pci express* base specification, rev. 1.1 (http:// www.pcisig.com) . refer to the specification subsections that follow for more information: ? section 4.3 electrical sub-block of pci express* base specification, rev. 1.1 : ? section 4.3.1 electrical sub-block requirements ? section 4.3.2 electrical signal specifications ? section 4.3.3 differential transmitter (tx) output specifications ? section 4.3.4 differential receiver (rx) input specifications ? section 4.3.3.1 tx compliance eye diagrams ? section 4.3.3.1 rx compliance eye diagrams figure 49-13.ddr2 command clock to dqs skew b6564-01 ddr_dqs t skew_ck-dqs 0.5xvcc t skew_ck-dqs ddr_ck ddr_ck#
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1847 intel ? ep80579 integrated processor table 49-20. pci express* differential receiver (rx) specifications symbol parameter min nom max unit figures notes z rx-diff-dc rx dc differential input impedance 80 100 120 ohms - 1 z rx-dc rx dc input common mode impedance 40 50 60 ohms - 1, 2 z rx-high- imp-dc rx powered down dc input common mode impedance 200k - - ohms - 3 ui unit interval 399.88 400 400.12 ps - 5 v rx-diffp-p differential peak-to-peak input voltage (at spec load) 0.175 - 1.2 v 49-15 6, 4 t rx-eye minimum receiver eye width 0.40 - - ui 49-15 6, 7 t rx-eye- median-to- max-jitter maximum time between the jitter median and maximum deviation from the median --0.3ui- 6, 7 v rx-cm-acp ac peak common mode input voltage - - 150 mv - 6 rl rx-diff differential return loss 15 - db - 8 rl rx-cm common mode return loss 6 - db - 8 v rx-idle- det-diffp-p electrical idle detect threshold 65 - 175 mv - t rx-idle- det-diff- entertime unexpected electrical idle enter detect threshold integration time --10ms- l rx-skew total skew - 20 ns - notes: 1. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 49-14 (not the ep80579 itself) must be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram as shown in figure 49-15 ). if the clocks to the rx and tx are not derived from the same clock chip the tx ui must be used as a reference for the eye diagram. 2. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5ms transition time before receiver termination values must be met on all un-configured lanes of a port. 3. the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. this term must be measured at 300mv above the rx ground. 4. pci-express mvdiff p-p = pea0_xp[x] - pea0_xn[x] 5. no test load is necessarily associated with this value. 6. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 49-14 and measured over any 250 consecutive unit intervals. also refer to the receiver compliance eye diagram as shown in figure 49-15 . that is, the receiver device must be replaced with 50 terminations to ground on each half of the signal pair for the purpose of measuring this parameter. if the clocks to the rx and tx are not derived from the same clock chip the tx ui must be used as a reference for the eye diagram. 7. a trx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the trx-eye-median-to-max- jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total.6 ui jitter budget collected over any 250 consecutive tx uis. it must be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same clock chip, the appropriate average tx ui must be used as the reference for the eye diagram. 8. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d? line (for example, as measured by a vector network analyzer with 50 probes ? see figure 49-15 ). note that the series capacitors ctx is optional for the return loss measurement.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1848 order number: 320066-003us table 49-21. pci express* differential transmitter (tx) specifications (sheet 1 of 2) symbol parameter min nom max unit figures notes v tx-cm-dc- active-idle- delta tx absolute delta of dc common mode voltage during l0 and electrical idle 0 - 100 mv - 1 v tx-cm-dc- line-delta tx absolute delta of dc common mode voltage between d+ and d? 0-25mv- 1 v tx-dc-cm tx dc common mode voltage 0 - 3.6 v - 2 i tx-short tx short circuit current limit - 90 ma - 4 z tx-diff-dc tx dc differential impedance 80 100 120 ohms - z tx-dc tx dc impedance 40 - - ohms - l tx-skew tx lane-to-lane output skew - - 500 ps + 2ui - 3 c tx tx ac coupling capacitor 75 - 200 nf - 6 v o7 tx output voltage 800 - 1200 mvdiff p-p - 5 ui unit interval 399.88 400 400.12 ps - 7 v tx-diffp-p differential peak-to-peak output voltage 0.800 - 1.2 v 49-16 8 v tx-de- ratio de-emphasized differential output voltage ratio ?3.0 ?3.5 ?4.0 db 49-16 8 t tx-eye minimum tx eye width 0.70 - ui 49-16 8 , 9 t tx-eye- median-to- max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.15 ui - 8 , 9 t tx-rise , t tx-fall d+/d? tx output rise/fall time 0.125 - - ui - 8, 11 v tx-cm-acp ac peak common mode output voltage -20mv - 8 notes: 1. specified at the measurement point into a timing and voltage compliance test load as shown in figure 49-14 and measured over any 250 consecutive unit intervals. also refer to the transmitter compliance eye diagram as shown in figure 49-15 . 2. the allowed dc common mode voltage under any conditions. refer to section 4.3.1.8 in the pci- express* specification for further details. 3. static skew between any two transmitter lanes within a single link 4. the allowed current when any output is shorted to ground. 5. pci-express mvdiff p-p = pex_xp[x] - pex_xn[x] 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. 7. no test load is necessarily associated with this value. 8. specified at the measurement point into a timing and voltage compliance test load as shown in figure 49-14 and measured over any 250 consecutive unit intervals. also refer to the transmitter compliance eye diagram as shown in figure 49-16 . 9. a ttx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of ttx- jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the ttx-eye- median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. note that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal, as opposed to the average value. 10. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return less measurements is 50 to ground for both the d+ and d? line (for example, as measured by a vector network analyzer with 50 probes ? see figure 49-16 ). note that the series capacitors ctx is optional for the return loss measurement. 11. measured between 20?80% at transmitter pack age pins into a test load as shown in figure 49-16 for both vtx-d+ and vtx-d?. 12. refer to section 4.3.1.8 in the pci-express* specification for further details.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1849 intel ? ep80579 integrated processor v tx-cm-dc- active-idle- delta absolute delta of dc common mode voltage during l0 and electrical idle 0 100 mv - 8 v tx-cm-dc- line-delta absolute delta of dc common mode voltage between d+ and d? 020mv 8 v tx-idle- diffp electrical idle differential peak output voltage 020mv 8 v tx-rcv- detect the amount of voltage change allowed during receiver detection 600 mv 12 t tx_idle- min minimum time spent in electrical idle 50 ui t tx-idle- set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 20 ui t tx-idle-to- diff-data maximum time to transition to valid tx specification after leaving an electrical idle condition 20 ui t tx-idle- rcv-detect- max maximum time spent in electrical idle before initiating a receiver detect sequence 100 ms 12 rl tx-diff differential return loss 10 db 10 rl tx-cm common mode return loss 6 db 10 t crosslink crosslink random timeout 0 1 ms table 49-21. pci express* differential transmitter (tx) specifications (sheet 2 of 2) symbol parameter min nom max unit figures notes notes: 1. specified at the measurement point into a timing and voltage compliance test load as shown in figure 49-14 and measured over any 250 consecutive unit intervals. also refer to the transmitter compliance eye diagram as shown in figure 49-15 . 2. the allowed dc common mode voltage under any conditions. refer to section 4.3.1.8 in the pci- express* specification for further details. 3. static skew between any two transmitter lanes within a single link 4. the allowed current when any output is shorted to ground. 5. pci-express mvdiff p-p = pex_xp[x] - pex_xn[x] 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. 7. no test load is necessarily associated with this value. 8. specified at the measurement point into a timing and voltage compliance test load as shown in figure 49-14 and measured over any 250 consecutive unit intervals. also refer to the transmitter compliance eye diagram as shown in figure 49-16 . 9. a ttx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of ttx- jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the ttx-eye- median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. note that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal, as opposed to the average value. 10. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return less measurements is 50 to ground for both the d+ and d? line (for example, as measured by a vector network analyzer with 50 probes ? see figure 49-16 ). note that the series capacitors ctx is optional for the return loss measurement. 11. measured between 20?80% at transmitter pack age pins into a test load as shown in figure 49-16 for both vtx-d+ and vtx-d?. 12. refer to section 4.3.1.8 in the pci-express* specification for further details.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1850 order number: 320066-003us 49.5.3.3 pci express* clock specifications table 49-22. pci express* clock dc specifications symbol parameter min nom max unit notes v il input low voltage ?0.150 0 0.150 v 1 v ih input high voltage 0.660 0.710 0.850 v 1 v cross(abs) absolute crossing point 0.250 0.550 v 1, 2, 6 v cross(rel) relative crossing point 0.250 + 0.5 x (v havg ? 0.710) 0.550 + 0.5 x (v havg ? 0.710) v1, 3, 6, 7 v cross range of crossing points 0.140 v 1 v rbm ringback margin 0.200 v 1, 4 v tr threshold region v cross ? 0.100 v cross + 0.100 v1, 5 notes: 1. refer to figure 49-17 and figure 49-18 . 2. crossing voltage is defined as the instantaneous voltage when the rising edge of pea_clkp is equal to the falling edge of pea_clkn. 3. v havg is the statistical average of the v h measured by the oscilloscope. 4. ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum falling edge ringback. 5. threshold region is defined as a region entered around the crossing point voltage in which the differential receiver switches. it includes input threshold hysteresis. 6. the crossing point must meet the absolute and relative crossing point specifications simultaneously. 7. v havg can be measured directly using ?vtop? on agilent* scopes and ?high? on tektronix* scopes. table 49-23. pci express* clock timings symbol parameter min typical max units figure notes pea_clk frequency 100 mhz clock tolerance 300 300 ppm tp pea_clk period 9.872 ns 49-17 tccjitter cycle to cycle jitter 125 ps duty cycle 45 55 % t5 pea_clk rise time 175 700 ps 49-17 trise pea_clk rise time variation 125 ps t6 pea_clk fall time 175 700 ps 49-17 tfall pea_clk fall time variation 125 ps pea_clk slew rate 0.5 1.6 v/ns 1 , 2 rise/fall matching 20 % notes: 1. rise/fall times and slew rates are measured single ended between 245 mv and 455 mv of the clock swing. 2. slew rate specifications apply to both rising and falling edges.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1851 intel ? ep80579 integrated processor 49.5.3.3.1 pci express* receiver compliance eye diagram figure 49-15 shows the pci express* rx compliance eye diagram. for more details related to the rx compliance eye diagrams refer to section 4.3.4 of the pci express* base specification, rev. 1.1. figure 49-14.pci express* transmitter test load b6565-01 tx silicon + package c = c tx c = c tx r = 50o r = 50o d-package pin d-package pin figure 49-15.pci express* receiver compliance eye diagram b6566-01 v rx-diff = 0mv (d+ d- crossing point v rx-diff = 0mv (d+ d- crossing point v rx-diffp-p-min = 175 mv 0.4ui = t rx-eye-min
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1852 order number: 320066-003us 49.5.3.3.2 pci express* transmitter compliance eye diagram figure 49-16 shows the pci express* tx compliance eye diagram. for more details related to the transmit compliance eye diagrams refer to section 4.3.3.1 of the pci express* base specification, rev. 1.1. figure 49-16.pci express* transmitter compliance eye diagram b6567-01 v tx-diff = 0mv (d+ d- crossing point v tx-diff = 0mv (d+ d- crossing point [de-emphasized bit] 566 mv (3 db) >= v tx-diffp-p-min =>=505 mv (4db) 0.7ui = 1ui ? 0.3ui (j tx-total-max ) [transition bit] v tx-diffp-p-min =>=800 mv [transition bit] v tx-diffp-p-min =>=800 mv
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1853 intel ? ep80579 integrated processor figure 49-17.differential clock waveform figure 49-18.differential clock cross-point specification overshoot vh vl undershoot rising edge ringback falling edge ringback ringback margin crossing voltage crossing voltage b6568-01 tp tph pea_clkn tp = t1: pea_clk period t2: pea_clk period stability (not shown) tph = t3: pea_clk pulse high time tpl = t4: pea_clk pulse low time t5: pea_clk rise time through the threshold region t6: pea_clk fall time through the threshold region threshold region tpl pea_clkp b6569-01 650 600 550 500 200 660 670 680 850 vhavg (mv) crossing point (mv) 250 mv 250 + 0.5 (vhavg ? 710) 550 mv 550 + 0.5 (vhavg ? 710) 690 700 840 830 820 810 800 790 780 770 760 750 740 730 720 710 450 400 350 250 300
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1854 order number: 320066-003us 49.5.4 serial ata (sata) the ep80579 has an integrated sata host controller that supports independent dma operation on two ports and supports data transfer rates of up to 3.0 gb/s (300 mb/s). this technology consists of a receiver and transmitter. the ep80579 sata ports support gen1 electrical specifications for ?short? backplane and external desktop applications running at 1.5gbp/s. these are defined on page 12 of the serial ata ii: electrical specification revision 1.0 26-may 2004 . the ep80579 silicon and platform supports sata hot plug. use of an interlock switch is optional. while sata controllers commonly provide hot plug functionality, sata cable assemblies are not standardized, especially the sata power cable. to support sata hot plug, any ep80579 platform needs to support a sata 15-pin power connector interface with a hot plug compatible sata hdd. the ep80579 supports the serial ata specification, revision 1.0a . the ep80579 also supports several optional sections of the serial ata ii: extensions to serial ata 1.0 specification, revision 1.0 (ahci support is required for some elements). this section describes the electrical characteristics of the sata interface. 49.5.4.1 sata signal list for sata pin descriptions, refer to table 48-17, ?serial ata interface signals? on page 1753 . 49.5.4.2 sata dc characteristics table 49-25. sata dc input characteristics (gpio and sataled#) table 49-24. sata dc input characteristics (sata_rx[p,n]) symbol parameter conditions gen 1 m gen 2 m units notes v imin10 minimum input voltage 240 240 mvdiff p-p 1 v imax10 maximum input voltage 600 750 mvdiff p-p 1 notes: 1. sata vdiff, tx (vimax/min10) is measured at the sata connector on the transmit side (generally, the motherboard connector), where sata mvdiff p-p = |sata[x]txp/rxp - sata[x]txn/rxn| symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v - v il input voltage low - - - 0.8 v - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1855 intel ? ep80579 integrated processor 49.5.4.3 sata dc output characteristics table 49-27. sata dc output characteristics (sataled#) 49.5.4.3.1 sata_clk the 100mhz serial ata reference clock (sataclkp, sataclkn) is the main clock for the sata interface. the reference clock is used by the sata pll to generate the clocks of the sata interface and is implemented on the system as a ground-terminated, low- voltage differential signal pair driven by the system clock chip. 49.5.4.4 sata led the sataled# output is driven whenever the bsy bit is set in any sata port. the sataled# is an active-low open-collector output. when sataled# is low, the led is active. when sataled# is high, the led is inactive. table 49-26. sata dc output characteristics (sata_tx(p,n)) symbol parameter conditions gen 1 m gen 2 m units note v omin8 minimum output voltage 400 400 mvdiff p-p 1 v omax8 maximum output voltage 600 700 mvdiff p-p 1 notes: 1. sata vdiff, tx (vomax/min8) is measured at the sata connector on the transmit side closest to the iich (generally, the motherboard connector), where sata mv diff p-p = |sataxtxp - sataxtxn symbol parameter conditions min typical max units v oh output voltage high l out =-6ma 2.4 - v v ol output voltage low l out =6ma - - 0.4 v oh output current at high voltage v oh =2.4 - - -6 ma ol output current at low voltage v ol =0.8 2 - - ma table 49-28. sata dc clock specifications (sata_clkn, sata_clkp) symbol parameter conditions min typical max units vil12 input low voltage -0.150 0.150 v vih12 input high voltage 0.660 0.850 v vcross(abs) absolute crossing point 0.250 0.550 v
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1856 order number: 320066-003us 49.5.4.5 sata ac characteristics 49.5.5 universal serial bus (usb) the ep80579 has (2) universal serial bus 2.0 interface that can be configured as master, but not as a slave interface. the usb interface supports both usb 1.1 and usb 2.0 signaling. usb1.1 has a low- speed mode (1.5 mbps) and a full-speed mode (12 mbps). usb 2.0 works at high speed lvds mode with a data rate of 480 mbps. the driver operates in voltage mode for usb 1.1 and current mode for usb 2.0. the receiver can detect single-ended/ differential-ended classical signals as well as high speed lvds signals. this section describes the electrical characteristics of the usb interface. 49.5.5.1 usb signal list for usb pin description refer to table 48-18, ?usb interface signals? on page 1755 . table 49-29. sata clock (sata_clkp, sata_clkn) parameter min typical max units period 9.997 - 10.0533 ns rise time 175 - 700 ps fall time 175 - 700 ps table 49-30. sata interface timings symbol parameter min typical max units notes ui gen1 operating data period 666.43 666.6667 670.12 ps 5 ui gen2 operating data period (3 gbps) 333.21 333.3333 335.06 ps 5 rise time (gen1) 0.10 - 0.41 ui 1 , 5 fall time (gen1) 0.10 - 0.41 ui 2 , 5 rise time (gen2) 0.20 0.3 0.41 ui 1 , 5 fall time (gen2) 0.20 0.3 0.41 ui 2 , 5 tx differential skew - - 20 ps comreset 310.4 320 329.6 ns 3 comwake transmit spacing 103.5 106.7 109.9 ns 3 oob operating data period 646.67 - 686.67 ns 4 notes: 1. 20% - 80% at transmitter 2. 80% - 20% at transmitter 3. as measured from 100 mv differential cros s points of last and first edges of burst. 4. operating data period during out-of-band burst transmissions 5. unit interval (ui). equal to the time required to transmit one bit.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1857 intel ? ep80579 integrated processor 49.5.5.2 usb dc characteristics 49.5.5.2.1 usb transreceiver dc characteristics the dc electrical specifications of the usb transreceivers in the ep80579 (usbp0, usbn0, usbp1, usbn1) are compliant with the usb v2.0 specification from april 27, 2000 (refer to section 7.3.2 bus timing/electrical characteristics for more information). external resistors are not required on usbp0, usbn0, usbp1 and usbn1. the chip integrates the 15 k pull-down and provides an output driver impedance of 45 ohm, which requires no external series resistor. 49.5.5.2.2 usb lvttl inputs dc characteristics the dc electrical specifications for the lvttl inputs are described in table 49-31 . table 49-31. usb overcurrent indicators dc input (oc[1:0]) symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - vcc3_3 +0.3v v- v il input voltage low - -0.4 - 0.8 v - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1858 order number: 320066-003us 49.5.5.2.3 usb lv differential dc characteristics the dc electrical specifications for the lv differential signals are described in ta b l e 4 9 - 3 2 . table 49-32. usb lv differential dc characteristics (usbn[1:0], usbp[1:0]) symbol parameter min max unit i ol /i oh notes v di input differential input sensitivity 0.2 v 1 , 2 , 4 v cm input differential common mode range 0.8 2.5 v 1 , 2 , 3 v se input single-ended receiver threshold 0.8 2.0 v 1 , 2 v crs output signal crossover voltage 1.3 2.0 v 2 v hssq input hs squelch detection threshold 100 150 mv 1 v hsdsc input hs disconnect detection threshold 525 625 mv 1 v hscm input hs data signaling common mode voltage range ? 50 500 mv 1 v hsoi output hs idle level ? 10.0 10.0 mv 1 v hsoh output hs data signaling high 360 440 mv 1 v hsol output hs data signaling low ? 10.0 10.0 mv 1 v chirpj output chirp j level 700 1100 mv 1 v chirpk output chirp k level ? 900 ? 500 mv 1 v ol6 output low voltage 0.4 v 5 ma 2 v oh6 output high voltage vcc3_3 ? 0.5 v-2 ma 2 v il4 input low voltage ? 0.5 0.3(vcc3_3) v v ih4 input high voltage 0.5(vcc3_3) vcc3_3 + 0.5 v notes: 1. applies to high-speed usb 2.0 2. applies to low-speed and full-speed 3. includes vdi range 4. vdi = usbp[x] - usbn[x]
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1859 intel ? ep80579 integrated processor 49.5.5.2.4 usb clock (clk48) dc input specifications the dc electrical specifications for the clock input are described in table 49-33 . table 49-33. usb clock (clk48) dc input specifications 49.5.5.3 usb ac characteristics 49.5.5.3.1 usb transreceiver ac specifications the ac electrical specifications of the usb transreceivers in the ep80579 are compliant with the usb v2.0 specification from april 27, 2000 . 49.5.5.3.2 transreceiver timing waveforms the timing waveform specifications of the usb transreceivers in the ep80579 are compliant with the usb v2.0 specification from april 27, 2000 . 49.5.5.4 usb ac specifications symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - vcc3_3 +0.3v v- v il input voltage low - -0.4 - 0.8 v - leak input leakage current v in =3.3v - - 60 a - c in input-pin capacitance ---10pf 1 notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. table 49-34. usb input clock (clk48) ac specifications parameters min typical max units figure operating frequency 48 mhz - frequency tolerance 100 ppm - duty cycle 45 - 55 % - high time 7 - - ns 49-19 low time 7 - - ns 49-19 rise time - - 1.2 ns 49-19 fall time - - 1.2 ns 49-19
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1860 order number: 320066-003us figure 49-19.clock timing table 49-35. usb timing specifications (sheet 1 of 2) parameter min max units figure notes high-speed source 49-20 7 usbp[x], usbn[x] driver rise time 0.8 1.2 ns 49-20 1 , 6 c l = 10 pf usbp[x], usbn[x] driver fall time 0.8 1.2 ns 1 , 6 c l = 10 pf full-speed source 8 usbp[x], usbn[x] driver rise time 4 20 ns 49-20 1 c l = 50 pf usbp[x], usbn[x] driver fall time 4 20 ns 49-20 1 c l = 50 pf source differential driver jitter: to n e x t tra n s i t i o n for paired transitions - 3.5 - 4 3.5 4 ns ns 49-21 2 , 3 source se0 interval of eop 160 175 ns 4 source jitter for differential transition to se0 tra n si t i on - 25ns 49-21 5 receiver data jitter tolerance: to n e x t tra n s i t i o n for paired transitions - 18.5 - 9 18.5 9 ns ns 49-21 3 eop width: must accept as eop 82 ns 49-22 4 width of se0 interval during differential transition 14 ns low-speed source 9 usbp[x], usbn[x] driver rise time 75 300 ns 49-20 1 , 6 c l = 50 pf c l = 350 pf usbp[x], usbn[x] driver fall time 75 300 ns 49-20 1 , 6 c l = 50 pf c l = 350 pf notes: 1. driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum. 2. timing difference between the differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swing point of data li ne at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. high-speed data rate has minimum of 479.760 mb/s and maximum of 480.240 mb/s 8. full-speed data rate has minimum of 11.97 mb/s and maximum of 12.03 mb/s. 9. low-speed data rate has a minimum of 1.48 mb/s and a maximum of 1.52 mb/s. b6570-01 period high time 2.0v 0.8v fall time rise time low time
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1861 intel ? ep80579 integrated processor source differential driver jitter: to n ex t tra n si t i o n for paired transitions - 25 - 14 25 14 ns ns 49-21 2 , 3 source se0 interval of eop 1.25 1.50 s 4 source jitter for differential transition to se0 transition - 40 100 ns 49-21 5 receiver data jitter tolerance: to n e x t tr a n s i t i o n for paired transitions - 152 - 200 152 200 ns ns 49-21 3 eop width: must accept as eop 670 ns 49-22 4 width of se0 interval during differential transition 210 ns table 49-35. usb timing specifications (sheet 2 of 2) parameter min max units figure notes high-speed source 49-20 7 usbp[x], usbn[x] driver rise time 0.8 1.2 ns 49-20 1 , 6 c l = 10 pf usbp[x], usbn[x] driver fall time 0.8 1.2 ns 1 , 6 c l = 10 pf full-speed source 8 notes: 1. driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum. 2. timing difference between the differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swing point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. high-speed data rate has minimum of 479.760 mb/s and maximum of 480.240 mb/s 8. full-speed data rate has minimum of 11.97 mb/s and maximum of 12.03 mb/s. 9. low-speed data rate has a minimum of 1.48 mb/s and a maximum of 1.52 mb/s. figure 49-20.usb rise and fall times differential data lines 90% 10% 10% 90% t r t f rise time fall time c l c l low-speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf full-speed: 4 to 20 ns at c l = 50 pf high-speed: 0.8 to 1.2 ns at c l = 10 pf
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1862 order number: 320066-003us figure 49-21.usb jitter paired transitions consecutive transitions crossover points t period differential data lines jitter figure 49-22.usb eop width differential data lines eop width data crossover level tperiod
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1863 intel ? ep80579 integrated processor 49.5.6 system management bus (smbus) the smbus is smbus 2.0 compliant and is also compatible with most 2-wire components that are i 2 c compatible. the host interface allows the ep80579 to communicate via smbus, the slave interface allows external microcontrollers to access system resource in the iich. the smb does not support access to internal configuration registers. access to the external dimms is through the iich, via i 2 c. this is used to determine the nature of the dimms present in order to configure the memory subsystem correctly, including the configuration of the d-unit. this section describes the electrical characteristics of the system management bus (smbus) interface. 49.5.6.1 smbus signal list for smbus pin description refer to table 48-15, ?smbus interface signals? on page 1750 . 49.5.6.2 smbus dc characteristics table 49-36. smbus dc input characteristics symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v 2 v il input voltage low - - - 0.8 v 2 leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1864 order number: 320066-003us 49.5.6.3 smbus ac characteristics ol output sink current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1865 intel ? ep80579 integrated processor table 49-40. smbus clock timings (smbclk) parameter conditions min. typical max. units notes operating frequency 10 100 khz smb_clk high time 4.0 50 us 1 smb_clk low time 4.7 us smb_clk rise time 1000 ns smb_clk fall time 300 ns note: 1. the max high time provides a simple guaranteed method for devices to detect bus idle conditions table 49-41. smbus output ac characteristics sym parameter min typical max unit fig notes t19 bus frequency 10 100 khz 49-23 per smbus specification t20 signal rise time 1000 ns 49-23 2 t21 signal fall time 300 ns 49-23 3 notes: 1. a device times out when any clock low exceeds this parameter. 2. measured from (v il -0.15 v) to (v ih +0.15 v). 3. measured from (v ih +0.15 v) to (v il -0.15 v), 1 k pull-up, 400 pf load. figure 49-23.smbus transaction t130 smbclk smbdata t131 t19 t134 t20 t21 t135 t132 t18 t133
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1866 order number: 320066-003us figure 49-24.smbus timeout b6572-01 t137 smbclk smbdata t138 t138 start clk ack stop clk ack
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1867 intel ? ep80579 integrated processor 49.5.7 uart this section describes the universal asynchronous receiver/transmitter (uart) serial port used for the two uarts that are integrated into the serial i/o unit and watchdog timer (siw). the uart can be controlled via programmed i/o. the basic programming model is the same for both uarts, with the only difference being the logical device number assigned to each. the serial port consists of a uart that supports all the functions of a standard 16550 uart, including hardware flow control interface. this section describes the electrical characteristics of the uart interface. 49.5.7.1 uart signal list for uart pin description refer to table 48-16, ?uart signals? on page 1751 . 49.5.7.2 uart dc characteristics table 49-42. uart dc input characteristics table 49-43. uart dc output characteristics symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - vcc33 +0.5 v- v il input voltage low - -0.5 - 0.8 v - leak input leakage current 00.9vcc33 -0.5 - - ma ol output current at low voltage v ol <0.1vcc33 - - 1.5 ma notes: 1. voh spec does not apply to signals that are open drain driver. open drain signals must have an external pull up resistor.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1868 order number: 320066-003us table 49-44. uart dc clock specification \ 49.5.7.3 uart ac characteristics the ac electrical specifications of the uart interface are compliant with the pci local bus specification , rev 3.0 (refer to ac specifications for 3.3v signaling for more information). 49.5.7.4 uart receiver ac specifications 49.5.7.4.1 uart transmitter ac specifications 49.5.7.4.2 uart clock timings 14.7456 mhz, and 48 mhz are supported for uart baud clock input. symbol parameter conditions min typical max units notes v ih input voltage high - 0.5vcc33 - vcc33 + 0.5 v- v il input voltage low - - - 0.8 v - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1869 intel ? ep80579 integrated processor 49.5.8 serial peripheral interface (spi) 1 this section describes the electrical characteristics of the serial peripheral interface. 49.5.8.1 spi signal list for spi pin description refer to table 48-13, ?spi interface signals? on page 1749 . 49.5.8.2 spi dc characteristics table 49-47. spi dc input characteristics table 49-48. spi dc output characteristics 49.5.8.3 spi ac characteristics 1. intel recommends using the spi for pre-boot firmware due to the reduced availability of lpc fwh. symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1870 order number: 320066-003us 49.5.9 low pin count (lpc) the lpc interface is used to control all the logical blocks on the serial i/o unit and watchdog timer (siw).lpc bus signals use pci 33 mhz electrical signal characteristics. refer to the low pin count (lpc) interface specification, rev 1.1 for more information. this section describes the electrical characteristics of the lpc interface. 49.5.9.1 lpc signal list for lpc pin description refer to table 48-14, ?lpc and fwh interface signals? on page 1749 . t184 setup of spi_miso with respect to serial clock falling edge at the host 16 - ns 49-25 - t185 hold of spi_miso with respect to serial clock falling edge at the host 0-ns 49-25 - t186 setup of spi_cs[1:0]# assertion with respect to serial clock rising at the host 30 - ns 49-25 - t187 hold of spi_cs[1:0]# deassertion with respect to serial clock falling at the host 30 - ns 49-25 - table 49-49. spi timing specifications (sheet 2 of 2) symbol parameter min max units figures notes notes: 1. the typical clock frequency driven by the ep80579 is 17.86 mhz. figure 49-25.spi timing diagram b6608-01 spi_clk spi_mosi spi_miso spi_cs# t186 t184 t185 t183 t187 t182 t182
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1871 intel ? ep80579 integrated processor 49.5.9.2 lpc dc characteristics table 49-50. lpc dc input characteristics table 49-51. lpc dc output characteristics table 49-52. lpc dc clock specifications symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - vcc33 +0.5 v- v il input voltage low - -0.5 - 0.8 v - leak input leakage current 00.9vcc33 -0.5 - - ma ol output current at low voltage v ol <0.1vcc33 - - 1.5 ma notes: 1. voh spec does not apply to signals that are open drain driver. open drain signals must have an external pull up resistor. symbol parameter conditions min typical max units notes v ih input voltage high - 0.5vcc33 - vcc33 + 0.5 v- v il input voltage low - - - 0.8 v - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1872 order number: 320066-003us 49.5.9.3 lpc ac characteristics 49.5.9.3.1 lpc timing specification 49.5.9.3.2 lpc timing diagrams table 49-53. lpc clock ac characteristics parameter min max units figure period 30 33.3 ns 49-26 high time 11 - ns 49-26 low time 11 - ns 49-26 rise time - 3 ns 49-26 fall time - 3 ns 49-26 table 49-54. lpc input timing specification parameter min typical max units figure lad[3:0]/fwh[3:0] setup time to pciclk rising 7 ns 49-27 lad[3:0/fwh[3:0]] hold time from pciclk rising 0 ns 49-27 ldrq[1:0]# setup time to pciclk rising 12 ns 49-27 ldrq[1:0]# hold time from pciclk rising 0 ns 49-27 table 49-55. lpc output timing specification parameter min typical max units figure lad[3:0]/fwh[3:0] valid delay from pciclk rising 2 11 ns 49-28 lad[3:0]/fwh[3:0] output enable delay from pciclk rising 2ns 49-29 lad[3:0]/fwh[3:0] float delay from pciclk rising 28 ns 49-30 lframe#/fwh[4] valid delay from pciclk rising 2 11 ns 49-28 figure 49-26. lpc clock (pciclk) timing diagram 2.0v 0.8v period high time low time fall time rise time
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1873 intel ? ep80579 integrated processor figure 49-27. lpc input setup and hold timing diagram figure 49-28. lpc valid delay from rising clock edge diagram figure 49-29. lpc output enable delay diagram clock vt input hold time setup time vt 1.5v pciclk clock 1.5v valid delay vt output pciclk clock output output enable delay vt 1.5v pciclk
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1874 order number: 320066-003us 49.5.9.3.3 lpc reset the lpc controller does not adhere to the section of the lpc specification that says ?lreset# is always asserted after lpcpd#?. lreset # is not always asserted after lpcpd#. 49.5.10 general purpose i/o (gpio) gpio are general-purpose i/o signals. these signals can be used for slow-speed, software-controlled i/o. this section describes the electrical characteristics of the gpio interface. 49.5.10.1 gpio signal list for gpio pin description refer to table 48-11, ?general-purpose io signals? on page 1744 . 49.5.10.2 gpio dc characteristics table 49-56. gpio dc input characteristics figure 49-30. lpc float delay diagram input vt output float delay symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - vcc33 +0.5 v- v il input voltage low - -0.5 - 0.8 v - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1875 intel ? ep80579 integrated processor table 49-57. gpio dc output characteristics 49.5.10.3 gpio ac specifications the ac electrical specifications of the gpio interface are compliant with the pci local bus specification, rev. 3.0 (refer to the ac specifications for 3.3v signaling for more information). 49.5.11 iich interrupt signal this section describes the electrical characteristics of the iich interrupt signal interface. 49.5.11.1 iich interrupt signal list for iich interrupt signal pin descriptions, refer to table 48-12, ?iich interrupt signals? on page 1748 . 49.5.11.2 iich interrupt signal dc characteristics table 49-58. iich interrupt signal dc input characteristics symbol parameter conditions min typical max units notes v oh output voltage high l out =-0.5ma 0.9vcc 33 --v 1 v ol output voltage low l out =1.5ma - - 0.1vcc 33 v- notes: 1. voh spec does not apply to signals that are open drain driver. open drain signals must have an external pull up resistor. symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1876 order number: 320066-003us 49.5.11.3 iich interrupt signal ac input, output characteristics the ac electrical specifications of the iich interrupt signal are compliant with the pci local bus specification, rev . 3.0 (refer to ac specifications for 3.3v signaling for more information). 49.5.11.4 iich interrupt signal timing specification 49.5.11.5 iich clock ac specifications v ol output voltage low l out =6ma - 0.4 v - oh output current at high voltage v oh =2.4 - - 1.5 ma - ol output current at low voltage v ol =0.8 - - -0.5 ma - table 49-59. iich interrupt signal dc output characteristics (sheet 2 of 2) symbol parameter conditions min typical max units notes notes: 1. voh spec does not apply to signals that are open drain driver. open drain signals must have an external pull up resistor. table 49-60. iich interrupt signal timing specification parameter min typical max units note serirq setup time to pciclk rising 7 ns 49-31 serirq hold time from pciclk rising 0 ns 49-31 figure 49-31. iich interrupt signal timing diagram table 49-61. iich clock (clk14) ac specifications (sheet 1 of 2) parameters min typical max units figure note operating frequency 14.31818 mhz - period 67 - 70 ns high time 20 - - ns 49-32 notes: 1. clk14 edge rates in a system as measured from 0.8 v to 2.0 v. clock vt input hold time setup time vt 1.5v pciclk serirq
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1877 intel ? ep80579 integrated processor 49.5.12 real time clock (rtc) this section describes the electrical characteristics of the real time clock interface. 49.5.12.1 rtc signal list for real time clock pin description refer to table 48-10, ?real time clock interface signals? on page 1744 . 49.5.12.2 rtc dc characteristics table 49-62. rtc dc input characteristics (rtest#) low time 20 - - ns 49-32 rising edge rate 1.0 - 4.0 v/ns 49-32 1 falling edge rate 1.0 - 4.0 v/ns 49-32 1 figure 49-32. iich clock (clk14) timing diagram table 49-61. iich clock (clk14) ac specifications (sheet 2 of 2) parameters min typical max units figure note notes: 1. clk14 edge rates in a system as measured from 0.8 v to 2.0 v. 2.0v 0.8v period high time low time fall time rise time symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v - v il input voltage low - - - 0.8 v - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1878 order number: 320066-003us table 49-63. rtc dc clock input characteristics (rtcx[2:1]) 49.5.12.3 rtc ac characteristics symbol parameter min typical max units v il input voltage low - - 0.10 v v ih input voltage high 0.40 - 1.2 v c l rtcx1 typical value 6 pf c l rtcx2 typical value 6 pf notes: 1. 3.3 v clock input 2. guaranteed by design. table 49-64. rtc clock input (rtcx[2:1])timing values symbol parameter min nominal max units notes rtcx[2:1] rtc clock frequency 32.768 khz 1 , 2 to l e r a n c e this parameter specifies the crystal tolerance for rtcx[2:1] -20 - +20 ppm notes: 1. rtcx[1] can be connected to a crystal along with rtcx[2] or to an oscillator 2. when using an oscillator only rtcx[1] is connected and rtcx[2] can remain unconnected. table 49-65. rtc clock output (susclk) timings parameters min typical max units figure note operating frequency - 32.768 - khz - 1 duty cycle 30 - 70 % high time 10 - - us 49-33 low time 10 - - us 49-33 notes: 1. susclk is the rtc generator output figure 49-33.rtc clock output (susclk) timing diagram 2.0v 0.8v period high time low time fall time rise time
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1879 intel ? ep80579 integrated processor 49.5.13 gigabit ethernet (gbe : rmii, rgmii, mdio, eeprom) the ep80579 contains three gigabit ethernet macs. the gbe ethernet macs contained in the ep80579 resemble the intel ? 82545 gigabit ethernet controller. the ep80579 gigabit ethernet (gbe) mac is based on a fourth generation gigabit mac to provide a standard ieee 802.3 ethernet interface for 1000base-t, 100base-tx, and 10base-t applications. the mac is capable of transmitting and receiving data rates of 10/100/1000 mbps. through the gbe interfaces, the ep80579 can be connected to reduced ethernet (rmii), or reduced gmii (rgmii) external phy devices. the ep80579 can support both 3.3v and 2.5v phy for the gbe interface. the media outputs use 2.5v drivers that are 3.3v tolerant. this is a violation of the rmii specification, which calls for ttl level outputs (not lvttl) and 5v input level tolerance. all major phy devices that may be used in an ep80579 system are expected to drive a maximum voltage of 3.3v. rgmii version 1.3 is specified as a 2.5v cmos level i/o interface and as such, the ep80579 is fully compliant. rgmii version 2.0 is specified as a 1.5 v hstl i/o interface and the ep80579 is not compliant with this standard. all phy devices that are used with the ep80579 must support version 1.3. the mdio, mdc, and serial eeprom bus are implemented with 2.5v i/o drivers. management data input/output (mdio) interface provides a path to transfer control information and status between the phy and the ep80579. the mdio interface allows the software to continuously poll the phy?s configuration registers through and reprogram the gbe configuration. management data clock (mdc) is sourced by the ep80579 to the phy devices as a timing reference for the mdio interface. a single four-wire microwire* interface is provided for connection of an optional, externally connected serial eeprom. the serial eeprom may be used to provide configuration information to the gbe macs upon power-up or reset. all three macs share the same eeprom. this section describes the electrical characteristics of the gbe interface. 49.5.13.1 gigabit ethernet signal list for gigabit ethernet mac pin description refer to table 48-22, ?gigabit ethernet interface signals? on page 1760 . 49.5.13.2 gigabit ethernet dc characteristics 49.5.13.2.1 dc characteristics: rm ii and rgmii mode of operation table 49-66. dc input characteristics: rmii mode of operation (sheet 1 of 2) symbol parameter conditions min typical max units notes v ih input high voltage v ih > v ih _min v cc = min 2.0 - 3.6 v - v il input low voltage v ih > v il _max v cc = min --0.8 v - i ih input high current v cc = max v in = 2.5 v --15 ua -
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1880 order number: 320066-003us table 49-67. dc output characteristics: rmii mode of operation table 49-68. dc input characteristics: rgmii mode of operation table 49-69. dc output characteristics: rgmii mode of operation i il input low current v cc = max v in = 0.4 v -15 - - ua - c in input pin cap --8 pf 1 notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. symbol parameter conditions min typical max units notes v oh output high voltage v cc = 2.5v i oh = -1ma 2.4 - see notes v 1 , note 2 v oh output high voltage v cc = 2.375v i oh = -1ma 2.2 - see notes v 1 , note 2 v ol output low voltage v cc = min i ol = 1ma --0.4v notes: 1. the rmii buffer is powered from the 2.5v power rail - the output signal level is 100mv below the rail for rmii. in the ideal case, the voh equals the 2.4v in accordance to the rmii specification. if the 2.5v power rail drops below the ideal value the buffer will violate the rmii specification and the 0.4v margin between voh/vih will be reduced under this condition. 2. v oh max = vcc25 for gbe ports 1 and 2 or vccsus25 for gbe port 0 symbol parameter conditions min typical max units notes v ih input high voltage v ih > v ih _min v cc = min 1.7 - 3.6 v - v il input low voltage v ih > v il _max v cc = min --0.7 v - i ih input high current v cc = max v in = 2.5 v --15 ua - i il input low current v cc = max v in = 0.4 v -15 - - ua - c in input pin cap - - 8 pf note 1 notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. symbol parameter conditions min typical max units notes v oh output high voltage v cc = 2.5v i oh = -1ma 2.4 - see notes v 1 v ol output low voltage v cc = min i ol = 1ma -- 0.4 v notes: 1. v oh max = vcc25 for gbe ports 1 and 2 or vccsus25 for gbe port 0 table 49-66. dc input characteristics: rmii mode of operation (sheet 2 of 2) symbol parameter conditions min typical max units notes
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1881 intel ? ep80579 integrated processor table 49-70. dc input characterist ics: mdio mode of operation table 49-71. dc output characteristics: mdio mode of operation 49.5.13.2.2 dc characteristics: eeprom interface symbol parameter conditions min typical max units notes v ih input high voltage v ih > v ih _min v cc = min 2.0 - 3.6 v - v il input low voltage v ih > v il _max v cc = min --0.8 v - i ih input high current v cc = max v in = 2.5 v --15 ua - i il input low current v cc = max v in = 0.4 v -15 - - ua - leak input leakage current 0 v ih _min v cc = min 1.7 - 3.6 v - v il input low voltage v ih > v il _max v cc = min -- 0.7 v - c in input pin cap - - 8 pf 1 notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1882 order number: 320066-003us table 49-73. dc output charac teristics: eeprom interface 49.5.13.2.3 gbe dc clock specifications table 49-74. reference clock dc input specification: (gbe_refclk_rmii, gbe_refclk) 49.5.13.3 gigabit ethernet ac characteristics 49.5.13.3.1 frequency requirements ta b l e 4 9 - 7 5 provides the frequency of all input clocks in a different mode of operation. 49.5.13.3.2 gbe ethernet interface ? rgmii mode this section describes the gbe ethernet reference clock transmit and receive timings when operating in rgmii mode. rgmii works in source synchronous mode, where transmission and receive are done with respect to txclk and rxclk. in rgmii mode, txclk and rxclk run at 2.5/25/125mhz. in 2.5/25mhz mode, both transmit and receive occurs on rising edges of the clock. at 125mhz, data transfer (both tx and rx) occurs on both edges of the clock (same as ddr2). the rgmii interface gets rx clock from the phy and tx clock from the mac. both mac and phy receive a 125mhz reference clock from the board. the rgmii outputs uses 2.5v drivers that are 3.3v tolerant. figure 49-34 shows the gbe block diagram with the signal connections in rgmii mode. symbol parameter conditions min typical max units v oh output high voltage v cc = 2.5v i oh = -1ma 2.4 - =vccsus25 v v ol output low voltage v cc = min i ol = 1ma -- 0.4 v symbol parameter conditions min typical max units notes v ih input high voltage v ih > v ih _min v cc = min 1.7 - 3.6 v - v il input low voltage v ih > v il _max v cc = min --0.7 v - i ih input high current v cc = max v in = 2.5 v --15 ua - i il input low current v cc = max v in = 0.4 v -15 - - ua - c in input pin cap - - 8 pf note 1 notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. table 49-75. frequencies of all input clocks model clock name frequency rmii gbe_refclk_rmii 50 mhz rgmii gben_rxclk 2.5/25/125 mhz gben_txclk 2.5/25/125 mhz gbe_refclk 125 mhz
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1883 intel ? ep80579 integrated processor 49.5.13.3.3 gbe ethernet interface ? rgmii mode reference clock table 49-76 shows the rgmii 125 mhz reference clock ac specifications. figure 49-35 shows the rgmii 125 mhz reference clock timing diagram. figure 49-34.gbe rgmii mode signal connection block diagram b6573-01 gben_txclk gben mac 1000/100/10 base phy rgmii signals 125 mhz source clock vcc 2.5v 5% gbe i/o vcc 125/25/2.5 mhz 125/25/2.5 mhz gben_txctl gben_txdata[3:0] gtx_clk tx_en txd[3:0] gbe i/o vcc rx_clk rx_dv rxd[3:0] 125 mhz ref clk gben_rxclk gben_rxctl gben_rxdata[3:0] gbe_refclk table 49-76. gbe rgmii reference clock timing values symbol parameter min nominal max units notes t 1 rgmii reference clock period - 8.0 - ns 1 frequency accuracy -50 - +50 ppm 1 t 2 duty cycle with respect to t 1 (nom.) 45 50 55 % 1 , 5 t 3 low to high rise time (20% to 80%) - - 0.75 ns 2 , 5 t 4 high to low fall time (80% to 20%) - - 0.75 ns 3 , 5 t jitter cycle to cycle jitter - - 80 ps 4 , 5 peak to peak jitter (aggregate) - - 150 ps 4 , 5 notes: 1. applies to gben_refclk signal operating in rgmii mode. 2. measurement points for rise time are 20% gbe v cc to 80% gbe v cc . 3. measurement points for fall time are 80% gbe v cc to 20% gbe v cc . 4. the maximum allowable jitter is 80 ps. this jitter can be less but never greater than 80 ps. this reference clock jitter directly translates into the jitter produced on the gben_txclk signal. for example, a 40 ps jitter on the reference clock input would generate the same 40 ps jitter on the gben_txclk signal. 5. guaranteed by design. these values are typical values seen for this process, but not measured during production testing.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1884 order number: 320066-003us 49.5.13.3.4 gbe ethernet interface ? rgmii mode transmit timings ta b l e 4 9 - 7 6 shows the ac specifications. figure 49-35.rgmii 125 mhz reference clock timing diagram b6574-01 t 1 t 2 t 2 t 3 t 4 v cc(80%) v cc(20%) gbe_refclk table 49-77. gbe transmit timing values ? rgmii mode symbol parameter min nominal max units notes t 1 rgmii output clock period (1000 base) 7.2 8.0 8.8 ns 1 , 7 t 1 rgmii output clock period (100 base) 36 40 44 ns 1 , 7 t 1 rgmii output clock period (10 base) 360 400 440 ns 1 , 7 t 2 1000 base duty cycle with respect to t 1 (nom.) 45 50 55 % 1, 3, 7 t 2 100/10 base duty cycle with respect to t 1 (nom.) 40 50 60 % 1, 3, 7 t 3 low to high rise time (20% to 80%) - - 0.75 ns 1, 4, 7 t 4 high to low fall time (80% to 20%) - - 0.75 ns 1 , 5 , 7 t 5 data to clock output skew (at transmitter) -500 0 500 ps 2 , 7 t 6 data to clock output skew (at receiver) 1 - 2.6 ns 6 , 7 notes: 1. this applies to the gben_txclk signal operating in rgmii mode. 2. this applies to the gben_txdata[3:0] signals for rgmii mode. 3. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. 4. measurement points for rise time are 20% gbe v cc to 80% gbe v cc . 5. measurement points for fall time are 80% gbe v cc to 20% gbe v cc . 6. the rgmii specification v1.3 requires the board design to induce trace delay such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the gben_txclk signal between the mac output and the phy input. this method would require ?x-inches? of trace to routed for the gben_txclk signal. some phys solve this by supporting an internal delay within the phy. refer to your chosen phy data sheet for additional information on these clock delay modes. 7. guaranteed by design. these values are typical values seen for this process, but not measured during production testing.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1885 intel ? ep80579 integrated processor figure 49-36 shows the rgmii transmit timing diagram. figure 49-36.gbe transmit waveform ? rgmii mode gben_txclk ( at transmitter ) t 2 t 1 t 2 t 3 t 4 gben_txdata [3:0] gben_txctl txdata[3:0] txctl gben_txclk ( at receiver ) t 3 / t 4 t 5 t 6 v cc( 80%) v cc (20%) txdata [7:4]
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1886 order number: 320066-003us 49.5.13.3.5 gbe ethernet interface ? rgmii mode receive timings ta b l e 4 9 - 7 8 shows the ac specification. figure 49-37 shows the rgmii receive timing diagram. 49.5.13.3.6 design to test loads the i/os are implemented to support a 5pf load to ground for ac timing. table 49-78. gbe receive timing values ? rgmii mode symbol parameter min nominal max units notes t 1 rgmii input clock period (1000 base) 7.2 8.0 8.8 ns 1 , 6 t 1 rgmii input clock period (100 base) 36 40 44 ns 1 , 6 t 1 rgmii input clock period (10 base) 360 400 440 ns 1 , 6 t 2 1000 base duty cycle with respect to t 1 (nom.) 45 50 55 % 1 , 3, 6 t 2 100/10 base duty cycle with respect to t 1 (nom.) 40 50 60 % 1 , 3, 4, 6 t 3 low to high rise time (20% to 80%) - - 1.0 ns 1 , 5, 6 t 4 high to low fall time (80% to 20%) - - 1.0 ns 1 , 5, 6 t 5 data to clock output skew (at transmitter) -500 0 500 ps 1 , 3, 6 t 6 data to clock output skew (at receiver) 1 - 2.6 ns 6 notes: 1. this applies to the gben_rxclk signal operating in rgmii mode. 2. this applies to the gben_rxdata[3:0] signals for rgmii mode. 3. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. 4. measurement points for rise time are 20% gbe v cc to 80% gbe v cc . 5. measurement points for fall time are 80% gbe v cc to 20% gbe v cc . 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. figure 49-37.gbe receive waveform ? rgmii mode b6575-01 t 2 t 1 t 2 t 3 t 4 gben_rxdata[3:0] gben_rxdata[8] rxdata[3:0] rxdata[7:4] rxdv t 3 / t 4 t 5 t 6 v cc( 80%) v cc (20%) gben_rxclk[0] (at receiver) gben_rxclk[0] (at transmitter)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1887 intel ? ep80579 integrated processor 49.5.13.3.7 gbe ethernet interface ? rmii mode this section describes the ac timings for gbe interface when the interconnect is designed for a rmii interface. in rmii mode of operation, both transmit and receive (tx_data and rx_data) are with respect to external clock, which in 10/100 base t is 50 mhz. figure 49-38 shows the gbe signal connections used in rmii mode for 10/100 base connections. an external clock is sourcing the reference clock. figure 49-39 shows the timing diagram for rmii mode of operation. table 49-79 shows the transmit and receive timing values for rmii 100/10 base mode of operation. figure 49-38.gbe rmii mode signal connection block diagram ? external clock source b6576-01 gben_ txctl gben mac 10/100 base phy rmii signals 50 mhz source clock vcc 2.5v 5% gbe i/o vcc gben_ txdata[3] gben_ txdata[1:0] tx_en tx_er txd[1:0] gbe i/o vcc crs_dv rx_er rxd[1:0] ref_clk gben_rxctl gben_rxdata[3] gben_rxdata[1:0] gbe_refclk_rmii figure 49-39.gbe rmii transmit and receive waveforms ? rmii mode b6577-01 20ns t su gben_rxdata[3:0] gben_rxctl data data t hold gbe_refclk_rmii
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1888 order number: 320066-003us 49.5.13.3.8 mdio timing specification this section describes the ac timing for the mdio interface. table 49-79. gbe transmit and receive timing values ? rmii 100/10 base mode symbol parameter min typical max units notes ref_clk frequency - 50 - mhz ref_clk duty cycle 35 65 % 1 ref_clk jitter - - 80 ps tsu txd[1:0], tx_en,rxd[1:0], crs_dv, rx_er data setup to ref_clk rising edge 4ns thold txd[1:0], tx_en,rxd[1:0], crs_dv, rx_er data hold from ref_clk rising edge 2ns notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. figure 49-40.mdio output timing diagram (ep80579 is sourcing mdio) figure 49-41.mdio input timing diagram (phy is sourcing mdio) b6599-01 mdc mdio t 1 t 2 b6551-01 mdc mdio t 5 t 3 t 4
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1889 intel ? ep80579 integrated processor 49.5.13.3.9 eeprom timing specification this section describes the ac timing for the eeprom interface. figure 49-42 shows a typical eeprom read operation generated by the ep80579. table 49-80. mdio timings values symbol parameter min max units figure notes t 1 mdio, clock to output timing with respect to rising edge of mdc clock mdc/2 + 10 ns ns 49-40 - t 2 mdio output hold timing after the rising edge of mdc clock 10 ns 49-40 - t 3 mdio input setup prior to rising edge of mdc clock 10 ns 49-41 - t 4 mdio input hold time after the rising edge of mdc clock 0- ns 49-41 - t5 mdc clock period - 500 ns 49-41 1 notes: 1. the mdc clock period is 641 ns in sku 2 and 8 figure 49-42.eeprom interface timing diagram table 49-81. eeprom read operation (sheet 1 of 2) step parameter 1 the ep80579 activates the eeprom by asserting eecs. 2 after the chip select, the ep80579 starts driving data. it drives a 1 for the start bit, then a 10 (binary) for the read opcode. 3 the ep80579 starts driving the clock after driving the initial start bit. the eeprom device latches a bit on every rising edge of the clock. the output data is driven near the falling edge of the clock to maximize setup and hold times. likewise the read data is sampled near the falling edge of the clock. 4 after driving the start bit and read opcode ep 80579 drives the address, starting at the most significant bit. a 256-word eeprom requires 8 ad dress bits (as shown in the diagram), while a 64- word eeprom requires only 6 address bits. b6591-01 eecs eesk a7 a6 a5 a4 110 a3 a2 a1 a1 eedi d15 d14 d1 d 0 eedo 7 6 5 4 2 3 1 tcs tck tsu th start read opcode=10 tcsl
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1890 order number: 320066-003us 49.5.13.4 gbe reset conditions there is no special reset sequence required for gbe i/o buffers. gbe receives a power- on reset signal from the cru, but drives in put data present on the input pins into the core during reset. core logic forces all outputs to high-z during reset. 49.5.13.5 rcomp the gbe rcomp (resistive compensation) circuitry dynamically compensates the gbe i/o output drivers for variations in operating conditions due to process, temperature, voltage and pcb layout. these variations are measured through a resistive mechanism in two special i/o pads. the resistive mechanism on those i/o pads reference external resistors that the user provides to match output driver strength. thus the output driver impedance can be tuned specifically to the application pcb characteristics for nominal signal transfer into the transmission lines formed by the pcb traces. the rcomp design is nominally set to operate at 50 ohm, but the user is free to set the impedance in the range 45 ohm to 55 ohm. two rcomp pins are provided to establish the gbe output driver impedance, one to control the drive high strength, and one to control the drive low strength. these rcomp outputs drive into external resistors. the drivers form a resistor divider and the voltages developed in these dividers are co mpared to a reference voltage. the rcomp state machine independently adjusts the strength of the drivers making them stronger or weaker until the comparator signals that the voltage is greater than or less than the reference. the state machine continues making adjustments causing the comparators to oscillate between two strength settings just above and just below the comparator trip point. logic in the rcomp state machine recognizes when this "dithering" between the two values has begun, and holds the strength output for the gbe outputs fixed at one of the two settings. note this algorithm is independently and concurrently applied to the drive high strength and to the drive low strength. 5 an internal pullup is implemented on the eedo pin so the pin initially floats high. when the eeprom latches its last address bit it drives eedo low. this can be used during the initial read to determine the size of the eeprom. a 64-word eeprom drives "data out" low after 6 address bits, while a 256- word eeprom drives "data out" low after 8 address bits. 6 after driving its "data out" low, the eeprom device drives 16 data bits, starting at the most significant bit. each bit is driven after the rising edge of the clock. 7 after the read cycle, the ep80579 stops driving the cl ock and deasserts the chip select. when the chip select is deasserted the eeprom stops driving the data. table 49-82. eeprom timing values symbol parameter min max units figure notes tcs chip select to first clock edge. 1024 3048 ns 49-42 1 tck eeprom clock cycle 1024 4160 ns 49-42 1 tsu setup time before rising clock edge. 480 - ns 49-42 1 th hold time after rising clock edge. 480 - ns 49-42 1 tcsl chip select deassertion time 992 - ns 49-42 1 notes: 1. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. table 49-81. eeprom read operation (sheet 2 of 2) step parameter
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1891 intel ? ep80579 integrated processor the gbe rcomp controller starts operation when the gbe_aux_pwr_good input is asserted. this condition indicates the power supplies are stable; the condition also indicates that the gbe_refclk input is being driven with a 125mhz clock. the gbe_refclk input is divided by either 4 or 16 and then used to drive the rcomp state machine. software accessible registers that provide options to monitor/overwrite internal bias and comparator output are also present. 49.5.13.6 voltage domains the gbe ports and associated miscellaneous i/os (mdio, ee, refclk, pme_wake, and rcomp) are powered with 2.5v power supp ly. a secondary low current 3.3v power supply is also required to allow 3.3v input level tolerance. the gbe io interface supports ?wake-on-lan? operation and therefore some of the i/o signals are powered with sustain power supplies that are always powered on while other i/o signals are powered with ?core? power supplies that are only active when the remainder of the chip is powered on. gbe port 0 and the miscellaneous mdio, ee, refclk, pme_wake, and rcmp ios are powered through the sustain power supply vccsus25, and the 3.3v vccgbepsus for 3.3v input tolerance. gbe ports 1 and 2 are powered with the vcc25 power supply and the vccgbe33 is connected for 3.3v input level tolerance. the user may consider connecting vccgbepsus power supply pins to the vccpsus power supply and connecting vccgbe33 to the vcc33 power supply on the pcb in order to reduce the number of regulators used in the system. vcc25 and vccsus25 are only used in the gbe io interface section of the chip. 49.5.14 time division multiplex (tdm) this section describes the electrical characteristics of the tdm interface. 49.5.14.1 tdm signal list for tdm pin descriptions, refer to table 48-23, ?tdm interface signals,? on page 1764 . 49.5.14.2 tdm dc characteristics table 49-83. tdm dc input characteristics symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1892 order number: 320066-003us table 49-84. tdm dc output characteristics 49.5.14.3 tdm dc clock specification table 49-85. tdm dc clock input specifications (rx_clkn) symbol parameter conditions min typical max units notes v oh output voltage high l out =-6ma 2.0 - - v 1 v ol output voltage low l out =6ma - - 0.4 v - oh output current at high voltage v oh =2.4 -12 -27 -48 ma - ol output current at low voltage v ol =0.8 12 18 26 ma - notes: 1. voh spec does not apply to signals that are open drain driver. open drain signals must have an external pull up resistor. symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1893 intel ? ep80579 integrated processor 49.5.14.4 tdm ac characteristics 49.5.14.4.1 transmit and receive timings table 49-87. tdm, serial timings values symbol parameter min max units notes t 1 setup time of tx_frame, rx_frame, and rx_data_in prior to the rising edge of clock 5ns 1 , 2 , 3 t 2 hold time of tx_frame, rx_frame, and rx_data_in after the rising edge of clock 0ns 1 , 2 , 3 t 3 setup time of tx_frame, rx_frame, and rx_data_in prior to the falling edge of clock 5ns 1 , 2 , 3 t 4 hold time of tx_frame, rx_frame, and rx_data_in after the falling edge of clock 0ns 1 , 2 , 3 t 5 rising edge of clock to output delay for tx_frame, rx_frame, and tx_data_out 15 ns 1 , 4 t 6 falling edge of clock to output delay for tx_frame, rx_frame, and tx_data_out 15 ns 1 , 3 , 4 t 7 output hold delay after rising edge of final clock for tx_frame, rx_frame, and tx_data_out 0ns 1 , 3 , 4 t 8 output hold delay after falling edge of final clock for tx_frame, rx_frame, and tx_data_out 0ns 1 , 3 , 4 t 9 tx_clk period and rx_clk period 1/ 8.192 mhz 1/ 512 khz ns 5 , 6 notes: 1. tx_clk and rx_clk may be coming from external independ ent sources or being driven by the ep80579. the signals are shown to be synchronous for illustrative purposes and are not required to be synchronous. 2. applicable to when the rx_frame and tx_frame signals are being driven by an external source as inputs into the ep80579. always applicable to rx_data_in. 3. the rx_frame and tx_frame can be configured to accept data on the rising or falling edge of the given reference clock. rx_frame and rx_data_in signals are synchronous to rx_clk and tx_frame and tx_data_out signals are synchronous to the tx_clk. 4. applicable to when the rx_frame and tx_frame signals ar e being driven by the ep80579 to an external source. always applicable to tx_data_out. 5. the tx_clk can be configured to be driven by an external source or be driven by the ep80579. the slowest clock speed that can be accepted or driven is 512 khz. the maximum clock speed that can be accepted or driven is 8.192 mhz. the clock duty cycle accepted is 50/50 + 20%. 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1894 order number: 320066-003us 49.5.14.4.2 tdm transmit and receive timing diagrams 49.5.15 local expansion bus (leb) the local expansion bus is a 16-bit 33-80mhz bus with 8 programmable chip selects. this section describes the electrical characteristics of the leb interface. 49.5.15.1 leb signal list for local expansion bus pin descriptions, refer to table 48-24, ?expansion bus signals? on page 1765 . figure 49-43.tdm, serial timings b6431-01 valid data valid data valid data valid data t2 t9 t1 t 3 t4 t6 t5 t7 t8 as outputs: (tx or rx) frame (negative edge) (tx or rx) frame (positive edge) (tx or rx) frame (positive edge) as inputs: tx_clk/rx_clk (tx or rx) frame (negative edge) rx_data (positive edge) tx_data (negative edge) rx_data (negative edge) tx_data (positive edge)
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1895 intel ? ep80579 integrated processor 49.5.15.2 leb dc characteristics table 49-88. leb dc input characteristics table 49-89. leb dc output characteristics 49.5.15.2.1 leb dc clock specification table 49-90. leb dc clock input specifications (external clock) symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1896 order number: 320066-003us 49.5.15.3 leb ac characteristics 49.5.15.3.1 local expansion bus synchronous operation figure 49-44.local expansion bus synchronous timing table 49-91. local expansion bus synchronous operation timing values symbol parameter 33 mhz 66 mhz 80 mhz units notes min max min max min max t 1 valid rising edge of ex_clk to valid signal on the output. 8.5 8.0 7.5 ns 1 t 2 valid signal hold time after the rising edge of ex_clk 111ns 1, 4 t 3 valid data signal on an input prior to the rising edge of ex_clk 2.5 2.5 2.5 ns 1 t 4 required hold time of a data input after the rising edge of ex_clk 0.5 0.5 0.5 ns 1, 4 t 5 valid control signal on an input prior to the rising edge of ex_clk 3.5 3.5 3.5 ns 1 t 6 required hold time of a control input after the rising edge of ex_clk 0.5 0.5 0.5 ns 1 , 4 cload load capacitance 5 60 5 50 5 40 pf 4 notes: 1. drive settings do not apply to ex_cs# signals and are expected to be point to point. 2. ex_control_signals output signals consist of ex_ale, ex _addr, ex_cs#, ex_rd#, ex_wr#, ex_wait# 3. ex_control_signals input signals consist of ex_addr, ex_cs#, ex_burst, ex_rd#, ex_wr# 4. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. b6578-01 t 4 t 1 ex_data_be#, parity - output_signals ex_clk ex_control signals ? output_signals ex_data_be#, parity - input_signals ex_control signals ? input_signals t 2 t 3 t 6 t 5
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1897 intel ? ep80579 integrated processor 49.5.16 controller area network (can) the ep80579 provides a can interface that in cludes support for can 2.0b protocol, 11- bit and 29-bit identifiers, and supports bit rates up to 1 mbps. the ep80579 provides support for various external phy chips, such as the ti-sn65hvd230d transceiver. this section describes the electrical characteristics of the can interface. 49.5.16.1 can signal list for a pin description for the can interface, refer to ta bl e 4 8 - 2 1 , ? c o n t r o l l e r a r e a network bus signals? on page 1759 . 49.5.16.2 can dc characteristics table 49-92. can dc input characteristics 49.5.17 synchronous serial port (ssp) this section describes the electrical characteristics of the ssp interface. 49.5.17.1 ssp signal list for a pin description for the ssp interface, refer to table 48-25, ?ssp interface signals? on page 1768 . symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1898 order number: 320066-003us 49.5.17.2 ssp dc characteristics this section describes the dc characteristics of the ssp interface. table 49-94. ssp dc input characteristics 49.5.17.2.1 ssp dc output characteristics table 49-95. ssp dc output characteristics table 49-96. ssp dc clock specification symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - v - v il input voltage low - - - 0.8 v - ol output current at low voltage v ol <0.8 - - 4 ma - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1899 intel ? ep80579 integrated processor 49.5.17.2.2 ssp block diagram figure 49-45 shows the ssp signal connections used when connecting to multiple analog-to-digital convertors, with a multi-bus connection, and using an external clock generation mode. figure 49-45.ssp signal connection block diagram - multi-drop connections b6589-01 gpio[21] ssp & gpio interface adc/dac 1 ssp signals 3.6864 mhz external clock vcc33 3.3v 5% vcc33 vcc33 txd rxd frame ssp_txd ssp_rxd ssp_sfrm gpio[13] device_en clk adc/dac 0 vcc33 clk txd rxd frame device_en ssp_sclk ssp_extclk ssp_extclk provides the clock to the logic as well as the ssp_sclk pin. ssp_sclk can operate at a maximum of ssp_extclk/2 mhz in this configuration.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1900 order number: 320066-003us 49.5.17.3 ssp ac characteristics table 49-97. ssp timing values and test conditions symbol parameter min nominal max units notes ssp_sclk clock period of ssp_sclk when the clock is being generated from the internally generated 3.6864 mhz clock - 271 - ns 1 , 3 , 4 - ssp_sclk clock period that can be produced when the clock is being generated from the external 3.6864 mhz clock via ssp_extclk 542 - - ns 1 , 3 ssp_extclk clock period when the clock is being generated from the externally supplied maximum clock rate of 3.6864 mhz clock 271 - - ns 1 , 3 t 1 output valid delay from ssp_extclk to ssp_sclk in external clock mode 2-15ns 1 , 3 t 2 input setup time for data prior to the valid edge of ssp_sclk. these signals include ssp_rxd. 15 - - ns 1 , 5 t 3 input hold time for data after the valid edge of ssp_sclk. these signals include ssp_srxd. 0- -ns 1 , 3 , 5 t 4 ssp_sclk clock to output valid delay from output signals. these signals include ssp_txd and ssp_sfrm. --6ns 1 , 2 , 3 , 5 t 5 output data hold valid from valid edge of ssp_sclk. these signals include ssp_txd and ssp_sfrm. 1- -ns 1 , 2 , 3 , 5 notes: 1. timing was designed for a system load between 5pf and 40pf 2. clock jitter on the ssp_sclk is designed to be an average of the specified clock frequency. the sspsclk jitter specification is unspecified. 3. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. 4. for low-power sku configured for internal mode the ssp_sclk is 360 ns from an internal generated 2.777 mhz clock. 5. for reference purposes, the timing diagram shows a positive clock edge launch and a positive clock edge capture, however, depending on the frame format selected, each transmitted bit is driven on either the rising or falling edge of ssp_sclk, and is sampled on the opposite clock edge. figure 49-46.ssp interface timing diagram b6590-02 ssp_extclk ssp_sclk ssp_rxd ssp_txd ssp_sfrm t 4 t 5 t 2 t 3 t 1
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1901 intel ? ep80579 integrated processor 49.5.18 ieee 1588-2008 hardware assist interface this section describes the electrical characteristics of the ieee 1588-2008 hardware assist interface. 49.5.18.1 ieee 1588-2008 hardware assist signal list for a pin description for the ieee 1588-2008 hardware assist interface, refer to table 48-26, ?ieee 1588-2008 hardware assist interface signals? on page 1768 . 49.5.18.2 ieee 1588-2008 hardware assist dc characteristics table 49-98. ieee 1588-2008 hardware assist dc input characteristics table 49-99. ieee 1588-2008 hardware assist dc output characteristics 49.5.18.3 ieee 1588-2008 hardware assist ac characteristics the ieee 1588-2008 hardware assist interface is an edge-dependent interface and has no critical ac timing requirements. 49.5.19 iich miscellaneous signals (pme#, pcirst#, spkr) this section describes the electrical characteristics of the iich miscellaneous signals. 49.5.19.1 iich miscellaneous signal list for a pin description for the iich miscellaneous signals, refer to table 48-28, ?miscellaneous signals? on page 1770 . symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v - v il input voltage low - - - 0.8 v - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1902 order number: 320066-003us 49.5.19.2 iich miscellaneous signals dc characteristics table 49-100.iich miscellaneous signals dc input characteristics table 49-101.iich miscellaneous signals dc output characteristics 49.5.19.3 iich miscellaneous signals ac characteristics the ac electrical specifications of the ep80579 iich miscellaneous signals are compliant with the pci local bus specification , rev. 3.0 (refer to ac specifications for 3.3v signaling for more information). 49.5.20 clock resource unit (cru) the cru unit is responsible for generating and distributing the clocks to the various functional units within the soc. this section describes the electrical characteristics of the global clock signals. 49.5.20.1 cru signal list for a pin description for the cru signals, refer to table 48-5, ?global clock and reset (cru) signals? on page 1736 . symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v - v il input voltage low - - - 0.8 v - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1903 intel ? ep80579 integrated processor 49.5.20.2 cru dc characteristics table 49-102.cru differential clock dc specifications symbol parameter min typical max units figure notes v il input low voltage -0.150 0.00 0.150 v 49-47 1 v ih input high voltage 0.660 0.710 0.850 v 49-47 1 v cross(abs ) absolute crossing point 0.250 n/a 0.550 v 49-47 , 49-48 1, 2, 3, 6, 9 v cross(rel) relative crossing point 0.250+0.5(v havg-0.71) n/a 0.550+0.5(v havg-0.71) v 49-47 , 49-48 1, 2, 3, 6, 7, 9 v cross range of crossing point n/a n/a 0.140 v 49-47 , 49-48 1, 2, 8, 9 v rbm ringback margin 0.200 n/a n/a v 49-47 1, 4, 9 v tm threshold margin v cross -0.10 n/a v cross +0.10 v 49-47 1, 5, 9 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. crossing voltage is defined as the instantaneous voltage va lue when the rising edge of clkp100 equals the falling edge of clkn100. 3. vhavg is the statistical average of the vh measured by the oscilloscope. 4. ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum falling edge ringback. 5. threshold region is defined as a region entered around the crossing point voltage in which the differential receiver switches. it includes input threshold hysteresis. 6. the crossing point must meet the absolute and relative crossing point specifications simultaneously. 7. vhavg can be measured directly using "vtop" on agilent* scopes and "high" on tektronix* scopes. 8. v cross is defined as the total variation of all crossing voltages as defined in note 2. 9. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. figure 49-47.cru differential clock waveform overshoot vh vl undershoot rising edge ringback falling edge ringback ringback margin crossing voltage crossing voltage b4965-01 tp tpl tph clkn100 clkp100 tp = t1: clk100 period t2: clk100 period stability (not shown) tph = t3: clk100 pulse high time tpl = t4: clk100 pulse low time threshold region
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1904 order number: 320066-003us 49.5.20.3 cru ac specifications figure 49-48.cru differential clock cross-point specification b6569-01 650 600 550 500 200 660 670 680 850 vhavg (mv) crossing point (mv) 250 mv 250 + 0.5 (vhavg ? 710) 550 mv 550 + 0.5 (vhavg ? 710) 690 700 840 830 820 810 800 790 780 770 760 750 740 730 720 710 450 400 350 250 300 table 49-103.cru differential input clock timing specifications (sheet 1 of 2) symbol parameter min nom max unit figures notes clkn100/clkp100 (100mhz fsb clock) - clk100 frequency - 100 mhz - - -duty cycle45-55%-- t1 clk100 period 9.997 - 10.20 ns 49-47 1, 6 t2 clk100 period stability n/a - 200.00 ps - 2, 6 - frequency tolerance - - 350 ppm - - - clock jitter - 50 150 ps - - t3 t ph clk100 pulse high time 3.94 5.00 6.12 ns 49-47 4, 6 t4 t pl clk100 pulse low time 3.94 5.00 6.12 ns 49-47 4, 6 t5 clk100 rise time 175 - 700 ps 49-47 3, 5, 6 t6 clk100 fall time 175 - 700 ps 49-47 3, 5, 6 notes: 1. the period specified here is the average period. a given period may vary from this specification as governed by the period stability specification (t2). 2. in this context, period stability is defined as the worst case timing difference between successive crossover voltages. in other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 3. slew rate is measured between the 35% and 65% points of the clock swing (vl to vh). 4. combining the longest clock-high and clock-low times would violate the max clock period, and that combining the shortest clock-high and clock-low times would violate the minimum clock period. the clock-high and clock-low times specify the most extreme allowable combination of clock period and duty cycle. 5. slew rate specifications apply to both rising and falling edges. 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1905 intel ? ep80579 integrated processor 49.5.21 sideband miscellaneous signals this section describes the electrical characteristics of the sideband miscellaneous signals. 49.5.21.1 sideband miscellaneous signals signal list for a pin description for these sideband signals, refer to table 48-6, ?sideband miscellaneous signals? on page 1737 . 49.5.21.2 sideband miscellaneous signals dc characteristics table 49-104.sideband miscellaneous signals dc input characteristics clkn100/clkp100 (133mhz fsb clock) - clk100 frequency - 133 mhz - - -duty cycle45-55%- 6 t1 clk100 period 7.497 - 7.65 ns 49-47 1, 6 t2 clk100 period stability n/a - 200 ps 2, 6 - frequency tolerance - - 350 ppm - - - clock jitter - 50 150 ps - - t3 t ph clk100 pulse high time 3.375 3.75 4.2075 ns 49-47 4, 6 t4 t pl clk100 pulse low time 3.375 3.75 4.2075 ns 49-47 4, 6 t5 clk100 rise time 175 700 ps 49-47 3, 5, 6 t6 clk100 fall time 175 700 ps 49-47 3, 5, 6 table 49-103.cru differential input clock timing specifications (sheet 2 of 2) symbol parameter min nom max unit figures notes notes: 1. the period specified here is the average period. a given period may vary from this specification as governed by the period stability specification (t2). 2. in this context, period stability is defined as the worst case timing difference between successive crossover voltages. in other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 3. slew rate is measured between the 35% and 65% points of the clock swing (vl to vh). 4. combining the longest clock-high and clock-low times would violate the max clock period, and that combining the shortest clock-high and clock-low times would violate the minimum clock period. the clock-high and clock-low times specify the most extreme allowable combination of clock period and duty cycle. 5. slew rate specifications apply to both rising and falling edges. 6. guaranteed by design. these values are typical values seen for this process, but not measured during production testing. symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v - v il input voltage low - - - 0.8 v - leak input leakage current 0 intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1906 order number: 320066-003us table 49-105.sideband miscellaneous signals dc output characteristics 49.5.21.3 sideband miscellaneous signals ac characteristics refer to figure 6-6, ?powergood reset sequence? on page 172 and figure 6-7, ?hard reset sequence? on page 173 for sideband miscellaneous signal timing details. 49.5.22 imch reset this section describes the electrical characteristics of the imch reset signals. 49.5.22.1 imch reset signal list for a pin description for the imch reset signals, refer to table 48-7, ?imch reset signals? on page 1739 . 49.5.22.2 imch reset signals dc characteristics table 49-106.imch reset signals dc input characteristics 49.5.22.3 imch reset signals ac characteristics refer to figure 6-6, ?powergood reset sequence? on page 172 and figure 6-7, ?hard reset sequence? on page 173 for imch reset signal timing details. symbol parameter conditions min typical max units notes v oh output voltage high l out =-0.5ma 0.9vcc33 - - v 1 v ol output voltage low l out =1.5ma - - 0.1vcc33 v oh output current at high voltage v oh >0.9vcc33 -0.5 - - ma ol output current at low voltage v ol <0.1vcc33 - - 1.5 ma notes: 1. voh spec does not apply to signals that are open drain driver. open drain signals must have an external pull up resistor. symbol parameter conditions min typical max units notes v ih input voltage high - 2.0 - - v - v il input voltage low - - - 0.8 v - leak input leakage current 0 august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1907 intel ? ep80579 integrated processor 49.5.23 jtag this section describes the electrical characteristics of the jtag interface. 49.5.23.1 jtag signal list for a pin description for the jtag signals, refer to table 48-27, ?jtag interface signals? on page 1769 . 49.5.23.2 jtag dc characteristics table 49-108.jtag dc output specifications (bpm4_prdy_out) 49.5.23.3 jtag ac characteristics table 49-107.jtag dc specifications (except bpm4_prdy_out) symbol parameter conditions min typical max units notes v ih tms, tdi, trst# input-high voltage 0.8 1.4 v 2 v il tms, tdi, trst# input-low voltage -0.5 0.4 v 2 r on tdo ron impedance 5 16 3 notes: 1. 1.2v i/o buffers 2. these values are typical values seen by the manufacturing process and are not tested 3. guaranteed by design. symbol parameter conditions min typical max units v oh output voltage high l out =-6ma 2.0 v v ol output voltage low l out =6ma 0.4 v oh output current at high voltage v oh =2.4 -12 -27 -48 ma ol output current at low voltage v ol =0.8 12 18 26 ma note: 3.3 v i/o buffers table 49-109.jtag timing specifications (sheet 1 of 2) symbol parameter conditions min max units figures notes t jtf tck frequency tck at 25 mhz and period 40ns 025mhz- t tch tck high time measured at 0.6v 7.0 ns - 1 , 5 t tcl tck low time measured at 0.6v 7.0 ns - 1 , 5 notes: 1. 1.2v i/o buffers 2. these values are typical values seen by the manufacturing process and are not tested 3. for tms, tdi and trst#. 4. tck input threshold voltage. 5. guaranteed by design.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1908 order number: 320066-003us 49.5.23.3.1 jtag timing diagrams and test conditions t tcr tck rise time 0.3v to 0.72v 5 ns - 1 , 5 t tcf tck fall time 0.72v to 0.3v 5 ns - 1 , 5 t tis1 input setup to tck- -tdi, tms 3.0 ns 49-50 3 t tih1 input hold from tck--tdi, tms 2.0 ns 49-50 3 t tov1 tdo output valid delay relative to falling edge of tck 4.25 13.25 ns 49-49 2 , 5 t of1 tdo float delay relative to falling edge of tck 4.25 13.25 ns 49-49 4 , 5 figure 49-49.jtag output timing measurement waveforms table 49-109.jtag timing specifications (sheet 2 of 2) symbol parameter conditions min max units figures notes notes: 1. 1.2v i/o buffers 2. these values are typical values seen by the manufacturing process and are not tested 3. for tms, tdi and trst#. 4. tck input threshold voltage. 5. guaranteed by design. b6432-01 clk output delay fall output delay rise output float vlest tov1 tov1 tof vtall vrise vm vt
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1909 intel ? ep80579 integrated processor figure 49-50.jtag input timing measurement waveforms b6433-01 v test v th v tl v th v tl valid v max v test v test t ih1 t is1 clk input
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1910 order number: 320066-003us
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1911 intel ? ep80579 integrated processor 50.0 thermal specifications and design considerations the ep80579 requires a thermal solution that maintains the maximum case temperature defined in table 50-1, ?ep80579 thermal design power (tdp) and maximum case temperature specifications (tc-max)? . any attempt to operate outside these operating limits may result in permanent damage to the processor and potentially other components in the system. as processor technology changes, thermal management becomes increasingly crucial when building computer systems. maintaining the proper thermal environment is key to reliable long-term system operation. a complete thermal solution includes both component-level and system- level thermal management features. refer to the intel ? ep80579 integrated processor product line thermal design guide for a thorough treatment of thermal design considerations. to allow for the optimal operation and long-term reliability of intel ? architecture-based systems, the system/processor thermal solution must be designed such that the processor remains within the minimum and maximum case temperature (t c-max ) specifications at the corresponding thermal design power (tdp) value listed in ta bl e 5 0 - 1 . thermal solutions that are not designed to provide this level of thermal capability may affect the long-term reliability of the processor and the system. the case temperature is defined at the geometric top center of the integrated heat spreader (ihs). the ep80579 monitors die temperature using athermal sensor.the thermal sensor (described in section 50.2, ?thermal sensor? ) must be used to determine when the maximum specified component temperature has been reached. the on-die thermal sensor is designed to help protect the processor in the unlikely event that an application exceeds the tdp recommendation for a sustained period of time. for more details on the usage of this feature, refer to section 50.2, ?thermal sensor? . in all cases, the thermal sensor feature must be enabled for the processor to remain within the operating limits. 50.1 thermal characteristics consult the intel ? ep80579 integrated processor product line thermal design guide for complete information about thermal characteristics. contact your local intel sales office or your distributor to obtain the latest version.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1912 order number: 320066-003us 50.1.1 specifications 50.1.2 thermal design power (tdp) dissipation the thermal design power (tdp) values in ta b l e 5 0 - 1 assume full-speed operation by all peripherals and internal components in a realistic application. this tdp value provides a high-level estimate for target applications. the processor?s power is specified as thermal design power (tdp) for thermal solution design. tdp is defined as a system design target associated with the maximum component operating temperature specifications. tdp values are determined based on typical dc electrical specification and maximum component temperature for a realistic- case application running at maximum utilization. the intel tdp specification is a recommended design point and is not representative of the absolute maximum power the processor may dissipate under worst-case conditions. for any excursions beyond tdp, the processor passive cooling feature is available to maintain the processor thermal specifications. refer to section 50.2, ?thermal sensor? refer to section 50.0, ?thermal specifications and design considerations? for further thermal specifications. 50.2 thermal sensor an independent thermal sensor helps control the silicon temperature by activating the thermal control sequence when the ep80579 reaches its maximum operating temperature. the temperature at which the ep80579 activates this thermal control sequence is not user configurable and is not visible to the software. the thermal sensor is an independent sens or that provides two outputs, thrmtrip# and prochot#. refer to section 50.2.1, ?catastrophic thermal protection? for details about thrmtrip# and to section 50.2.2, ?thermal sensor features? for details about prochot#. the ep80579 provides the ia-32 core thermal monitor. the ia-32 core thermal monitor has a throttling capability that can be activated via software or pre-boot firmware. refer to section 50.2.2.2, ?processor passive cooling? and section 50.2.2.3, ?on- demand passive cooling? for details. table 50-1. ep80579 thermal design powe r (tdp) and maximum case temperature specifications (t c-max ) intel ? ep80579 integrated processor intel ? ep80579 integrated processor with intel ? quickassist technology sku 28461375 processor frequency (mhz) 600 600 1066 1200 600 1066 1066 1200 tdp 1 (watts) 1111181913202021 t case-max 100 c 100 c97 c95 c 100 c97 c97 c95 c notes: 1. thermal design power (tdp) is a system design target associated with the maximum component operating temperature specifications. tdp values are determined based on typical dc electrical specification and maximum component temperature for a realistic-case application running at maximum utilization.
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1913 intel ? ep80579 integrated processor 50.2.1 catastrophic thermal protection the ep80579 provides catastrophic thermal protection via an on-die thermal sensor that detects when the silicon has reached approximately 20c above t case-max . this catastrophic trip point is programmed at the factory. the catastrophic trip point will initiate the processor thermal trip control sequence, which is described in section 50.2.1.1, ?thrmtrip# control sequence? . once the thermal sensor has detected this over heat condition, thrmtrip# is asserted. thrmtrip# is also available as an input pin to support platform thermal management requirements. an external thermal sensor could be implemented to monitor the platform thermal condition, asserting thrmtrip# when catastrophic thermal conditions exist on the platform. the ep80579 receives this signal and initiates the thrmtrip# control sequence described in section 50.2.1.1, ?thrmtrip# control sequence? . note: intel recommends that an external thermal sensor be used to protect the ep80579 and the system against excessive temperature. even with the activation of thrmtrip#, which halts all internal clocks and activity, leakage current can be high enough such that the ep80579 cannot be protected in all conditions without completely removing the supplied power source. if the external thermal sensor detects the silicon has reached a catastrophic temperature approximately 20c above tcase-max, or if the thrmtrip# signal is asserted, the vcc supply to the processor must be turned off within 500 ms to prevent silicon damage due to thermal runaway. 50.2.1.1 thrmtrip# control sequence a catastrophic thermal trip event will assert thrmtrip#, which indicates that the on- die thermal sensor has detected an overheat condition. intel recommends that immediate action be taken to prevent silicon damage. the temperature which the ep80579 activates this thermal control sequence is not user configurable and is not software visible. the following list provides additional information: ? if thrmtrip# goes active, the processor is indicating an overheat condition, and will immediately transition to an s5 state. however, since the processor has overheated, it will not respond to the stpclk# pin with a stop grant special cycle. therefore, the ep80579 will not wait for one. ? immediately upon seeing thrmtrip# low, ep80579 will initiate a transition to the s5 state, drive signals slp_s3#, slp_s4#, slp_s5# low, and set the cts bit. the transition will generally look like a power button override. ? when a thrmtrip# event occurs, the ep80579 must power down immediately without following the normal s0 -> s5 path. this can happen in parallel, but the ep80579 must immediately enter a power down state. the ep80579 will do this by driving signals slp_s3#, slp_s4#, and slp_s5# within 3 pciclks after sampling thrmtrip# active. ? if the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it are no longer executing cycles properly. therefore, if thrmtrip# goes active, any other components that are relying on state machine logic to perform the power down, may not power down correctly. because the state machine may not be working, the system may not power down completely. the ep80579 will follow the flow in the steps that follow for thrmtrip#: 1. at boot (pltrst# low), thrmtrip# ignored. 2. after power-up (pltrst# high), if thrmtrip# sampled active, slp_s3#, slp_s4#, and slp_s5# fire, and normal sequence of sleep machine starts.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1914 order number: 320066-003us 3. until sleep machine enters the s5 state, slp_s3#, slp_s4#, and slp_s5# stay active, even if thrmtrip# is now inactive. this is the equivalent of ?latching? the thermal trip event. 4. when the s5 state reached, return to step 1 above, otherwise stay here. if the ep80579 never gets to s5, the ep80579 does not reboot until power is cycled. during boot, thrmtrip# is ignored until slp_s3#, pwrok, vrmpwrgd, and pltrst# are all ?1?. during entry into a powered-down state (due to s3,s4, s5 entry, power cycle reset, etc.) thrmtrip# is ignored until any of the following occurs: ?slp_s3# = 0 ?pwrok = 0 ? vrmpwrgd = 0 1. set the afterg3_en bit 2. clear the pwrbtn_sts bit 3. clear all the gpe0_en register bits 4. clear the smb_wak_sts bit only if smb_wak_sts was set due to smbus slave receiving message and not set due to smbalert. note: the thrmtrip# pin must be glitch free. 50.2.2 thermal sensor features prochot# is asserted when the silicon temperature has reached the maximum operating limit. if the ep80579 reaches the trip temperature indicated in table 50-1, ?ep80579 thermal design power (tdp) and maximum case temperature specifications (tc-max)? , then prochot# is asserted and the ep80579 initiates a smi# or sci. prochot# provides platform visibility of a thermal condition determined by the thermal sensor. prochot# should be implemented in the platform design as a thermal warning, by initiating passive cooling, turning on fans or power management. when prochot# is asserted, intel recommends that power management software begins a processor-initiated passive cooling routine, which is described in section 50.2.2.2, ?processor passive cooling? . for platform thermal sensor designs, on-demand throttling is provided. section 50.2.2.3, ?on-demand passive cooling? provides more information. 50.2.2.1 prochot# control sequence the prochot# signal is a status output pin from the thermal sensor. the signal indicates that the ep80579 has reached the maximum operating limit. when this maximum operating temperature is reached, power management software or pre-boot firmware should take action to reduce the temperature. the ep80579 follows these behaviors with regard to the prochot# signal: ? based on the prochot# signal activation, the ep80579 generates an smi# or sci (depending on sci_en). ? if the prochot_pol bit is set low, when prochot# goes low, the prochot_sts bit will be set. this indicates that the thermal threshold has been exceeded. if the prochot_en bit is set, then when prochot_sts goes active, either an smi# or sci# will be generated (depending on the sci_en bit being set). the power management software (pre-boot firmware or acpi) can then take measures to start reducing the temperature. examples include shutting unneeded subsystems or halting the processor. another method to reduce the temperature is processor-
august 2009 intel ? ep80579 integrated processor product line datasheet order number: 320066-003us 1915 intel ? ep80579 integrated processor initiated passive cooling. refer to section 50.2.2.2, ?processor passive cooling? for more information. ? by setting the prochot_pol bit to high, another smi# or sci# can optionally be generated when the prochot# signal goes back high. this allows the software (pre-boot firmware or acpi) to turn off the cooling methods. ? prochot# assertion does not cause a tco event message in s3 or s4. the level of the signal is not reported in the heartbeat message. 50.2.2.2 processor passive cooling the ep80579 provides a processor-initiated passive cooling feature that actives a clock throttling mechanism, which can be used by power management software or pre-boot firmware to reduce the temperature. the force_thtl bit allows the pre-boot firmware to force passive cooling independent of the acpi software (which uses the th tl_en and thtl_dty bits). the force_thtl bit has the following behavior: ? if the force_thtl bit is set, the ep80579 will start throttling using the ratio in the prochot_dty field. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted while in thermal throttle mode. the stpclk# throttle period is 1024 pciclks (pciclk = 33 mhz). throttling only occurs if the system is in the c0 state. if in the c2, c3, or c4 state, no throttling occurs. note: refer to table 50-2 for duty cycle ratio settings. ? if the force_thtl bit is turned off (cleared), the ep80579 will stop throttling, unless the thtl_en bit is set (indicating that acpi software is attempting throttling). ? if both the thtl_en and force_thtl bits are set, then the iich uses the duty cycle defined by the prochot_dty field, not the thtl_dty field. (prochot_dty has higher priority). ? once the prochot_dty field is written, subsequent writes have no effect until pltrst# goes active. 50.2.2.3 on-demand passive cooling the ep80579 provides an on-demand passive cooling feature, which may be used in customer designs that require power management capabilities that take advantage of clock throttling. the on-demand feature is similar to the processor passive cooling in that it supports clock throttling, but the on-demand feature is initiated by software setting the thtl_en and thtl_dty bits. the on-demand passive cooling feature behaves as follows: ? software sets the thtl_dty bits to select throttle ratio and the thtl_en bit to enable the throttling. ? throttling results in stopclk# active for a minimum time of 12.5% and a maximum of 87.5%. the period is 1024 pci clocks (pciclk = 33 mhz). thus, the stopclk# signal can be active for as little as 128 pci clocks or as much as 896 pci clocks. the actual slowdown (and cooling) of the processor will depend on the instruction stream, because the processor is allowed to finish the current instruction. furthermore, the ep80579 waits for the stop-grant cycle before starting the count for the time the stopclk# signal is active. note: refer to table 50-2 for duty cycle ratio settings.
intel ? ep80579 integrated processor intel ? ep80579 integrated processor product line datasheet august 2009 1916 order number: 320066-003us table 50-2. prochot_dty/thtl_dty throttle ratios throttle mode pci clocks default (will be 50%) 512 87.5% 896 75.0% 768 62.5% 640 50% 512 37.5% 384 25% 256 12.5% 128
language: english compare now send feedback product specs intel ? processors intel ? ep80579 integrated processo r intel ? ep80579 integrated processo r with intel? quickassist technology series intel? ep80579 integrated processor with intel? quickassist technology, 600 mhz intel? ep80579 inte g rated processor with inte l? quickassist technolo g y, 600 mhz compare now add to compare a dditional information quick links embedded pcn/mdds information search distributors products formerly tolapai download datasheet specifications ordering / sspecs / steppings ordering / sspecs / steppings block diagrams specifications status launched launch date q3'08 # of cores 1 # of threads 1 clock speed 600 mhz l2 cache 256 kb fsb parity no instruction set 32-bit embedded options available yes supplemental sku no max tdp 13 w vid voltage range 1.0 max memory size (dependent on memory type) 4 gb memory types ddr2-400 / ddr2-533 / ddr2-667 / ddr2-800 # of memory channels 1 physical address extensions 32-bit ecc memory supported yes integrated graphics no dual display capable no macrovision* license required no pci express revision 1.1 pci express configurations 1x8, 2x4, or 2x1 usb revision usb 2.0 # of usb ports 2 # of sata ports 2 integrated lan 10/100/1000 general purpose io 36 gpio page 1 of 3 intel? ep80579 integrated processor with intel? quickassi st technology, 600 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34315/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
uart 2 t case 100c package size 37.5mm x 37.5mm low halogen options available no intel? turbo boost technology no intel? hyper-threading technology no intel? virtualization technology (vt-x) no intel? virtualization techno logy for directed i/o (vt-d) no intel? trusted execution technology no intel? 64 no idle states no enhanced intel speedstep? technology no intel? demand based switching no intel? active management technology no intel? quick resume technology no intel? quiet system technology no intel? quickassist technology yes intel? hd audio technology no intel? ac97 technology no intel? matrix storage technology no intel? fast memory access no intel? flex memory access no execute disable bit yes ordering and spec information ordering and spec information intel? ep80579 integrated proc essor with intel? quickassist technology, 80579eb600c, 600mhz socket step step tdp ordering code spec code low halogen vt-x fcbga1088 13 w nu80579eb600c no no block diagrams disclaimers page 2 of 3 intel? ep80579 integrated processor with intel? quickassi st technology, 600 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34315/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
? announced? skus are not yet available. please re fer to the launch date for market availability. enabling execute disable bit functionality requires a pc with a processor with execute disable bit capability and a supporting operating system. check with your pc manufac turer on whether your system delivers execute disable bit functionality. 64-bit computing on intel? architecture requires a computer system with a processor, chipset, bios, operating system, device dr ivers and applications enabled for intel? 64 architecture. processors will not operate (including 32-bit operation) without an intel 64 a rchitecture-enabled bios. performance will vary depending on your hardware and softw are configurations. consult with your system vendor for more in formation. hyper-threading technology (ht technology) requires a computer system with an intel? processor supporting ht technology and an ht t echnology enabled chipset, bios and operating system. performance will vary depending on the specific hardware and software you use. see www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support ht technology. intel? virtualization technology requires a computer system with a processor, chipset, bios, virtual machine monitor (vmm) and for some uses, certain platform software, enabled for it. functionality, pe rformance or other benefit will vary depending on hardware an d software configurations. intel virtualization technology-enabled vmm applications are currently in development. note: prices subject to change without notice. prices are for direct intel customers in 1000-unit bulk quantities and, unless s pecified, represent the latest technology versions of the products. taxes and shippi ng, etc. not included. prices ma y vary for other package types and shipment quantities, and special promotional arrangements may apply. intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. see http://www.intel.com/products/processor_number for details. system and maximum tdp is based on worst case scenarios. actual tdp may be lower if not all i/os for chipsets are used. a ll information provided is subject to change at any time, without notice. intel may make changes to manufacturing life cycle, s pecifications, and product descriptions at any time, without notice. the information herein is provided "as-is" and intel does not make any re presentations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compa tibility of the products listed. please contact system vendor for more information on specific products or systems. low halogen implies the following: bromine and/or chlorine in materials that may be used during processing, but do not remain within the final product are not inc luded in this definition. the halogens fluorine (f), iodine (i), and astatine (at) are not restricted by this standard. ? bfr/cfr and pvc-free? definition: : a ll pcb laminates mus t meet br and cl requirements for lo w halogen as defined in ipc-4101b for components other than pcb laminates, all homogeneous materials must contain < 900 ppm (0.09%) of bromine [if th e bromine (br ) source is from bfrs] and < 900 ppm (0.09%) of chlorine [if the chlorine (cl) source is from cfrs or pvc. higher concentrations of br a nd cl are allowed in homogenous materials of components other than pcb laminates as long as their sources are not bfrs, cfrs, pvc. a lthough the elemental analysis for br and cl in homogeneous materials can be performed by any analytical method with sufficient sensitivity and selectivity, the presence or absence of bfrs, cfrs or pvc must be verified by any acceptable analytical techniques that all ow for the unequivocal identification of the specific br or cl compounds, or by appropriate material declar ations agreed to between custom er and supplier. max turbo frequency refers to the maximum si ngle-core frequency that can be achieved with intel? turbo boost technology, which r equires a pc with a processor with intel turbo boost technology capability. intel turbo boost technology performance varies depending on hardware, software, and overall system configuration. check with your pc manufacturer on whether your system delivers intel turbo boost t echnology. see www.intel.com/technology/turboboost/ for more information. some products can support aes new instruct ions with a processor configuration update, in particular, i7-2630qm/i7-2635qm, i7-26 70qm/i7- 2675qm, i5-2430m/i5-2435m, i5-2410m/i5-2415m. please contact oem for the bios that includes the latest processor configuration update. page 3 of 3 intel? ep80579 integrated processor with intel? quickassi st technology, 600 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34315/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
language: english type here to search products compare queue (0) send feedback product specs intel ? processors intel ? ep80579 integrated processo r intel ? ep80579 integrated processor with intel? quickassist technology series i ntel ? ep80579 i ntegrated processor wi th i ntel ? qui cka ssi st technol ogy, 1066 mhz i ntel ? ep80579 i ntegrated processor wi th i ntel ? qui cka ssi st technol ogy, 1066 mhz compare now (0) add to compare addi ti onal i nform ati on qui ck li nks em bedded pcn/ mdds i nform ati on search di stri butors products fo rm e rl y tol apai dow nl oad datasheet speci fi cati ons essenti al s memory speci fi cati ons graphi cs speci fi cati ons expansi on opti ons i / o speci fi cati ons package speci fi cati ons advanced technol ogi es o rderi ng / sspecs / steppi ngs o rderi ng / sspecs / steppi ngs bl ock di agram s speci fi cati ons essenti al s status launched launch date q3' 08 # of cores 1 # of threads 1 clock speed 1 ghz l2 cache 256 kb fsb parity no instruction set 32- bi t embedded options available yes supplemental sku no lithography 90 nm max tdp 20 w vid voltage range 1. 3 memory speci fi cati ons max memory size (dependent on memory type) 4 gb memory types ddr2- 400 / ddr2- 533 / ddr2- 667 / ddr2- 800 # of memory channels 1 physical address extensions 32- bi t ecc memory supported yes graphi cs speci fi cati ons integrated graphics no dual display capable no macrovision* license required no expansi on opti ons pci express revision 1. 1 pci express configurations 1x8, 2x4, or 2x1 m enu com m uni ti es fi nd content what can we hel p you fi nd today? usa ( engl i sh) ? i ntel corporati on pri vacy *tradem arks term s of use i nvestor rel ati ons j ob s contact us support com pany i nform ati on page 1 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1066 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34313/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
i / o speci fi cati ons usb revision usb 2. 0 # of usb ports 2 # of sata ports 2 integrated lan 10/ 100/ 1000 general purpose io 36 gpi o uart 2 package speci fi cati ons t case 97 c package size 37. 5mm x 37. 5m m low halogen options available no advanced technol ogi es intel? turbo boost technology no intel? hyper-threading technology no intel? virtualization technology (vt-x) no intel? virtualization techno logy for directed i/o (vt-d) no intel? trusted execution technology no intel? 64 no idle states no enhanced intel speedstep? technology no intel? demand based switching no intel? active management technology no intel? quick resume technology no intel? quiet system technology no intel? quickassist technology yes intel? hd audio technology no intel? ac97 technology no intel? matrix storage technology no intel? fast memory access no intel? flex memory access no execute disable bit yes orderi ng and spec i nform ati o n orderi ng and spec i nform ati on i ntel ? ep80579 i ntegrated processor wi th i ntel ? qui cka ssi st technol ogy, 80579ed004c, 1066 mhz i ntel ? ep80579 i ntegrated processor wi th i ntel ? qui cka ssi st technol ogy, 80579ed004ct, 1066 mhz, extended tem p socket step step tdp ordering code spec code low halogen vt-x fcbga1088 20 w nu80579ed004c no no socket step step tdp ordering code spec code low halogen vt-x fcbga1088 20 w nu80579ed004ct no no bl ock di agram s m enu com m uni ti es fi nd content what can we hel p you fi nd today? usa ( engl i sh) ? i ntel corporati on pri vacy *tradem arks term s of use i nvestor rel ati ons j ob s contact us support com pany i nform ati on page 2 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1066 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34313/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
m enu com m uni ti es fi nd content what can we hel p you fi nd today? usa ( engl i sh) ? i ntel corporati on pri vacy *tradem arks term s of use i nvestor rel ati ons j ob s contact us support com pany i nform ati on page 3 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1066 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34313/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
di scl ai mers ? announced? sku s are not yet avai l abl e. pl ease re fe r to th e launch date fo r market avai l abi l i ty . enabl i ng execute di sabl e bi t functi onal i ty requi re s a pc wi th a processor wi th execute di sabl e bi t capabi l i ty and a supporti ng operati ng system . check wi th your pc m anufacturer on whether your system del i vers execute di sabl e bi t functi onal i ty . 64- bi t com puti ng on i ntel ? archi te ctu re requi re s a com puter system wi th a processor, chi pset, bi os, operati ng system , devi ce dri vers and appl i cati ons enabl ed fo r i ntel ? 64 archi te ctu re . processors wi l l not operate ( i ncl udi ng 32- bi t operati on) wi th o u t an i ntel 64 archi tecture- enabl ed bi os. perform ance wi l l vary dependi ng on your h a rd w a re and softw are confi gurati ons. consul t wi th your system vendor fo r more i nform ati on. hyper- threadi ng technol ogy ( ht technol ogy) re q u i re s a com puter system wi th an i ntel ? processor supporti ng ht technol ogy and an ht technol ogy enabl ed chi pset, bi os and operati ng system . perform ance wi l l vary dependi ng on th e speci fi c hardw are and so ftw a re you use. see www. i ntel . com / products/ ht/ hyperthreadi ng_m ore. htm fo r more i nform ati on i ncl udi ng detai l s on whi ch processors support ht technol ogy. i ntel ? vi rtu a l i zati on technol ogy re q u i re s a com puter system wi th a processor, chi pset, bi os, vi rtu a l machi ne moni to r ( vmm) and fo r som e uses, certai n pl atform softw are, enabl ed fo r i t. functi onal i ty , perform ance or other benefi t wi l l vary dependi ng on hardw are and so ftw a re confi gurati ons. i ntel vi rtu a l i zati on technol ogy- enabl ed vmm appl i cati ons are cu rre n tl y i n devel opm ent. note: pri ces subj ect to change wi th o u t noti ce. pri ces are fo r di re ct i ntel custom ers i n 1000- uni t bul k quanti ti es and, unl ess speci fi ed, represent th e l atest technol ogy versi ons of th e products. taxes and shi ppi ng, etc. not i ncl uded. pri ces may vary fo r other package ty p e s and shi pm ent quanti ti es, and speci al prom oti onal arrangem ents may appl y. i ntel processor num bers are not a measure of perform ance. processor num bers di ffe re n ti ate fe a tu re s wi th i n each processor fa m i l y, not across di ffe re n t processor fa m i l i es. see h ttp : / /www. i ntel . com / products/ processor_num ber fo r detai l s. system and maxi mum tdp i s based on worst case scenari os. actual tdp may be l ow er i f not al l i / os fo r chi psets are used. al l i nform ati on provi ded i s subj ect to change at any ti me, wi th o u t noti ce. i ntel may make ch an ge s to m anufacturi ng l i fe cycl e, speci fi cati ons, and product descri pti ons at any ti me, wi th o u t noti ce. the i nform ati on herei n i s provi ded "a s- i s" and i ntel does not make any representati ons or w a rra n ti es w hatsoever re g a rd i ng accuracy of th e i nform ati on, nor on th e product fe a tu re s, avai l abi l i ty , functi onal i ty , or com pati bi l i ty of th e products l i sted. pl ease contact system vendor fo r more i nform ati on on speci fi c products or system s. low hal ogen i mpl i es th e fo l l ow i ng: brom i ne and/ or chl ori ne i n materi al s th a t may be used duri ng processi ng, but do not re m a i n wi th i n th e fi nal product are not i ncl uded i n th i s defi ni ti on. the hal ogens fl uori ne ( f) , i odi ne ( i ) , and astati ne ( at) are not re stri cted by th i s standard. ? bfr/ cfr and pvc- free? defi ni ti on: : al l pcb l am i nates must m eet br and cl re q u i re m e n ts fo r l ow hal ogen as defi ned i n i pc- 4101b for com ponents other th a n pcb l am i nates, al l hom ogeneous materi al s must contai n < 900 ppm ( 0. 09% ) of brom i ne [ i f th e brom i ne ( br) source i s fro m bfrs] and < 900 ppm ( 0. 09% ) of chl ori ne [ i f th e chl ori ne ( cl ) source i s fro m cfrs or pvc. hi gher concentrati ons of br and cl are al l ow ed i n hom ogenous materi al s of com ponents other th a n pcb l am i nates as l ong as th e i r sources are not bfrs, cfrs, pvc. al th o u g h th e el em ental anal ysi s fo r br and cl i n hom ogeneous materi al s can be perform ed by any anal yti cal method wi th su ffi ci ent sensi ti vi ty and sel ecti vi ty , th e presence or absence of bfrs, cfrs or pvc must be veri fi ed by any acceptabl e anal yti cal techni ques th a t al l ow fo r the unequi vocal i denti fi cati on of th e speci fi c br or cl com pounds, or by appropri ate materi al decl arati ons agreed to betw een cu sto m er and suppl i er. max turbo frequency re fe rs to th e maxi mum si ngl e- co re frequency th a t can be achi eved wi th i ntel ? turbo boost technol og y , whi ch re q u i re s a pc wi th a processor wi th i ntel turbo boost technol ogy capabi l i ty . i ntel turbo boost technol ogy perform ance vari es dependi ng on h a rd w a re , so ftw a re , and overal l system confi gurati on. check wi th your pc m a n u fa ctu re r on whether your system del i vers i ntel turbo boost technol ogy. see www. i ntel . com / technol ogy/turboboost/ fo r more i nform ati on. som e products can support aes new i nstructi ons wi th a processor confi gurati on update, i n parti cul ar, i 7- 2630qm /i 7- 2635qm , i 7- 2670qm /i 7- 2675qm , i 5- 2430m / i 5- 2435m , i 5- 2410m / i 5- 2415m . pl ease contact oem fo r th e bi os th a t i ncl udes th e l atest processor confi gurati on update. m enu com m uni ti es fi nd content what can we hel p you fi nd today? usa ( engl i sh) ? i ntel corporati on pri vacy *tradem arks term s of use i nvestor rel ati ons j ob s contact us support com pany i nform ati on page 4 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1066 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34313/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
language: english type here to search products compare queue (0) send feedback product specs intel ? processors intel ? ep80579 integrated processo r intel ? ep80579 integrated processor with intel? quickassist technology series intel? ep80579 integrated processor with intel? quickassist technology, 1200 mhz intel? ep80579 integrated processor with intel? quickassist technology, 1200 mhz compare now (0) add to compare a dditional information quick links embedded pcn/mdds information search distributors products formerly tolapai download datasheet specifications essentials memory specifications graphics specifications expansion options i/o specifications package specifications advanced technologies ordering / sspecs / steppings ordering / sspecs / steppings block diagrams specifications essentials status launched launch date q3'08 # of cores 1 # of threads 1 clock speed 1.2 ghz l2 cache 256 kb fsb parity no instruction set 32-bit embedded options available yes supplemental sku no lithography 90 nm max tdp 21 w vid voltage range 1.3 memory specifications max memory size (dependent on memory type) 4 gb memory types ddr2-400 / ddr2-533 / ddr2- 667 / ddr2-800 # of memory channels 1 physical address extensions 32-bit ecc memory supported yes graphics specifications integrated graphics no dual display capable no macrovision* license required no expansion options pci express revision 1.1 page 1 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1200 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34311/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
pci express configurations 1x8, 2x4, or 2x1 i/o specifications usb revision usb 2.0 # of usb ports 2 # of sata ports 2 integrated lan 10/100/1000 general purpose io 36 gpio uart 2 package specifications t case 95c package size 37.5mm x 37.5mm low halogen options available no advanced technologies intel? turbo boost technology no intel? hyper-threading technology no intel? virtualization technology (vt-x) no intel? virtualization technol ogy for directed i/o (vt-d) no intel? trusted execution technology no intel? 64 no idle states no enhanced intel speedstep? technology no intel? demand based switching no intel? active management technology no intel? quick resume technology no intel? quiet system technology no intel? quickassist technology yes intel? hd audio technology no intel? ac97 technology no intel? matrix storage technology no intel? fast memory access no intel? flex memory access no execute disable bit yes orderin g and spec information ordering and spec information intel? ep80579 integrated proces sor with intel? quickassist te chnology, 80579ed009c, 1200 mhz socket step step tdp ordering code spec code low halogen vt-x fcbga1088 21 w NU80579ED009C no no block diagrams page 2 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1200 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34311/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
page 3 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1200 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34311/intel-ep80579-inte g rate d -processo r -with-intel-qui ...
disclaimers ? announced? skus are not yet available. please refer to the launch date for market availability. enabling execute disable bit functionality requires a pc with a processor with execute disable bit capability and a supporting operating system. check with your pc manufac turer on whether your sy stem delivers execute disable bit functionality. 64-bit computing on intel? architecture requires a computer system with a processor, chipset, bios, operating system, device dr ivers and applications enabled for intel? 64 architecture. processors will not operate (including 32-bit operation) without an intel 64 a rchitecture-enabled bios. performance will vary depending on your hardware and softwa re configurations. consult with your system vendor for more in formation. hyper-threading technology (ht technology) requires a computer system with an intel? processor supporting ht technology and an ht t echnology enabled chipset, bios and operating system. performance will vary depending on the specific hardware and software you use. see www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support ht technology. intel? virtualization technology requires a computer system with a processor, chipset, bios, virtual machine monitor (vmm) and for some uses, certain platform software, enabled for it. functionality, pe rformance or other benefit will vary depending on hardware an d software configurations. intel virtualization technology-enabled vmm applications are currently in development. note: prices subject to change without notice. prices are for direct intel customers in 1000-unit bulk quantities and, unless s pecified, represent the latest technology versions of the products. taxes and shippi ng, etc. not included. prices ma y vary for other package types and shipment quantities, and special promotional arrangements may apply. intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. see http://www.intel.com/products/processor_number for details. system and maximum tdp is based on worst case scenarios. actual tdp may be lower if not all i/os for chipsets are used. a ll information provided is subject to change at any time, withou t notice. intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. the information herein is provided "as-is" and intel does not make any re presentations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compa tibility of the products listed. please contact system vendor for more information on specific products or systems. low halogen implies the following: bromine and/or chlorine in materials that may be used during processing, but do not remain within the final product are not inc luded in this definition. the halogens fluorine (f), iodine (i), and astatine (at) are not restricted by this standard. ? bfr/cfr and pvc-free? definition: : a ll pcb laminates must meet br and cl requirem ents for low halogen as defined in ipc-4101b for components other than pcb la minates, all homogeneous materi als must contain < 900 ppm (0.09% ) of bromine [if the bromine (br ) source is from bfrs] and < 900 ppm (0.09%) of chlorine [if the chlorine (cl) source is from cfrs or pvc. higher concentrations of br a nd cl are allowed in homogenous materials of components other than pcb laminates as long as their sources are not bfrs, cfrs, pvc. a lthough the elemental analysis for br and cl in homogeneous materials can be performed by any analytical method with sufficient sensitivity and selectivity, the presence or absence of bfrs, cfrs or pvc must be verified by any acceptable analytical techniques that all ow for the unequivocal identification of the specific br or cl compounds, or by appropriate material declar ations agreed to between custom er and supplier. max turbo frequency refers to the maximum single-core frequency that can be achieved with intel? turbo boost technology, which requires a pc with a processor with intel turbo boost technology capability. intel turbo boost technology performance varies depending on hardware, software, and overall system configuration. check with your pc manufacturer on whether your system delivers intel turbo boost t echnology. see www.intel.com/technology/turboboost/ for more information. some products can support aes new instructions with a processo r configuration update, in particular, i7-2630qm/i7-2635qm, i7-26 70qm/i7- 2675qm, i5-2430m/i5-2435m, i5-2410m/i5-2415m. please contact oem for the bios that includes the latest processor configuration update. page 4 of 4 intel? ep80579 integrated processor with intel? quickassi st technology, 1200 mhz 18-au g -2011 htt p ://ark.intel.com/ p roducts/34311/intel-ep80579-inte g rate d -processo r -with-intel-qui ...

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